Method, computer device, medium and apparatus for synchronizing across clock domains

Abstract

The application relates to the technical field of integrated circuits and provides a cross-clock-domain synchronization method, computer equipment, a medium and an apparatus. The synchronization method comprises the following steps: outputting a synchronized data enable signal in a second clock domain through a first asynchronous first-in-first-out memory; and outputting a synchronized data signal in the second clock domain through a second asynchronous first-in-first-out memory. The conversion and processing across clock domains are realized, the data path delay is effectively reduced, a low-power-consumption, high-integration, low-delay synchronization solution is provided, and the conversion and processing across clock domains are flexibly and timely adapted to different clock domain requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a cross-clock-domain synchronization method, a computer device, a medium and an apparatus. BACKGROUND

[0002] In application scenarios such as large data centers, high-performance computing centers, and cloud computing platforms, high-speed data transmission technologies such as SERializer / DESerializer (SERDES) technology are widely used. Using high-speed serialization data transmission protocols, a clock signal is embedded in the serial data for transmission, and at the receiving end, a recovered clock is obtained through Clock and Data Recovery (CDR) for data sampling. However, the recovered clock is not synchronized with the local clock at the receiving end, and there may be a certain frequency difference and phase difference. In addition, with the increasing system integration and functional complexity of System on Chip (SOC), there may be multiple different clock domains within a chip, and communication between modules in different clock domains also needs to overcome synchronization problems to achieve cross-clock-domain data interaction. Similar to the case of multiple different clock domains within a single chip such as an SOC chip, there may also be multiple different clock domains between different chips within the same system, and communication between these chips in different clock domains also faces the problem of frequency difference and phase difference, so it is necessary to overcome the synchronization problem between clock signals in different clock domains and ensure normal data transmission.

[0003] In the prior art, in order to avoid data loss and transmission errors due to asynchronization, elastic buffering is generally used to absorb the frequency difference and phase difference between different clock domains, and special symbol sequences are also transmitted on the data transmission bus that transmits valid data. Data transmission protocols, such as the Peripheral Component Interconnect Express (PCIe) bus specification, define special symbol sequences specifically for compensating for clock frequency differences. Special symbol sequences are inserted on the PCIe bus and enter the elastic buffer together with valid data sequences. Through special symbol detection and special symbol-related operations such as copying and deleting, buffer overflow and data loss are avoided. However, the detection of special symbols and special symbol-related operations result in additional hardware overhead and increased data path delay, and increase the overall power consumption of the circuit, which is not conducive to meeting the chip design requirements of low power consumption, high integration, and low latency.

[0004] Therefore, the present application provides a cross-clock-domain synchronization method, a computer device, a medium and an apparatus to address the technical problems in the prior art. SUMMARY

[0005] In a first aspect, the present application provides a synchronization method across clock domains. The synchronization method comprises: outputting, by a first asynchronous first-in-first-out memory, a synchronized data enable signal in a second clock domain, wherein the first asynchronous first-in-first-out memory comprises a first data terminal, a first write control terminal and a first read control terminal, the first data terminal is connected to a first data enable signal in a first clock domain, the first write control terminal is connected to a first clock signal in the first clock domain, the first read control terminal is connected to a second clock signal in the second clock domain, the first data enable signal is used to gate the first clock signal to obtain a gated first clock signal, and the synchronized data enable signal is used to gate the second clock signal to obtain a gated second clock signal; and outputting, by a second asynchronous first-in-first-out memory, a synchronized data signal in the second clock domain, wherein the second asynchronous first-in-first-out memory comprises a second data terminal, a second write control terminal and a second read control terminal, the second data terminal is connected to a first data signal in the first clock domain, the second write control terminal is connected to the gated first clock signal, and the second read control terminal is connected to the gated second clock signal.

[0006] According to the first aspect of the present application, the first asynchronous first-in-first-out memory is used to output the synchronized data enable signal in the second clock domain by using the optimized circuit connection relationship, and the gated first clock signal and the gated second clock signal are generated by the gating logic on the basis of the output of the synchronized data enable signal by the first asynchronous first-in-first-out memory, and then the second asynchronous first-in-first-out memory is used to output the synchronized data signal in the second clock domain. In this way, the compensation problem of the frequency difference and the phase difference between the first clock domain and the second clock domain is converted into the problem of determining the minimum delay configuration of the delay operation of the read clock timing of the second asynchronous first-in-first-out memory by training. For the asynchronous application scenario, the position of the read clock relative to the write clock of the first asynchronous first-in-first-out memory is adjusted by gating the read clock of the first asynchronous first-in-first-out memory, so as to adjust the readout time of the data enable signal by the first asynchronous first-in-first-out memory, and then the delay operation of the read clock timing of the second asynchronous first-in-first-out memory is performed, so as to ensure that the second asynchronous first-in-first-out memory provides complete and correct read data function. The minimum delay configuration is determined by training, and on the basis of making up the frequency difference and the phase difference between the first clock signal and the second clock signal, the conversion and processing across clock domains are realized, the data path delay is effectively reduced, a low-power, high-integration, low-latency synchronization solution is provided, and flexible and timely adaptation to different clock domain requirements for conversion and processing across clock domains is realized.

[0007] In a possible implementation of the first aspect of the application, the synchronization method further comprises: when the output of the second asynchronous first-in-first-out memory is incorrect, delaying adjustment of read-write clock timing of the first asynchronous first-in-first-out memory, so as to determine a minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory, and the minimum delay configuration is used to ensure that the output of the second asynchronous first-in-first-out memory is correct.

[0008] In a possible implementation of the first aspect of the application, the synchronization method further comprises: when the output of the second asynchronous first-in-first-out memory is incorrect, generating a data enable signal with a length of a single cycle of the first clock signal as the first data enable signal, which is used to turn on the read-write clock of the second asynchronous first-in-first-out memory for one beat.

[0009] In a possible implementation of the first aspect of the application, the synchronization method further comprises: using test data as the first data signal, and comparing the test data and the synchronized data signal output by the second asynchronous first-in-first-out memory, so as to determine whether the output of the second asynchronous first-in-first-out memory is correct.

[0010] In a possible implementation of the first aspect of the application, when the output of the second asynchronous first-in-first-out memory is incorrect, the position of the read clock of the first asynchronous first-in-first-out memory relative to the write clock of the first asynchronous first-in-first-out memory is postponed, so as to adjust the readout time of the first asynchronous first-in-first-out memory for the first data enable signal, and the training process of the first data enable signal for one beat of the first clock signal is configured again until the output of the second asynchronous first-in-first-out memory is correct.

[0011] In a possible implementation of the first aspect of the application, when the output of the second asynchronous first-in-first-out memory is incorrect, the current delay value of the adjustable delay unit on the first read control end is gradually increased from the minimum delay value of the adjustable delay unit, and the read clock of the first asynchronous first-in-first-out memory received by the first asynchronous first-in-first-out memory through the first read control end is delayed according to the current delay value of the adjustable delay unit, so as to adjust the synchronized data enable signal output by the first asynchronous first-in-first-out memory, and the second clock signal after gating is adjusted so as to adjust the output of the second asynchronous first-in-first-out memory until the output of the second asynchronous first-in-first-out memory is correct.

[0012] In a possible implementation of the first aspect of the present application, the test data is N times M bits, where M is a data bit width of one cycle of the second clock signal, N is a ratio of a data bit width of one cycle of the first clock signal divided by the data bit width of one cycle of the second clock signal, N is a positive integer greater than or equal to 1, and the comparing the test data with the synchronous post-data signal output by the second asynchronous first-in-first-out memory comprises: comparing the lowest M bits of the test data with the M bits read by the second asynchronous first-in-first-out memory under the action of one cycle of the gated post-second clock signal.

[0013] In a possible implementation of the first aspect of the present application, the lowest M bits of the test data are all 1 and the other bits are all 0, and when the M bits read by the second asynchronous first-in-first-out memory under the action of one cycle of the gated post-second clock signal are all 1, it is determined that the output of the second asynchronous first-in-first-out memory is correct.

[0014] In a possible implementation of the first aspect of the present application, the frequency of the second clock signal is N integer times of the frequency of the first clock signal, and the data bit width of one cycle of the first clock signal is equal to N integer times of the data bit width of one cycle of the second clock signal.

[0015] In a possible implementation of the first aspect of the present application, the data transmission rate associated with the second clock signal is equal to the data transmission rate associated with the first clock signal.

[0016] In a possible implementation of the first aspect of the present application, the first clock domain is a write clock domain, the first clock signal is a write clock signal, the second clock domain is a read clock domain, the second clock signal is a read clock signal, and the frequency of the read clock signal is higher than the frequency of the write clock signal.

[0017] In a possible implementation of the first aspect of the present application, the write data bit width under one cycle of the write clock signal is equal to an integer multiple of the read data bit width under one cycle of the read clock signal, and the read data transmission rate associated with the read clock signal is equal to the write data transmission rate associated with the write clock signal.

[0018] In a possible implementation of the first aspect of the present application, the second asynchronous first-in-first-out memory is any one of a plurality of asynchronous first-in-first-out memories associated with the write clock domain and the read clock domain, the plurality of asynchronous first-in-first-out memories all use the read clock signal and adopt the same read data bit width, and the synchronous post-data enable signal is applicable to each of the plurality of asynchronous first-in-first-out memories.

[0019] In a possible implementation of the first aspect of the present application, the synchronization method further includes: copying the first asynchronous first-in-first-out memory for the plurality of asynchronous first-in-first-out memories respectively, thereby constructing a plurality of data channels corresponding to the plurality of asynchronous first-in-first-out memories one by one, wherein the plurality of data channels are isolated from each other in service.

[0020] In a possible implementation of the first aspect of the present application, the second clock domain belongs to any one of a plurality of read clock domains, and the synchronization method further includes: establishing a plurality of data channels independent of each other in the plurality of read clock domains by training the combination of the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory.

[0021] In a second aspect, the embodiments of the present application further provide a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method according to any one of the implementation manners of any one of the above aspects when executing the computer program.

[0022] In a third aspect, the embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and the computer instructions make the computer device execute the method according to any one of the implementation manners of any one of the above aspects when the computer instructions run on the computer device.

[0023] In a fourth aspect, the embodiments of the present application further provide a computer program product, which includes instructions stored in a computer readable storage medium, and the instructions make the computer device execute the method according to any one of the implementation manners of any one of the above aspects when the instructions run on the computer device.

[0024] In a fifth aspect, the present application provides a synchronization device for cross-clock domain. The synchronization device comprises: a first asynchronous first-in-first-out memory, wherein the first asynchronous first-in-first-out memory comprises a first data terminal, a first write control terminal and a first read control terminal, the first data terminal is connected to a first data enable signal of a first clock domain, the first write control terminal is connected to a first clock signal of the first clock domain, the first read control terminal is connected to a second clock signal of a second clock domain, the first asynchronous first-in-first-out memory is configured to output a synchronized data enable signal of the second clock domain, the first data enable signal is configured to gate the first clock signal to obtain a gated first clock signal, and the synchronized data enable signal is configured to gate the second clock signal to obtain a gated second clock signal; and a second asynchronous first-in-first-out memory, wherein the second asynchronous first-in-first-out memory comprises a second data terminal, a second write control terminal and a second read control terminal, the second data terminal is connected to a first data signal of the first clock domain, the second write control terminal is connected to the gated first clock signal, the second read control terminal is connected to the gated second clock signal, and the second asynchronous first-in-first-out memory is configured to output a synchronized data signal of the second clock domain.

[0025] By the fifth aspect of the present application, the first asynchronous first-in-first-out memory is used to output the synchronized data enable signal of the second clock domain by using the optimized circuit connection relationship, and the gated first clock signal and the gated second clock signal are generated by the gating logic on the basis of the output of the synchronized data enable signal of the first asynchronous first-in-first-out memory, and then the second asynchronous first-in-first-out memory is used to output the synchronized data signal of the second clock domain. In this way, the compensation problem of the frequency difference and the phase difference between the first clock domain and the second clock domain is converted into the problem of determining the minimum delay configuration of the delay operation of the read clock timing of the second asynchronous first-in-first-out memory by training. For the asynchronous application scenario, the position of the read clock relative to the write clock of the first asynchronous first-in-first-out memory is adjusted by gating the read clock of the first asynchronous first-in-first-out memory, so as to adjust the readout time of the data enable signal of the first asynchronous first-in-first-out memory, and then the delay operation of the read clock timing of the second asynchronous first-in-first-out memory is performed, so as to ensure that the second asynchronous first-in-first-out memory provides complete and correct read data function. The minimum delay configuration is determined by training, and on the basis of making up the frequency difference and the phase difference between the first clock signal and the second clock signal, the cross-clock domain conversion and processing are realized, the data path delay is effectively reduced, a low-power, high-integration, low-latency synchronization solution is provided, and flexible and timely adaptation to different clock domain requirements for cross-clock domain conversion and processing is realized.

[0026] In a possible implementation manner of the fifth aspect of the application, when the output of the second asynchronous first-in-first-out memory is incorrect, the synchronization device is configured to: delay adjust the read-write clock timing of the first asynchronous first-in-first-out memory, so as to determine a minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory, and the minimum delay configuration is used to ensure that the output of the second asynchronous first-in-first-out memory is correct.

[0027] In a possible implementation manner of the fifth aspect of the application, the first clock domain is a write clock domain, the first clock signal is a write clock signal, the second clock domain is a read clock domain, and the second clock signal is a read clock signal, and the frequency of the read clock signal is higher than the frequency of the write clock signal.

[0028] In a possible implementation manner of the fifth aspect of the application, the second asynchronous first-in-first-out memory is any one of a plurality of asynchronous first-in-first-out memories associated with the write clock domain and the read clock domain, the plurality of asynchronous first-in-first-out memories all use the read clock signal and adopt the same read data bit width, and the synchronization post-data enable signal is applicable to each of the plurality of asynchronous first-in-first-out memories. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] Figure 1 A schematic diagram of a cross-clock-domain application scenario;

[0031] Figure 2 A flowchart of a synchronization method across clock domains provided by an embodiment of the application;

[0032] Figure 3 A schematic diagram of a synchronization device across clock domains provided by an embodiment of the application;

[0033] Figure 4 A flowchart of a delay training method provided by an embodiment of the application;

[0034] Figure 5 A structural schematic diagram of a computing device provided by an embodiment of the application. DETAILED DESCRIPTION

[0035] The embodiments of the application will be further described in detail below with reference to the drawings.

[0036] It should be understood that in the description of the present application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first", "second", and the like, unless otherwise specified, are only used to distinguish the description purpose, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0037] Figure 1 is a schematic diagram of a cross-clock domain application scenario. As shown in Figure 1 , there are two different clock domains, in clock domain A101, there are associated clock signal A103, data signal A105 and data enable signal A107. In clock domain B121, there are associated clock signal B123, data signal B125 and data enable signal B127. Clock domain A101 and clock domain B121 as two different clock domains, may exist in the same chip, may exist between different chips in the same system, may exist between different computers, different servers, different computing nodes. In large data center, high performance computing center, cloud computing platform and other application scenarios, a large number of high-speed data transmission technology is applied, such as SERializer / DESerializer (SERDES) technology. Using high-speed serialization data transmission protocol, the clock signal is embedded into the serial data for transmission, and the recovered clock is obtained by clock and data recovery (CDR) at the receiving end, and then data sampling is performed. However, the recovered clock is not synchronized with the local clock of the receiving end, and there may be a certain frequency difference and phase difference. In addition, with the improvement of system integration and functional complexity of system on chip (SOC), there may be multiple different clock domains in a chip, and communication between modules in different clock domains also needs to overcome the synchronization problem to realize cross-clock domain data interaction. Similar to the case of multiple different clock domains existing in a single chip such as SOC chip, multiple different clock domains may exist between different chips in the same system, and communication between these chips in different clock domains also faces the problem of frequency difference and phase difference, so it is necessary to overcome the synchronization problem between clock signals in different clock domains and ensure normal data transmission service.

[0038] Referring back to Figure 1 , the asynchronization between clock domain A101 and clock domain B121 may cause frequency difference and phase difference in communication and data transmission service between the two clock domains, and further may cause data loss and transmission error. Figure 1The diagram also illustrates a cross-clock domain synchronization device 110 to overcome the asynchrony problem between clock domain A101 and clock domain B121. The cross-clock domain synchronization device 110 can perform cross-clock domain processing using a flexible buffer, such as asynchronous circuitry, like an asynchronous First-In-First-Out (FIFO) memory. After cross-clock domain processing by the cross-clock domain synchronization device 110, correct data operations, such as data read operations, can be achieved between the clock signal B123, data signal B125, and data enable signal B127 in clock domain B121. In some embodiments, Figure 1 The clock domain A101 shown is the write clock domain, and the clock domain B121 is the read clock domain. When there is a frequency difference and a phase difference between the clock source generating the write clock signal and the clock source generating the read clock signal, for example, when the requirement of the same clock source is not met, there is a clock phase difference between the write clock signal (clock signal A103 in clock domain A101) and the read clock signal (clock signal B123 in clock domain B121). Furthermore, this clock phase difference is uncertain when there is a frequency difference between the read and write clock signals. Additionally, depending on the application scenario and customer requirements, the frequency difference and phase difference between the clock signals in the two different clock domains may vary. For example, clock signal B123 in clock domain B121 may have switched to another operating frequency or its phase may have changed. If the synchronization problem is overcome by relying on special symbol detection and special symbol copying and deletion operations, then at the transmitting end (e.g., on the clock domain A101 side), the special symbol sequence is also transmitted on the data transmission channel of the transmitted data signal A105. Furthermore, at the receiving end (e.g., on the clock domain B121 side), special symbol detection and related operations are performed. This means that additional hardware resources are required on the clock domain B121 side, and data path latency and power consumption are increased. The following detailed description, in conjunction with the accompanying drawings and specific embodiments, describes a cross-clock domain synchronization method, computer device, medium, and apparatus provided by this application, which can be applied to applications such as... Figure 1 The cross-clock domain synchronization device 110 shown not only provides a low-power, highly integrated, and low-latency synchronization solution, but also enables flexible and timely adaptation to different clock domain requirements for cross-clock domain conversion and processing.

[0039] Figure 2 This is a flowchart illustrating a cross-clock domain synchronization method provided in an embodiment of this application. Figure 2 As shown, the synchronization method includes the following steps.

[0040] Step S201: output a synchronous data enable signal in a second clock domain through a first asynchronous first-in-first-out memory, wherein the first asynchronous first-in-first-out memory comprises a first data terminal, a first write control terminal and a first read control terminal, the first data terminal is connected to a first data enable signal in a first clock domain, the first write control terminal is connected to a first clock signal in the first clock domain, the first read control terminal is connected to a second clock signal in the second clock domain, the first data enable signal is used to gate the first clock signal to obtain a gated first clock signal, and the synchronous data enable signal is used to gate the second clock signal to obtain a gated second clock signal.

[0041] Step S203: output a synchronous data signal in the second clock domain through a second asynchronous first-in-first-out memory, wherein the second asynchronous first-in-first-out memory comprises a second data terminal, a second write control terminal and a second read control terminal, the second data terminal is connected to a first data signal in the first clock domain, the second write control terminal is connected to the gated first clock signal, and the second read control terminal is connected to the gated second clock signal.

[0042] Referring to Figure 2 , the first clock signal, the first data enable signal and the first data signal are all in the first clock domain, and the second clock signal, the second data enable signal and the second data signal are all in the second clock domain. Referring to Figure 1The asynchronization between the clock domain A101 and the clock domain B121 shown can cause frequency difference and phase difference between the communication and data transmission service between the two clock domains, and further can cause data loss and transmission error. Here, the asynchronization problem can exist between the first clock domain and the second clock domain. The synchronized data enable signal in the second clock domain is output through the first asynchronous first-in-first-out memory, and the synchronized data signal in the second clock domain is output through the second asynchronous first-in-first-out memory. The synchronized data enable signal and the synchronized data signal in the second clock domain obtained through the above-mentioned processes complete the conversion and processing across the clock domains, can overcome the frequency difference and phase difference between the first clock signal and the second clock signal, and effectively avoid data loss and data transmission error. The first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory have similar structure design and principle, each has a data terminal, a write control terminal and a read control terminal, and further has an output terminal for output. The operation principle of the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory is similar: the write control terminal is used for connecting a write control signal, and the read control terminal is used for connecting a read control signal; under the action of the write control signal received through the write control terminal, the information received by the data terminal is written into the corresponding asynchronous first-in-first-out buffer, that is, the write clock timing of the corresponding asynchronous first-in-first-out buffer is established; under the action of the read control signal received through the read control terminal, the information buffered in the corresponding asynchronous first-in-first-out buffer is output, that is, the read clock timing of the corresponding asynchronous first-in-first-out buffer is established. Therefore, the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory respectively establish the corresponding write clock timing and read clock timing through the write control terminal and the read control terminal of each, and realize writing data into the corresponding asynchronous first-in-first-out memory and reading data from the corresponding asynchronous first-in-first-out memory for output.

[0043] With reference to the above-mentioned Figure 2, and the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory are used to output the synchronous data enable signal in the second clock domain and the synchronous data signal in the second clock domain respectively, so that the conversion and processing across the clock domains are realized. Specifically, the first asynchronous first-in-first-out memory comprises a first data end, a first write control end and a first read control end, the first data end is connected to the first data enable signal in the first clock domain, the first write control end is connected to the first clock signal in the first clock domain, and the first read control end is connected to the second clock signal in the second clock domain. In this way, the first write control end of the first asynchronous first-in-first-out memory is used to connect the write control signal of the first asynchronous first-in-first-out memory, i.e. the first clock signal, and the first read control end is used to connect the read control signal of the first asynchronous first-in-first-out memory, i.e. the second clock signal. The first asynchronous first-in-first-out memory writes the information received by the first data end into the first asynchronous first-in-first-out buffer under the action of the write control signal of the first asynchronous first-in-first-out memory received by the first write control end, and outputs the information buffered in the first asynchronous first-in-first-out buffer under the action of the read control signal of the first asynchronous first-in-first-out memory received by the first read control end, so that the first asynchronous first-in-first-out memory writes the first data enable signal under the action of the first clock signal, and reads and provides the output of the first asynchronous first-in-first-out memory under the action of the second clock signal. The output of the first asynchronous first-in-first-out memory is the synchronous data enable signal in the second clock domain.

[0044] With reference to the foregoing Figure 2, the first data enable signal is used to gate the first clock signal to obtain a gated first clock signal, and the synchronized data enable signal is used to gate the second clock signal to obtain a gated second clock signal. The design of introducing the gating logic means that the gating logic is enabled and disabled by the corresponding gating signals, and the corresponding clock signals are gated, so that the gated first clock signal and the gated second clock signal are obtained to establish the write and read clock timing of the second asynchronous first-in-first-out memory. Specifically, the second asynchronous first-in-first-out memory includes a second data terminal, a second write control terminal and a second read control terminal, the second data terminal is connected to the first data signal of the first clock domain, the second write control terminal is connected to the gated first clock signal, and the second read control terminal is connected to the gated second clock signal. In this way, the second write control terminal of the second asynchronous first-in-first-out memory is used to connect the write control signal of the second asynchronous first-in-first-out memory, that is, the gated first clock signal, and the second read control terminal of the second asynchronous first-in-first-out memory is used to connect the read control signal of the second asynchronous first-in-first-out memory, that is, the gated second clock signal. The second asynchronous first-in-first-out memory writes the information received by the second data terminal into the second asynchronous first-in-first-out buffer under the action of the write control signal of the second asynchronous first-in-first-out memory received by the second write control terminal, and outputs the information buffered in the second asynchronous first-in-first-out buffer under the action of the read control signal of the second asynchronous first-in-first-out memory received by the second read control terminal, so that the second asynchronous first-in-first-out memory writes the first data signal under the action of the gated first clock signal, and reads and provides the output of the second asynchronous first-in-first-out memory under the action of the gated second clock signal. The output of the second asynchronous first-in-first-out memory is the synchronized data signal of the second clock domain.

[0045] With reference to the above Figure 2, utilize the optimized circuit connection relationship, specifically, utilize the first asynchronous first-in-first-out memory to output the synchronized data enable signal in the second clock domain, and on the basis of the first asynchronous first-in-first-out memory outputting the synchronized data enable signal, generate the gated first clock signal and the gated second clock signal through the gate logic, and then utilize the second asynchronous first-in-first-out memory to output the synchronized data signal in the second clock domain; in this way, the compensation problem of the frequency difference and the phase difference possibly existing between the first clock domain and the second clock domain is converted into the problem of determining the minimum delay configuration of the delay operation of the read clock timing of the second asynchronous first-in-first-out memory through training. The first asynchronous first-in-first-out memory synchronizes the first data enable signal from the first clock domain to the synchronized data enable signal in the second clock domain, and uses the synchronized data enable signal for generating the gated second clock signal and then for establishing the read clock timing of the second asynchronous first-in-first-out memory, while the first data enable signal is used for generating the gated first clock signal and then for establishing the write clock timing of the second asynchronous first-in-first-out memory, so that the second asynchronous first-in-first-out memory synchronizes the first data signal from the first clock domain to the synchronized data signal in the second clock domain under the action of the gated read and write clock signals, that is, the cross-clock-domain synchronization of the data signal is completed. The delay operation of the read clock timing of the second asynchronous first-in-first-out memory can be completed through various technical means, for example, the edge elimination operation of the read clock timing of the first asynchronous first-in-first-out memory can be completed through the successive configuration of the gate enable, and for another example, the readout time of the data enable signal can be adjusted by delaying the read pointer of the first asynchronous first-in-first-out memory, and then the delay operation of the read clock timing of the second asynchronous first-in-first-first memory is completed. By observing the data readout result of the second asynchronous first-in-first-out memory, the minimum delay configuration can be determined, so that not only the cross-clock-domain conversion and processing are realized, but also the data path delay is effectively reduced. Figure 2The synchronization method across clock domains shown provides a low-power, high-integration, low-latency synchronization solution through the optimized circuit connection relationship contained therein and the respective operation principles of the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory. For asynchronous application scenarios, the position of the read clock relative to the write clock of the first asynchronous first-in-first-out memory is adjusted by gating the read clock, and the delay operation on the read clock timing of the second asynchronous first-in-first-out memory is performed, so that the second asynchronous first-in-first-out memory can provide complete and correct read data function. Moreover, unlike the detection of special symbols and special symbol-related operations, the minimum delay configuration determined by training does not require additional resources to detect special symbols and delete insertion operations. An embodiment of the minimum delay configuration determined by training includes: by checking the data readout result of the second asynchronous first-in-first-out memory and comparing it with the test data, if it is found that the second asynchronous first-in-first-out memory does not correctly complete the data readout function, the position of the read clock in the first asynchronous first-in-first-out memory relative to the write clock is delayed, so as to adjust the readout time of the data enable signal, and further delay the read clock of the second asynchronous first-in-first-out memory until the second asynchronous first-in-first-out memory correctly reads out data. In this way, the minimum delay configuration determined by training can complete the delay operation on the read clock timing of the second asynchronous first-in-first-out memory through any suitable implementation, for example, deploying an adjustable delay unit on the first read control end of the first asynchronous first-in-first-out memory for receiving the read clock of the first asynchronous first-in-first-out memory, i.e., the read control signal of the first asynchronous first-in-first-out memory, adjusting the readout time of the data enable signal by delaying the read pointer of the first asynchronous first-in-first-out memory, and further completing the delay operation on the read clock timing of the second asynchronous first-in-first-out memory. In this way, the compensation problem of the frequency difference and phase difference that may exist between the first clock domain and the second clock domain is converted into the minimum delay configuration problem of the delay operation on the read clock timing of the second asynchronous first-in-first-out memory determined by training. By adjusting the position of the read clock in the first asynchronous first-in-first-out memory relative to the write clock, the readout time of the data enable signal is adjusted, and further equivalent to adjusting the read clock of the second asynchronous first-in-first-out memory, the data transmission delay is minimized on the basis of compensating for the frequency difference and phase difference that may exist between the first clock signal and the second clock signal.

[0046] Continuing to refer to Figure 2 Depending on the application scenario requirements and customer needs, the frequency difference and phase difference between the respective clock signals in the two different clock domains may vary, for example, the clock signal in one clock domain may switch to another operating frequency or the phase may change. In the face of different clock domain requirements, Figure 2The synchronization method across clock domains can complete the training according to the latest clock domain requirement by measuring the output of the second asynchronous first-in-first-out memory and performing corresponding delay adjustment, and can achieve flexible and timely adaptation to different clock domain requirements for conversion and processing across clock domains. In addition, if there are multiple conversion and processing requirements across clock domains at the same time, for example, there are multiple chips or modules that need to be synchronized in the read clock domain, and for example, there are multiple data channels that need to be interacted across clock domains at the receiving end, in this case, one chip or module in the read clock domain can be selected as a representative, and the adaptation between the write clock domain and the read clock domain can be achieved through one training, and the minimum delay configuration obtained by training can be applied to other chips or modules in the same read clock domain. Therefore, when multiple conversion and processing requirements across clock domains apply to the same read clock domain and the same read clock signal, the synchronization between the write clock domain and the read clock domain can be trained to meet the needs of any number of conversion and processing across clock domains. In addition, by providing multiple second asynchronous first-in-first-out memories, multiple data channels, multiple data transmission lines, and multiple receiving ends can be provided with corresponding cross-clock domain synchronization processing, and by copying the first asynchronous first-in-first-out memory, multiple data transmission paths with business isolation between each other can be conveniently established. In the case of multiple second asynchronous first-in-first-out memories and corresponding multiple data transmission paths, the training stage is for the delay adjustment of the read clock relative to the write clock on the first asynchronous first-in-first-out memory and the minimum delay configuration obtained by training, so the training stage is common and one training can meet the cross-clock domain synchronization needs of multiple data transmission paths respectively. In the case of multiple second asynchronous first-in-first-out memories, the same second clock signal and the same gated second clock signal, i.e., the same read enable signal, are used, which means that the read enable signal adjusted in place through training can be used for the read control of any number of second asynchronous first-in-first-out memories. Therefore, the conversion of the data enable signal and the data signal from the write clock domain to the read clock domain is realized, which is beneficial to parallel data transmission. In the application scenarios of high-performance memories such as High Bandwidth Memory (HBM), multiple data channels may need to be provided with cross-clock domain synchronization processing, and the frequency of the read clock signal on the read clock domain side may need to be adjusted according to the data transmission business needs, for example, to change the working frequency to adjust the data transmission rate. By Figure 2 The synchronization method across clock domains can provide corresponding cross-clock domain synchronization processing for any number of data channels, and simplify the training process and reduce the training time, which is beneficial to improving the overall system efficiency.

[0047] In summary, Figure 2The synchronization method across clock domains shown utilizes an optimized circuit connection relationship, utilizes a first asynchronous first-in-first-out memory to output a synchronized data enable signal in a second clock domain, and on the basis of the first asynchronous first-in-first-out memory outputting the synchronized data enable signal, generates a gated first clock signal and a gated second clock signal through gate logic, and then utilizes a second asynchronous first-in-first-out memory to output a synchronized data signal in the second clock domain. In this way, the compensation problem of a frequency difference and a phase difference possibly existing between the first clock domain and the second clock domain is converted into the problem of determining the minimum delay configuration of a delay operation of a read clock timing of the second asynchronous first-in-first-out memory through training. For an asynchronous application scenario, the position of a read clock of the first asynchronous first-in-first-out memory relative to a write clock is adjusted, so as to adjust the readout time of the first asynchronous first-in-first-out memory for the data enable signal, and then the delay operation of the read clock timing of the second asynchronous first-in-first-out memory is performed, so as to ensure that the second asynchronous first-in-first-out memory provides complete and correct read data functions. Through training to determine the minimum delay configuration, on the basis of compensating for a frequency difference and a phase difference possibly existing between the first clock signal and the second clock signal, the conversion and processing across clock domains are realized, the data path delay is effectively reduced, not only a low-power, high-integration, low-latency synchronization solution is provided, but also flexible and timely adaptation to different clock domain requirements for conversion and processing across clock domains is realized.

[0048] Referring to Figure 3 In a possible implementation, the synchronization method further includes: when the output of the second asynchronous first-in-first-out memory is incorrect, delaying and adjusting the read-write clock timing of the first asynchronous first-in-first-out memory, so as to determine the minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory, the minimum delay configuration being used to ensure that the output of the second asynchronous first-in-first-out memory is correct. In this way, by measuring the output of the second asynchronous first-in-first-out memory, it can be judged whether the output of the second asynchronous first-in-first-out memory is correct. When the output of the second asynchronous first-in-first-out memory is incorrect, the read-write clock timing of the first asynchronous first-in-first-out memory is delayed and adjusted, so that the position of the read clock in the first asynchronous first-in-first-out memory relative to the write clock is adjusted successively, so as to adjust the readout time of the first asynchronous first-in-first-out memory for the data enable signal, and then the delay operation of the read clock timing of the second asynchronous first-in-first-out memory is performed, and finally the minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory determined ensures that the output of the second asynchronous first-in-first-out memory is correct, and effectively reduces the data path delay.

[0049] In some embodiments, the synchronization method further comprises generating a data enable signal of a length of a single cycle of the first clock signal as the first data enable signal for strobing a read-write clock of the second asynchronous first-in-first-out memory for one beat when the output of the second asynchronous first-in-first-out memory is incorrect. In this way, a low latency training scheme is implemented through the respective configuration of the data enable signal through which a minimum latency configuration is determined, such that not only is the cross-clock domain conversion and processing implemented, but also the data path latency is effectively reduced.

[0050] In one possible implementation, the synchronization method further comprises using test data as the first data signal and comparing the test data to the synchronized second data signal output by the second asynchronous first-in-first-out memory to determine whether the output of the second asynchronous first-in-first-out memory is correct. In this way, a low latency training scheme is facilitated by comparing the test data to the synchronized second data signal output by the second asynchronous first-in-first-out memory.

[0051] In one possible implementation, when the output of the second asynchronous first-in-first-out memory is incorrect, the position of the read clock of the first asynchronous first-in-first-out memory relative to the write clock of the first asynchronous first-in-first-out memory is delayed, so as to adjust the readout time of the first asynchronous first-in-first-out memory for the first data enable signal, and the training process of the first data enable signal for one clock cycle of the first clock signal is configured again until the output of the second asynchronous first-in-first-out memory is correct. In this way, the compensation problem of the frequency difference and the phase difference possibly existing between the first clock domain and the second clock domain is converted into the minimum delay configuration problem of the delay operation of determining the read clock timing of the second asynchronous first-in-first-out memory through training. When the output of the second asynchronous first-in-first-out memory is incorrect, the position of the read clock of the first asynchronous first-in-first-out memory relative to the write clock of the first asynchronous first-in-first-out memory is delayed, for example, by adjusting the position of the read clock relative to the write clock in the first asynchronous first-in-first-out memory step by step, so as to adjust the readout time of the first asynchronous first-in-first-out memory for the first data enable signal, which is equivalent to adjusting the read clock of the second asynchronous first-in-first-out memory, so as to realize the data transmission delay as low as possible on the basis of compensating the frequency difference and the phase difference possibly existing between the first clock signal and the second clock signal. Specifically, the training process of the data enable signal for one clock cycle of the first clock signal is configured again, the read and write clocks of the second asynchronous first-in-first-out memory are opened for one cycle, the test data is read out for comparison, and the process is repeated until the output of the second asynchronous first-in-first-out memory is correct. In the training and working process, the test data is configured, the first clock enable is opened for one cycle to open the read and write clocks of the second asynchronous first-in-first-out memory, the test data is read out, if incorrect, the readout time is delayed by configuring the gate of the read clock of the first asynchronous first-in-first-out memory, the first clock enable is opened for one cycle to open the read and write clocks of the second asynchronous first-in-first-out memory, the test data is read out, and the working mode is entered until the test data is correct. In the working mode, the first clock data enable is gated to N second clocks after being read out by the first asynchronous first-in-first-out memory.

[0052] In one possible implementation, when the output of the second asynchronous first-in-first-out memory is incorrect, the current delay value of the adjustable delay unit is gradually increased from the minimum delay value of the adjustable delay unit through the adjustable delay unit on the first read control terminal, and the read clock of the first asynchronous first-in-first-out memory received by the first asynchronous first-in-first-out memory through the first read control terminal is delayed according to the current delay value of the adjustable delay unit, thereby adjusting the synchronous data enable signal output by the first asynchronous first-in-first-out memory, adjusting the gated second clock signal so as to adjust the output of the second asynchronous first-in-first-out memory until the output of the second asynchronous first-in-first-out memory is correct. In this way, the minimum delay configuration is determined by training, and the delay operation on the read clock timing of the second asynchronous first-in-first-out memory can be completed by any suitable implementation, for example, an adjustable delay unit is deployed on the first read control terminal of the first asynchronous first-in-first-out memory for receiving the read clock of the first asynchronous first-in-first-out memory, that is, the read control signal of the first asynchronous first-in-first-out memory, the read time of the data enable signal is adjusted by delaying the read pointer of the first asynchronous first-in-first-out memory, thereby completing the delay operation on the read clock timing of the second asynchronous first-in-first-out memory. Here, the current delay value of the adjustable delay unit is gradually increased from the minimum delay value of the adjustable delay unit, and the read clock of the first asynchronous first-in-first-out memory received by the first asynchronous first-in-first-out memory through the first read control terminal is delayed according to the current delay value of the adjustable delay unit, thereby adjusting the synchronous data enable signal output by the first asynchronous first-in-first-out memory, adjusting the gated second clock signal so as to adjust the output of the second asynchronous first-in-first-out memory until the output of the second asynchronous first-in-first-out memory is correct, in this way, the minimum delay configuration is determined by training, the cross-clock-domain conversion and processing are realized, and the data path delay is effectively reduced. It should be understood that the circuit design of the present application can also have no adjustable delay unit, but the one-beat second clock is gated through a configuration signal, so that the read pointer of the first asynchronous first-in-first-out memory generated by the second clock is pushed back by one beat.

[0053] In a possible implementation, the test data is N times M bits, where M is a data bit width of one clock cycle of the second clock signal, and N is a ratio of a data bit width of one clock cycle of the first clock signal divided by the data bit width of one clock cycle of the second clock signal, N is a positive integer greater than or equal to 1, and the comparing the test data and the synchronous post-data signal output by the second asynchronous first-in-first-out memory comprises: comparing the lowest M bits of the test data and the M bits read by the second asynchronous first-in-first-out memory under the action of one clock cycle of the gated post-second clock signal. In some embodiments, the first clock domain is a write clock domain, and the second clock domain is a read clock domain, in which case N represents a write-to-read bit width ratio, that is, a ratio of a write-side bit width to a read-side bit width. By comparing the test data and the synchronous post-data signal output by the second asynchronous first-in-first-out memory, a low-delay training scheme is realized. In the training mode, the first data signal transmits test data, and by comparing the synchronous post-data signal output by the second asynchronous first-in-first-out memory with the test data, it can be determined whether the test data is completely read by the second asynchronous first-in-first-out memory. The first data enable signal is used for gating logic to generate a read-write clock of one clock cycle of the second asynchronous first-in-first-out memory. According to the frequency of the second clock signal, the corresponding duration of one clock cycle of data is determined, that is, a write cycle of the second asynchronous first-in-first-out memory, so that the data enable signal is kept at the level of opening gating during the valid period corresponding to one clock cycle of the second clock signal. The test data has a specific data format, and the test data is N times M bits, where N is a write-to-read bit width ratio, that is, a ratio of a write-side bit width of the write clock (the first clock signal) to a read-side bit width of the read clock (the second clock signal), and M is a read bit width of one clock cycle, that is, a data bit width of one clock cycle of the second clock signal. The test data is written in N times M bits under the action of one clock cycle of the write clock, that is, one clock cycle of the first clock signal, so the writing of the test data is one clock cycle of writing N times M bits. In contrast, the complete reading of the test data is completed in N clock cycles, and M bits are read in each clock cycle. For example, the frequency of the first clock signal can be set to 1 gigahertz (GHz), and the data bit width of one clock cycle of the first clock signal can be set to 6 bits, which means that 6 bits of test data are written under the action of one clock cycle of the write clock, that is, one clock cycle of the first clock signal; in contrast, the frequency of the second clock signal can be 1.5 GHz, and 2 bits of data are read under the action of one clock cycle of the read clock, that is, one clock cycle of the second clock signal, which requires 3 clock cycles to read the complete test data, or the frequency of the second clock signal can be 2 GHz, and 3 bits of data are read under the action of one clock cycle of the read clock, that is, one clock cycle of the second clock signal, which requires 2 clock cycles to read the complete test data.It can be seen that, for the frequency of the first clock signal (such as 1GHz) and the data bit width of one beat of the first clock signal (such as 6 bits), the write data bit width under one write clock is equal to an integer multiple of the read data bit width under one read clock, and each write is one beat, and the read needs N beats, N is the integer multiple. For example, N is 3, the read needs 3 beats, and each beat reads 2 bits, or for example, N is 2, the read needs 2 beats, and each beat reads 3 bits. In this way, through the test data configuration and the data enable signal configuration, a low-delay training scheme is realized, and the effective write data can be set to the lowest M bits of the test data, which corresponds to the information that can be obtained by one beat of reading, that is, the effective test data is actually the lowest M bits that can be obtained by one beat of the read clock, that is, the second clock signal. This means that only one clock cycle is needed to complete the training and debugging, and the data bit width read by one cycle of the read clock signal, that is, the data bit width of one beat of the second clock signal, can also be combined with the configuration of the data enable signal (for example, when the output of the second asynchronous first-in-first-out memory is incorrect, a data enable signal with a length of a single cycle of the first clock signal is generated as the first data enable signal, which is used to enable the read and write clock of the second asynchronous first-in-first-out memory for one beat), and the read enable signal is adjusted according to the minimum adjustment degree. By using the effective lowest M bits of the write test data, the lowest M bits can be set to all 1, so that when the read data is all 1, it means that the training is complete, and if the read data contains 0, it means that the training is not complete. In this way, the read data is compared with the target data configuration, and when the comparison fails, the delay is adjusted until the comparison is passed to obtain the minimum delay configuration. The read clock delay adjustment can be performed in any suitable manner, for example, the gate enable is configured to erase the edge of the read clock of the first asynchronous first-in-first-out memory, the data enable read time is gradually delayed by delaying the read pointer, the read time delay operation of the second asynchronous first-in-first-out memory is completed, and the observation is performed after the data read and write are initiated again after adjustment.

[0054] In some embodiments, the lowest M bits of the test data are set to all 1s and the rest of the bits are set to all 0s, and when the M bits read by the second asynchronous first-in-first-out memory under the second clock signal after the gating is all 1s, it is determined that the output of the second asynchronous first-in-first-out memory is correct. In this way, the read enable signal is adjusted each time, so as to change the read address, and each adjustment is the minimum change amount for the read address. Through the test data configuration and the data enable signal configuration, a low-delay training scheme is realized, and the effective test data is actually the lowest M bits that can be obtained by the second clock signal. This means that only one clock cycle is needed to complete the training and debugging, and by setting the lowest M bits of the test data to all 1s and the rest of the bits to all 0s, when the M bits read by the second asynchronous first-in-first-out memory under the second clock signal after the gating are all 1s, it means that the training is completed, and the minimum delay configuration is realized through the training.

[0055] In some embodiments, the frequency of the second clock signal is N integer times of the frequency of the first clock signal, and the data bit width under the first clock signal is equal to N integer times of the data bit width under the second clock signal. In some embodiments, the first clock domain is a write clock domain, and the second clock domain is a read clock domain, and the frequency of the second clock signal is higher than the frequency of the first clock signal, which means that the frequency of the write clock domain is relatively low, and the frequency of the read clock domain is relatively high, and the write data bit width under the write clock is equal to an integer multiple of the read data bit width under the read clock. In combination with the above-mentioned test data configuration, among the N times M bits of the test data, the lowest M bits can be set to all 1s, and the remaining (N-1) times M bits (high bits relative to the lowest M bits) are set to all 0s. If the training is completed, the second asynchronous first-in-first-out memory should read out the M all-1 output results completely, so as to match the setting of the lowest M bits of the test data being all 1s. If the training is not completed, it means that there is at least one 0 in the output results of the second asynchronous first-in-first-out memory, that is, the number of 1s is less than M. In this way, a low-delay training scheme is realized, and the delay of the data path is reduced.

[0056] In some examples, the data transmission rate associated with the second clock signal is equal to the data transmission rate associated with the first clock signal. In this way, the adaptation of the data transmission rate is realized, which is beneficial to improve the overall system efficiency.

[0057] In one possible implementation, the first clock domain is a write clock domain, the first clock signal is a write clock signal, the second clock domain is a read clock domain, the second clock signal is a read clock signal, and a frequency of the read clock signal is higher than a frequency of the write clock signal. In this way, the conversion and processing across clock domains are implemented, and the data path delay is effectively reduced.

[0058] In some embodiments, a write data bit width in one cycle of the write clock signal is equal to an integer multiple of a read data bit width in one cycle of the read clock signal, and a read data transfer rate associated with the read clock signal is equal to a write data transfer rate associated with the write clock signal. In this way, the write data bit width in one cycle of the write clock is equal to an integer multiple of the read data bit width in one cycle of the read clock. In combination with the configuration of the test data described above, among the N times M bits of the test data, the lowest M bits can be set to all 1s, and the remaining (N-1) times M bits (high bits relative to the lowest M bits) can be set to all 0s. If the training is completed, the second asynchronous first-in-first-out memory should completely read out the M all-1 output results, which can match the setting of the lowest M bits of the test data being all 1s. If the training is not completed, it means that there is at least one 0 in the output results of the second asynchronous first-in-first-out memory, i.e., the number of 1s is less than M. With the adaptation of the data transfer rate, the overall system efficiency is improved. Moreover, the read and write data transfer rates should be matched, which means cross-asynchronous processing at the same rate. Generally, if the rates are different, it is difficult to process long-time data transmission because the data storage depth required by the second asynchronous first-in-first-out memory cannot be expected. When working at the same data transfer rate, generally only a small storage depth of the second asynchronous first-in-first-out memory is needed, which can reduce the use of resources. Therefore, it is necessary to ensure that the write bit width is an integer multiple of the read bit width, and the read clock frequency is an integer multiple of the write clock frequency.

[0059] In some embodiments, the second asynchronous first-in-first-out memory is any of a plurality of asynchronous first-in-first-out memories associated with the write clock domain and the read clock domain, the plurality of asynchronous first-in-first-out memories all using the read clock signal and adopting the same read data bit width, and the synchronized post-data enable signal is applicable to each of the plurality of asynchronous first-in-first-out memories. If there is a simultaneous need for multiple cross-clock-domain conversion and processing, for example, there are multiple groups of chips or modules in the read clock domain that need to be synchronously processed, and for example, there are multiple data channels in the receiving end that need to be cross-clock-domain interacted, a chip or module under one of the read clock domains can be selected as a representative, and the adaptation between the write clock domain and the read clock domain is achieved through one training, and the minimum delay configuration obtained through the training can be applied to other chips or modules under the same read clock domain. The read enable signal adjusted through the training can be used for the read control of any number of second asynchronous first-in-first-out memories; thus, the conversion of the data enable signal and the data signal from the write clock domain to the read clock domain is achieved, which is conducive to the parallelization of data transmission. It should be understood that the second asynchronous first-in-first-out memory should be any of a plurality of asynchronous first-in-first-out memories of the same read-write clock domain, and the synchronized enable signal can be used for the plurality of asynchronous first-in-first-out memories, but the read-write clock domains of the plurality of asynchronous first-in-first-out memories are the same. By using the above training process, the asynchronous relationship between the pair of first and second clock domains is compensated for, and thus the training result of a pair of asynchronous clock asynchronous first-in-first-out memories can be extended to a plurality of asynchronous first-in-first-out memories of all read-write clock domains.

[0060] In some examples, the synchronization method further includes: copying the first asynchronous first-in-first-out memory for the plurality of asynchronous first-in-first-out memories respectively, thereby constructing a plurality of data channels corresponding one-to-one to the plurality of asynchronous first-in-first-out memories, wherein the plurality of data channels are traffic-isolated. In this way, by providing a plurality of second asynchronous first-in-first-out memories, a corresponding cross-clock-domain synchronization processing can be provided for a plurality of data channels, a plurality of data transmission lines, and a plurality of receiving ends, and by copying the first asynchronous first-in-first-out memory, a plurality of data transmission paths that are traffic-isolated from each other can be conveniently established; and in the case of a plurality of second asynchronous first-in-first-out memories and a corresponding plurality of data transmission paths, the training phase is for the delay adjustment of the read clock relative to the write clock on the first asynchronous first-in-first-out memory and the minimum delay configuration obtained through the training, and thus the training phase is common, and one training can meet the cross-clock-domain synchronization needs of the plurality of data transmission paths respectively. In this way, a corresponding cross-clock-domain synchronization processing can be provided for any number of data channels, and the training process is simplified and the training time is reduced, which is conducive to improving the overall system efficiency.

[0061] In some embodiments, the second clock domain belongs to any of a plurality of read clock domains, and the synchronization method further comprises: establishing a plurality of data channels in the plurality of read clock domains independently from each other by training the combination of the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory. As mentioned above, the training result of a pair of read-write clock domains, a single second asynchronous first-in-first-out memory can be extended to a plurality of asynchronous first-in-first-out memories. And each asynchronous first-in-first-out memory can copy a first asynchronous first-in-first-out memory for respective channel training. Here, for a first clock write clock domain and a plurality of second clock read clock domains, each pair of read-write clock relationship can be trained by a pair of first and second asynchronous first-in-first-out memory combinations to establish completely independent data channels of a plurality of read clock domains.

[0062] Figure 3 A schematic diagram of a cross-clock domain synchronization device provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the cross-clock domain synchronization device comprises a first clock domain 100 and a second clock domain 200. The first clock domain 100 comprises a first clock 101, a first write clock 102, a first asynchronous first-in-first-out memory 103, a first read clock 104, and a first read clock generator 105. The second clock domain 200 comprises a second clock 201, a second write clock 202, a second asynchronous first-in-first-out memory 203, a second read clock 204, and a second read clock generator 205. Figure 3As shown, the synchronization device comprises a first asynchronous first-in-first-out memory (asynchronous first-in-first-out memory C 310) and a second asynchronous first-in-first-out memory (asynchronous first-in-first-out memory D 330). The first asynchronous first-in-first-out memory (asynchronous first-in-first-out memory C 310) comprises a first data terminal (data terminal C 314), a first write control terminal (write control terminal C 312), and a first read control terminal (read control terminal C 316). The first data terminal (data terminal C 314) is connected to a first data enable signal (data enable signal C 307) in a first clock domain, the first write control terminal (write control terminal C 312) is connected to a first clock signal (clock signal C 303) in the first clock domain, the first read control terminal (read control terminal C 316) is connected to a second clock signal (clock signal D 323) in a second clock domain, and the first asynchronous first-in-first-out memory (asynchronous first-in-first-out memory C 310) is configured to output a synchronized data enable signal (synchronized data enable signal D 327 output by output terminal C 318) in the second clock domain. The first data enable signal (data enable signal C 307) is configured to gate the first clock signal (clock signal C 303) to obtain a gated first clock signal (gated clock signal C 350 obtained by gating logic A 340), and the synchronized data enable signal (synchronized data enable signal D 327 output by output terminal C 318) is configured to gate the second clock signal (clock signal D 323) to obtain a gated second clock signal (gated clock signal D 352 obtained by gating logic B 342). The second asynchronous first-in-first-out memory (asynchronous first-in-first-out memory D 330) comprises a second data terminal (data terminal D 334), a second write control terminal (write control terminal D 332), and a second read control terminal (read control terminal D 336). The second data terminal (data terminal D 334) is connected to a first data signal (data signal C 305) in the first clock domain, the second write control terminal (write control terminal D 332) is connected to the gated first clock signal (gated clock signal C 350 obtained by gating logic A 340), and the second read control terminal (read control terminal D 336) is connected to the gated second clock signal (gated clock signal D 352 obtained by gating logic B 342). The second asynchronous first-in-first-out memory (asynchronous first-in-first-out memory D 330) is configured to output a synchronized data signal (synchronized data signal D 325 output by output terminal D 338) in the second clock domain.

[0063] In summary, Figure 3The synchronization device across clock domains shown utilizes an optimized circuit connection relationship, utilizes a first asynchronous first-in-first-out memory to output a synchronized data enable signal in a second clock domain, and on the basis of the first asynchronous first-in-first-out memory outputting the synchronized data enable signal, generates a gated first clock signal and a gated second clock signal through gate logic, and then utilizes a second asynchronous first-in-first-out memory to output a synchronized data signal in the second clock domain. In this way, the compensation problem of a frequency difference and a phase difference that may exist between the first clock domain and the second clock domain is converted into the problem of determining the minimum delay configuration of the delay operation of the read clock timing of the second asynchronous first-in-first-out memory through training. For an asynchronous application scenario, the position of the read clock of the first asynchronous first-in-first-out memory relative to the write clock is adjusted, so as to adjust the readout time of the data enable signal of the first asynchronous first-in-first-out memory, and then the delay operation of the read clock timing of the second asynchronous first-in-first-out memory is performed, so as to ensure that the second asynchronous first-in-first-out memory provides complete and correct read data functions. Through training to determine the minimum delay configuration, on the basis of compensating for the frequency difference and the phase difference that may exist between the first clock signal and the second clock signal, the conversion and processing across clock domains are realized, the data path delay is effectively reduced, not only a low-power, high-integration, low-latency synchronization solution is provided, but also flexible and timely adaptation to different clock domain requirements for conversion and processing across clock domains is realized.

[0064] Referring to Figure 4 In a possible implementation, when the output of the second asynchronous first-in-first-out memory is incorrect, the synchronization device is configured to: delay adjust the read-write clock timing of the first asynchronous first-in-first-out memory, so as to determine the minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory, and the minimum delay configuration is configured to ensure that the output of the second asynchronous first-in-first-out memory is correct. In this way, by measuring the output of the second asynchronous first-in-first-out memory, it can be judged whether the output of the second asynchronous first-in-first-out memory is correct. When the output of the second asynchronous first-in-first-out memory is incorrect, the read-write clock timing of the first asynchronous first-in-first-out memory is delay adjusted. In this way, by successively adjusting the position of the read clock relative to the write clock in the first asynchronous first-in-first-out memory, the readout time of the data enable signal of the first asynchronous first-in-first-out memory is adjusted, and then the delay operation of the read clock timing of the second asynchronous first-in-first-out memory is performed. Finally, the minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory determined not only ensures that the output of the second asynchronous first-in-first-out memory is correct, but also effectively reduces the data path delay.

[0065] In a possible implementation, the first clock domain is a write clock domain, the first clock signal is a write clock signal, the second clock domain is a read clock domain, the second clock signal is a read clock signal, and the frequency of the read clock signal is higher than the frequency of the write clock signal. In this way, the conversion and processing across clock domains are realized, and the data path delay is effectively reduced.

[0066] In some embodiments, the second asynchronous first-in-first-out memory is any of a plurality of asynchronous first-in-first-out memories associated with the write clock domain and the read clock domain, each of the plurality of asynchronous first-in-first-out memories using the read clock signal and adopting the same read data bit width, and the synchronous post-data enable signal is applicable to each of the plurality of asynchronous first-in-first-out memories. In this way, the conversion of the data enable signal and the data signal from the write clock domain to the read clock domain is realized, and parallelization of data transmission is facilitated.

[0067] Figure 4 A flowchart of a delay training method provided by an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the delay training method includes the following steps. Figure 4

[0068] Step S401: Start training.

[0069] Step S403: The firmware configures the training enable signal to be high, initiates training, and configures the low M bits of the N times M bits of training data to be valid.

[0070] Step S405: The firmware triggers the pre-logic reset, the read-write clock of the always-on FIFO1, and configures the initial clock gating number, adjusts the FIFO1 read-write clock timing by gating the CLK2.

[0071] Step S407: The firmware triggers the FIFO2 reset, resets the read-write pointers and buffered data in the FIFO2.

[0072] Step S409: The firmware configures the training trigger signal to be high and then low, and the logic generates a data enable signal for starting the FIFO2 read-write clock.

[0073] Step S411: The firmware observes the FIFO2 read value and compares it with the low M bits of the test data.

[0074] Step S413: Whether the value is correct. If not, step S415 is performed, and if yes, step S417 is performed.

[0075] Step S415: The firmware configures the pre-logic gate enable signal to be high and then low, which is used to gate the CLK2 of the FIFO1 and delay the data readout of the FIFO1. ​

[0076] Step S417: The firmware triggers the FIFO2 to reset, resetting the read-write pointer in the FIFO2 and the buffered data.

[0077] Step S419: The firmware configures the training enable signal to be low.

[0078] Step S420: End the training.

[0079] Figure 5 The illustrated delay training method implements a low-delay training scheme, which only needs one clock cycle to complete the training and debugging, and the data bit width read by using one cycle of the read clock signal is the data bit width of one beat of the second clock signal. In addition, the configuration of the data enable signal (when the output of the second asynchronous first-in-first-out memory is incorrect, a data enable signal with a length of a single cycle of the first clock signal is generated as the first data enable signal, which is used to start the read-write clock of the second asynchronous first-in-first-out memory for one beat) is combined, which realizes the adjustment of the read enable signal according to the minimum adjustment degree, and the effective lowest M bits in the test data written can be set to all 1. In this way, when it is detected that all the read data are 1, it means that the training is completed, and if the read data contain 0, it means that the training is not completed. In this way, the read data is compared with the target data configuration, and when the comparison fails, the delay is adjusted until the minimum delay configuration is obtained after the comparison passes. The read clock delay adjustment can be performed in any suitable manner, for example, the gate enable is configured to perform the read clock edge elimination of the first asynchronous first-in-first-out memory, the data enable read time is gradually delayed by delaying the read pointer, the read time delay operation of the second asynchronous first-in-first-out memory is completed, and the observation is performed after the data read-write is initiated again after the adjustment. In this way, the minimum delay configuration is determined through the training, the cross-clock-domain conversion and processing are realized, and the data path delay is effectively reduced.

[0080] Figure 5is a structural schematic diagram of a computing device provided in an embodiment of the present application. The computing device 500 includes one or more processors 510, a communication interface 520, and a memory 530. The processor 510, the communication interface 520, and the memory 530 are connected to each other through a bus 540. Optionally, the computing device 500 can further include an input / output interface 550 connected with an input / output device for receiving a parameter set by a user and the like. The computing device 500 can be used to implement part or all of the functions of the device embodiments or the system embodiments in the above-described embodiments of the present application; the processor 510 can also be used to implement part or all of the operation steps of the method embodiments in the above-described embodiments of the present application. For example, the specific implementation of the computing device 500 performing various operations can refer to the specific details in the above-described embodiments, for example, the processor 510 is used to perform part or all of the steps in the above-described method embodiments or part or all of the operations in the above-described method embodiments. For another example, in the embodiments of the present application, the computing device 500 can be used to implement part or all of the functions of one or more components in the above-described device embodiments, in addition, the communication interface 520 can be specifically used for communication functions necessary for implementing the functions of these devices, components, and the like, and the processor 510 can be specifically used for processing functions necessary for implementing the functions of these devices, components, and the like.

[0081] It should be understood that, Figure 5 The computing device 500 can include one or more processors 510, and the plurality of processors 510 can cooperatively provide processing capability in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the plurality of processors 510 can constitute a processor sequence or a processor array, or the plurality of processors 510 can be divided into a main processor and an auxiliary processor, or the plurality of processors 510 can have different architectures such as using a heterogeneous computing architecture. In addition, Figure 5 The computing device 500 shown, the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 500 can include more or fewer components than those shown, or combine certain components, or split certain components, or have a different arrangement of components. Figure 5

[0082] ​The processor 510 can have various specific implementations. For example, the processor 510 can include one or more combinations of a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU), a data processing unit (DPU), or the like, and embodiments of the present application are not limited in this regard. The processor 510 can also be a single core processor or a multiple core processor. The processor 510 can be a combination of a CPU and a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 510 can also be implemented by a logic device with built-in processing logic, such as an FPGA or a digital signal processor (DSP), etc. The communication interface 520 can be a wired interface or a wireless interface, used for communication with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless local area network interface, etc.

[0083] The memory 530 can be a non-volatile memory, for example, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The memory 530 can also be a volatile memory, which can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, for example, a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synchlink DRAM (SLDRAM), and a direct rambus RAM (DR RAM). The memory 530 can also be used for storing programs codes and data to be used in the processor 510 to invoke the program codes stored in the memory 530 to execute the partial or all of the steps of the above method embodiments, or to execute the corresponding functions of the above device embodiments. Further, the computing device 500 can include more or less components, or have different configurations of components than those shown, depending upon the needs of the user. Figure 5 More or less components can be used or different configurations of components can be used.

[0084] The bus 540 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 540 can be divided into an address bus, a data bus, a control bus, etc. In addition to including a data bus, the bus 540 can also include a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity,Figure 1 Only one bus or bus type is used in the figure, but it is understood that the computer system 100 can use more buses or bus types.

[0085] The method and device provided by the embodiments of the present application are based on the same inventive concept, and the embodiments, implementation manners, examples or implementation modes of the method and device are similar in principle for solving problems, and thus the embodiments, implementation manners, examples or implementation modes of the method and device can be referred to each other, and the repeated parts will not be described herein. The embodiments of the present application further provide a system, which includes a plurality of computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0086] The embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0087] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. The present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both software and hardware aspects. Embodiments of the present application can be implemented in software, hardware, firmware or any combination thereof. Embodiments of the present application can be implemented as computer program products that comprise computer executable code, which when loaded and executed by a computer, cause the computer to carry out the steps of the processes described in the embodiments of the present application. The present application can take the form of a computer program product which can be embodied in one or more computer-usable storage media including a computer- readable storage medium having computer-usable program code embodied thereon. The computer-usable program code can be downloaded from a website, computer, server or data center through wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means to another website, computer, server or data center. The computer-usable storage media can be any available media that can be accessed by a computer and includes both a removable memory and a non-removable memory. The computer-usable storage media can be a magnetic medium, e.g., a floppy disk, a hard disk drive, a magnetic tape, an optical medium, or a semiconductor medium. The semiconductor medium can be a solid state disk, a random access memory, a flash memory, a read only memory, a programmable read only memory, an electrically programmable read only memory, a register, or any other suitable storage medium.

[0088] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application. Each block in the flowcharts and / or block diagrams and combinations of blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, an embedded processor or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowcharts and / or block diagrams block or blocks. Figure 1 The flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application can be described in the general context of computer-executable instructions, such as program modules, being executed by a computer in processing applications. Generally, program modules can include routines, programs, objects, components, data structures, program logic, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of the program code means for executing steps of the methods disclosed herein. Figure 1 The flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application can be described in the general context of computer-executable instructions, such as program modules, being executed by a computer in processing applications. Generally, program modules can include routines, programs, objects, components, data structures, program logic, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of the program code means for executing steps of the methods disclosed herein. Figure 1one or more processes and / or functions specified in the flow block or blocks Figure 1 one or more processes and / or functions specified in the flow block or blocks Figure 1 one or more processes and / or functions specified in the flow block or blocks ​ one or more processes and / or functions specified in the flow block or blocks

[0089] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiments of the present application can be adjusted, combined or deleted in sequence according to actual needs; the modules in the system of the embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.

Claims

1. A method of synchronization across clock domains, the method comprising: The synchronization method comprises: outputting a synchronized post-data enable signal in a second clock domain through a first asynchronous first-in-first-out memory, wherein the first asynchronous first-in-first-out memory comprises a first data terminal, a first write control terminal and a first read control terminal, the first data terminal is connected to a first data enable signal in a first clock domain, the first write control terminal is connected to a first clock signal in the first clock domain, the first read control terminal is connected to a second clock signal in the second clock domain, the first data enable signal is used to gate the first clock signal to obtain a gated post-first clock signal, and the synchronized post-data enable signal is used to gate the second clock signal to obtain a gated post-second clock signal; outputting a synchronized post-data signal in the second clock domain through a second asynchronous first-in-first-out memory, wherein the second asynchronous first-in-first-out memory comprises a second data terminal, a second write control terminal and a second read control terminal, the second data terminal is connected to a first data signal in the first clock domain, the second write control terminal is connected to the gated post-first clock signal, and the second read control terminal is connected to the gated post-second clock signal. The first clock domain is a write clock domain, the first clock signal is a write clock signal, the second clock domain is a read clock domain, and the second clock signal is a read clock signal.

2. The synchronization method of claim 1, wherein, The synchronization method further comprises: delaying and adjusting read and write clock timing of the first asynchronous first-in-first-out memory when the output of the second asynchronous first-in-first-out memory is incorrect, so as to determine a minimum delay configuration of the read and write clock timing of the first asynchronous first-in-first-out memory, and the minimum delay configuration is used to ensure that the output of the second asynchronous first-in-first-out memory is correct.

3. The synchronization method of claim 2, wherein, The synchronization method further comprises: generating a data enable signal with a length of a single period of the first clock signal as the first data enable signal when the output of the second asynchronous first-in-first-out memory is incorrect, so as to open the read and write clock of the second asynchronous first-in-first-out memory for one beat.

4. The synchronization method of claim 1, wherein, The synchronization method further comprises: using test data as the first data signal, and comparing the test data and the synchronized post-data signal output by the second asynchronous first-in-first-out memory, so as to determine whether the output of the second asynchronous first-in-first-out memory is correct.

5. The synchronization method of claim 4, wherein, When the output of the second asynchronous first-in-first-out memory is incorrect, delaying the position of the read clock of the first asynchronous first-in-first-out memory relative to the write clock of the first asynchronous first-in-first-out memory, so as to adjust the readout time of the first asynchronous first-in-first-out memory for the first data enable signal, and configuring the training process of the first data enable signal for one beat of the first clock signal again until the output of the second asynchronous first-in-first-out memory is correct.

6. The synchronization method of claim 4, wherein, When the output of the second asynchronous first-in-first-out memory is incorrect, a current delay value of an adjustable delay unit on the first read control terminal is gradually increased from a minimum delay value of the adjustable delay unit, and a read clock of the first asynchronous first-in-first-out memory received by the first read control terminal is delayed according to the current delay value of the adjustable delay unit, so as to adjust the synchronous data enable signal output by the first asynchronous first-in-first-out memory, thereby adjusting the gated second clock signal so as to adjust the output of the second asynchronous first-in-first-out memory, until the output of the second asynchronous first-in-first-out memory is correct.

7. The synchronization method of claim 4, wherein, The test data is N times M bits, where M is a data bit width of one cycle of the second clock signal, N is a ratio of a data bit width of one cycle of the first clock signal divided by the data bit width of one cycle of the second clock signal, and N is a positive integer greater than or equal to 1. Comparing the test data and the synchronous data signal output by the second asynchronous first-in-first-out memory includes comparing the lowest M bits of the test data and the M bits read by the second asynchronous first-in-first-out memory under the action of the gated second clock signal.

8. The synchronization method of claim 7, wherein, The lowest M bits of the test data are all 1 and the other bits are all 0, and when the M bits read by the second asynchronous first-in-first-out memory under the action of the gated second clock signal are all 1, it is determined that the output of the second asynchronous first-in-first-out memory is correct.

9. The synchronization method of claim 7, wherein, The frequency of the second clock signal is N integer times of the frequency of the first clock signal, and the data bit width of one cycle of the first clock signal is equal to N integer times of the data bit width of one cycle of the second clock signal.

10. The synchronization method of claim 9, wherein, The data transmission rate associated with the second clock signal is equal to the data transmission rate associated with the first clock signal.

11. The synchronization method of claim 1, wherein, The frequency of the read clock signal is higher than the frequency of the write clock signal.

12. The synchronization method of claim 11, wherein, The write data bit width under one cycle of the write clock signal is equal to an integer multiple of the read data bit width under one cycle of the read clock signal, and the read data transmission rate associated with the read clock signal is equal to the write data transmission rate associated with the write clock signal.

13. The synchronization method of claim 11, wherein, The second asynchronous first-in-first-out memory is any one of a plurality of asynchronous first-in-first-out memories associated with the write clock domain and the read clock domain, the plurality of asynchronous first-in-first-out memories all use the read clock signal and adopt the same read data bit width, and the synchronous data enable signal is applicable to each of the plurality of asynchronous first-in-first-out memories.

14. The synchronization method of claim 13, wherein, The synchronization method further includes: The first asynchronous first-in-first-out memory is replicated for the plurality of asynchronous first-in-first-out memories respectively, so as to construct a plurality of data channels corresponding to the plurality of asynchronous first-in-first-out memories one by one, and the plurality of data channels are traffic-isolated.

15. The synchronization method of claim 11, wherein, The second clock domain belongs to any one of a plurality of read clock domains, and the synchronization method further includes: A plurality of data lanes in the plurality of read clock domains are established independently from each other by training a combination of the first asynchronous first-in-first-out memory and the second asynchronous first-in-first-out memory.

16. A computer device, comprising: The computer device comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the method according to any one of claims 1 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and when the computer instructions are executed on a computer device, the computer device executes the method according to any one of claims 1 to 15.

18. A synchronization apparatus across clock domains, the apparatus comprising: The synchronization device comprises: The first asynchronous first-in-first-out memory, wherein the first asynchronous first-in-first-out memory comprises a first data end, a first write control end, and a first read control end, the first data end is connected to a first data enable signal of a first clock domain, the first write control end is connected to a first clock signal of the first clock domain, and the first read control end is connected to a second clock signal of a second clock domain, the first asynchronous first-in-first-out memory is used to output a synchronized data enable signal in the second clock domain, the first data enable signal is used to gate the first clock signal to obtain a gated first clock signal, and the synchronized data enable signal is used to gate the second clock signal to obtain a gated second clock signal; The second asynchronous first-in-first-out memory, wherein the second asynchronous first-in-first-out memory comprises a second data end, a second write control end, and a second read control end, the second data end is connected to a first data signal of the first clock domain, the second write control end is connected to the gated first clock signal, and the second read control end is connected to the gated second clock signal, and the second asynchronous first-in-first-out memory is used to output a synchronized data signal in the second clock domain, The first clock domain is a write clock domain, the first clock signal is a write clock signal, the second clock domain is a read clock domain, and the second clock signal is a read clock signal.

19. The synchronization apparatus of claim 18, wherein, When the output of the second asynchronous first-in-first-out memory is incorrect, the synchronization device is used to adjust the read-write clock timing of the first asynchronous first-in-first-out memory, thereby determining a minimum delay configuration of the read-write clock timing of the first asynchronous first-in-first-out memory, and the minimum delay configuration is used to ensure that the output of the second asynchronous first-in-first-out memory is correct.

20. The synchronization apparatus of claim 18, wherein, The frequency of the read clock signal is higher than the frequency of the write clock signal.

21. The synchronization apparatus of claim 20, wherein, The second asynchronous first-in-first-out memory is any one of a plurality of asynchronous first-in-first-out memories associated with the write clock domain and the read clock domain, the plurality of asynchronous first-in-first-out memories all use the read clock signal and adopt the same read data bit width, and the synchronized data enable signal is applicable to each of the plurality of asynchronous first-in-first-out memories.

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