Wafer processing structure and wafer processing method

Abstract

The invention discloses a wafer processing structure and a wafer processing method, and the wafer processing method comprises the steps: firstly forming an annular groove in an edge region of a wafer, then removing a part of wafer material at the bottom of the annular groove to form a stress release groove, and finally carrying out the half-cutting processing of the wafer in a device region to form a scribing groove. The stress release groove serves as a preset stress weak point, and in the subsequent process of forming the scribing groove through half-cutting treatment, mechanical impact and local stress generated by a cutting tool can be actively guided to the stress release groove and released at the stress release groove. Therefore, disordered accumulation and expansion of stress generated in the half-cutting treatment process at the edge of the scribing groove are inhibited, gaps or subfissures are not easy to form at the edge of the wafer, the edge structure integrity of the half-cut wafer is improved, the overall mechanical strength of the wafer is enhanced, and the service life of the wafer is prolonged. And the yield and the reliability of the wafer in the subsequent processing, conveying and packaging processes can be improved.

Description

Technical Field

[0001] The invention relates to the semiconductor field, and more particularly to wafer processing structures and wafer processing methods. Background Technology

[0002] In the field of semiconductor technology, as the integration and performance requirements of integrated circuits continue to increase, advanced packaging technology plays an increasingly crucial role in the chip manufacturing process.

[0003] To achieve high-density interconnects and enhance chip reliability, the industry generally adopts a strategy of completing some packaging processes at the wafer stage. Among these processes, dicing the wafer to form individual chip units and effectively encapsulating and protecting the chips are fundamental steps to ensure the yield and performance of the final product.

[0004] To achieve the above objectives, one specific technical approach is to first employ a half-cutting process, pre-dividing the wafer surface along predetermined dicing lines without completely cutting through the wafer. Subsequently, the chip, which has formed the prototype of an independent unit, is packaged using a filling and encapsulation material. This aims to simultaneously achieve comprehensive coverage and protection of the chip's front functional area and the sidewalls exposed after the half-cutting. However, this process still has many shortcomings. Summary of the Invention

[0005] This invention provides a wafer processing structure and a wafer processing method to improve the edge structure integrity of a halved wafer and enhance the overall mechanical strength of the wafer.

[0006] To address the aforementioned problems, the present invention provides a wafer processing method, comprising: providing a wafer including a device region and an edge region surrounding the device region; performing an edge trimming process within the edge region of the wafer to form an annular groove; removing a portion of the wafer material at the bottom of the annular groove to form a stress relief groove for releasing stress at the wafer edge; and after forming the stress relief groove, performing a half-cutting process on the wafer in the device region to form a dicing groove.

[0007] Optionally, the wafer processing method further includes: after forming the annular groove and before performing the half-cutting process, at least the sidewall of the annular groove near the device region is ion implanted and annealed to form a reinforcing layer that is harder or more resilient than the wafer material.

[0008] Optionally, the ion implantation step includes: forming a third mask layer on the wafer, the third mask layer covering the device region and exposing the sidewall of the annular groove near the device region; and using the third mask layer as a mask to perform ion implantation on the sidewall of the annular groove near the device region.

[0009] Optionally, in the step of ion implantation at least on the sidewall of the annular groove near the device region, the implanted ions include implanted carbon ions and / or nitrogen ions.

[0010] Optionally, in the step of forming the stress relief groove, the radial dimension of the stress relief groove is smaller than the radial dimension of the annular groove.

[0011] Optionally, in the step of forming the annular groove, the annular groove has a first depth; in the step of forming the dicing groove, the dicing groove has a second depth, the second depth being less than the first depth, so as to form a structurally continuous wafer bottom below the dicing groove.

[0012] Optionally, in the step of forming the stress relief groove, a portion of the thickness of the wafer material near the bottom of the sidewall of the annular groove near the device region is removed, so that the stress relief groove is formed at the bottom of the sidewall of the annular groove near the device region.

[0013] Optionally, the step of forming the annular groove includes: forming a first mask layer on the wafer surface, the first mask layer covering the device area and exposing a portion of the edge area; the first mask layer being a mask, etching the wafer material in the exposed portion of the first mask layer to form the annular groove; or, within the edge area of ​​the wafer, removing a portion of the wafer edge material by physical cutting to form the annular groove.

[0014] Optionally, in the step of forming the annular groove, the depth of the annular groove is 200 μm to 400 μm.

[0015] Optionally, in the step of forming the annular groove, the distance from the sidewall of the annular groove near the device region to the device region is greater than or equal to 100 μm.

[0016] Optionally, the step of forming the stress relief groove includes: forming a second mask layer, the second mask layer exposing a portion of the bottom of the annular groove; using the second mask layer as a mask, etching the wafer material at the bottom of the annular groove to form the stress relief groove; the wafer processing method further includes: removing the second mask layer after forming the stress relief groove.

[0017] Optionally, the wafer processing method further includes: after the half-cutting process, forming a coating layer in the dicing groove, the annular groove, and on top of the device area.

[0018] Optionally, the step of forming a coating layer in the dicing groove, the annular groove, and on top of the device area includes: providing a coating material film; applying the coating material film to the front side of the wafer using a lamination process, wherein the coating material film is formed in the dicing groove, the annular groove, and on top of the device area; trimming the coating material film to remove the coating material film formed radially on the outer side of the wafer, thereby forming the coating layer such that the edge of the wafer is coplanar with the edge of the coating layer.

[0019] Optionally, the step of forming a coating layer in the dicing groove, the annular groove, and on top of the device area includes: forming a molding die on the wafer, the molding die covering the device area and contacting the edge area, forming a molding cavity between the wafer and the molding die; and injecting molding compound into the molding cavity to form the coating layer.

[0020] Optionally, in the step of forming a coating layer in the dicing groove, the annular groove, and on top of the device area, the thickness of the coating layer on the annular groove is greater than the thickness of the coating layer on the dicing groove.

[0021] Optionally, in the step of edging within the edge region of the wafer, material of the wafer edge portion thickness is removed to form the annular groove, the annular groove being an annular stepped groove, the bottom surface of the annular groove being connected to the wafer sidewall.

[0022] The present invention also provides a wafer processing structure, comprising: a wafer including a device region and an edge region surrounding the device region; an annular groove located within the edge region of the wafer; a stress relief groove located in a portion of the bottom region of the annular groove and within a portion of wafer material; and a dicing groove located at the top of the device region of the wafer.

[0023] Optionally, the wafer processing structure further includes a reinforcement layer, at least located on the sidewall of the annular groove near the device region, the reinforcement layer being harder or more resilient than the wafer material.

[0024] Optionally, the material of the reinforcing layer includes one or both of silicon carbide and silicon nitride.

[0025] Optionally, the radial dimension of the stress relief groove is smaller than the radial dimension of the annular groove.

[0026] Optionally, the annular groove has a first depth, and the dicing groove has a second depth, the second depth being less than the first depth.

[0027] Optionally, the stress relief groove is located at the bottom of the sidewall of the annular groove near the device area.

[0028] Optionally, the depth of the annular groove is 200 μm to 400 μm.

[0029] Optionally, the distance from the sidewall of the annular groove near the device area to the device area is greater than or equal to 100 μm.

[0030] Optionally, the wafer processing structure further includes: an overlay layer located within the dicing groove and the annular groove and covering the top of the device region.

[0031] Optionally, the thickness of the coating layer on the annular groove is greater than the thickness of the coating layer on the dicing groove.

[0032] Optionally, the annular groove is an annular stepped groove, and the bottom surface of the annular groove is connected to the sidewall of the wafer.

[0033] Optionally, the edge of the wafer is coplanar with the edge of the cladding layer.

[0034] Compared with the prior art, the technical solution of the invention has the following advantages:

[0035] The wafer processing method provided in this invention first forms an annular groove in the edge region of the wafer, then removes a portion of the wafer material at the bottom of the annular groove to form a stress relief groove, and finally performs a half-cutting process on the wafer in the device area to form a dicing groove. By pre-forming a stress relief groove in the annular groove before performing the wafer half-cutting process, the stress relief groove serves as a pre-set stress weak point. During the subsequent half-cutting process to form the dicing groove, the mechanical impact and local stress generated by the cutting tool are actively guided to the stress relief groove and released there. This suppresses the disordered accumulation and expansion of stress generated during the half-cutting process at the edge of the dicing groove, making it less likely for notches or microcracks to form at the wafer edge. This improves the edge structural integrity of the wafer after half-cutting, strengthens the overall mechanical strength of the wafer processing structure, and is beneficial to improving the yield and reliability of the wafer in subsequent processing, transport, and packaging processes.

[0036] Optionally, the wafer processing method further includes: after forming the annular groove and before performing the half-cutting process, performing ion implantation on at least the sidewall of the annular groove near the device region to form a reinforcement layer that is harder or more resilient than the wafer material. By pre-forming a reinforcement layer on at least the sidewall of the annular groove near the device region through ion implantation, the mechanical strength of the sidewall of the annular groove near the device region is improved in terms of the intrinsic properties of the material, thereby effectively resisting the high-frequency impact and local stress brought by the cutting tool during the subsequent half-cutting process. Therefore, this reinforcement layer can suppress the generation and propagation of microcracks during the half-cutting process, making it less likely for notches or microcracks to form at the wafer edge, improving the edge structure integrity of the wafer after half-cutting, strengthening the overall mechanical strength of the wafer, and contributing to improving the yield and reliability of the wafer in subsequent processing, transport, and packaging processes. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1 This is a flowchart of key steps in the wafer processing method of this invention embodiment;

[0039] Figures 2 to 16 This is a schematic diagram of the structure corresponding to the key steps in the wafer processing method of this invention. Detailed Implementation

[0040] As the background technology reveals, existing technologies suffer from yield issues in subsequent packaging stages after wafers undergo a half-cutting process. Specifically, the characteristics of half-cutting leave microscopic gaps and defects at the edges of the dicing channels. These gaps and defects disrupt the integrity of the wafer edge structure, becoming stress concentration points. Therefore, when subsequent lamination is used for encapsulation, the necessary trimming step after lamination induces mechanical stress at these gaps, easily leading to microcracks that propagate along the cracks. If liquid resin encapsulation is used instead, these edge gaps and dicing channels create capillary action, causing the liquid encapsulant to flow unexpectedly and rapidly along the dicing channel at the curing front. This makes it impossible to precisely control the encapsulation range and shape, resulting in incomplete encapsulation, overflow, or adhesion between chip units, leading to packaging failures. In summary, the initial defects introduced by the half-cutting process in existing technologies cause yield problems in various subsequent packaging paths.

[0041] To address the aforementioned technical problems, the wafer processing method provided in this invention first forms an annular groove in the edge region of the wafer. Then, a portion of the wafer material is removed from the bottom of the annular groove to form a stress-relief groove. Finally, the wafer in the device region is half-cut to form a dicing groove. By pre-forming a stress-relief groove within the annular groove before half-cutting, this stress-relief groove serves as a pre-defined stress weak point. During the subsequent half-cutting process to form the dicing groove, the mechanical impact and localized stress generated by the cutting tool are actively guided to the stress-relief groove and released there. This suppresses the disordered accumulation and expansion of stress generated during the half-cutting process at the edge of the dicing groove, making it less likely for notches or microcracks to form at the wafer edge. This improves the edge structural integrity of the wafer after half-cutting, strengthens the overall mechanical strength of the wafer processing structure, and is beneficial for improving the yield and reliability of the wafer in subsequent processing, transport, and packaging processes.

[0042] The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the invention.

[0043] Accordingly, the present invention provides a method for processing wafers. Figure 1 This is a flowchart of key steps in the wafer processing method of this invention embodiment; Figures 2 to 16 This is a schematic diagram of the structure corresponding to the key steps in the first embodiment of the wafer processing method of the present invention.

[0044] Combination Figure 1 ,refer to Figure 2 A wafer 100 is provided, the wafer 100 including a device region I and an edge region II surrounding the device region I.

[0045] Device region I, as the core functional area carrying semiconductor devices, divides wafer 100 into device region I and the surrounding edge region II. This allows all subsequent preprocessing steps used to eliminate edge defects and enhance the mechanical strength of wafer 100 edges, including edge dicing, stress relief trench formation, and ion implantation, to be applied at predetermined locations within edge region II. This also ensures that device region I maintains structural integrity during subsequent half-cutting operations, making sensitive semiconductor devices less susceptible to stress concentration or accidental damage, thus significantly improving the final product yield and reliability of semiconductor wafer 100.

[0046] In some embodiments, during the step of providing wafer 100, multiple phase-spaced chip regions (not shown in the figure) are arranged in a matrix in device region I. In the subsequent packaging process, a half-cut operation is performed along the edge of each chip region in device region I to separate the top phases of adjacent chip units.

[0047] In some embodiments, the chip area is rectangular or square.

[0048] In some embodiments, the chip includes, but is not limited to, a memory chip, an application-specific integrated circuit (ASIC), an analog integrated circuit (Analog IC), a microcontroller unit (MCU), etc.

[0049] Combination Figure 1 ,refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 The top view shows that the edge region II of the wafer 100 is truncated to form an annular groove 101.

[0050] By dicing the edge region II of the wafer 100 to form an annular groove 101, the original microcracks or defects that may exist at the outermost edge of the wafer 100 due to cutting or handling processes are actively removed. This reconstructs the edge of the wafer 100, providing an ideal initial interface for subsequent half-cutting and packaging processes. It avoids stress concentration at the original defect sites, allowing for control of the edge quality of the subsequent half-cutting groove and helping to suppress the generation of microcracks from the source. Therefore, the annular groove 101 not only releases stress and strengthens the edge, but also accommodates subsequent encapsulation materials, allowing for controlled subsequent lamination or molding processes.

[0051] In some embodiments, the annular groove 101 is a 360° annular structure that is continuously closed along the circumferential direction of the wafer 100.

[0052] The 360° continuity of the annular groove 101 ensures that all locations in the edge region II of wafer 100 receive the same treatment, resulting in identical edge structures in all radial directions of wafer 100. This leads to consistent mechanical properties and avoids stress concentration points or weak points in the process caused by local structural discontinuities in wafer 100. Therefore, regardless of the angle or location from which subsequent mechanical stress or coating material acts on the edge of wafer 100, the same protective effect is achieved, strengthening the overall mechanical strength of the wafer and improving the yield and reliability of wafer 100 in subsequent processing, transport, and packaging.

[0053] In some embodiments, the step of forming the annular groove 101 includes: removing material of the edge portion thickness of the wafer 100 by physical cutting within the edge region II of the wafer 100 to form the annular groove 101.

[0054] By using a high-precision cutting tool to cut the edge region II of wafer 100, material in the target area of ​​edge region II can be quickly removed, eliminating multiple steps such as photomask preparation, coating, and removal, thus simplifying the process flow. Therefore, in scenarios where processing accuracy requirements are relatively relaxed or cost-effectiveness needs to be considered, physically cutting the edge region II of wafer 100 is beneficial for reducing overall manufacturing costs and shortening the production cycle.

[0055] In other embodiments, the step of forming the annular groove includes: forming a first mask layer on the wafer surface, the first mask layer covering the device area and exposing a portion of the edge area; using the first mask layer as a mask, etching the wafer material in the portion of the exposed area of ​​the first mask layer by, for example, dry etching, to form the annular groove.

[0056] The first mask layer covers the device area and exposes a portion of the edge area, thereby defining the processing area. For example, the exposed wafer material in the edge area can be removed by dry etching. The depth, width, and sidewall morphology of the annular groove can be controlled, resulting in a smoother edge of the formed annular groove. This reduces additional damage introduced by mechanical processing, resulting in a higher quality and better consistency of the final edge structure. Consequently, it is beneficial to improve the formation quality of the stress relief groove and reinforcement layer formed based on the annular groove.

[0057] It should be noted that, in the step of forming the annular groove 101, the distance L from the sidewall of the annular groove 101 near the device region I to the device region I (e.g., ...) Figure 3 (As shown) is greater than or equal to 100um.

[0058] By limiting the minimum safe distance between the inner wall of the annular groove 101 and the device area I, a physical isolation zone is established between the processing area of ​​the annular groove 101 and the device area I. This effectively prevents damage to the outermost chip area of ​​the device area I due to alignment errors during the formation of the annular groove 101 (whether by etching or physical cutting). This ensures that the electrical performance and reliability of the devices in the device area I are not affected by edge processing.

[0059] In some embodiments, during the step of forming the annular groove 101, the depth of the annular groove 101 is 200 μm to 400 μm.

[0060] If the depth of the annular groove 101 is taken as the first depth H, and the first depth H is too small, for example, less than 200 μm, then the depth margin left for the half-cutting process is limited in order to ensure the principle of "half-cutting depth is less than edge-cutting depth". In addition, the edge surface of the wafer 100 is usually a concentrated area of ​​original defects and processing damage. If the first depth H is too small, it may not be able to completely remove the defects on the edge surface of the wafer 100, so that the stress source is not completely removed, resulting in the effect of the annular groove 101 not being significantly improved. Conversely, if the first depth H is too large, for example, more than 400 μm, the excessively deep cut will increase the mechanical stress acting on the wafer 100, which may form a new stress concentration point at the bottom of the annular groove 101, thereby increasing the risk of microcracks in the wafer 100 during the edge-cutting process.

[0061] In some embodiments, during the step of forming the annular groove 101, the radial width d of the annular groove 101 (e.g., Figure 3 (As shown) ranges from 300μm to 3000μm.

[0062] In the step of forming the annular groove 101, the radial width d of the annular groove 101 should not be too large or too small. If the radial width d of the annular groove 101 is too small, for example, less than 300 μm, it is prone to two risks. First, at the process implementation level, an excessively narrow annular groove 101 places high demands on the precision and stability of the cutting tool, which is difficult to achieve economically. Second, the outermost edge of the wafer 100 usually has more original defects and processing damage. An excessively narrow annular groove 101 may not be able to completely remove these defects, resulting in the stress source not being completely removed, and the annular groove 101 not significantly improving the effect of subsequent packaging processes. Conversely, if the radial width d of the annular groove 101 is too large, for example, exceeding 3000 μm, it will occupy too much of the effective wafer 100 area that could be used to place the chip, reducing the output and utilization rate of a single wafer 100 and increasing costs. Furthermore, from a mechanical perspective, excessive removal of edge material from the wafer reduces the overall rigidity of wafer 100, making it prone to warping and hindering process control. Therefore, the radial width d of the annular groove 101 is 300 μm to 3000 μm, maximizing the effective area of ​​wafer 100 while ensuring complete removal of edge defect areas and providing a sufficient operating window for subsequent processes.

[0063] In some embodiments, during the edge trimming process in the edge region II of the wafer 100, material of the edge portion thickness of the wafer 100 is removed, and the resulting annular groove 101 is an annular stepped groove, the bottom surface of which is connected to the sidewall of the wafer 100.

[0064] By removing material from the edge portion of wafer 100, the annular groove 101 becomes an annular stepped groove. The bottom surface of the annular groove 101 is connected to the sidewall of wafer 100. This means that the process of removing material from wafer 100 not only involves digging a groove downwards on the surface of wafer 100, but also removes the outermost edge of wafer 100, which is prone to notches and defects, forming an open groove structure. This allows subsequent processes, such as lamination and trimming or molding compound filling, to be carried out on the edge of wafer 100 with regular edges, strengthening the overall mechanical strength of the wafer and improving the yield and reliability of wafer 100 in subsequent processing, transport, and packaging.

[0065] Combination Figure 1 ,refer to Figures 5 to 8 A portion of the wafer 100 material of a certain thickness is removed from the bottom part of the annular groove 101 to form a stress relief groove 102, which is used to release the stress at the edge of the wafer 100.

[0066] By forming a stress relief groove 102 at the bottom of the annular groove 101, the stress relief groove 102 serves as a pre-set stress concentration point and structural weak point at the edge of the wafer 100. The mechanical impact and local stress generated by the cutting tool during subsequent half-cutting are actively guided to the stress relief groove 102. These stresses can be safely released at the stress relief groove 102 through the slight yielding or deformation of the material, so that the stress will not accumulate and spread disorderly at the edge of the dicing groove in the subsequent process. This makes it less likely for notches or microcracks to form at the edge of the wafer 100, thus improving the edge structural integrity of the wafer 100 after half-cutting.

[0067] In some embodiments, during the step of forming the stress relief groove 102, the radial dimension of the stress relief groove 102 is smaller than the radial dimension of the annular groove 101.

[0068] The radial dimension (i.e., radial width) of the stress relief groove 102 is smaller than the radial dimension of the annular groove 101, so that the stress relief groove 102 is located in a part of the annular groove 101. In other words, the stress relief range of the stress relief groove 102 is limited to a part of the annular groove 101, which is less likely to damage the overall structure of the annular groove 101, and makes the annular groove 101 have enough bottom area to support the encapsulation material in the subsequent process.

[0069] In some embodiments, in the step of forming the stress relief groove 102, a portion of the thickness of wafer 100 material is removed from the bottom of the sidewall of the annular groove 101 near the device region I, so that the stress relief groove 102 is formed at the bottom of the sidewall of the annular groove 101 near the device region I.

[0070] By forming the stress relief groove 102 at the bottom of the side wall of the annular groove 101 near the device region I, the stress concentration point is set on the path closest to and weakest to the subsequent half-cut dicing groove. This allows the stress wave originating from the dicing groove to be intercepted and absorbed, which is equivalent to setting a barrier on the potential crack propagation path, preventing stress from penetrating into the device region I and maximizing the protection of the device region I.

[0071] In some embodiments, the step of forming the stress relief groove 102 includes: forming a second mask layer 103, the second mask layer 103 exposing a portion of the bottom of the annular groove 101; using the second mask layer 103 as a mask, etching the wafer material at the bottom of the annular groove 101 to form the stress relief groove 102; the wafer processing method further includes: as Figure 7 and Figure 8 As shown, Figure 8 yes Figure 7 From the top view, after forming the stress relief groove 102, the second mask layer 103 is removed.

[0072] By using a second mask layer 103 to expose the material of the annular groove 101 to be etched away, a patterned definition is achieved. Specifically, by using photolithography to open a window on the second mask layer 103 at the position corresponding to the bottom of the annular groove 101, and then using the second mask layer 103 as a mask for etching, the position and depth of the stress relief groove 102 can be controlled. This is beneficial to improving the edge structure integrity of the halved wafer 100, strengthening the overall mechanical strength of the wafer, and improving the yield and reliability of the wafer 100 in subsequent processing, transport, and packaging processes.

[0073] In some embodiments, the material of the second mask layer 103 includes photoresist, and the second mask layer 103 is removed by an ashing process accordingly.

[0074] Combination Figure 1 ,refer to Figure 9 and Figure 10 The wafer processing method further includes: after forming the annular groove 101 and before performing the half-cutting process, at least the sidewall of the annular groove 101 near the device region I is ion implanted and annealed to form a reinforcing layer 105 that is harder or more resilient than the wafer 100 material.

[0075] By pre-forming a reinforcement layer 105 on at least the sidewall of the annular groove 101 near the device region I through ion implantation and annealing, the mechanical strength of the sidewall of the annular groove 101 near the device region I is improved in terms of material properties, thereby effectively resisting the high-frequency impact and local stress brought by the cutting tool during the subsequent half-cutting process. Therefore, the reinforcement layer 105 can suppress the generation and propagation of microcracks during the half-cutting process, improve the edge structure integrity of the wafer 100 after half-cutting, and enhance the overall mechanical strength of the wafer.

[0076] In some embodiments, the ion implantation step includes: forming a third mask layer 104 on the wafer 100, the third mask layer 104 covering the device region I and exposing the sidewall of the annular groove 101 near the device region I; and performing ion implantation on the sidewall of the annular groove 101 near the device region I using the third mask layer 104 as a mask.

[0077] By exposing the sidewall of the annular groove 101 near the device region I using a third mask layer 104, selective ion implantation can be performed on at least the sidewall of the annular groove 101 near the device region I. This strengthens the sidewall of the annular groove 101 near the device region I while preventing the implanted ions from causing unintended damage or changes in the electrical performance of the active devices within the device region I. Therefore, the third mask layer 104 ensures the controllability of the formation location and process of the strengthening layer 105, maximizing the strengthening effect while protecting the functional integrity of the devices in the device region I.

[0078] In some embodiments, in the step of ion implantation at least on the sidewall of the annular groove 101 near the device region I, the implanted ions include implanted carbon ions and / or nitrogen ions.

[0079] Carbon ions and / or nitrogen ions are selected for implantation, and they react with the silicon material of wafer 100 to form high-strength, high-hardness compounds, such as silicon carbide (SiC) or silicon nitride (SiN). Therefore, when wafer 100 in device region I is subsequently halved, the sidewalls of the reinforcement layer 105 formed by ion implantation can effectively resist the mechanical impact and local high stress generated by the high-speed rotation of the cutting tool. This makes it less likely for cracks to form and propagate due to stress concentration at the edge of the cutting groove during the cutting process, thus avoiding the formation of new gaps or defects at the edge of wafer 100 after halving. This is beneficial to improving the yield and reliability of wafer 100 in subsequent processing, transport, and packaging.

[0080] It should be noted that after carbon ions are implanted into the silicon substrate, a high-temperature annealing process provides sufficient activation energy for the implanted carbon atoms, enabling them to chemically react with the surrounding silicon atoms. This results in the precipitation or synthesis of silicon carbide microcrystals within the sidewall of the annular groove 101 near device region I. As a hard ceramic material, silicon carbide exhibits hardness and wear resistance far exceeding that of pure silicon. Therefore, the silicon carbide formed at the edge of wafer 100 effectively resists the scratches and impacts caused by the high-speed rotation of the cutting blade, significantly reducing the probability of material breakage or microcracks at the wafer edge due to mechanical stress.

[0081] It should also be noted that after nitrogen ions are implanted into the silicon substrate, a high-temperature annealing process provides sufficient activation energy for the implanted nitrogen ions, enabling them to chemically react with silicon atoms. This forms a thin layer of silicon nitride with stable chemical properties and higher hardness than silicon on the sidewall of the annular groove 101 near device region I, improving the wear resistance of the sidewall of the annular groove 101 near device region I. On the other hand, due to the size difference between nitrogen and silicon atoms, and the volume effect of the silicon nitride phase during formation, the introduction of nitrogen ions will generate lattice distortion in the silicon lattice of the implanted region, thereby forming a compressive stress field. The compressive stress can actively counteract and balance the tensile stress generated in the cut tip region due to the action of the tool during subsequent cutting, reducing the probability of crack initiation and propagation.

[0082] Specifically, the material of the reinforcing layer 105 includes one or both of silicon carbide and silicon nitride.

[0083] In some embodiments, such as Figure 10As shown, the wafer processing method further includes: after forming the strengthening layer 105, removing the third mask layer 104. The material of the third mask layer 104 includes photoresist, and correspondingly, the third mask layer can be removed by an ashing process.

[0084] Combination Figure 1 ,refer to Figure 11 and Figure 12 , Figure 12 yes Figure 11 From the top view, after forming the stress relief groove 102, the wafer 100 in the device region I is half-cut to form a dicing groove 106.

[0085] The wafer processing method provided in this embodiment of the invention first forms an annular groove 101 in the edge region II of the wafer 100, then removes part of the wafer 100 material at the bottom of the annular groove 101 to form a stress relief groove 102, and finally performs a half-cutting process on the wafer 100 in the device region I to form a dicing groove 106. Before performing the wafer 100 half-cutting process, a stress relief groove 102 is pre-formed in the annular groove 101. The stress relief groove 102 serves as a pre-set stress weak point. During the subsequent half-cutting process to form the dicing groove 106, the mechanical impact and local stress generated by the cutting tool are actively guided to the stress relief groove 102 and released there. This suppresses the disordered accumulation and expansion of stress generated during the half-cutting process at the edge of the dicing groove 106, making it less likely for notches or microcracks to form at the edge of the wafer 100. This improves the edge structural integrity of the wafer 100 after half-cutting, strengthens the overall mechanical strength of the wafer, and helps improve the yield and reliability of the wafer 100 in subsequent processing, transport, and packaging processes.

[0086] Moreover, in this embodiment of the invention, the half-cutting process is performed after the annular groove 101, stress relief groove 102, and edge reinforcement are completed. This ensures that the half-cutting process is carried out on an optimized wafer 100 with high stress resistance. The pre-set stress relief groove 102 actively guides and dissipates the cutting stress, and the reinforcement layer 105 resists the impact. This suppresses uncontrollable damage to the edge of the dicing groove 106, improves the edge structure integrity of the wafer 100 after half-cutting, and strengthens the overall mechanical strength of the wafer processing structure. This is beneficial to improving the yield and reliability of the wafer 100 in subsequent processing, transport, and packaging processes.

[0087] In some embodiments, the annular groove 101 has a first depth H, and the dicing groove 106 has a second depth h, the second depth h being less than the first depth, such that a structurally continuous bottom of the wafer 100 is formed below the dicing groove 106.

[0088] By controlling the first depth H of the annular groove 101 to be greater than the second depth h of the dicing groove 106, it is ensured that the substrate portion of the wafer 100 has an uncut continuous structure below all dicing grooves 106. This enhances the overall mechanical strength and rigidity of the wafer processing structure, thereby preventing the wafer 100 from becoming fragile due to the dicing grooves 106. This provides a solid structural foundation for the wafer 100 in subsequent processes such as transfer, lamination, or molding, making the wafer 100 less prone to breakage due to uneven stress or vibration. It strengthens the overall mechanical strength of the wafer and helps improve the yield and reliability of the wafer 100 in subsequent processing, transfer, and packaging.

[0089] It should be noted that in the step of half-cutting the wafer 100 in the device region I, there are multiple dicing grooves 106, and a portion of the dicing grooves 106 extend along a first direction, while another portion of the dicing grooves 106 extend along a second direction. The first direction and the second direction are perpendicular to each other, so that the tops of multiple chip units are separated.

[0090] refer to Figure 13 and Figure 14 The wafer processing method further includes: after the half-cutting process, forming a coating layer 107 in the dicing groove 106, the annular groove 101 and the top of the device region I.

[0091] A covering layer 107 is formed in the dicing groove 106, the annular groove 101, and on the top of the device area I. The covering layer 107 provides comprehensive encapsulation and protection for the front side of the chip and the sidewalls exposed after half-cutting, thereby achieving electrical insulation and physical isolation for individual chips. This protects the chips from external moisture, impurities, and mechanical damage, resulting in a wafer processing structure formed by the pre-processed and half-cut wafer 100 with high reliability and environmental tolerance.

[0092] In some embodiments, during the step of forming the coating layer 107 in the dicing groove 106, the annular groove 101, and the top of the device region I, the thickness of the coating layer 107 on the annular groove 101 is greater than the thickness of the coating layer 107 on the dicing groove 106. Since the first depth H of the annular groove 101 is greater than the second depth h of the dicing groove 106, the thickness of the coating layer 107 on the annular groove 101 is greater than the thickness of the coating layer 107 on the dicing groove 106 after the coating layer 107 is formed.

[0093] In some embodiments, the step of forming a coating layer 107 in the dicing groove 106, the annular groove 101, and the top of the device region I includes: providing a coating material film 108; applying the coating material film 108 to the front side of the wafer 100 using a lamination process, wherein the coating material film is formed in the dicing groove 106, the annular groove 101, and the top of the device region; trimming the coating material film 108 to remove the coating material film 108 formed radially on the outer side of the wafer 100, thereby forming the coating layer 107 such that the edge of the wafer 100 is coplanar with the edge of the coating layer 107.

[0094] Because the edge of wafer 100 is intact and without gaps under the action of stress relief groove 102 and reinforcement layer 105, it provides a stable structural support for subsequent edge trimming operations after wafer 100 is encapsulated using coating material film 108, thereby eliminating stress concentration points. Therefore, the mechanical stress during the edge trimming process will no longer extend along the edge defects, allowing automated edge trimming to be carried out safely and accurately, ultimately forming a smooth sidewall of coating layer 107 that is coplanar with the edge of wafer 100, which is beneficial to improving the yield and automation level of lamination packaging.

[0095] In some embodiments, the material of the coating film 108 includes a thermosetting adhesive film, which includes epoxy resin, curing agent, toughening agent / elastomer, and filler.

[0096] It should be noted that in the step of applying the coating material film 108 to the front side of the wafer 100 using the lamination process, the thermosetting adhesive film is covered on the half-cut wafer 100. Under vacuum, the thermosetting adhesive film is softened and flowed by heating and applying pressure to completely fill the dicing groove 106 and the annular groove 101. After the thermosetting adhesive film is filled into the dicing groove 106 and the annular groove 101, it can be cured by ultraviolet (UV) irradiation.

[0097] In other embodiments, reference is made to Figure 15 and Figure 16 The step of forming a coating layer 107 in the dicing groove 106, the annular groove 101, and on top of the device region I includes: forming a molding die 109 (e.g., on the wafer 100) on the wafer 100. Figure 15 As shown, the molding fixture 109 covers the device region I and contacts the edge region II, forming a molding cavity between the wafer 100 and the molding fixture 109; molding compound is injected into the molding cavity to form the encapsulation layer 107.

[0098] A closed molding cavity is constructed using molding jig 109 and wafer 100, providing a precise molding space for the injection and curing of liquid molding compound. This allows for effective control over the final shape of the package, ensuring that the molding compound fills the dicing groove 106 and covers each chip unit. Therefore, combined with the defect-free edges of the pre-treated wafer 100, this method effectively suppresses the disordered flow of molding compound caused by capillary action, ensuring the feasibility and reliability of the molding process and facilitating the achievement of high-quality, highly consistent chip-level molding.

[0099] It should be noted that, in the step of injecting molding compound into the molding cavity, the molding compound includes epoxy molding compound (EMC). Epoxy molding compound is typically a solid powder, granules, or block at room temperature. During the molding process, it is heated to a molten state, transforming into a highly fluid, viscous liquid, which is then injected into the molding cavity under high pressure, filling the space between the molding cavity and the wafer 100.

[0100] It should be noted that in the step of forming the molding die 109 on the wafer 100, the device area I of the wafer 100 and the top of the molding die 109 are spaced apart.

[0101] A gap is reserved between the molding jig 109 and the device area I of the wafer 100 to ensure that the molding jig 109 does not directly contact the active devices and other structures on the surface of the device area I during the molding and pressure holding process. This avoids mechanical pressure damage or stress damage to the chip, thereby protecting the electrical performance and structural integrity of the chip. This allows the molding process to be carried out without damaging the core components, which is conducive to ensuring the functional integrity and reliability of the final product.

[0102] It should be noted that after removing the molding fixture 109, a support step is formed in the edge region II, which is composed of the coating layer 107 and the bottom surface of the annular stepped groove, providing a physical reference surface for subsequent wafer 100 cutting or testing processes.

[0103] This invention also provides a wafer processing structure, combined with Figure 11 ,refer to Figure 14 and Figure 16 The diagram illustrates the structure of the wafer processing structure of the present invention.

[0104] The present invention also provides a wafer processing structure, comprising: a wafer 100, the wafer 100 including a device region I and an edge region II surrounding the device region I; an annular groove 101 located within the edge region II of the wafer 100; a stress relief groove 102 located in a portion of the bottom region of the annular groove 101 and within a portion of the wafer 100 material, the stress relief groove 102 being used to release stress at the edge of the wafer 100; and a dicing groove 106 located at the top of the wafer 100 in the device region I.

[0105] Device region I, as the core functional area carrying the semiconductor device, is divided into edge region II surrounding it. This allows edge processing steps such as edge trimming, stress relief trench 102 formation, and ion implantation to be applied precisely at predetermined locations within edge region II. This also ensures that device region I maintains structural integrity during subsequent half-cutting operations, making the sensitive semiconductor device less susceptible to stress concentration or accidental damage, thus improving the yield and reliability of the final product.

[0106] The wafer processing structure further includes an overlay layer 107, located within the dicing groove 106 and the annular groove 101 and covering the top of the device region I.

[0107] The cladding layer 107 is located within the dicing groove 106 and covers the top of the device area I, thereby isolating and protecting the front and sidewalls of the chip unit in the device area I. The cladding layer 107 fills the annular groove 101, thereby forming a complete and continuous annular reinforcement structure around the wafer 100. This solidifies the individual chips separated by the dicing groove 106 and the bottom of the wafer 100 into a composite whole, which helps to improve the overall mechanical strength and processing reliability of the wafer processing structure in the back-end process, thereby optimizing the packaging quality and yield of the final product.

[0108] In some embodiments, the material of the coating layer 107 formed by the lamination process includes epoxy resin.

[0109] In some embodiments, device region I has multiple spaced-apart chip regions arranged in a matrix.

[0110] In some embodiments, the chip area is rectangular or square.

[0111] In some embodiments, multiple chip units are formed within device region I. These chip units include, but are not limited to, memory chips, application-specific integrated circuits (ASICs), analog integrated circuits (Analog ICs), and microcontroller units (MCUs).

[0112] In some embodiments, the annular groove 101 is located within the edge region II of the wafer 100.

[0113] The annular groove 101 makes it less likely for microcracks or defects to appear at the outermost edge of the wafer 100, thus providing a structural basis for the dicing groove 106 and the stress relief groove 102, and avoiding stress concentration at the edge defects of the wafer 100. The annular groove 101 is not only a structure for relieving stress and strengthening the edge, but it is also used to accommodate the subsequent cladding layer 107.

[0114] In some embodiments, the annular groove 101 is a 360° annular structure that is continuously closed along the circumferential direction of the wafer 100.

[0115] The annular groove 101 is a continuously closed annular structure along the circumference of wafer 100. The 360° continuity of the annular groove 101 ensures that all locations in the edge region II of wafer 100 receive the same treatment, resulting in identical edge structures in all radial directions of wafer 100. Consequently, it easily achieves uniform mechanical properties, thus avoiding stress concentration points or weak points in the process caused by local structural discontinuities in wafer 100. Therefore, regardless of the angle or location from which subsequent mechanical stress or packaging material acts on the edge of wafer 100, the same protective effect can be achieved, enhancing the overall mechanical strength of the wafer.

[0116] It should be noted that the distance L from the side wall of the annular groove 101 near the device region I to the device region I is greater than or equal to 100 μm.

[0117] By limiting the minimum safe distance between the inner wall of the annular groove 101 and the device area I, an isolation zone is established between the processing area of ​​the annular groove 101 and the device area I. This effectively prevents damage to the outermost chip area in the device area I due to alignment errors during the formation of the annular groove 101 (whether by etching or physical cutting). This ensures that the electrical performance and reliability of the devices in the device area I are not affected by edge processing.

[0118] In some embodiments, the depth of the annular groove 101 is a first depth H, ranging from 200 μm to 400 μm. If the first depth H is too small, for example, less than 200 μm, the depth margin left for the half-cutting process is limited to ensure the principle that "the half-cutting depth is less than the cutting edge depth." Furthermore, the edge surface of the wafer 100 is typically a concentrated area of ​​original defects and processing damage. If the first depth H is too small, it may not be able to completely remove defects from the edge surface of the wafer 100, resulting in the stress source not being completely removed, and thus the improvement in the effect of the annular groove 101 is not significant. Conversely, if the first depth H is too large, for example, exceeding 400 μm, stress concentration points are likely to exist at the bottom of the annular groove 101, increasing the risk of microcracks forming at the edge of the wafer processing structure.

[0119] In some embodiments, the radial width of the annular groove 101 is 300 μm to 3000 μm.

[0120] If the radial width d of the annular groove 101 is too small, for example, less than 300 μm, it faces a double risk. First, at the process implementation level, an excessively narrow annular groove 101 places high demands on the precision and stability of the cutting tool, making it difficult to achieve economically. Second, the outermost edge of the wafer 100 is usually a region where original defects are concentrated; an excessively narrow annular groove 101 will prevent the stress sources at the wafer 100 edge from being completely removed, resulting in defects remaining on the annular groove 101. Conversely, if the radial width d of the annular groove 101 is too large, for example, exceeding 3000 μm, it will encroach on too much of the effective wafer 100 area that could be used to lay out the chips, reducing the output and utilization rate of a single wafer 100 and increasing costs. Furthermore, from a mechanical point of view, an excessively large radial width of the annular groove 101 will reduce the overall rigidity of the wafer 100, making it prone to warping, which is detrimental to process control. Therefore, the radial width d of the annular groove 101 is set to 300 μm to 3000 μm.

[0121] In some embodiments, the annular groove 101 is an annular stepped groove, and the bottom surface of the annular groove 101 is connected to the sidewall of the wafer 100.

[0122] The annular groove 101 is an annular stepped groove, and the bottom surface of the annular groove 101 is connected to the sidewall of the wafer 100. This means that the annular groove 101 is set at the outermost edge where notches and defects are most likely to occur, which makes the overall mechanical strength of the wafer higher and is conducive to improving the yield and reliability of the wafer in subsequent processing, transport and packaging processes.

[0123] In some embodiments, a stress relief groove 102 is located in a portion of the bottom region of the annular groove 101 and in a portion of the wafer 100 material, the stress relief groove 102 being used to release stress at the edge of the wafer 100.

[0124] The stress relief groove 102 serves as a pre-set stress concentration point and structural weak point at the edge of the wafer 100. It actively guides the mechanical impact and local stress during the wafer processing structure formation process to the stress relief groove 102, so that the stress is safely released through slight yielding or deformation, without disorderly accumulation and expansion. This helps to reduce the gaps or microcracks at the edge of the wafer 100.

[0125] In some embodiments, the radial dimension of the stress relief groove 102 is smaller than the radial dimension of the annular groove 101.

[0126] The radial dimension (i.e. radial width) of the stress relief groove 102 is set to be smaller than the radial dimension of the annular groove 101, so that the stress relief groove 102 is located in a part of the annular groove 101. In other words, the stress relief range of the stress relief groove 102 is limited to a part of the annular groove 101, which is less likely to damage the overall structure of the annular groove 101. At the same time, the annular groove 101 has enough bottom area to support the covering layer 107.

[0127] In some embodiments, the stress relief groove 102 is located at the bottom of the side wall of the annular groove 101 near the device region I.

[0128] By forming the stress relief groove 102 at the bottom of the sidewall of the annular groove 101 near the device region I, the stress concentration point is set on the path closest to and weakest to the dicing groove 106. This allows the stress waves generated during the formation of the dicing groove 106 to be intercepted and absorbed. This is equivalent to setting up a barrier on the potential crack propagation path, preventing stress from penetrating into the device region I and maximizing the protection of the device region I.

[0129] The wafer processing structure further includes a reinforcement layer 105, which is located at least on the sidewall of the annular groove 101 near the device region I, and the reinforcement layer 105 is harder or more resilient than the wafer 100 material.

[0130] The reinforcing layer 105 is harder or more resilient than the wafer 100 material, thereby suppressing the generation and propagation of microcracks during the formation of the dicing groove 106, making it less likely for notches or microcracks to form at the edge of the wafer 100, and enhancing the overall mechanical strength of the wafer.

[0131] In some embodiments, the material of the reinforcing layer 105 includes one or both of silicon carbide and silicon nitride.

[0132] The reinforcing layer 105 is a high-strength, high-hardness compound, which enables it to resist mechanical impacts and localized high stress. It is less prone to crack formation and propagation due to stress concentration, thus reducing the likelihood of notches or defects forming at the edge of wafer 100. This helps ensure the structural integrity and surface finish of the wafer 100 edge, and improves the yield and reliability of the wafer in subsequent processing, transport, and packaging.

[0133] It should be noted that silicon carbide, as a hard ceramic material, has a hardness and wear resistance far exceeding that of pure silicon. By forming a SiC microcrystalline layer in the sidewall of the annular groove 101 near the device region I, a robust physical barrier can be formed, which greatly reduces the probability of material breakage or microcracks caused by mechanical stress.

[0134] It should also be noted that silicon nitride, as a chemically stable material with a hardness higher than silicon, forms a silicon nitride layer on the sidewall of the annular groove 101 near device region I, improving the wear resistance of the sidewall of the annular groove 101 near device region I. On the other hand, due to the size difference between nitrogen and silicon atoms, and the volume effect of the silicon nitride phase during formation, the introduction of nitrogen ions will generate lattice distortion in the silicon lattice of the implantation region, thereby forming a compressive stress field. This compressive stress can actively counteract and balance the tensile stress generated in the dicing tip region due to the action of the tool during the formation of the dicing groove 106, reducing the probability of crack initiation and propagation.

[0135] In some embodiments, the dicing groove 106 is located on top of the wafer 100 of the device region I.

[0136] The dicing groove 106 is located on the top of the wafer 100 in the device region I and is used to define each chip unit. This allows for the pre-division of each chip unit without completely cutting through the wafer 100, thereby preserving the continuity and integrity of the bottom of the wafer 100. The bottom of the wafer 100 serves as a structural support to enhance the mechanical strength of the wafer 100 and effectively suppress wafer 100 breakage or microcrack propagation caused by stress during subsequent wafer 100 transfer and processing. In addition, the dicing groove 106 also provides space for the formation of the cladding layer 107.

[0137] In some embodiments, there are multiple dicing slots 106, and a portion of the dicing slots 106 extend along a first direction and another portion of the dicing slots 106 extend along a second direction. The first direction and the second direction are perpendicular to each other, so that the tops of the multiple chip units are separated.

[0138] In some embodiments, the annular groove 101 has a first depth H, and the dicing groove 106 has a second depth h, the second depth h being less than the first depth H, such that a structurally continuous bottom of the wafer 100 is formed below the dicing groove 106.

[0139] By controlling the second depth h of the annular groove 101 to be less than the first depth H, it is ensured that the substrate portion of the wafer 100 has an uncut continuous structure below all the dicing grooves 106, thereby enhancing the overall mechanical strength and rigidity of the wafer processing structure. This prevents the wafer 100 from becoming fragile due to the dicing grooves 106, making the wafer less prone to breakage due to uneven force or vibration, strengthening the overall mechanical strength of the wafer, and improving the yield and reliability of the wafer in subsequent processing, transport and packaging processes.

[0140] In some embodiments, since the first depth H of the annular groove 101 is greater than the second depth h of the dicing groove 106, the thickness of the covering layer 107 on the annular groove 101 is greater than the thickness of the covering layer 107 on the dicing groove 106.

[0141] In some embodiments, such as Figure 14 As shown, the edge of the cladding layer 107 is coplanar with the edge of the wafer 100. The cladding layer 107 is formed by a lamination process and an edge trimming process, which makes the wafer structure edge neat, ensures mechanical strength, and has high morphological consistency, which is beneficial to improving the wafer yield and the reliability of the wafer in subsequent processing and transportation.

[0142] In other embodiments, such as Figure 16 As shown, when the annular groove 101 is an annular stepped groove, the cladding layer 107 and the bottom surface of the annular groove 101 form a supporting step. The cladding layer 107 is formed by molding. The supporting steps of the cladding layer 107 and the bottom groove of the annular groove 101 enable the wafer processing structure to identify, align, and position itself in subsequent automated processes such as full dicing, dicing, pick-and-place, or probe testing.

[0143] The wafer processing structure can be formed using the processing method described in the foregoing embodiments, or it can be formed using other processing methods. For a detailed description of the wafer processing structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0144] While the embodiments of the present invention have been disclosed above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the invention should be determined by the scope defined in the claims.

Claims

1. A method for processing a wafer, characterized in that, include: A wafer is provided, the wafer including a device region and an edge region surrounding the device region; An edge trimming process is performed within the edge region of the wafer to form an annular groove; A portion of the wafer material at the bottom of the annular groove is removed to form a stress relief groove, which is used to release stress at the wafer edge. After the stress relief groove is formed, the wafer in the device area is half-cut to form a dicing groove.

2. The wafer processing method according to claim 1, characterized in that, The wafer processing method further includes: after forming the annular groove and before performing the half-cutting process, performing ion implantation and annealing on at least the sidewall of the annular groove near the device region to form a reinforcing layer that is harder or more resilient than the wafer material.

3. The wafer processing method according to claim 2, characterized in that, The ion implantation steps include: A third mask layer is formed on the wafer, the third mask layer covering the device region and exposing the sidewall of the annular groove near the device region; Using the third mask layer as a mask, ion implantation is performed on the sidewall of the annular groove near the device region.

4. The wafer processing method according to claim 2, characterized in that, In the step of ion implantation at least on the sidewall of the annular groove near the device region, the implanted ions include implanted carbon ions and / or nitrogen ions.

5. The wafer processing method according to claim 1, characterized in that, In the step of forming the stress relief groove, the radial dimension of the stress relief groove is smaller than the radial dimension of the annular groove.

6. The wafer processing method according to claim 1, characterized in that, In the step of forming the annular groove, the annular groove has a first depth; In the step of forming the dicing groove, the dicing groove has a second depth, which is less than the first depth, so as to form a structurally continuous wafer bottom below the dicing groove.

7. The wafer processing method according to claim 1, characterized in that, In the step of forming the stress relief groove, a portion of the thickness of the wafer material near the bottom of the sidewall of the annular groove near the device area is removed, so that the stress relief groove is formed at the bottom of the sidewall of the annular groove near the device area.

8. The wafer processing method according to claim 1, characterized in that, The step of forming the annular groove includes: A first mask layer is formed on the surface of the wafer, the first mask layer covering the device area and exposing a portion of the edge area; the first mask layer is a mask, and the wafer material in the exposed portion of the first mask layer is etched to form the annular groove; Alternatively, within the edge region of the wafer, the material of the wafer edge portion thickness can be removed by physical cutting to form the annular groove.

9. The wafer processing method according to claim 1, characterized in that, In the step of forming the annular groove, the depth of the annular groove is 200 μm to 400 μm.

10. The wafer processing method according to claim 1, characterized in that, In the step of forming the annular groove, the distance from the sidewall of the annular groove near the device area to the device area is greater than or equal to 100 μm.

11. The wafer processing method according to claim 1, characterized in that, The step of forming the stress relief groove includes: A second mask layer is formed, which exposes a portion of the bottom of the annular groove; Using the second mask layer as a mask, the wafer material at the bottom of the annular groove is etched to form the stress relief groove; The wafer processing method further includes: after forming the stress relief groove, removing the second mask layer.

12. The wafer processing method according to claim 1, characterized in that, The wafer processing method further includes forming a coating layer in the dicing groove, the annular groove, and on top of the device area after the half-cutting process.

13. The wafer processing method according to claim 12, characterized in that, The step of forming a coating layer in the dicing groove, the annular groove, and on top of the device area includes: Provide coating material film; The coating material film is applied to the front side of the wafer using a lamination process, and the coating material film is formed in the dicing groove, the annular groove and on top of the device area; The coating material film is trimmed to remove the coating material film formed radially on the outer side of the wafer, forming the coating layer such that the edge of the wafer is coplanar with the edge of the coating layer.

14. The wafer processing method according to claim 12, characterized in that, The step of forming a coating layer in the dicing groove, the annular groove, and on top of the device area includes: A molding die is formed on the wafer, the molding die covering the device region and contacting the edge region, and a molding cavity is formed between the wafer and the molding die. Molding material is injected into the molding cavity to form the coating layer.

15. The wafer processing method according to claim 12, characterized in that, In the step of forming a coating layer in the dicing groove, the annular groove, and on top of the device area, the thickness of the coating layer on the annular groove is greater than the thickness of the coating layer on the dicing groove.

16. The wafer processing method according to claim 1, characterized in that, In the step of shaving the edge region of the wafer, the material of the wafer edge portion thickness is removed to form the annular groove, the annular groove being an annular stepped groove, and the bottom surface of the annular groove being connected to the wafer sidewall.

17. A wafer processing structure, characterized in that, include: A wafer, the wafer including a device region and an edge region surrounding the device region; An annular groove is located within the edge region of the wafer; The stress relief groove is located in a portion of the bottom of the annular groove and is situated within a portion of the wafer material. The dicing groove is located on the top of the wafer in the device area.

18. The wafer processing structure according to claim 17, characterized in that, The wafer processing structure also includes: A reinforcing layer, at least located on the sidewall of the annular groove near the device region, is harder or more resilient than the wafer material.

19. The wafer processing structure according to claim 18, characterized in that, The reinforcing layer is made of one or both of silicon carbide and silicon nitride.

20. The wafer processing structure according to claim 17, characterized in that, The radial dimension of the stress relief groove is smaller than the radial dimension of the annular groove.

21. The wafer processing structure according to claim 17, characterized in that, The annular groove has a first depth, and the dicing groove has a second depth, the second depth being less than the first depth.

22. The wafer processing structure according to claim 17, characterized in that, The stress relief groove is located at the bottom of the side wall of the annular groove near the device area.

23. The wafer processing structure according to claim 17, characterized in that, The depth of the annular groove is 200 μm to 400 μm.

24. The wafer processing structure according to claim 17, characterized in that, The distance from the sidewall of the annular groove near the device area to the device area is greater than or equal to 100 μm.

25. The wafer processing structure according to claim 17, characterized in that, The wafer processing structure further includes a cladding layer located within the dicing groove and the annular groove and covering the top of the device area.

26. The wafer processing structure according to claim 25, characterized in that, The thickness of the coating layer on the annular groove is greater than the thickness of the coating layer on the dicing groove.

27. The wafer processing structure according to claim 17, characterized in that, The annular groove is an annular stepped groove, and the bottom surface of the annular groove is connected to the sidewall of the wafer.

28. The wafer processing structure according to claim 25, characterized in that, The edge of the wafer is coplanar with the edge of the cladding layer.

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