Metal oxide semiconductor (MOS) flip chip packaging structure and packaging method thereof

Abstract

The invention provides an MOS flip chip packaging structure and a packaging method thereof. The MOS flip chip packaging structure comprises a packaging substrate and a flip chip, wherein the flip chip is provided with a plurality of bumps; a first source electrode bonding pad, a first drain electrode bonding pad and two first grid electrode bonding pads are formed on the front surface of the packaging substrate, gradient diversion trenches are formed in the first source electrode bonding pad, the first drain electrode bonding pad and the two first grid electrode bonding pads, and a solder buffer layer is formed in each gradient of the gradient diversion trenches; when the plurality of bumps are welded with the first source electrode bonding pad, the first drain electrode bonding pad and the two first grid electrode bonding pads in a one-to-one correspondence manner, the gradient diversion trench and the solder buffer layer can guide and fuse solder generated by fusing the plurality of bumps, so that a solid crystal layer is formed between the packaging substrate and the flip chip; the problems that due to the fact that an existing substrate welding structure is uneven in welding strength, bridging risk is increased and stress is concentrated, short circuit or electrical abnormity is likely to be caused, fatigue of a packaging structure is accelerated, and the service life is shortened are solved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip packaging, and particularly relates to a MOS flip chip packaging structure and a packaging method thereof. BACKGROUND

[0002] MOS flip chip packaging is a packaging technology that directly inverts a chip with the front face downward on a substrate through solder balls or bumps to achieve a shorter electrical connection path and higher packaging density.

[0003] A substrate welding structure disclosed in a patent with the publication number CN218414564U includes a substrate, the substrate is provided with a containing groove; a first pad provided on the substrate, the first pad is provided with an opening corresponding to the containing groove, so that the first pad is arranged around the containing groove; a second pad provided in the containing groove; wherein the first pad and the second pad are electrically connected with the substrate, and the first pad and the second pad are used for corresponding welding with conductive bumps of a flip chip, so that the containing groove corresponds to receive solder. Although the containing groove can receive solder, there is still a problem of uneven solder flow and local accumulation in high-temperature reflow soldering, especially at the connection between the conductive plating layer and the pad, which easily leads to uneven welding strength, increased bridging risk, and causes short circuit or electrical abnormality. At the same time, the second pad is suspended and the conductive wire support structure is easy to cause stress concentration due to the difference in material thermal expansion under thermal cycling, which accelerates the fatigue of the packaging structure and shortens the service life.

[0004] Therefore, it is urgent to develop a MOS flip chip packaging structure and a packaging method thereof that can ensure stable electrical connection and reduce the risk of stress concentration. SUMMARY

[0005] The present application aims to solve the problem that the existing substrate welding structure leads to short circuit or electrical abnormality, and accelerates the fatigue of the packaging structure and shortens the service life due to uneven welding strength, increased bridging risk and stress concentration.

[0006] In order to achieve the above-mentioned purpose, the present application provides a MOS flip chip packaging structure and a packaging method thereof.

[0007] According to a first aspect of the present application, a MOS flip chip packaging structure is provided, comprising a packaging substrate and a flip chip having a plurality of bumps thereon;

[0008] A first source pad, a first drain pad and two first gate pads are formed on the front face of the packaging substrate, and a gradient flow groove is formed in each of the first source pad, the first drain pad and the two first gate pads, and a solder buffer layer is formed in each gradient of the gradient flow groove;

[0009] When the plurality of bumps are welded one-to-one with the first source pad, the first drain pad and the two first gate pads, the gradient flow guide groove and the solder buffer layer can guide and fuse the solder generated by melting of the plurality of bumps to form a die bonding layer between the packaging substrate and the flip chip.

[0010] Optionally, the solder buffer layer is provided with a receiving groove for receiving the molten solder.

[0011] Optionally, the bottom of the first source pad and the first drain pad are each formed with a plurality of solder counterbores for receiving the solder flowing back to the bottom thereof.

[0012] Optionally, the first source pad, the first drain pad and the two first gate pads are each provided with a conductive post counterbore, and the conductive post counterbore is formed with a conductive post.

[0013] Optionally, the packaging substrate is formed with a first isolation layer and a second isolation layer for electrically isolating the first source pad and the first drain pad and the first drain pad and the two first gate pads, respectively.

[0014] Optionally, the packaging substrate is a copper clad ceramic substrate.

[0015] Optionally, the reverse side of the copper clad ceramic substrate is formed with a second source pad, a second drain pad and two second gate pads, and the second source pad, the second drain pad and the two second gate pads are connected one-to-one with the first source pad, the first drain pad and the two first gate pads through conductive posts.

[0016] Optionally, the packaging substrate is a copper frame substrate.

[0017] Optionally, the reverse side of the copper frame substrate is provided with a plurality of pins connected one-to-one with the conductive posts in the first source pad, the first drain pad and the two first gate pads, and the plurality of pins are used for electrical connection with external devices.

[0018] According to a second aspect of the present application, a MOS flip chip packaging method is also provided for forming the MOS flip chip packaging structure as claimed in any one of the above, and the MOS flip chip packaging method comprises:

[0019] providing a packaging substrate;

[0020] forming a first source pad, a first drain pad and two first gate pads on the packaging substrate;

[0021] forming a gradient flow guide groove in the first source pad, the first drain pad and the two first gate pads;

[0022] The solder buffer layer is formed in the gradient flow groove;

[0023] The bumps are welded one by one with the first source electrode pad, the first drain electrode pad and the two first gate electrode pads to form a die bonding layer between the packaging substrate and the flip chip.

[0024] The present application has the following advantages:

[0025] The MOS flip chip packaging structure provided by the present application forms the first source electrode pad, the first drain electrode pad and the two first gate electrode pads on the front surface of the packaging substrate, and forms the gradient flow groove in the first source electrode pad, the first drain electrode pad and the two first gate electrode pads, so that when the bumps are welded one by one with the first source electrode pad, the first drain electrode pad and the two first gate electrode pads, the gradient flow groove and the solder buffer layer can guide and fuse the solder generated by the melting of the bumps to form a die bonding layer between the packaging substrate and the flip chip. Compared with the existing substrate welding structure, the gradient flow groove of the present application can effectively realize the directional flow and uniform distribution of the solder during the reflow welding process. The solder flows in order from outside to inside through the step-by-step change structure, avoiding the generation of solder accumulation or voids. The solder buffer layer arranged in each gradient can absorb the expansion or shrinkage stress of the solder during the heat cycle, relieve the stress concentration problem of the welding interface, thereby improving the welding uniformity, enhancing the connection reliability, reducing the short circuit risk caused by solder side creep or bridging, and improving the stability and service life of the packaging structure.

[0026] Further, the present application forms a plurality of solder counterbores at the bottom of the first source electrode pad and the first drain electrode pad for accommodating the solder flowing to the bottom, which can prevent the phenomenon of solder expanding upward along the sidewall of the bumps or outward of the pads, thereby effectively avoiding the risk of bridging or short circuit.

[0027] The MOS flip chip packaging method provided by the present application belongs to the same overall inventive concept as the MOS flip chip packaging structure of the present application, and should at least have the same technical effects as the MOS flip chip packaging structure of the present application. The present application will not be described here.

[0028] According to the above content, the technical scheme of the present application can effectively solve the problems of uneven welding strength, increased risk of bridging and stress concentration in the existing substrate welding structure, which can easily cause short circuit or electrical abnormality, and accelerate the fatigue of the packaging structure and shorten the service life.

[0029] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0030] The present application can be better understood by reference to the following description together with the accompanying drawings, in which like reference numerals indicate identical or similar elements, and in which:

[0031] Figure 1 A structural schematic diagram of a MOS flip chip packaging structure under a first perspective according to an embodiment of the present application is shown;

[0032] Figure 2 A structural schematic diagram of a MOS flip chip packaging structure under a second perspective according to an embodiment of the present application is shown;

[0033] Figure 3 A structural schematic diagram of a MOS flip chip packaging structure under a third perspective according to an embodiment of the present application is shown;

[0034] Figure 4 A structural schematic diagram of a MOS flip chip packaging structure under a fourth perspective according to an embodiment of the present application is shown;

[0035] Figure 5 A structural schematic diagram of a MOS flip chip packaging structure under a fifth perspective according to an embodiment of the present application is shown;

[0036] Figure 6 A structural schematic diagram of a MOS flip chip packaging structure under a sixth perspective according to an embodiment of the present application is shown;

[0037] Figure 7 A sectional view of a MOS flip chip packaging structure according to an embodiment of the present application is shown;

[0038] Figure 8 A structural schematic diagram of a MOS flip chip packaging structure under a first perspective according to another embodiment of the present application is shown;

[0039] Figure 9 A structural schematic diagram of a MOS flip chip packaging structure under a second perspective according to another embodiment of the present application is shown;

[0040] Figure 10 A structural schematic diagram of a MOS flip chip packaging structure under a third perspective according to another embodiment of the present application is shown;

[0041] Figure 11 A structural schematic diagram of a MOS flip chip packaging structure under a fourth perspective according to another embodiment of the present application is shown;

[0042] Figure 12Fig. 5 shows a structural schematic diagram of a MOS flip chip packaging structure according to another specific embodiment of the present application;

[0043] Figure 13 Fig. 6 shows a structural schematic diagram of a MOS flip chip packaging structure according to another specific embodiment of the present application;

[0044] Figure 14 Fig. 7 shows a sectional view of a MOS flip chip packaging structure according to another specific embodiment of the present application;

[0045] Figure 15 Fig. 8 shows a structural schematic diagram of a flip chip according to an embodiment of the present application;

[0046] Figure 16 Fig. 9 shows a flow schematic diagram of a MOS flip chip packaging method according to an embodiment of the present application.

[0047] Reference Signs:

[0048] 1 - packaging substrate; 2 - bump; 3 - flip chip; 4 - first source pad; 5 - first drain pad; 6 - first gate pad; 7 - gradient flow guide groove; 701 - solder buffer layer; 7011 - accommodation groove; 8 - die bonding layer; 9 - solder counterbore; 10 - conductive column counterbore; 11 - conductive column; 12 - first isolation layer; 13 - second isolation layer; 14 - second source pad; 15 - second drain pad; 16 - second gate pad; 17 - solder sink groove; 18 - first heat sink; 1801 - electrical through hole; 19 - first packaging protection layer; 20 - first shell; 21 - pin; 22 - second heat sink; 23 - second packaging protection layer; 24 - second shell. DETAILED DESCRIPTION

[0049] In order to enable a person skilled in the art to more fully understand the technical solutions of the present application, in the following, exemplary embodiments of the present application will be described more fully and in detail with reference to the accompanying drawings. Obviously, one or more of the embodiments of the present application described below are only one or more of the specific manners in which the technical solutions of the present application can be implemented, and are not exhaustive. It should be understood that the technical solutions of the present application can be implemented in other manners belonging to the same general inventive concept without being limited by the exemplary described embodiments. Based on one or more embodiments of the present application, all other embodiments obtained by a person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0050] Reference Signs: Figures 1-15The embodiment of the present application provides a MOS flip chip packaging structure, which comprises a packaging substrate 1 and a flip chip 3 with a plurality of bumps 2 on the packaging substrate 1.

[0051] A first source pad 4, a first drain pad 5 and two first gate pads 6 are formed on the front surface of the packaging substrate 1, and a gradient flow groove 7 is formed in each of the first source pad 4, the first drain pad 5 and the two first gate pads 6; and a solder buffer layer 701 is formed in each gradient of the gradient flow groove 7.

[0052] When the plurality of bumps 2 are welded one by one with the first source pad 4, the first drain pad 5 and the two first gate pads 6, the gradient flow groove 7 and the solder buffer layer 701 can guide and fuse the solder generated by melting of the plurality of bumps 2, so as to form a die bonding layer 8 between the packaging substrate 1 and the flip chip 3.

[0053] In an embodiment, the solder buffer layer 701 is provided with a containing groove 7011 for containing the molten solder.

[0054] Specifically, the gradient flow groove can effectively realize the directional flow and uniform distribution of the solder in the reflow welding process. The gradient flow groove guides the solder to flow orderly from outside to inside through the gradually changing structure, so that the accumulation or cavity of the solder is avoided; and the solder buffer layer arranged in each gradient can absorb the expansion or shrinkage stress of the solder in the heat cycle process, so as to relieve the stress concentration problem of the welding interface. Meanwhile, the containing groove 7011 can receive the molten solder, so as to improve the welding uniformity, enhance the connection reliability, reduce the short circuit risk caused by the side creep or bridging of the solder, and improve the stability and service life of the packaging structure.

[0055] In an embodiment, the bottom of the first source pad 4 and the first drain pad 5 is formed with a plurality of solder counterbores 9 for containing the solder reflowing to the bottom. Specifically, when the molten solder reflows to the contact area of the pad and the bump 2 under the action of surface tension and wets the surface of the pad, the molten solder can sink into the plurality of solder counterbores 9, so as to further prevent the phenomenon that the solder expands upwards along the side wall of the plurality of bumps 2 or to the outside of the pad, thereby effectively avoiding the bridging or short circuit risk.

[0056] In a specific embodiment, the shape of the cross section of the first source pad 4 is oval or rectangular.

[0057] In a specific embodiment, the shape of the cross section of the first drain pad 5 is T-shaped.

[0058] In a specific embodiment, the shape of the cross section of the two first gate pads 6 is circular or rectangular.

[0059] Specifically, the shapes of the plurality of bumps 2 are set to correspond to the first source pad 4, the first drain pad 5, and the two first gate pads 6 one by one. Thus, the alignment accuracy and the contact area in the soldering process can be effectively improved, the uniform distribution of the solder in the reflow process is ensured, the offset, bridging or soldering cavity caused by shape mismatch is avoided, the soldering strength and the reliability of the electrical connection are enhanced, and the risk of structural failure caused by stress concentration in the packaging process is reduced.

[0060] In an embodiment, a conductive column counterbore 10 is arranged in the first source pad 4, the first drain pad 5, and the two first gate pads 6, and a conductive column 11 is formed in the conductive column counterbore 10.

[0061] In an embodiment, a first isolation layer 12 and a second isolation layer 13 are formed on the packaging substrate 1 to electrically isolate the first source pad 4 and the first drain pad 5, and the first drain pad 5 and the two first gate pads 6, respectively.

[0062] The packaging substrate 1 of the present application has the following two specific embodiments:

[0063] As shown in the drawings, Figures 1-7 In a first specific embodiment, the packaging substrate 1 is a copper-clad ceramic substrate.

[0064] In an embodiment, a second source pad 14, a second drain pad 15, and two second gate pads 16 are formed on the back of the copper-clad ceramic substrate, and the second source pad 14, the second drain pad 15, and the two second gate pads 16 are connected to the first source pad 4, the first drain pad 5, and the two first gate pads 6 one by one through the conductive column 11. To build a vertical conduction path, the electrical signals on the front of the flip chip 3 and the copper-clad ceramic substrate can be efficiently and stably transmitted to the back of the packaging substrate, and electrically connected to external devices through the second source pad 14, the second drain pad 15, and the two second gate pads 16, thereby realizing three-dimensional wiring and multi-functional integration. This not only improves the wiring flexibility and space utilization of the copper-clad ceramic substrate, but also enhances the electrical performance and thermal conduction efficiency of the packaging structure.

[0065] In a specific embodiment, the cross-sectional shape of the second source pad 14, the second drain pad 15, and the two second gate pads 16 is rectangular.

[0066] In an embodiment, a solder sink 17 is arranged in the second source pad 14, the second drain pad 15, and the two second gate pads 16 to accommodate molten solder. When the external device is electrically connected to the back of the copper-clad ceramic substrate through the solder, the soldering strength and the reliability of the electrical connection are enhanced.

[0067] In a specific embodiment, the first isolation layer 12 and the second isolation layer 13 are formed by etching the copper layer on the front surface of the copper clad ceramic substrate to expose the ceramic surface. Specifically, the ceramic material itself has excellent electrical insulation and thermal conductivity. In the copper clad ceramic substrate, the originally fully covered copper layer is electrically conductive and thermally conductive. If the circuit areas formed by the pads share the same copper layer, it is easy to cause electrical interference or short circuit between circuits. By etching to remove part of the copper layer and exposing the ceramic substrate, a physical and electrical isolation band is formed. The first isolation layer 12 and the second isolation layer 13 can effectively block the unintended flow of current between different circuit areas due to the high insulation of the ceramic, thereby achieving electrical isolation.

[0068] At the same time, although the ceramic is not conductive, it has good heat conduction capacity and can still allow heat to spread laterally on its surface, thereby achieving thermal energy balance and achieving thermal management. Therefore, the first isolation layer 12 and the second isolation layer 13 not only ensure the safe operation of the circuit, but also maintain the overall thermal conductivity of the substrate.

[0069] In an embodiment, the back surface of the copper clad ceramic substrate is connected with a first heat sink 18 for dissipating heat from the flip chip 3. Specifically, the first heat sink 18 is composed of a heat dissipation substrate and heat dissipation fins, which can dissipate the heat generated by the operation of the flip chip 3 outward. Its application principle is the prior art, and the present application will not be repeated here.

[0070] In a specific embodiment, the heat dissipation substrate of the first heat sink 18 is provided with a plurality of electrical through holes 1801 corresponding to the second source pad 14, the second drain pad 15 and the two second gate pads 16. The plurality of electrical through holes 181 are respectively used for electrical connection of the second source pad 14, the second drain pad 15 and the two second gate pads 16 with external equipment.

[0071] In an embodiment, the flip chip 3 and the copper clad ceramic substrate are formed with a first packaging protection layer 19 for protection.

[0072] In a specific embodiment, the first packaging protection layer 19 is formed by coating the flip chip 3 and the copper clad ceramic substrate with epoxy resin material.

[0073] Specifically, the epoxy resin has good insulation performance, which can avoid the risk of short circuit between circuits and prolong the service life of the device. It can effectively prevent the flip chip 3 and the copper clad ceramic substrate from being affected by environmental factors such as external moisture, dust and mechanical impact, while enhancing the bonding strength between the flip chip 3 and the copper clad ceramic substrate, improving the stability and reliability of the overall packaging structure, thereby playing the role of mechanical support, environmental protection and electrical insulation.

[0074] In one embodiment, a first housing 20 is arranged on the side of the first heat sink 18 facing the copper clad ceramic substrate, and the first housing 20 encapsulates the first encapsulation layer 19. Specifically, the first housing 20 can provide additional mechanical protection, environmental sealing and electromagnetic shielding for the packaging structure, thereby improving the overall reliability and service life of the packaging structure. In addition, the first housing 20 is made of a metal material such as aluminum.

[0075] As shown in Figures 8-15 , in a second specific embodiment, the packaging substrate 1 is a copper frame substrate.

[0076] In one embodiment, the back side of the copper frame substrate is provided with a plurality of pins 21 connected to the conductive pillars 11 in the first source electrode pad 4, the first drain electrode pad 5 and the two first gate electrode pads 6 one by one, and the plurality of pins 21 are used for electrical connection with external devices.

[0077] In one embodiment, the first isolation layer 12 and the second isolation layer 13 are etched 2 / 3 along the front-to-back direction of the copper frame substrate, as shown in Figure 8 . Specifically, the first isolation layer 12 and the second isolation layer 13 can form an electrical breakpoint in the originally continuous copper layer, thereby achieving electrical isolation between different regions; at the same time, since the copper layer is not completely etched through, the remaining part of the copper layer can still realize the conduction and connection of the local region, achieving the partition control of the conductive path. Therefore, the formation of the first isolation layer 12 and the second isolation layer 13 not only effectively blocks the current crosstalk between different circuit regions, but also retains the conductive ability of the specific region, realizing the unification of electrical isolation and local conduction control.

[0078] In another embodiment, the first isolation layer 12 and the second isolation layer 13 are formed by depositing ceramic material in the groove formed by etching 2 / 3 along the front-to-back direction of the copper frame substrate, as shown in Figure 9 . Specifically, the ceramic material has excellent electrical insulation performance and also has a certain thermal conductivity. By embedding the ceramic material in the copper frame substrate, an electrical breakpoint can be formed in the originally continuous copper structure, thereby achieving electrical isolation between different circuit regions and preventing current crosstalk or short circuit; at the same time, the ceramic material can still allow partial heat conduction, which helps to maintain the thermal balance of the local region, realizing the thermal and electrical collaborative management under the condition of compact structure. Therefore, the first isolation layer 12 and the second isolation layer 13 not only improve the electrical safety of the packaging structure, but also enhance the stability and reliability of the overall system.

[0079] In one embodiment, the side of the flip chip 3 away from the plurality of bumps 2 is connected with a second heat sink 22 for dissipating heat from the flip chip 3. Specifically, the second heat sink 22 has the same structure and working principle as the first heat sink 18, which will not be described here.

[0080] In one embodiment, the flip chip 3 and the copper frame substrate are formed with a second packaging protective layer 23 for protecting the same. Specifically, the second packaging protective layer 23 has the same material and principle as the first packaging protective layer 19, which will not be repeated here.

[0081] In one embodiment, the second heat sink 22 is provided with a second shell 24 which covers the second packaging protective layer 23 on the side facing the flip chip 3. Specifically, the second shell 24 has the same material and principle as the first shell 20, which will not be repeated here.

[0082] Notably, one end of the plurality of pins 21 is exposed to the outside of the second shell 24 to achieve electrical connection with external equipment.

[0083] The MOS flip chip packaging structure provided by the present application is characterized in that the front surface of the packaging substrate is formed with a first source pad, a first drain pad and two first gate pads, and the first source pad, the first drain pad and the two first gate pads are each formed with a gradient flow groove. When the plurality of bumps are welded one by one with the first source pad, the first drain pad and the two first gate pads, the gradient flow groove and the solder buffer layer can guide and fuse the solder generated by the melting of the plurality of bumps to form a die bonding layer between the packaging substrate and the flip chip. Compared with the existing substrate welding structure, the gradient flow groove of the present application can effectively realize the directional flow and uniform distribution of the solder during the reflow welding process. The solder is guided to flow orderly from the outside to the inside through the step-by-step change structure, avoiding the generation of solder accumulation or voids. The solder buffer layer arranged in each gradient can absorb the expansion or shrinkage stress of the solder during the heat cycle, relieving the stress concentration problem of the welding interface, thereby improving the welding uniformity, enhancing the connection reliability, reducing the short circuit risk caused by solder side creep or bridging, and improving the stability and service life of the packaging structure.

[0084] Further, the present application is characterized in that the bottom of the first source pad and the first drain pad is formed with a plurality of solder counterbores for accommodating the solder flowing to the bottom thereof, which can prevent the phenomenon of solder expanding upward along the sidewall of the plurality of bumps or outward of the pad, thereby effectively avoiding the risk of bridging or short circuit.

[0085] Correspondingly, as shown in Figure 16 The MOS flip chip packaging method provided by the present application is used to form the MOS flip chip packaging structure in any one of the above embodiments, and includes the following steps:

[0086] Step S11: providing a packaging substrate 1;

[0087] Step S12: forming the first source pad 4, the first drain pad 5 and the two first gate pads 6 on the packaging substrate 1;

[0088] Step S13: forming the gradient flow grooves 7 in the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0089] Step S14: forming the solder buffer layer 701 in the gradient flow grooves 7;

[0090] Step S15: welding the bumps 2 with the first source pad 4, the first drain pad 5 and the two first gate pads 6 one by one to form the die bonding layer 8 between the packaging substrate 1 and the flip chip 3.

[0091] In an embodiment, in step S12, forming the first source pad 4, the first drain pad 5 and the two first gate pads 6 on the packaging substrate 1 specifically includes the following steps:

[0092] Step S121: coating photoresist on the front surface of the packaging substrate 1 and exposing with a mask to define the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6, and at the same time, forming a patterned protective layer in the non-pad area;

[0093] Step S122: etching the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6.

[0094] In an embodiment, the etching method for the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 is dry etching or wet etching to remove the excess conductive metal layer and form the required pad structure.

[0095] In an embodiment, after step S122, etching the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6, it further includes:

[0096] Etching the patterned protective layer formed in the non-pad area to form the first isolation layer 12 and the second isolation layer 13.

[0097] In an embodiment, in step S13, forming the gradient flow grooves 7 in the first source pad 4, the first drain pad 5 and the two first gate pads 6 specifically includes the following steps:

[0098] Step S131: forming a patterned protective layer in the gradient area of the first source pad 4, the first drain pad 5 and the two first gate pads 6.

[0099] Step S132: etching the other areas according to the preset gradient to form the gradient flow groove 7.

[0100] In an embodiment, in step S14, the solder buffer layer 701 is formed in the gradient flow groove 7, specifically including the following steps:

[0101] Step S141: etching the patterned protection layer in each gradient of the gradient flow groove 7 to expose the pad surface to form the solder buffer layer 701.

[0102] In an embodiment, after step S141, etching the patterned protection layer in each gradient of the gradient flow groove 7 to expose the pad surface to form the solder buffer layer 701, further including:

[0103] Etching the solder buffer layer 701 to form a receiving groove 7011.

[0104] In an embodiment, in step S15, the plurality of bumps 2 are correspondingly soldered to the first source pad 4, the first drain pad 5, and the two first gate pads 6 before forming the die bonding layer 8 between the packaging substrate 1 and the flip chip 3, further including the following steps:

[0105] Etching the bottom of the first source pad 4 and the first drain pad 5 to form a plurality of solder counterbores 9;

[0106] Etching the bottom of the first source pad 4, the first drain pad 5, and the two first gate pads 6 to form a conductive pillar counterbore 10;

[0107] Depositing a conductive metal in the conductive pillar counterbore 10 to form a conductive pillar 11.

[0108] In an embodiment, in step S15, the plurality of bumps 2 are correspondingly soldered to the first source pad 4, the first drain pad 5, and the two first gate pads 6 to form the die bonding layer 8 between the packaging substrate 1 and the flip chip 3, specifically including the following steps:

[0109] Step S151: printing or dispensing solder paste in the first source pad 4, the first drain pad 5, and the two first gate pads 6;

[0110] Step S152: correspondingly abutting and pressing the plurality of bumps 2 of the flip chip 3 into the first source pad 4, the first drain pad 5, and the two first gate pads 6 by an external patch device;

[0111] Step S153: placing the patched packaging substrate 1 into an external reflow soldering furnace and heating to melt the solder and wet the pad surface, and forming the die bonding layer 8 after cooling.

[0112] The MOS flip chip packaging method of the present application will be described below through specific examples:

[0113] Example 1:

[0114] Step S21: providing a copper-coated ceramic substrate;

[0115] Step S22: forming a first source pad 4, a first drain pad 5 and two first gate pads 6 on the copper-coated ceramic substrate;

[0116] Step S23: forming a gradient flow groove 7 in the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0117] Step S24: forming a solder buffer layer 701 in the gradient flow groove 7;

[0118] Step S25: welding a plurality of bumps 2 with the first source pad 4, the first drain pad 5 and the two first gate pads 6 one by one to form a die bonding layer 8 between the copper-coated ceramic substrate and the flip chip 3.

[0119] In one embodiment, in step S22, forming the first source pad 4, the first drain pad 5 and the two first gate pads 6 on the copper-coated ceramic substrate specifically includes the following steps:

[0120] Step S221: coating photoresist on the front surface of the copper-coated ceramic substrate and exposing with a mask to define the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6, while forming a patterned protective layer in the non-pad area;

[0121] Step S222: etching the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6.

[0122] In one embodiment, after step S222, etching the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6, it further includes:

[0123] Etching the patterned protective layer formed in the non-pad area to expose the ceramic layer to form a first isolation layer 12 and a second isolation layer 13.

[0124] In one embodiment, in step S23, forming a gradient flow groove 7 in the first source pad 4, the first drain pad 5 and the two first gate pads 6 specifically includes the following steps:

[0125] Step S231: forming a patterned protection layer in the gradient region within the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0126] Step S232: etching the other regions according to a preset gradient to form the gradient flow grooves 7.

[0127] In an embodiment, in step S24, a solder buffer layer 701 is formed in the gradient flow grooves 7, specifically including the following steps:

[0128] Step S241: etching the patterned protection layer in each gradient of the gradient flow grooves 7 to expose the pad surface to form the solder buffer layer 701.

[0129] In an embodiment, after step S241, etching the patterned protection layer in each gradient of the gradient flow grooves 7 to expose the pad surface to form the solder buffer layer 701, further includes:

[0130] Etching the solder buffer layer 701 to form a receiving groove 7011.

[0131] In an embodiment, in step S25, before the flip chip 3 and the copper clad ceramic substrate are bonded to form the die bonding layer 8, further including:

[0132] Etching the bottom of the first source pad 4 and the first drain pad 5 to form a plurality of solder counterbores 9;

[0133] Etching the bottom of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form conductive pillar counterbores 10;

[0134] Depositing a conductive metal in the conductive pillar counterbores 10 to form conductive pillars 11.

[0135] In an embodiment, after the conductive metal is deposited in the conductive pillar counterbores 10 to form the conductive pillars 11, further including:

[0136] Coating photoresist on the reverse side of the copper clad ceramic substrate and exposing with a mask to define the patterned region of the second source pad 14, the second drain pad 15 and the two second gate pads 16;

[0137] Etching the patterned region of the second source pad 14, the second drain pad 15 and the two second gate pads 16 to form the second source pad 14, the second drain pad 15 and the two second gate pads 16.

[0138] In one embodiment, after the etching of the patterned areas of the second source pad 14, the second drain pad 15 and the two second gate pads 16 to form the second source pad 14, the second drain pad 15 and the two second gate pads 16, the method further comprises:

[0139] Exposing the photoresist within the second source pad 14, the second drain pad 15 and the two second gate pads 16 and using a mask to define the patterned areas;

[0140] Etching the patterned areas to form the solder sink 17.

[0141] In one embodiment, in step S25, the soldering of the bumps 2 to the first source pad 4, the first drain pad 5 and the two first gate pads 6 one by one to form the die bonding layer 8 between the copper clad ceramic substrate and the flip chip 3 comprises the following steps:

[0142] Step S251: printing or dispensing solder paste within the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0143] Step S252: abutting and pressing the bumps 2 of the flip chip 3 one by one into the first source pad 4, the first drain pad 5 and the two first gate pads 6 by an external patching device;

[0144] Step S253: coating epoxy resin glue on the copper clad ceramic substrate and the flip chip 3;

[0145] Step S254: placing the patched copper clad ceramic substrate into an external reflow soldering furnace and heating to melt the solder and wet the pad surface, and forming the die bonding layer 8 and the first encapsulation protection layer 19 after cooling.

[0146] In one embodiment, after placing the patched copper clad ceramic substrate into an external reflow soldering furnace and heating to melt the solder and wet the pad surface, and forming the die bonding layer 8 and the first encapsulation protection layer 19 in S254, the method further comprises:

[0147] Printing or dispensing solder paste on the back of the copper clad ceramic substrate;

[0148] Patching the first heat sink 18 to the designated area on the back of the copper clad ceramic substrate, and exposing a plurality of electrical through holes 1801;

[0149] Placing the patched copper clad ceramic substrate into an external reflow soldering furnace and heating to solidly connect the first heat sink 18 to the copper clad ceramic substrate.

[0150] In one embodiment, after placing the patched copper clad ceramic substrate into an external reflow soldering furnace and heating to solidly connect the first heat sink 18 to the copper clad ceramic substrate, the method further comprises:

[0151] cutting the copper clad ceramic substrate to form a plurality of independent packaging structures;

[0152] mounting the first shell 20 on each independent packaging structure.

[0153] Embodiment 1 of the present application uses a copper clad ceramic substrate as a packaging substrate, which can simultaneously exert the high insulation, low thermal expansion coefficient of ceramic and the excellent electrical conductivity and thermal conductivity of copper layer, significantly improving the thermal management capability, electrical performance and long-term reliability of the packaging structure.

[0154] Embodiment 2:

[0155] Step S31: providing a copper frame substrate;

[0156] Step S32: forming a first source pad 4, a first drain pad 5 and two first gate pads 6 on the copper frame substrate;

[0157] Step S33: forming a gradient flow groove 7 in the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0158] Step S34: forming a solder buffer layer 701 in the gradient flow groove 7;

[0159] Step S35: welding a plurality of bumps 2 with the first source pad 4, the first drain pad 5 and the two first gate pads 6 one by one to form a die bonding layer 8 between the copper frame substrate and the flip chip 3.

[0160] In one embodiment, in step S32, forming the first source pad 4, the first drain pad 5 and the two first gate pads 6 on the copper frame substrate specifically includes the following steps:

[0161] Step S321: coating photoresist on the front surface of the copper frame substrate and exposing with a mask to define the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6, while forming a patterned protective layer in the non-pad area;

[0162] Step S322: etching the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6.

[0163] In one embodiment, after step S322, etching the pattern area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6, it further includes:

[0164] Etching the patterned protective layer formed by the non-pad area to the opposite direction of the copper frame substrate by 2 / 3 to form the first isolation layer 12 and the second isolation layer 13.

[0165] In another embodiment, after the step S322 of etching the patterned area of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form the first source pad 4, the first drain pad 5 and the two first gate pads 6, further comprising:

[0166] Etching the patterned protective layer formed by the non-pad area to the opposite direction of the copper frame substrate by 2 / 3 to form the trench;

[0167] Depositing a ceramic material in the trench to form the first isolation layer 12 and the second isolation layer 13.

[0168] In one embodiment, the step S33 of forming the gradient flow groove 7 in the first source pad 4, the first drain pad 5 and the two first gate pads 6 comprises the following steps:

[0169] Step S331: forming a patterned protective layer in the gradient area of the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0170] Step S332: etching the other areas according to the preset gradient to form the gradient flow groove 7.

[0171] In one embodiment, the step S34 of forming the solder buffer layer 701 in the gradient flow groove 7 comprises the following steps:

[0172] Step S341: etching the patterned protective layer in each gradient of the gradient flow groove 7 to expose the pad surface to form the solder buffer layer 701.

[0173] In one embodiment, after the step S341 of etching the patterned protective layer in each gradient of the gradient flow groove 7 to expose the pad surface to form the solder buffer layer 701, further comprising:

[0174] Etching the solder buffer layer 701 to form the accommodation groove 7011.

[0175] In one embodiment, before the step S35 of welding the plurality of bumps 2 with the first source pad 4, the first drain pad 5 and the two first gate pads 6 one by one to form the die bonding layer 8 between the copper frame substrate and the flip chip 3, further comprising the following steps:

[0176] Etching the bottom of the first source pad 4 and the first drain pad 5 to form a plurality of solder counterbores 9;

[0177] etching the bottom of the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form a conductive post sink 10;

[0178] depositing a conductive metal in the conductive post sink 10 to form a conductive post 11.

[0179] In an embodiment, after depositing a conductive metal in the conductive post sink 10 to form a conductive post 11, further comprising:

[0180] soldering a plurality of pins 21 one by one on the conductive post 11 on the reverse side of the copper frame substrate.

[0181] In an embodiment, in step S35, soldering the plurality of bumps 2 one by one to the first source pad 4, the first drain pad 5 and the two first gate pads 6 to form a die bonding layer 8 between the copper frame substrate and the flip chip 3, specifically comprising the following steps:

[0182] step S351: printing or dotting solder paste in the first source pad 4, the first drain pad 5 and the two first gate pads 6;

[0183] step S352: abutting and pressing the plurality of bumps 2 of the flip chip 3 one by one into the first source pad 4, the first drain pad 5 and the two first gate pads 6 by an external patch device;

[0184] step S353: coating epoxy resin glue on the copper frame substrate and the flip chip 3, and exposing a plurality of pins 21;

[0185] step S354: placing the patched copper frame substrate into an external reflow soldering furnace and heating to melt the solder and wet the pad surface, and forming a die bonding layer 8 and a second packaging protection layer 23 after cooling.

[0186] In an embodiment, after placing the patched copper frame substrate into an external reflow soldering furnace and heating to melt the solder and wet the pad surface, and forming a die bonding layer 8 and a second packaging protection layer 23 in S354, further comprising:

[0187] printing or dotting solder paste on the reverse side of the copper frame substrate;

[0188] patching a second heat sink 22 to a designated area on the reverse side of the flip chip 3;

[0189] placing the patched copper frame substrate into an external reflow soldering furnace and heating so that the second heat sink 22 is fixedly connected to the flip chip 3.

[0190] In an embodiment, after placing the patched copper frame substrate into an external reflow soldering furnace and heating so that the second heat sink 22 is fixedly connected to the flip chip 3, further comprising:

[0191] cutting the copper frame substrate to form several independent packaging structures;

[0192] mounting the second shell 24 on each independent packaging structure.

[0193] The copper frame substrate adopted by the embodiment 2 of the present application has excellent electrical conductivity and thermal conductivity, which can effectively improve the electrical performance and heat dissipation efficiency of the packaging structure; it has high mechanical strength and low thermal expansion coefficient, which helps to improve the stability and reliability of the packaging structure and reduce the welding cracking or structural deformation caused by thermal stress; in addition, the copper frame is easy to form a complex lead pattern through etching or stamping process, which is suitable for high-density and small-size packaging requirements.

[0194] In addition, although one or more embodiments of the present application have been described above, it should be understood by those skilled in the art that the present application can be implemented in any other form without departing from the spirit and scope of the present application. Therefore, the above-described embodiments are illustrative rather than limiting, and many modifications and substitutions are obvious to those skilled in the art without departing from the spirit and scope of the present application as defined by the appended claims.

Claims

1. A MOS flip-chip package structure, characterized in that, Includes a packaging substrate and a flip chip with several bumps thereon; A first source pad, a first drain pad, and two first gate pads are formed on the front side of the packaging substrate. Gradient current guide grooves are formed in the first source pad, the first drain pad, and the two first gate pads. A solder buffer layer is formed in each gradient of the gradient current guide groove. When several bumps are soldered one-to-one with the first source pad, the first drain pad, and the two first gate pads, the gradient channel and the solder buffer layer can guide and fuse the solder generated by the melting of the bumps to form a die bond layer between the packaging substrate and the flip chip.

2. The MOS flip-chip packaging structure according to claim 1, characterized in that, The solder buffer layer is provided with a receiving groove for accommodating molten solder.

3. The MOS flip-chip packaging structure according to claim 2, characterized in that, The bottom of both the first source pad and the first drain pad has a plurality of solder countersunk holes for accommodating solder that flows back to its bottom.

4. The MOS flip-chip packaging structure according to claim 3, characterized in that, The first source pad, the first drain pad, and the two first gate pads are all provided with conductive post counterbore holes, and conductive posts are formed in the conductive post counterbore holes.

5. The MOS flip-chip packaging structure according to claim 4, characterized in that, The packaging substrate has a first isolation layer and a second isolation layer formed thereon for electrically isolating the first source pad and the first drain pad, and the first drain pad and the two first gate pads, respectively.

6. The MOS flip-chip package structure according to claim 5, characterized in that, The packaging substrate is a copper-clad ceramic substrate.

7. The MOS flip-chip package structure according to claim 6, characterized in that, The copper-clad ceramic substrate has a second source pad, a second drain pad, and two second gate pads formed on its reverse side. The second source pad, the second drain pad, and the two second gate pads are all connected to the first source pad, the first drain pad, and the two first gate pads one by one through conductive pillars.

8. The MOS flip-chip package structure according to claim 5, characterized in that, The packaging substrate is a copper frame substrate.

9. The MOS flip-chip package structure according to claim 8, characterized in that, The reverse side of the copper frame substrate is provided with a number of pins that correspond one-to-one with the conductive pillars in the first source pad, the first drain pad and the two first gate pads. The pins are used for electrical connection with external devices.

10. A method for packaging a MOS flip chip, characterized in that, The MOS flip-chip packaging method for forming the MOS flip-chip package structure as described in claim 1 includes: Provide a packaging substrate; A first source pad, a first drain pad, and two first gate pads are formed on the packaging substrate; Gradient current guide grooves are formed in the first source pad, the first drain pad, and the two first gate pads; A solder buffer layer is formed within the gradient flow channel; Several bumps are soldered one-to-one with the first source pad, the first drain pad, and two first gate pads to form a die bond layer between the package substrate and the flip chip.

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