Core particle module and packaging structure

Abstract

The embodiment of the invention provides a core particle module and a packaging structure, and the core particle module comprises a plurality of core particles and a controller, each core particle comprises a plurality of interface regions, and each interface region is configured to be capable of being matched with a plurality of interface regions of other core particles; the controller is configured to control interconnection among the plurality of core particles, and is configured to control an interface area of one of the plurality of core particles to be connected with a different interface area of another one of the plurality of core particles under the condition of different core particle arrangement.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor packaging, and in particular, to a chiplet module and a packaging structure. BACKGROUND

[0002] In the field of semiconductor packaging, chiplet technology can split a large chip into multiple small chips (or chiplets), and integrate these small chips together through packaging technology to achieve the function of a large chip. This chip architecture formed by integrating multiple small chips together can improve the performance of the chip, reduce costs, and shorten the development cycle. SUMMARY

[0003] According to at least one embodiment of the present disclosure, a chiplet module is provided, comprising: a plurality of chiplets, wherein each chiplet comprises a plurality of interface regions, and each interface region is configured to be able to match a plurality of interface regions of other chiplets; and a controller configured to control the interconnection between the plurality of chiplets, and configured to control a connection of an interface region of one of the plurality of chiplets to a different interface region of another of the plurality of chiplets in different chiplet arrangement cases.

[0004] In the chiplet module according to at least one embodiment of the present disclosure, each of the plurality of chiplets has a plurality of edges and a plurality of edge interface regions respectively disposed on the plurality of edges; and the controller is configured to control a connection of an edge interface region of one of the plurality of chiplets to an edge interface region of another of the plurality of chiplets located on a different edge in different chiplet arrangement cases.

[0005] In the chiplet module according to at least one embodiment of the present disclosure, each of the plurality of chiplets has a first edge and a second edge, and has a first edge interface region and a second edge interface region respectively located on the first edge and the second edge; and the controller is configured to control a connection of the first edge interface region of a first chiplet of the plurality of chiplets to the second edge interface region of a second chiplet of the plurality of chiplets in a first chiplet arrangement case, and control a connection of the first edge interface region of the first chiplet to a first edge interface region of the second chiplet in a second chiplet arrangement case.

[0006] In the chiplet module according to at least one embodiment of the present disclosure, the first chiplet arrangement case includes that the first chiplet and the second chiplet have the same orientation and are arranged in translation in a first arrangement direction parallel to a main surface of the chiplet, and the first edge interface region of the first chiplet and the second edge interface region of the second chiplet are opposite to each other in the first arrangement direction; and the second chiplet arrangement case includes that the first chiplet and the second chiplet are rotationally symmetrical to each other, and the first edge interface region of the first chiplet and the first edge interface region of the second chiplet are opposite to each other in the first arrangement direction.

[0007] According to at least one of the embodiments of the present disclosure, the plurality of core particles each further has a third edge and a fourth edge, and has a third edge interface region and a fourth edge interface region located at the third edge and the fourth edge respectively, wherein the third edge and the fourth edge extend in a direction intersecting with the first edge and the second edge; and the controller is configured to control the third edge interface region of the first core particle to be connected with the fourth edge interface region of a third core particle in the plurality of core particles in a third core particle arrangement, and to control the third edge interface region of the first core particle to be connected with a third edge interface region of the third core particle in a fourth core particle arrangement.

[0008] According to at least one of the embodiments of the present disclosure, the third core particle arrangement includes that the first core particle and the third core particle have the same orientation and are arranged in translation parallel to a second arrangement direction of a main surface of a core particle, and the third edge interface region of the first core particle and the fourth edge interface region of the third core particle are opposite to each other in the second arrangement direction; and the fourth core particle arrangement includes that the first core particle and the third core particle are rotationally symmetrical to each other, and the third edge interface region of the first core particle and the third edge interface region of the fourth core particle are opposite to each other in the second arrangement direction.

[0009] According to at least one of the embodiments of the present disclosure, the first edge and the second edge of the plurality of core particles have the same first length, and the third edge and the fourth edge of the plurality of core particles have the same second length, the first length being greater than or equal to the second length.

[0010] According to at least one of the embodiments of the present disclosure, the controller is further configured to control the first edge interface region of the first core particle to be connected with a third edge interface region or a fourth edge interface region of a second core particle in another core particle arrangement, the another core particle arrangement including that the first core particle and the second core particle are rotationally symmetrical to each other, and the first edge interface region of the first core particle and the third edge interface region or the fourth edge interface region of the second core particle are opposite to each other in the first arrangement direction.

[0011] According to at least one of the embodiments of the present disclosure, the first edge, the second edge, the third edge and the fourth edge of the plurality of core particles each have the same length.

[0012] According to at least one embodiment of the present disclosure, in a die module, one of the plurality of dies is a first connection die, another of the plurality of dies is a second connection die, and the first connection die and the second connection die are adjacent to each other and electrically connected; the first connection die comprises a first interface region, the first interface region comprises n first interfaces; the second connection die comprises a second interface region, the second interface region comprises n second interfaces, where n≥1; and the controller is configured to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a first connection order in a first die arrangement, and to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a second connection order in a second die arrangement, wherein in the first connection order, the i th first interface of the first connection die is configured to be connected with the i th second interface of the second connection die; and in the second connection order, the i th first interface of the first connection die is configured to be connected with the n-i+1 th second interface of the second connection die, where 1≤i≤n.

[0013] According to at least one embodiment of the present disclosure, in a die module, one of the plurality of dies is a first connection die, another of the plurality of dies is a second connection die, and the first connection die and the second connection die are adjacent to each other and electrically connected; the first connection die comprises a first interface region, the first interface region comprises n first interfaces; the second connection die comprises a second interface region, the second interface region comprises n second interfaces, where n≥1; and the controller is configured to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a first connection order in a first die arrangement, and to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a second connection order in a second die arrangement, wherein in the first connection order, the i th first interface of the first connection die is configured to be connected with the i th second interface of the second connection die; and in the second connection order, the i th first interface of the first connection die is configured to be connected with the n-i+1 th second interface of the second connection die, where 1≤i≤n.

[0014] According to at least one embodiment of the present disclosure, in a die module, one of the plurality of dies is a first connection die, another of the plurality of dies is a second connection die, and the first connection die and the second connection die are adjacent to each other and electrically connected; the first connection die comprises a first interface region, the first interface region comprises n first interfaces; the second connection die comprises a second interface region, the second interface region comprises n second interfaces, where n≥1; and the controller is configured to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a first connection order in a first die arrangement, and to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a second connection order in a second die arrangement, wherein in the first connection order, the i th first interface of the first connection die is configured to be connected with the i th second interface of the second connection die; and in the second connection order, the i th first interface of the first connection die is configured to be connected with the n-i+1 th second interface of the second connection die, where 1≤i≤n.

[0015] According to at least one embodiment of the present disclosure, in a die module, one of the plurality of dies is a first connection die, another of the plurality of dies is a second connection die, and the first connection die and the second connection die are adjacent to each other and electrically connected; the first connection die comprises a first interface region, the first interface region comprises n first interfaces; the second connection die comprises a second interface region, the second interface region comprises n second interfaces, where n≥1; and the controller is configured to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a first connection order in a first die arrangement, and to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a second connection order in a second die arrangement, wherein in the first connection order, the i th first interface of the first connection die is configured to be connected with the i th second interface of the second connection die; and in the second connection order, the i th first interface of the first connection die is configured to be connected with the n-i+1 th second interface of the second connection die, where 1≤i≤n.

[0016] According to at least one embodiment of the present disclosure, in a die module, one of the plurality of dies is a first connection die, another of the plurality of dies is a second connection die, and the first connection die and the second connection die are adjacent to each other and electrically connected; the first connection die comprises a first interface region, the first interface region comprises n first interfaces; the second connection die comprises a second interface region, the second interface region comprises n second interfaces, where n≥1; and the controller is configured to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a first connection order in a first die arrangement, and to control the first interface region of the first connection die and the second interface region of the second connection die to be connected in a second connection order in a second die arrangement, wherein in the first connection order, the i th first interface of the first connection die is configured to be connected with the i th second interface of the second connection die; and in the second connection order, the i th first interface of the first connection die is configured to be connected with the n-i+1 th second interface of the second connection die, where 1≤i≤n.

[0017] According to at least one embodiment of the present disclosure, the plurality of core particles are arranged in an array along a first arrangement direction and / or a second arrangement direction parallel to the main surface of the core particle, and any two adjacent core particles in the plurality of core particles are configured to be arranged in translation with the same orientation or to be rotationally symmetric to each other along the first arrangement direction or the second arrangement direction.

[0018] According to at least one embodiment of the present disclosure, a package structure is provided, comprising: the core particle module according to any one of the above; and an interconnection member, wherein the plurality of core particles are electrically connected to each other through the interconnection member. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, and not limit the present disclosure.

[0020] FIG. 1A and FIG. 1B A schematic plan view of a core particle module according to some embodiments of the present disclosure is shown.

[0021] FIG. 2A to FIG. 2D A schematic plan view of a core particle module according to some other embodiments of the present disclosure is shown.

[0022] FIG. 3A to FIG. 3D A schematic plan view of a core particle module according to yet some other embodiments of the present disclosure is shown.

[0023] FIG. 4A and FIG. 4B A schematic plan view of a core particle module according to still some other embodiments of the present disclosure is shown.

[0024] FIG. 5A and FIG. 5B A schematic view of the interconnection between core particles in a core particle module according to some embodiments of the present disclosure is shown.

[0025] FIG. 6A to FIG. 6C A schematic plan view of a core particle according to some embodiments of the present disclosure is shown.

[0026] FIG. 7 A schematic plan view of a package structure according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0029] Chip-based technology breaks down large chips into multiple smaller chips (i.e., chips), allowing each chip to be made smaller, reducing chip design complexity and cycle time, and improving product yield. With the continuous development of chip manufacturing and packaging processes, the bandwidth requirements for chips are increasing, while the power consumption and chip width occupied by chips are expected to decrease. Based on these bandwidth and width requirements, chips can have multiple interface areas. When a chip includes multiple interface areas, maximizing chip reuse and optimizing interconnections between chips is a crucial research topic in chip-based technology.

[0030] This disclosure provides a core module, including: a plurality of cores, wherein each core includes a plurality of interface areas, and each interface area is configured to match multiple interface areas of other cores; and a controller configured to control the interconnection between the plurality of cores, and configured to control an interface area of ​​one of the plurality of cores to connect with a different interface area of ​​another of the plurality of cores in different core arrangement conditions.

[0031] In the chip module of this disclosure embodiment, each interface area of ​​each chip can be matched with multiple interface areas of other chips, and the controller supports the connection of the interface area of ​​each chip to different interface areas of other chips under different chip arrangements, thereby enabling the chips to be interconnected in multiple arrangements and connection methods, thereby improving the reuse rate of chips and the flexibility of chip arrangement and connection, and thus significantly saving the cost of chip fabrication.

[0032] In this document, configuring a certain interface area of ​​a core to match multiple interface areas of other cores means that the interface area of ​​that core has a matching interface with each of the multiple interface areas of other cores, and the matching interfaces can transmit signals when connected. The interface area of ​​a core is connected to the corresponding interface area of ​​other cores based on the corresponding core arrangement, and is not limited to being simultaneously connected to multiple interface areas of other cores. In some embodiments, within a core module, the interface areas of cores can be connected one-to-one.

[0033] FIG. 1A to FIG. 4B A schematic plan view of a chip module according to some embodiments of the present disclosure is shown, which schematically illustrates a planar arrangement of a plurality of chips in the chip module.

[0034] In some embodiments, the chip module 500 includes a plurality of chips 100, and each chip 100 includes a plurality of interface regions IR; the plurality of chips 100 are interconnected, and the interface region of each chip is electrically connected to a corresponding interface region of another chip. Each interface region is configured to match multiple interface regions of other chips. For example, the chip module also includes a controller configured to control the interconnection between the plurality of chips 100 and to support any interface region IR of one of the plurality of chips to be connected to a different interface region IR of another of the plurality of chips in different chip arrangements. In some embodiments, the controller may include control modules (not shown) embedded in the interconnected chips; alternatively, the controller may be or include control modules disposed in a separate control chip, which is not limited herein.

[0035] refer to FIG. 1A to FIG. 3D In some embodiments, the multiple interface regions IR of each core chip include interface region 1, interface region 2, interface region 3, interface region 4, interface region 5, interface region 6, interface region 7, and interface region 8, wherein each interface region can be matched with multiple interface regions of other core chips. Taking interface region 1 as an example, the interface region 1 of each core chip can be matched with interface regions 6 and 2 of other core chips, and can be connected to interface regions 6 of other core chips or to interface regions 2 based on the arrangement of the core chips.

[0036] For example, FIG. 1A and FIG. 1B The diagram shows two possible arrangements of two core particles 100. For ease of description, the core particle 100 on the left side of the diagram is referred to as the first core particle D1, and the core particle 100 on the right side of the diagram is referred to as the second core particle D2. FIG. 1A In the shown core arrangement, the first core D1 and the second core D2 are arranged along the first arrangement direction AD1. Interface regions 1 and 2 of the first core D1 are respectively opposite to and electrically connected to interface regions 6 and 5 of the second core D2 along the first arrangement direction AD1. FIG. 1BIn the illustrated core arrangement, the first core D1 and the second core D2 are arranged along the first arrangement direction AD1. Interface regions 1 and 2 of the first core D1 are respectively opposite to and connected to interface regions 2 and 1 of the second core D2 along the first arrangement direction AD1. In this document, "two interface regions opposite each other in an arrangement direction" means that the two interface regions face each other and at least partially overlap in that arrangement direction.

[0037] For example, the controller controls the interface area 1 of the first core D1 to connect with the interface area 6 of the second core D2 in the first core arrangement, and controls the interface area 1 of the first core D1 to connect with the interface area 2 of the second core D2 in the second core arrangement. For example, the controller controls the interface area 2 of the first core D1 to connect with the interface area 5 of the second core D2 in the first core arrangement, and controls the interface area 2 of the first core D1 to connect with the interface area 1 of the second core D2 in the second core arrangement.

[0038] In some embodiments, each of the plurality of cores has a plurality of sides and a plurality of edge interface regions respectively disposed on the plurality of sides; the controller is configured to control an edge interface region of one of the plurality of cores to connect with an edge interface region of another of the plurality of cores located on a different side in different core arrangements.

[0039] In some embodiments, each of the plurality of cores has a first side and a second side, and has a first side interface region and a second side interface region located on the first side and the second side, respectively; and the controller is configured to control the first side interface region of the first core in the plurality of cores to connect with the second side interface region of the second core in the plurality of cores in the second core arrangement, and to control the first side interface region of the first core to connect with the first side interface region of the second core in the second core arrangement.

[0040] In some embodiments, the first core arrangement includes the first core and the second core having the same orientation and being arranged in a translational direction parallel to the main surface of the core, such that the first side interface region of the first core and the second side interface region of the second core are opposite to each other in the first arrangement direction; the second core arrangement includes the first core and the second core being rotationally symmetrical to each other, and the first side interface region of the first core and the first side interface region of the second core being opposite to each other in the first arrangement direction.

[0041] The first side and the second side are two different sides of the core. In some embodiments, the first side and the second side may be parallel to each other on the core, or they may be intersecting sides of the core. The following example illustrates this with the first side and the second side being parallel to each other. (Reference) FIG. 1A andFIG. 1B For example, each core 100 has multiple core edges, including a first edge S1, a second edge S2, a third edge S3, and a fourth edge S4, and includes multiple edge interface regions respectively disposed on the multiple core edges. For example, the first edge S1 and the second edge S2 are parallel to each other, the third edge S3 and the fourth edge S4 are parallel to each other, and the extending directions of the third edge S3 and the fourth edge S4 intersect with the extending directions of the first edge S1 and the second edge S2, for example, perpendicularly. Here, a core edge refers to the edge (i.e., sidewall) of the core, and an edge interface region located on a core edge means that the edge interface region is disposed close to the core edge.

[0042] For example, the multiple edge interface regions of the core 100 include two or more edge interface regions selected from the following: first edge interface region 101 located on the first side S1, second edge interface region 102 located on the second side S2, third edge interface region 103 located on the third side S3, and fourth edge interface region 104 located on the fourth side S4. Setting multiple interface regions on multiple sides of the core can increase the core's bandwidth and allow for a smaller core size. In this paper, the terms first edge interface region, second edge interface region, third edge interface region, and fourth edge interface region are used only to distinguish interface regions located on different core edges, and do not impose restrictions on the type of each interface region.

[0043] For example, in some examples, the first edge interface area 101 includes interface area 1 and interface area 2, the second edge interface area 102 includes interface area 5 and interface area 6, the third edge interface area 103 includes interface area 3 and interface area 4, and the fourth edge interface area 104 includes interface area 7 and interface area 8. It should be understood that the number of interface areas included in each edge interface area shown in the figure is merely illustrative. In other examples, the edge interface area may also include a single interface area or two or more interface areas, and this disclosure does not impose any limitations on this.

[0044] In some embodiments, the first side interface region 101 and the second side interface region 102 of each core are each configured to match multiple edge interface regions of other cores, for example, they can match the first side interface region 101 and the second side interface region 102 of other cores.

[0045] For example, such as FIG. 1AAs shown, the controller is configured to connect the first side interface region 101 of the first core D1 and the second side interface region 102 of the second core D2 in the first core arrangement. For example, in the first core arrangement, the first core D1 and the second core D2 have the same orientation and are arranged in a translational direction AD1 parallel to the main surface of the core; the first side interface region 101 of the first core D1 and the second side interface region 102 of the second core D2 are opposite to each other in the first arrangement direction AD1, so that the first side interface region 101 and the second side interface region 102 can be connected with a shorter interconnection distance. Multiple core translational arrangement refers to multiple cores translating relative to each other in a direction parallel to the main surface of the core without any change in orientation such as rotation.

[0046] like FIG. 1B As shown, the controller is configured to control the mating connection of the first side interface region 101 of the first core D1 and the first side interface region 101 of the second core D2 in the second core arrangement. For example, in the second core arrangement, the first core D1 and the second core D2 have different orientations, for example, they can be rotationally symmetrical to each other; the first side interface region 101 of the first core D1 and the first side interface region 101 of the second core D2 can be opposite each other in the first arrangement direction AD1, so that they can be connected with a shorter interconnection distance.

[0047] In this paper, rotational symmetry of multiple components means that the orientation of one component after rotation around a certain angle is the same as the orientation of another component, but it does not require that the rotated component completely coincide with the orientation of the other component. For example, in FIG. 1B In the example shown, the orientation of the second core D2 after rotating 180° is the same as that of the first core D1.

[0048] The orientation of a core chip includes the orientation of each edge of the core chip and their relative positional relationships. Multiple core chips having the same orientation means that the corresponding edges of multiple core chips have the same orientation, and the relative positional relationships between the edges are also the same. For example, in... FIG. 1A In the example shown, the first core D1 and the second core D2 have the same orientation, wherein the first side S1, the second side S2, the third side S3 and the fourth side S4 of each core are respectively facing right, left, down and up.

[0049] exist FIG. 1B In the example shown, the first core D1 and the second core D2 have different orientations, for example, they are rotated 180 degrees relative to each other. The first side S1, the second side S2, the third side S3 and the fourth side S4 of the first core D1 face right, left, down and up respectively, while the first side S1, the second side S2, the third side S3 and the fourth side S4 of the second core D2 face left, right, up and down respectively.

[0050] In some embodiments, multiple chips 100 have the same interface region configuration, for example, they may be identical chips formed using the same semiconductor process. That is, in addition to having the same interface region configuration, the internal structures of the multiple chips 100 are also substantially the same. In other embodiments, multiple chips 100 have the same interface region configuration, but may be chips formed using different semiconductor processes. For example, although these chips 100 have the same interface region configuration, their internal structures may be different, for example, they may include different functional modules.

[0051] In some embodiments, a plurality of cores 100 of the core module may be arranged in an array comprising one or more rows and / or one or more columns. Here, the array may include a single-row array, a single-column array, or an array comprising multiple rows and columns.

[0052] FIG. 1A and FIG. 1B An example is shown where multiple cores 100 are arranged in a single-row array. For example, multiple cores 100 are arranged in a row along a first arrangement direction AD1, wherein the first side and the second side of each core extend parallel to each other in a direction intersecting (e.g., perpendicular) to the first arrangement direction AD1, and are opposite to each other in the first arrangement direction AD1. In these examples, the core 100 may include at least a first side interface region 101 and a second side interface region 102, and may optionally include (e.g., omit) a third side interface region 103 and a fourth side interface region 104.

[0053] FIG. 2A to FIG. 2D An example is shown where multiple cores 100 are arranged in a multi-row, multi-column array. In some embodiments, each side of a core 100 may be provided with an edge interface region, which may facilitate the expansion of the core array.

[0054] In some embodiments, each of the plurality of cores further has a third-side interface region and a fourth-side interface region located on the third side and the fourth side, respectively, wherein the extending directions of the third side and the fourth side intersect the extending directions of the first side and the second side; the controller is configured to control the third-side interface region of the first core to connect with the fourth-side interface region of the third core among the plurality of cores when the third cores are arranged, and to control the third-side interface region of the first core to connect with the third-side interface region of the third core when the fourth core is arranged.

[0055] In some embodiments, the third core arrangement includes the first core and the third core having the same orientation and being arranged in a translational direction parallel to the main surface of the core, and the third side interface region of the first core and the fourth side interface region of the third core being opposite to each other in the second arrangement direction; the fourth core arrangement includes the first core and the third core being rotationally symmetrical to each other, and the third side interface region of the first core and the third side interface region of the fourth core being opposite to each other in the second arrangement direction.

[0056] refer to FIG. 2A to FIG. 2D In some embodiments, multiple cores 100 are arranged in an array comprising multiple rows and columns along a first arrangement direction AD1 and a second arrangement direction AD2. The first arrangement direction AD1 and the second arrangement direction AD2 intersect each other, for example, substantially perpendicular to each other. For example, the first arrangement direction AD1 is a row direction and the second arrangement direction AD2 is a column direction, or vice versa. Exemplarily, in each core, the first side S1 and the second side S2 extend in the same direction as the second arrangement direction AD2, and the first side S1 and the second side S2 are opposite to each other in a direction perpendicular to the extension direction; the third side S3 and the fourth side S4 extend in the same direction as the first arrangement direction AD1, and are opposite to each other in a direction perpendicular to the extension direction.

[0057] In some embodiments, the third side interface region 103 and the fourth side interface region 104 of each core are each configured to match multiple interface regions of other cores, such as the third side interface region 103 and the fourth side interface region 104 of other cores, and can be connected to the third side interface region 103 of other cores or the fourth side interface region 104 of other cores under the control of the controller based on the core arrangement.

[0058] For example, the multiple cores 100 include a first core D1, a second core D2, a third core D3, and a fourth core D4. Taking the first core D1 as an example, in... FIG. 2A , FIG. 2B In the illustrated core arrangement, the third side interface region 103 of the first core D1 is connected to the fourth side interface region 104 of the third core D3; FIG. 2C , FIG. 2D In the shown core arrangement, the third side interface region 103 of the first core D1 is connected to the third side interface region 103 of the third core D3.

[0059] For example, in FIG. 2A and FIG. 2B In the core arrangement shown, the interface area 3 and interface area 4 of the third side interface area 103 of the first core D1 are connected to the interface area 8 and interface area 7 of the fourth side interface area 104 of the third core D3, respectively.

[0060] like FIG. 2A and FIG. 2B As shown, the first core D1 and the third core D3 have the same orientation and are arranged in a translational manner in the second arrangement direction AD2. The third side S3 of the first core D1 and its third side interface area 103 and the fourth side S4 of the third core D3 and its fourth side interface area 104 are opposite to each other in the second arrangement direction AD2, so that the corresponding interfaces of the first core D1 and the third core D3 can be connected with a shorter interconnection distance.

[0061] For example, in FIG. 2C and FIG. 2D In the shown core arrangement, the interface area 3 and interface area 4 of the third side interface area 103 of the first core D1 are connected to the interface area 4 and interface area 3 of the third side interface area 103 of the third core D3, respectively.

[0062] like FIG. 2C and FIG. 2D As shown, the first core D1 and the third core D3 have different orientations, for example, they are rotationally symmetrical to each other. The third side S3 of the first core D1 and its third side interface region 103 are opposite to each other in the second arrangement direction AD2, so that the corresponding interfaces of the first core D1 and the third core D3 can be connected with a shorter interconnection distance. For example, the orientation of the third core D3 after rotating 180° along a direction parallel to the main surface of the core is the same as the orientation of the first core D1.

[0063] refer to FIG. 2A to FIG. 2D The arrangement and connection of the other adjacent core particles arranged in the second arrangement direction AD2 are similar to those described above for the first core particle D1 and the third core particle D3, and will not be repeated here.

[0064] The arrangement and connection method of adjacent core particles in the first arrangement direction AD1 are the same as those mentioned above. FIG. 1A and FIG. 1B The descriptions of the first core D1 and the second core D2 are similar.

[0065] For example, the first side interface region 101 and the second side interface region 102 of each core particle are each configured to match the first side interface region 101 and the second side interface region 102 of other core particles, and can be connected to the first side interface region 101 or the second side interface region 102 of other core particles based on the core particle arrangement. For example, in FIG. 2A In the shown core arrangement, the first core D1 and the second core D2 have the same orientation and are arranged in a translational manner along the first arrangement direction AD1; the first side interface region 101 of the first core D1 is connected to the second side interface region 102 of the second core D2.

[0066] existFIG. 2B to FIG. 2D In the illustrated core arrangement, the first core D1 and the second core D2 have different orientations, for example, they are rotationally symmetrical to each other. For example, the orientation of the second core D2 after rotating 180 degrees is the same as that of the first core D1; the first side interface region 101 of the first core D1 is connected to the first side interface region 101 of the second core.

[0067] FIG. 2A to FIG. 2D The present disclosure exemplifies only some connection methods of the first core D1 and the second core D2, and is not limited thereto. In other examples, the second side S2 of the first core D1 may be opposite to the second side S2 of the second core D2 in the first arrangement direction AD1, and the second side interface area 102 of the first core D1 may be connected to the second side interface area 102 of the second core D2. In still other examples, the second side S2 of the first core D1 may be opposite to the first side S1 of the second core D2 in the first arrangement direction AD1, and the second side interface area 102 of the first core D1 may be connected to the first side interface area 101 of the second core D2.

[0068] The arrangement and connection of the third core D3 and the fourth core D4 are similar to those described above for the first core D1 and the second core D2, and will not be repeated here. Within the same core module, the arrangement and connection of the first core D1 and the second core D2 may be the same as or different from those of the third core D3 and the fourth core D4.

[0069] In some embodiments, the first and second sides of the plurality of core particles have the same first length, and the third and fourth sides of the plurality of core particles have the same second length, wherein the first length is greater than or equal to the second length.

[0070] refer to FIG. 2A to FIG. 2D For example, the first side S1 and the second side S2 of multiple core particles 100 have the same first length, and the third side S3 and the fourth side S4 of multiple core particles 100 have the same second length. For example, the core particle 100 may be rectangular in shape, and the first length is greater than the second length; the first side S1 and the second side S2 may be collectively referred to as the long side, and the third side S3 and the fourth side S4 may be collectively referred to as the short side. In this embodiment, each interface area of ​​each core particle located on each long side can be matched with any interface area of ​​other core particles located on any long side, and can be connected to the long side interface area of ​​the corresponding core particle based on the corresponding core particle arrangement; each interface area of ​​each core particle located on each short side can be matched with any interface area of ​​other core particles located on any short side, and can be connected to the short side interface area of ​​the corresponding core particle based on the corresponding core particle arrangement.

[0071] For example, the first side interface region 101 of each core 100 can be matched with the first side interface region 101 and the second side interface region 102 of any other core 100, and the controller can be configured to control the first side interface region 101 of one core 100 to be connected to the first side interface region 101 of another core 100 in one core arrangement, and to control the first side interface region 101 of the core 100 to be connected to the second side interface region 102 of another core 100 in another core arrangement.

[0072] Correspondingly, the second side interface region 102 of each core 100 can be matched with the first side interface region 101 and the second side interface region 102 of any other core 100, and the controller can be configured to control the second side interface region 102 of one core 100 to connect with the first side interface region 101 of another core 100 in one core arrangement, and to control the second side interface region 102 of the core 100 to connect with the second side interface region 102 of another core 100 in another core arrangement. In some embodiments, unless otherwise defined, if two interface regions are connected to each other, the core edges where the two interface regions are located are adjacent to each other and face each other, thereby reducing the connection distance between the two interface regions.

[0073] For example, the third side interface region 103 of each core 100 can be matched with the third side interface region 103 and the fourth side interface region 104 of any other core 100, and the controller can be configured to control the third side interface region 103 of one core 100 to be connected to the third side interface region 103 of another core 100 in one core arrangement, and to control the third side interface region 103 of the core 100 to be connected to the fourth side interface region 104 of another core 100 in another core arrangement. Correspondingly, the fourth side interface region 104 of each core 100 can be matched with the third side interface region 103 and the fourth side interface region 104 of any other core 100, and the controller can be configured to control the fourth side interface region 104 of one core 100 to connect with the third side interface region 103 of another core 100 in one core arrangement, and to control the fourth side interface region 104 of the core 100 to connect with the fourth side interface region 104 of another core 100 in another core arrangement.

[0074] Because each interface area of ​​each chip can be matched with multiple interface areas of other chips, and connections can be made between different interface areas of other chips based on different chip arrangements, the reuse and interconnection of the same chip are supported and improved, significantly reducing tape-out costs. The arrangement and connection methods of multiple chips can be more flexible. For example, regardless of whether multiple chips are arranged by translation or rotation, interconnection between chips can be achieved with a shorter interconnection distance. For example, in a chip module, multiple chips may include chips facing the same direction and / or chips facing different directions. In each pair of adjacent chips that are connected to each other, the orientations of the two adjacent chips may be the same or different.

[0075] For example, among multiple cores 100, the orientation of the first core D1 is used as the reference orientation, and the orientations of the other cores can be the same as the reference orientation, or they can be different from the reference orientation, for example, rotated 180 degrees relative to the reference orientation.

[0076] For example, such as FIG. 2A As shown, all cores 100 have the same orientation, i.e., none are rotated. The interface regions 1 and 2 of the first side S1 of the first core D1 are respectively opposite to and electrically connected to the interface regions 6 and 5 of the second side S2 of the second core D2 in the first arrangement direction AD1; the interface regions 3 and 4 of the third side S3 of the first core D1 are respectively opposite to and electrically connected to the interface regions 8 and 7 of the third core D3 in the second arrangement direction AD2; the interface regions 3 and 4 of the third side S3 of the second core D2 are respectively opposite to and electrically connected to the interface regions 8 and 7 of the fourth side S4 of the fourth core D4 in the second arrangement direction AD2; the interface regions 1 and 2 of the first side S1 of the third core D3 are respectively opposite to and electrically connected to the interface regions 6 and 5 of the second side S2 of the fourth core D4 in the first arrangement direction AD1.

[0077] For example, refer to FIG. 2B In some embodiments, some cores in a plurality of cores have the same orientation, while another portion of cores have a different orientation, for example, rotated 180 degrees relative to the first portion of cores. In some embodiments, adjacent cores arranged in a first arrangement direction have different orientations and are rotationally symmetrical to each other, for example, rotated 180 degrees relative to each other; adjacent cores arranged in a second arrangement direction have the same orientation.

[0078] For example, the first core D1 and the third core D3 have the same first orientation, and the second core D2 and the fourth core D4 have the same second orientation and are rotationally symmetrical with respect to the first core D1 and the third core D3. For example, the second orientation is rotated 180 degrees relative to the first orientation.

[0079] In this embodiment, interface regions 1 and 2 of the first side S1 of the first core particle D1 are respectively opposite to and electrically connected to interface regions 2 and 1 of the first side S1 of the second core particle D2 in the first arrangement direction AD1; interface regions 7 and 8 of the fourth side S4 of the second core particle D2 are respectively opposite to and electrically connected to interface regions 4 and 3 of the third side S3 of the fourth core particle D4 in the second arrangement direction AD2; interface regions 1 and 2 of the first side S1 of the third core particle D3 are respectively opposite to and electrically connected to interface regions 2 and 1 of the first side of the fourth core particle D4 in the first arrangement direction AD1. The connection method of the first core particle D1 and the third core particle D3 is the same as... FIG. 2A The same applies as shown, so I will not repeat it here.

[0080] refer to FIG. 2C In some embodiments, adjacent core particles arranged in the first arrangement direction AD1 have different orientations and are rotationally symmetrical with each other, for example, they may be rotated 180 degrees relative to each other; and adjacent core particles arranged in the second arrangement direction AD2 have different orientations and are rotationally symmetrical with each other, for example, they may be rotated 180 degrees relative to each other. For example, the first core particle D1 and the fourth core particle D4 have the same first orientation, and the second core particle D2 and the third core particle D3 have the same second orientation and are rotationally symmetrical with respect to the first core particle D1 and the fourth core particle D4. For example, the second orientation is rotated 180 degrees relative to the first orientation.

[0081] In this embodiment, the connection method of the first core D1 and the second core D2 is the same as... FIG. 2B The same as shown; the interface regions 3 and 4 of the third side S3 of the first core D1 are respectively opposite to and electrically connected to the interface regions 4 and 3 of the third core D3 in the second arrangement direction AD2; the interface regions 7 and 8 of the fourth side S4 of the second core D2 are respectively opposite to and electrically connected to the interface regions 8 and 7 of the fourth core D4; the interface regions 5 and 6 of the second side S2 of the third core D3 are respectively opposite to and electrically connected to the interface regions 6 and 5 of the second side S2 of the fourth core D4 in the first arrangement direction AD1.

[0082] refer to FIG. 2D In some embodiments, the first core D1 has a first orientation, and the other second cores D2, third core D3, and fourth core D4 all have the same second orientation and are rotationally symmetrical with respect to the first core D1. For example, the second orientation is rotated 180 degrees relative to the first orientation.

[0083] In this embodiment, the connection method of the first core particle D1 and the second core particle D2, as well as the connection method of the first core particle D1 and the third core particle D3, are the same as those described above. FIG. 2C The same applies as shown, and will not be repeated here. Interface regions 7 and 8 of the fourth side S4 of the second core D2 are respectively opposite to and electrically connected to interface regions 4 and 3 of the third side S3 of the fourth core D4 in the second arrangement direction AD2. Interface regions 5 and 6 of the second side S2 of the third core D3 are respectively opposite to and electrically connected to interface regions 2 and 1 of the first side S1 of the fourth core D4 in the first arrangement direction AD1.

[0084] In some embodiments, the controller is further configured to control the connection of the first side interface region of the first core to the third side interface region or the fourth side interface region of the second core in another core arrangement, wherein the other core arrangement includes rotational symmetry between the first core and the second core, and the first side interface region of the first core and the third side interface region or the fourth side interface region of the second core are opposite to each other in the first arrangement direction.

[0085] In some embodiments, the first, second, third, and fourth sides of the plurality of core particles have the same length.

[0086] FIG. 3A to FIG. 3D A schematic plan view of a chip module according to other embodiments of the present disclosure is shown.

[0087] In some embodiments, the interface area of ​​each edge in each core can be configured to match two or more edge interface areas of other cores, for example, it can match the edge interface area of ​​each edge in multiple edge interface areas of other cores, and can be connected to the interface area of ​​the corresponding edge based on the corresponding core arrangement under the control of the controller.

[0088] refer to FIG. 3A to FIG. 3D For example, each of the first side interface area 101, second side interface area 102, third side interface area 103, and fourth side interface area 104 of each of the plurality of cores 100 is configured to match the first side interface area 101, second side interface area 102, third side interface area 103, and fourth side interface area 104 of the other cores 100, and for example, can be connected to the first side interface area 101 of the other cores 100 under the control of the controller based on one core arrangement, connected to the second side interface area 102 of the other cores 100 under the control of the controller based on another core arrangement, connected to the third side interface area 103 of the other cores 100 under the control of the controller based on yet another core arrangement, and connected to the fourth side interface area 104 of the other cores 100 under the control of the controller based on yet another core arrangement.

[0089] In some embodiments, the multiple sides of each core 100 have the same side length and have substantially the same interface area arrangement. For example, the planar shape of the core 100 may be square, i.e., the first side S1, the second side S2, the third side S3, and the fourth side S4 have the same length.

[0090] In some embodiments, the interface region on each side of each chip 100 can be disposed opposite to and electrically connected to the interface region on any side of another chip 100. In this way, chip reuse can be further improved, chip fabrication costs can be reduced, and the flexibility of chip arrangement can be increased.

[0091] For example, such asFIG. 3A As shown, the first core D1 and the second core D2 are rotationally symmetrical to each other. For example, the orientation of the second core D2 is rotated 180 degrees relative to the orientation of the first core D1. The interface region 1 and interface region 2 (i.e., the first side interface region 101) of the first side S1 of the first core D1 are opposite to and electrically connected to the interface region 2 and interface region 1 (i.e., the first side interface region 101) of the first side S1 of the second core D2, respectively.

[0092] For example, such as FIG. 3B As shown, the first core D1 and the second core D2 have the same orientation and are arranged in a translational manner along the first arrangement direction AD1. The interface area 1 and interface area 2 of the first side S1 of the first core D1 (i.e., the first side interface area 101) are respectively opposite to and electrically connected to the interface area 6 and interface area 5 of the second side S2 of the second core D2 (i.e., the second side interface area 102).

[0093] For example, such as FIG. 3C As shown, the first core D1 and the second core D2 are rotationally symmetrical to each other. For example, the orientation of the second core D2 is rotated 90 degrees relative to the orientation of the first core D1. The interface regions 1 and 2 of the first side S1 of the first core D1 (i.e., the first side interface region 1) are respectively opposite to and electrically connected to the interface regions 4 and 3 of the third side S3 of the second core D2 (i.e., the third side interface region 103).

[0094] For example, such as FIG. 3D As shown, the first core D1 and the second core D2 are rotationally symmetrical to each other. For example, the orientation of the second core D2 is rotated 90 degrees relative to the orientation of the first core D1. The interface regions 1 and 2 of the first side S1 of the first core D1 (i.e., the first side interface region 1) are respectively opposite to and electrically connected to the interface regions 8 and 7 of the fourth side S4 of the second core D2 (i.e., the fourth side interface region 104).

[0095] It should be understood that FIG. 3A to FIG. 3D The number of cores included in the illustrated core module is for illustrative purposes only and is not intended to limit the scope of this disclosure. In some embodiments, the core module may further include multiple cores arranged in the column direction. Since each core has an interface area on all four sides, more cores can be added in both the row and column directions based on product requirements.

[0096] FIG. 3A to FIG. 3D The first edge interface region 101 of the first core particle is shown as an example of its connection with different edge interface regions of other core particles under different core particle arrangements. It should be understood that the first edge interface region 101 of the first core particle in these diagrams can also be replaced by the second edge interface region 102, the third edge interface region 103 or the fourth edge interface region 104.

[0097] In the above embodiments, the example is that the core has an interface area on all four sides, but this disclosure is not limited thereto.

[0098] In other embodiments, interface areas may not be provided on certain edges of the core 100. For example, when the core module includes only a single row of cores arranged along a first arrangement direction or only a single column of cores arranged along a second arrangement direction, interface areas may be provided on the edges of the cores perpendicular to the corresponding arrangement direction, while interface areas on the edges extending in the same direction as the arrangement direction may be omitted. For example, in FIG. 1A and FIG. 1B , FIG. 3A to FIG. 3D In the example shown, the core particles are arranged along a first arrangement direction AD1. Interface areas can be provided on the first side S1 and the second side S2, whose extension direction is perpendicular to the first arrangement direction AD1, while the interface areas on the third side S3 and the fourth side S4, whose extension direction is the same as the first arrangement direction AD1, can be omitted. In this example, multiple interface areas of the core particles are provided on two parallel sides, while interface areas can be omitted on the other two sides.

[0099] In other embodiments, the multiple interface areas of the core may also be located on two intersecting sides, while the other two sides may not have interface areas.

[0100] FIG. 4A and FIG. 4B A schematic plan view of a chip module according to other embodiments of the present disclosure is shown.

[0101] refer to FIG. 4A and FIG. 4B For example, each core 100 has a first side interface area 101 disposed on the first side S1 and a third side interface area 103 disposed on the third side S3. The first side interface area 101 and the third side interface area 103 of each core 100 can be matched with the first side interface area 101 and the third side interface area 103 of another core 100, and can be connected to the first side interface area 101 of another core 100 under the control of the controller based on the core arrangement, or connected to the third side interface area 103 of another core under the control of the controller based on the arrangement of another core.

[0102] In this example, the core module includes an odd number of cores, but the number of cores shown is for illustrative purposes only and is not limited thereto.

[0103] In some embodiments, one of the plurality of cores is a first connecting core, and the other of the plurality of cores is a second connecting core, wherein the first connecting core and the second connecting core are adjacent to each other and electrically connected; the first connecting core includes a first interface area, the first interface area including n first interfaces; the second connecting core includes a second interface area, the second interface area including n second interfaces, where n≥1; the controller is configured to control the first interface area of ​​the first connecting core and the second interface area of ​​the second connecting core to be connected in a first connection order in the first core arrangement, and to control the first interface area of ​​the first connecting core and the second interface area of ​​the second connecting core to be connected in a second connection order in the second core arrangement, wherein in the first connection order, the i-th first interface of the first connecting core is configured to be connected to the i-th second interface of the second connecting core; and in the second connection order, the i-th first interface of the first connecting core is configured to be connected to the (n-i+1)-th second interface of the second connecting core, where 1≤i≤n.

[0104] In some embodiments, one of the first and second core arrangement configurations includes the first and second connecting cores having the same orientation and being arranged in a translational manner in a direction parallel to the main surface of the core, and the other of the first and second core arrangement configurations includes the first and second connecting cores being rotationally symmetrical to each other.

[0105] In some embodiments, the rotational symmetry of the first connecting core and the second connecting core includes the orientation of the first connecting core and the orientation of the second connecting core rotating 180° or 90° relative to each other.

[0106] FIG. 5A and FIG. 5B The diagram shows an enlarged plan view of the interface areas in a chip module according to some embodiments of the present disclosure, illustrating different connection methods between the interface areas. For the sake of brevity, FIG. 5A and FIG. 5B Only the two connected interface areas of each core are shown, and the overall structure of the core is not shown.

[0107] refer to FIG. 5A and FIG. 5BIn some embodiments, the multiple cores in the core module include a first connecting core cd1 and a second connecting core cd2 that are adjacent to each other and electrically connected. The first connecting core cd1 includes a first interface region IR1 disposed near its core edge, and the first interface region IR1 includes n first interfaces; the second connecting core cd2 includes a second interface region IR2 disposed near its core edge, and the second interface region IR2 includes n second interfaces; where n≥1; FIG. 5A and FIG. 5B The example uses n=4. Each interface area may also include more than 4 interfaces; or, in other examples, each interface area may include 1, 2, or 3 interfaces. This disclosure does not limit the number of interfaces in an interface area. Double arrows in the diagram represent interconnections between interfaces.

[0108] In some embodiments, interconnected interface regions may have substantially the same interface configuration, such as having the same number of interfaces. For example, a first connecting core cd1 and a second connecting core cd2 are arranged along the arrangement direction AD, and a first interface region IR1 and a second interface region IR2 are opposite each other in the arrangement direction AD, with the extension direction of the core edge being substantially perpendicular to the arrangement direction AD. In some embodiments, the plurality of interfaces included in each of the first interface region IR1 and the second interface region IR2 are arranged along the length direction of their respective edges (i.e., substantially perpendicular to the arrangement direction AD). For example, the four first interfaces included in the first interface region IR1 are arranged in a direction perpendicular to the arrangement direction AD and are respectively numbered as the first interface 11 (or the first first interface), the second interface 12 (or the second first interface), the third interface 13 (or the third first interface), and the fourth interface 14 (or the fourth first interface). For example, the second interface area IR2 includes four second interfaces arranged in a direction perpendicular to the arrangement direction AD, and are respectively numbered as the first interface 11 (or the first second interface), the second interface 12 (or the second second interface), the third interface 13 (or the third second interface) and the fourth interface 14 (or the fourth second interface).

[0109] In some embodiments, the controller is configured to support the interface areas of the chip in multiple connection methods, such as supporting the chip interface areas to be connected in reverse connection order. For example, the controller may be configured to control the first interface area IR1 of the first connecting chip CD1 and the second interface area IR2 of the second connecting chip CD2 to be connected in a first connection order when the chips are arranged in a first chip arrangement, and to control the first interface area IR1 of the first connecting chip CD1 and the second interface area IR2 of the second connecting chip CD2 to be connected in a second connection order when the chips are arranged in a second chip arrangement.

[0110] For example, in the first connection sequence, the i-th first interface of the first connection core cd1 is connected to the i-th second interface of the second core, and in the second connection sequence, the i-th first interface of the first connection core cd1 is connected to the (n-i+1)-th second interface of the second core, where 1≤i≤n. i is the sequence number of the interface in the multiple sequentially arranged interfaces.

[0111] refer to FIG. 5A In some embodiments, the first connecting core cd1 and the second connecting core cd2 have the same orientation and are arranged in a translational manner along the arrangement direction AD. In this case, the first interface area IR1 and the second interface area IR2 have the same orientation, the multiple interfaces in each interface area are arranged in the same order, and the interfaces with the same serial number are opposite each other along the arrangement direction AD and can be electrically connected to each other under the control of the controller. For example, the first interface 11 of the first interface area IR1 is connected to the first interface 11 of the second interface area IR2; the second interface 12 of the first interface area IR1 is connected to the second interface 12 of the second interface area IR2; the third interface 13 of the first interface area IR1 is connected to the third interface 13 of the second interface area IR2; the fourth interface 14 of the first interface area IR1 is connected to the fourth interface 14 of the second interface area IR2, and so on.

[0112] refer to FIG. 5B In some embodiments, the first connecting core cd1 and the second connecting core cd2 have different orientations and are rotationally symmetrical with each other, for example, rotated 180 degrees relative to each other. In this case, the first interface region IR1 and the second interface region IR2 have different orientations, the arrangement order of multiple interfaces in each interface region is reversed, and the i-th interface in the first interface region IR1 is opposite to the (n-i+1)-th interface in the second interface region IR2 in the arrangement direction AD and can be electrically connected to each other under the control of the controller. For example, the first interface 11 of the first interface region IR1 is connected to the fourth interface 14 of the second interface region IR2; the second interface 12 of the first interface region IR1 is connected to the third interface 13 of the second interface region IR2; the third interface 13 of the first interface region IR1 is connected to the second interface 12 of the second interface region IR2; and the fourth interface 14 of the first interface region IR1 is connected to the first interface 11 of the second interface region IR2. This pattern continues when each interface region includes fewer or more interfaces.

[0113] In some embodiments, the chips can be interconnected using interface standards such as UCIe, PCIe, and XSR, or they can be interconnected using custom interface standards. This disclosure does not impose any limitations.

[0114] In the chip module of this embodiment, since the controller supports different connection orders between interface areas, that is, it supports the interface areas to be connected in a first connection order and the interface areas to be connected in a second connection order opposite to the first connection order, the chips can be arranged and connected in different ways, and can be interconnected with a smaller connection path in different arrangement cases.

[0115] For example, the first connecting core cd1 and the second connecting core cd2 may have the same orientation and be arranged in a translational manner along the arrangement direction AD, and the first interface region IR1 and the second interface region IR2 may be opposite to each other along the arrangement direction AD and connected by one of the first connection sequence and the second connection sequence (e.g., FIG. 5A The first connection sequence shown is used to connect the two components. For example, the first connecting core cd1 and the second connecting core cd2 are rotationally symmetrical to each other, and the first interface region IR1 and the second interface region IR2 are opposite to each other in the arrangement direction AD and are connected by another connection sequence (e.g., the first connection sequence and the second connection sequence). FIG. 5B (The second connection sequence shown) is connected.

[0116] In some embodiments, FIG. 1A to FIG. 4B and FIG. 1A to FIG. 4B The first connecting core cd1 and the second connecting core cd2 shown can be any of multiple cores arranged in any direction AD (e.g., FIG. 1A to FIG. 2D Two adjacent and electrically connected cores 100 in either the first arrangement direction AD1 or the second arrangement direction AD2 shown in the diagram can be, for example, FIG. 5A The adjacent first core D1 and second core D2, adjacent first core D1 and third core D3, adjacent second core D2 and fourth core D4, or adjacent third core D3 and fourth core D4 shown. The first interface area IR1 can be the edge interface area of ​​the corresponding core located on either side, and the second interface area IR2 can be the edge interface area of ​​the corresponding core located on either side.

[0117] refer to FIG. 5B as well as FIG. 5A and FIG. 5B In some embodiments, the interface areas on the same length sides of each core 100 have substantially the same interface configuration. For example, each interface area 1 / 2 / 5 / 6 in the first side interface area 101 and the second side interface area 102 has substantially the same interface configuration and number of interfaces, and the interface arrangement order of these interface areas may be the same or different. Taking the first core D1 and the second core D2 as examples, when the interface configuration and arrangement order of the first and second sides of each core 100 are the same, if the first core D1 and the second core D2 are arranged in a translated manner, then the first side interface area 101 of the first core D1 and the second side interface area 102 of the second core D2 adopt... FIG. 3A to FIG. 4BThe connection is performed in the order shown; when the first core D1 and the second core D2 are arranged in a rotationally symmetrical manner, the first side interface region 101 of the first core D1 and the first side interface region 101 of the second core D2 adopt... FIG. 5A The connections are made in the order shown. The connection methods for the third and fourth sides of each core are similar to those described above for the first and second sides, and will not be repeated here.

[0118] refer to FIG. 5B as well as FIG. 6A and FIG. 6B In some embodiments, the interface areas on all sides of each core 100 have substantially the same interface configuration, and since the controller supports different connection orders between interface areas, the interface areas of adjacent cores that are opposite each other in the arrangement direction can be connected regardless of how the cores are arranged (rotated or not rotated, rotated 90 degrees or 180 degrees), and the interconnection distance is small.

[0119] FIG. 6A and FIG. 6B A schematic plan view of a core according to some embodiments of the present disclosure is shown.

[0120] In some embodiments, each core includes an edge interface region located on a core edge, the edge interface region being symmetrically arranged with respect to an axis of symmetry perpendicular to the core edge, the axis of symmetry extending through the center of the core edge. The core edge can be any one of a first side, a second side, a third side, and a fourth side of the core, and correspondingly, the edge interface region can be any one of the first side interface region, the second side interface region, the third side interface region, and the fourth side interface region of the core.

[0121] In some embodiments, one or more of the plurality of core particles are each a single core particle, and the edge of the core particle is the edge of the single core particle; or one or more of the plurality of core particles are each a core particle combination including a plurality of sub-core particles, and the edge of the core particle is the edge of the corresponding sub-core particle or a combined edge composed of the edges of the plurality of sub-core particles in the core particle combination.

[0122] FIG. 6A and FIG. 6B Taking the first edge interface region 101 located on the first edge S1 of the core particle 100 as an example, the positional relationship between the edge interface region of the core particle and the axis of symmetry of the core particle is explained.

[0123] like FIG. 6A and FIG. 6BAs shown, the core 100 is symmetrical with respect to the axis of symmetry AL, which is perpendicular to the first side S1 and extends through the center of the first side S1. The first side interface region 101 is symmetrical with respect to the axis of symmetry AL. In some embodiments, the first side interface region 101 may include one or more interface regions, and the symmetry of the first side interface region 101 with respect to the axis of symmetry means that the entirety of the one or more interface regions is symmetrical with respect to the axis of symmetry. For example, when the first side interface region 101 includes interface region 1 and interface region 2, interface region 1 and interface region 2 are symmetrical with respect to the axis of symmetry AL. In other examples, when the first side interface region 101 includes one interface region, the one interface region itself is symmetrical with respect to the axis of symmetry AL; similarly, when the first side interface region 101 includes two or more interface regions, the entirety of the first side interface region formed by the two or more interface regions is symmetrical with respect to the axis of symmetry AL.

[0124] refer to FIG. 6C In some embodiments, the core 100 may be a single core, and the first side S1 is a side of the single core, and the axis of symmetry AL is the axis of symmetry of the single core. (See reference...) FIG. 6A In some embodiments, the core 100 may be a core assembly, which may include multiple sub-cores, such as a first sub-core 100a and a second sub-core 100b. The multiple core edge of the core assembly includes the edges of the respective sub-cores and a combined edge formed by the edges of the multiple sub-cores. For example, the first edge S1 is a combined edge formed by the edges of the first sub-core 100a and the second sub-core 100b, and the axis of symmetry AL is the axis of symmetry of the core assembly; for example, the axis of symmetry AL is perpendicular to the combined edge and extends through the center of the combined edge. In this document, a single core refers to a single core.

[0125] In this paper, symmetry of the edge interface region with respect to the core particle's axis of symmetry includes both complete symmetry and approximate symmetry. Complete symmetry means that the core particle's axis of symmetry completely coincides with the axis of symmetry of the edge interface region perpendicular to that core particle edge, allowing the corresponding interface regions of the core particle to be perfectly aligned after rotation. Approximate symmetry means that the core particle's axis of symmetry is slightly offset from the axis of symmetry of the edge interface region, with the offset distance within an acceptable range, allowing the corresponding interface regions of the core particle to be approximately aligned after rotation without affecting the interconnection between the interface regions.

[0126] For example, FIG. 6BThe diagram illustrates a case where the edge interface region is approximately symmetrical about the core particle's axis of symmetry within an allowable error range. For example, the axis of symmetry of the core particle 100 perpendicular to the first side S1 is designated as the first axis of symmetry AL1, and the axis of symmetry of the first edge interface region 101 perpendicular to the first side S1 is designated as the second axis of symmetry AL2. The first axis of symmetry AL1 and the second axis of symmetry AL2 are offset by a distance in the extending direction of the first side S1. In some embodiments, the offset distance is less than or equal to five-thousandths of the side length of the first side S1. It should be understood that when the offset distance is zero, the first axis of symmetry AL1 and the second axis of symmetry AL2 coincide with each other, i.e. FIG. 1A to FIG. 4B and FIG. 6A The case shown is a perfectly symmetrical one.

[0127] It should be understood that, for FIG. 6B The settings of the edge interface areas of other core particles of the core 100 are the same as those mentioned above. FIG. 7 and FIG. 7 The descriptions of the first side and the first side interface area are similar, so they will not be repeated here.

[0128] In this embodiment of the disclosure, since each edge interface area is symmetrically arranged on the corresponding core edge, the interface areas of adjacent cores can be opposite each other in the arrangement direction and connected to each other with a shorter connection path, regardless of whether the adjacent cores are arranged by translation or rotation.

[0129] In some embodiments, the plurality of core particles are arranged in an array along a first arrangement direction and a second arrangement direction parallel to the main surface of the core particles, and any two adjacent core particles in the first arrangement direction or the second arrangement direction are configured to have the same orientation and be arranged in a translational or rotationally symmetrical manner.

[0130] In some embodiments, multiple cores have substantially the same size, and the multiple cores arranged along a first arrangement direction or a second arrangement direction can be substantially aligned with each other, i.e., having edges aligned in the respective arrangement directions. This optimizes the core arrangement and module footprint.

[0131] Because each interface area of ​​the core is configured to match multiple interface areas of other cores, multiple cores can be arranged and connected in various ways. Furthermore, since the core has multiple edge interface areas, the core array can be expanded in multiple directions, and the size of each core can be set to be smaller, thereby significantly improving yield. It should be understood that the number of cores in each row or column of the core module shown in the figure is merely illustrative and is not intended to be limiting. The arrangement of the core array can be based on product requirements.

[0132] In some embodiments, the multiple chips in the chip module may be chips manufactured using the same semiconductor process. For example, these chips may be formed from the same wafer and have substantially the same chip structure. That is, multiple chips can be generated in a single tape-out, and interconnected with each chip in the manner described above, thereby scalable bandwidth and computing power. In other embodiments, the chip module of this disclosure can also be applied to the interconnection between chips manufactured using different processes (e.g., different process nodes). For example, this interconnection technology can be used to reuse previous generation chips, thereby also reducing tape-out costs.

[0133] This disclosure provides a packaging structure including a chip module and an interconnecting component as described in any of the above embodiments, wherein the plurality of chips are electrically connected to each other through the interconnecting component.

[0134] In some embodiments, multiple chips can be integrated together using various packaging methods. For example, interconnect components can be interposers, redistribution layers, packaging substrates, or other components used for interconnection between chips. The packaging structure can be flip-chip packaging, chip-on-wafer (CoW) packaging, chip-on-wafer-on-substrate (CoWoS) packaging, etc., and this disclosure does not limit the type of packaging structure.

[0135] FIG. 1A to FIG. 4B A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0136] refer to FIG. 7 For example, the packaging structure includes a chip module 500 and an interconnect component 600. The interconnect component 600 may be disposed on one side of the chip module 500 and provides interconnection between multiple chips 100. For example, the interconnect component 600 may include conductive lines for interconnecting multiple chips, and corresponding interfaces of the multiple chips are electrically connected to each other through the conductive lines. It should be noted that... ​ The illustration of adjacent cores in contact with each other is merely to show the corresponding interfaces connecting to each other, and does not imply that these cores are in physical contact with each other. ​ As shown, multiple core particles can be arranged side by side with intervals between them.

[0137] In some embodiments, the packaging structure may integrate one or more chip modules, each chip module being a chip; the packaging structure may also integrate other individual chips. In the chip modules and packaging structures of this disclosure, the chip type can be selected according to product requirements, and this disclosure does not impose any limitations on it.

[0138] In the chip module and packaging structure of the present disclosure embodiments, the interface area of ​​each chip can be matched with multiple interface areas of other chips, and the controller supports the interface area of ​​the chip to be connected with different interface areas under different chip arrangements, thereby supporting the reuse of the same chip, reducing the chip fabrication cost, and improving the flexibility of chip arrangement and connection.

[0139] The following points need to be explained:

[0140] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0141] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0142] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip module, characterized in that, include: Multiple cores, wherein each core includes multiple interface regions, and each interface region is configured to match multiple interface regions of other cores; as well as The controller is configured to control the interconnection between the plurality of cores and is configured to control an interface area of ​​one of the plurality of cores to connect with a different interface area of ​​another of the plurality of cores in different core arrangements.

2. The chip module according to claim 1, characterized in that, Each of the plurality of core particles has a plurality of sides and a plurality of edge interface areas respectively disposed on the plurality of sides; The controller is configured to control an edge interface region of one of the plurality of cores to connect to an edge interface region of another of the plurality of cores located on a different side, depending on the arrangement of the cores.

3. The chip module according to claim 1, characterized in that, Each of the plurality of core particles has a first side and a second side, and has a first side interface region and a second side interface region located respectively on the first side and the second side; and The controller is configured to connect the first side interface region of the first core in the plurality of cores to the second side interface region of the second core in the plurality of cores in the first core arrangement, and to connect the first side interface region of the first core to the first side interface region of the second core in the second core arrangement.

4. The chip module according to claim 3, characterized in that, The first core arrangement includes the first core and the second core having the same orientation and being arranged in a first arrangement direction parallel to the main surface of the core, such that the first side interface area of ​​the first core and the second side interface area of ​​the second core are opposite to each other in the first arrangement direction; The second core arrangement includes rotational symmetry between the first core and the second core, and the first side interface area of ​​the first core and the first side interface area of ​​the second core are opposite to each other in the first arrangement direction.

5. The chip module according to claim 3, characterized in that, Each of the plurality of core particles further comprises a third side and a fourth side, and has a third side interface region and a fourth side interface region respectively located on the third side and the fourth side, wherein the extending directions of the third side and the fourth side intersect the extending directions of the first side and the second side; and The controller is configured to connect the third side interface region of the first core to the fourth side interface region of the third core in the third core arrangement, and to connect the third side interface region of the first core to the third side interface region of the third core in the fourth core arrangement.

6. The chip module according to claim 5, characterized in that, The third core arrangement includes the first core and the third core having the same orientation and being arranged in a second arrangement direction parallel to the main surface of the core, and the third side interface area of ​​the first core and the fourth side interface area of ​​the third core being opposite to each other in the second arrangement direction; The fourth core arrangement includes the first core and the third core being rotationally symmetrical to each other, and the third side interface area of ​​the first core and the third side interface area of ​​the fourth core being opposite to each other in the second arrangement direction.

7. The chip module according to claim 5, characterized in that, The first and second sides of the plurality of core particles have the same first length, and the third and fourth sides of the plurality of core particles have the same second length, wherein the first length is greater than or equal to the second length.

8. The core module according to claim 5, characterized in that, The controller is also configured to control the connection of the first side interface area of ​​the first core to the third side interface area or the fourth side interface area of ​​the second core in another core arrangement, wherein the other core arrangement includes the first core and the second core being rotationally symmetrical to each other, and the first side interface area of ​​the first core and the third side interface area or the fourth side interface area of ​​the second core being opposite to each other in a first arrangement direction.

9. The chip module according to claim 8, characterized in that, The first, second, third, and fourth sides of the plurality of core particles all have the same length.

10. The chip module according to claim 1, characterized in that, One of the plurality of cores is a first connecting core, and the other of the plurality of cores is a second connecting core, wherein the first connecting core and the second connecting core are adjacent to each other and electrically connected; The first connector core includes a first interface area, and the first interface area includes n first interfaces; The second connector core includes a second interface region, which includes n second interfaces, where n ≥ 1; and The controller is configured to connect the first interface area of ​​the first connecting core and the second interface area of ​​the second connecting core in a first core arrangement according to a first connection order, and to connect the first interface area of ​​the first connecting core and the second interface area of ​​the second connecting core in a second core arrangement according to a second connection order. In the first connection sequence, the i-th first interface of the first connection core is configured to connect with the i-th second interface of the second connection core; and in the second connection sequence, the i-th first interface of the first connection core is configured to connect with the (n-i+1)-th second interface of the second connection core, where 1≤i≤n.

11. The chip module according to claim 10, characterized in that, One of the first and second core arrangement configurations includes the first and second connecting cores having the same orientation and being arranged in a translational manner in a direction parallel to the main surface of the core, and the other of the first and second core arrangement configurations includes the first and second connecting cores being rotationally symmetrical to each other.

12. The chip module according to claim 11, characterized in that, The rotational symmetry of the first connecting core and the second connecting core includes that the orientation of the first connecting core and the orientation of the second connecting core are rotated 180° or 90° relative to each other.

13. The chip module according to any one of claims 1-12, characterized in that, Each core includes an edge interface region located on a core edge, the edge interface region being symmetrically arranged with respect to an axis of symmetry perpendicular to the core edge, the axis of symmetry extending through the center of the core edge.

14. The chip module according to claim 13, characterized in that, One or more of the plurality of core particles are each a single core particle, and the edge of the core particle is the edge of the single core particle; or One or more of the core particles are each a core particle combination including multiple sub-core particles, and the core particle edge is the edge of the corresponding sub-core particle or a combination edge composed of the edges of multiple sub-core particles in the core particle combination.

15. The chip module according to any one of claims 1-12, characterized in that, The plurality of core particles are arranged in an array along a first arrangement direction and / or a second arrangement direction parallel to the main surface of the core particles. Any two adjacent core particles in the first arrangement direction or the second arrangement direction are configured to have the same orientation and be arranged in a translational or rotationally symmetrical manner.

16. A packaging structure, characterized in that, include: Chip module as described in any one of claims 1-15; as well as An interconnecting component, wherein the plurality of cores are electrically connected to each other via the interconnecting component.

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