Amplification circuit

Abstract

The invention provides an amplifier circuit which can be miniaturized and broadband. An amplifier circuit is provided with: a first distributor that distributes an input signal into a first signal and a second signal; the first amplifier is used for amplifying the first signal; the second amplifier is used for amplifying the second signal; a synthesizer which synthesizes the first signal and the second signal and outputs the synthesized signal as an output signal; and a CRLH line connected to at least one of a first line connecting the first distributor and the first amplifier and a second line connecting the first distributor and the second amplifier. The phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line is adjusted.

Description

Technical Field

[0001] This invention relates to amplifier circuits. Background Technology

[0002] As an amplifier circuit that amplifies high-frequency signals such as microwaves, a load-modulated balanced amplifier (LMBA) circuit is known (e.g., non-patent literature 1).

[0003] Existing technical documents

[0004] Non-patent literature

[0005] Non-patent literature 1: "Broadband RF-Input Continuous-Mode Load-Modulated Balanced Power Amplifier With Input Phase Adjustment" Jingzhou Pang et al. IEEE Transactions on Microwave Theory and Technology Vol. 68, No. 10 October, 2020, pp. 4466-4478

[0006] An amplifier circuit combines multiple signals and outputs them. Adjusting the phase of the combined signal improves characteristics such as efficiency. When the signal phase deviates from its optimal value, the characteristics deteriorate. A phase adjustment circuit is used to adjust the phase.

[0007] Furthermore, amplifier circuits require a wide operating bandwidth. Therefore, the phase adjustment circuitry also needs to be optimized for phase over a wide bandwidth. When transmission lines are used as phase adjustment lines, the line length increases. As a result, the amplifier circuit becomes larger. When the transmission lines are miniaturized, it becomes difficult to adjust the phase over a wide bandwidth. This disclosure was made in view of the above problems, and its object is to provide an amplifier circuit that can be miniaturized and has a wide bandwidth. Summary of the Invention

[0008] One embodiment of this disclosure is an amplifier circuit comprising: a first distributor for distributing an input signal into a first signal and a second signal; a first amplifier for amplifying the first signal; a second amplifier for amplifying the second signal; a synthesizer for combining the first signal and the second signal and outputting the synthesized signal as an output signal; and a CRLH line connected to at least one of a first line connecting the first distributor and the first amplifier and a second line connecting the first distributor and the second amplifier, for adjusting the phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line.

[0009] Invention Effects

[0010] According to this disclosure, an amplifier circuit that can be miniaturized and widened can be provided. Attached Figure Description

[0011] Figure 1A This is a circuit diagram illustrating the amplifier circuit of the first embodiment.

[0012] Figure 1B This is a diagram illustrating an example of a FET.

[0013] Figure 2A This is an example diagram illustrating phase dispersion.

[0014] Figure 2B This is a diagram illustrating the phase of a signal.

[0015] Figure 2C This is a diagram illustrating the phase of a signal.

[0016] Figure 3 This is a circuit diagram illustrating the amplifier circuit of the second embodiment.

[0017] Figure 4 This is a circuit diagram illustrating the amplifier circuit of the third embodiment.

[0018] Figure 5 This is a circuit diagram illustrating a comparative example of an amplifier circuit.

[0019] Figure 6A This is a diagram illustrating the phase.

[0020] Figure 6B The diagram illustrates the drain efficiency as an example.

[0021] Figure 6C This is a top view illustrating a transmission line.

[0022] Figure 6D This is an example of a top view of a CRLH line.

[0023] Figure 7 This is a circuit diagram illustrating the amplifier circuit of the fourth embodiment.

[0024] Figure 8 This is a circuit diagram illustrating the amplifier circuit of the fifth embodiment.

[0025] Explanation of reference numerals in the attached figures:

[0026] 10, 22: Distributor;

[0027] 11, 13, 13a, 13b: Amplifiers;

[0028] 12, 14: Lines;

[0029] 16, 16-1, 16-2, 16-3: Bias circuit;

[0030] 17: Synthesizer;

[0031] 18, 18-1, 18-2, 18-3: CRLH lines;

[0032] 19: Transmission lines;

[0033] 20: Matching circuit;

[0034] 22a, 22b, 22c, 22d, 24a, 24b, 24c, 24d: Ends;

[0035] 24: Load modulation circuit;

[0036] 30: substrate;

[0037] 32, 34, 35: Wiring patterns;

[0038] 36: Chip components;

[0039] 100, 110, 200, 300, 400, 500: Amplifier circuits. Detailed Implementation

[0040] [Description of embodiments of this disclosure]

[0041] First, the contents of the embodiments of this disclosure will be listed for explanation.

[0042] (1) One embodiment of this disclosure is an amplifier circuit comprising: a first distributor for distributing an input signal into a first signal and a second signal; a first amplifier for amplifying the first signal; a second amplifier for amplifying the second signal; a synthesizer for combining the first signal and the second signal and outputting the synthesized signal as an output signal; and a CRLH line connected to at least one of a first line connecting the first distributor to the first amplifier and a second line connecting the first distributor to the second amplifier, for adjusting the phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line. The CRLH line enables phase adjustment of the signal over a wide bandwidth. Furthermore, the line length does not need to be increased. Therefore, miniaturization and broadband operation of the amplifier circuit can be achieved.

[0043] (2) In (1) above, the synthesizer may also be a load modulation circuit that modulates the load of the second amplifier, and the amplifier circuit may be a load modulation balanced amplifier. This enables the load modulation balanced amplifier to be miniaturized and broadband.

[0044] (3) In (2) above, the amplifier circuit may also include a second distributor located on the second line, which distributes the second signal into a third signal and a fourth signal. The second amplifier includes a third amplifier and a fourth amplifier, the third amplifier amplifying the third signal and the fourth amplifier amplifying the fourth signal. The CRLH line is connected to at least one of the first line and the second line, between the first distributor and the second distributor. This enables the miniaturization and broadbanding of the load modulation balanced amplifier.

[0045] (4) In (3) above, the synthesizer may also have a first terminal, a second terminal, a third terminal, and a fourth terminal. The third signal, amplified by the third amplifier, is input to the first terminal; the fourth signal, amplified by the fourth amplifier, is input to the second terminal; the first signal, amplified by the first amplifier, is input to the third terminal; and the output signal is output from the fourth terminal. The CRLH circuit ensures that the phase of the synthesized signal in the synthesizer is close to optimal, thus enabling broadband amplification of the amplifier circuit.

[0046] (5) In (3) or (4) above, the amplifier circuit may also include a plurality of CRLH lines, which are connected to at least one of the first line and the second line, between the first distributor and the second distributor. This enables miniaturization and broadbanding of the amplifier circuit.

[0047] (6) In (5) above, the number of the multiple CRLH lines can be three or more. This enables the miniaturization and broadbanding of the amplifier circuit.

[0048] (7) In any of (1) to (6) above, the CRLH circuit may also have a first inductor, a first capacitor, a second inductor, and a second capacitor. If the CRLH circuit is located on the first circuit, the first inductor and the first capacitor are connected in series on the first circuit, and the second inductor and the second capacitor are connected separately between the first capacitor and the first amplifier. If the CRLH circuit is located on the second circuit, the first inductor and the first capacitor are connected in series on the second circuit, and the second inductor and the second capacitor are connected separately between the first capacitor and the second amplifier. The first capacitor has a DC (Direct Current) blocking function, thus enabling miniaturization of the amplifier circuit.

[0049] (8) In (7) above, the second inductor may also be connected to a bias power supply. When the CRLH line is located on the first line, the bias power supply supplies a bias voltage to the first amplifier. When the CRLH line is located on the second line, the bias power supply supplies a bias voltage to the second amplifier. This eliminates the need for a separate bias circuit, thus enabling miniaturization of the amplifier circuit.

[0050] (9) In any of (1) to (8) above, the amplifier circuit may also have two CRLH lines, a first CRLH line and a second CRLH line, which serve as the CRLH line, with the first CRLH line located on the first line and the second CRLH line located on the second line. This allows for adjustment of the phase of the first signal and the second signal.

[0051] [Details of the embodiments of this disclosure]

[0052] Hereinafter, specific examples of amplifier circuits according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is shown in the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0053] <First Implementation>

[0054] Figure 1AThis is a circuit diagram illustrating the amplifier circuit 100 of the first embodiment. The amplifier circuit 100 amplifies the signal Si input from the input terminal Tin and outputs the output signal So from the output terminal Tout. The signal So is a high-frequency signal. The frequency of the high-frequency signal is, for example, 0.5 GHz or higher and 10 GHz or lower.

[0055] A distributor 10 (first distributor) is connected to the input terminal Tin. An amplifier 11 (first amplifier) ​​is connected to one output terminal of the distributor 10. An amplifier 13 (second amplifier) ​​is connected to the other output terminal of the distributor 10.

[0056] Amplifiers 11 and 13 are, for example, field-effect transistors (FETs). FETs are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOS (Laterally Diffused Metal Oxide Semiconductors). Figure 1B This is a diagram illustrating an example of a FET. For example... Figure 1B As shown, in amplifiers 11 and 13, the source of the FET is grounded, and a bias voltage is applied to its gate. A high-frequency signal is input to the gate and output from the drain. Amplifiers 11 and 13 can each have multiple stages of FETs.

[0057] Amplifier 11 is connected to one input of synthesizer 17. Amplifier 13 is connected to the other input of synthesizer 17. The output of synthesizer 17 is connected to the output terminal Tout.

[0058] Designate the line between distributor 10 and amplifier 11 as line 12 (first line). Designate the line between distributor 10 and amplifier 13 as line 14 (second line).

[0059] A bias circuit 16 is provided in line 12. The bias circuit 16 includes a bias power supply Vgc, an inductor La, a capacitor Ca, and a capacitor Cb. Capacitor Ca is connected in series between the distributor 10 and the amplifier 11. One end of the inductor La is connected between capacitor Ca and the amplifier 11. The bias power supply Vgc is connected to the other end of the inductor La. One end of the capacitor Cb is connected between the inductor La and the bias power supply Vgc. The other end of the capacitor Cb is grounded. The bias power supply Vgc is a DC power supply. A bias voltage is supplied to the amplifier 11 from the bias circuit 16.

[0060] Line 14 includes a CRLH (Composite Right / Left-Handed Transmission Line) 18. The CRLH line 18 includes inductor L1 (first inductor), inductor L2 (second inductor), capacitor C1 (first capacitor), and capacitor C2 (second capacitor). As described later, the capacitors and inductors in the CRLH line 18 are, for example, chip components.

[0061] Inductor L1 and capacitor C1 are connected in series between distributor 10 and amplifier 13 in this order. Inductor L2 and capacitor C2 are connected in a branch between capacitor C1 and amplifier 13. One end of capacitor C2 is connected between capacitor C1 and amplifier 13. The other end of capacitor C2 is grounded.

[0062] One end of inductor L2 is connected in the line between capacitor C1 and amplifier 13 closer to the distributor 10 than the location where capacitor C2 is connected. The other end of inductor L2 is connected to a bias power supply Vgb. The bias power supply Vgb is a DC power supply that supplies bias voltage to amplifier 13. One end of capacitor C3 is connected between inductor L2 and bias power supply Vgb. The other end of capacitor C3 is grounded. Through capacitor C3, bias power supply Vgb is grounded at a high frequency, making it difficult for high-frequency signals to flow to bias power supply Vgb. The bias power supply Vgb of CRLH line 18 supplies bias voltage to amplifier 13.

[0063] The capacitances of capacitors C1 and C2 are denoted as C1 and C2. The inductances of inductors L1 and L2 are denoted as L1 and L2. The characteristic impedance Z0 of CRLH line 18 is represented by the following equation 1.

[0064] [Formula 1]

[0065]

[0066] The CRLH line 18 is designed such that the impedance of the port to which it is connected is consistent with the characteristic impedance Z0 of the CRLH line 18. The phase of the signal is also considered in the design of the CRLH line 18, as will be described later.

[0067] The input signal Si is received from the input terminal Tin. Distributor 10 divides the signal Si into signal Si1 (first signal) and signal Si2 (second signal). Signal Si1 propagates in line 12, is amplified by amplifier 11, and is input to synthesizer 17. Signal Si2 propagates in line 14, passes through CRLH line 18, is amplified by amplifier 13, and is input to synthesizer 17. CRLH line 18 adjusts the phase of signal Si2. Synthesizer 17 combines signal Si1 and signal Si2 and outputs the result as signal So to the output terminal Tout.

[0068] By bringing the phase of the synthesized signal in synthesizer 17 close to its optimal value, characteristics such as efficiency are improved. However, in high-frequency circuits, phase delay of the signal becomes a problem. Characteristics such as efficiency deteriorate due to the phase deviating from the optimal value. The optimal phase during synthesis varies depending on the frequency. In order to widen the operating frequency band of amplifier circuit 100, the phase of the synthesized signal is optimized over a wide frequency band.

[0069] Figure 2A This is an example diagram illustrating phase dispersion. The horizontal axis represents the phase of the signal at the point in time it travels through the line. The vertical axis represents the frequency of the signal. Figure 2A In the diagram, dashed lines represent phase dispersion in right-handed circuits. Dotted lines represent phase dispersion in left-handed circuits. Solid lines represent phase dispersion in CRLH circuit 18. Phase dispersion in right-handed circuits is linear. Phase dispersion in left-handed circuits is nonlinear. Phase dispersion in CRLH circuit 18 is a composite characteristic of both right-handed and left-handed circuits, exhibiting both nonlinear and linear components.

[0070] In right-handed transmission lines, the phase dispersion is linear, making it difficult to optimize the signal delay for each frequency. To vary the slope of the phase dispersion, the transmission line could be lengthened. However, this would increase the circuit size.

[0071] Figure 2B and Figure 2C This is a diagram illustrating the phase of a signal. Figure 2B This is an example of a right-handed circuit. Figure 2C This is an example of CRLH line 18. Figure 2B and Figure 2C The horizontal axis represents the signal frequency. The vertical axis represents the phase of the signal after passing through the line. The diagram illustrates the phase of signals with frequencies from 0 GHz to 16 GHz.

[0072] exist Figure 2B In the example shown, the phase change is linear across the entire frequency band in the graph. It is difficult to optimize the signal phase for each frequency. Figure 2CIn the example, frequencies above approximately 9 GHz constitute the linear portion, where the phase changes linearly. Frequencies below approximately 9 GHz constitute the non-linear portion, where the phase changes non-linearly. The slope of the linear portion is adjusted by varying the capacitance and inductance in the CRLH line 18, and the curve of the non-linear portion is also adjusted. Phase optimization can be achieved across the frequency band.

[0073] According to the first embodiment, a CRLH line 18 is provided on the line 14 connecting the distributor 10 and the amplifier 13. For example... Figure 2A As shown, the phase dispersion of the CRLH line 18 includes a nonlinear component, thus offering high freedom in phase design. By setting appropriate values ​​for the capacitance and inductance of the CRLH line 18, desired phase characteristics can be obtained over a wide bandwidth. By utilizing the CRLH line 18 to adjust the phase of the signal, the phase of the synthesized signal can be made close to optimal across a wide bandwidth. Furthermore, the line length of the CRLH line 18 can be increased without optimizing the phase. Therefore, the amplifier circuit 100 is miniaturized. Miniaturization and wide bandwidth of the amplifier circuit 100 can be achieved.

[0074] The operating frequency band of the amplifier circuit 100 is, for example, 0.5 GHz or higher, 1 GHz or higher, 1.5 GHz or higher, or 2 GHz or higher. Within these frequency bands, the phase of the synthesized signal should be close to the optimal value.

[0075] CRLH line 18 can be set on at least one of lines 12 and 14. For example... Figure 1A As in the example, CRLH line 18 can be set on line 14. CRLH line 18 can also be set on line 12. As described later. Figure 8 As in the example, CRLH line 18 can also be set on both lines 12 and 14.

[0076] Parasitic components are also considered in the design of CRLH circuit 18. For example, when designing a left-handed circuit with capacitor C1 and inductor L2, the parasitic components generated in this left-handed circuit are represented by inductor L1 and capacitor C2 in the design of CRLH circuit 18.

[0077] CRLH line 18 includes capacitors C1 and C2, inductor L1, and inductor L2. Capacitor C1 is connected in series with line 14 between distributor 10 and amplifier 13 to block DC signals. It is possible to omit the need for a separate capacitor for DC blocking in line 14, thus enabling miniaturization of amplifier circuit 100.

[0078] Inductor L2 of CRLH line 18 is connected to a bias power supply Vgb. A bias voltage is supplied to amplifier 13 from bias power supply Vgb. A separate bias circuit can be omitted from line 14, thus enabling miniaturization of amplifier circuit 100. Alternatively, the connection order in CRLH line 18 can be changed, with capacitor C1 located near distributor 10 and inductor L1 located near amplifier 13.

[0079] <Second Implementation>

[0080] (LMBA)

[0081] Figure 3 This is a circuit diagram illustrating the amplifier circuit 200 according to the second embodiment. Amplifier circuit 200 is a load-modulated balanced amplifier (LMBA). Descriptions of configurations identical to those in the first embodiment are omitted. Amplifier circuit 200 is used, for example, in a mobile communication base station.

[0082] The amplifier circuit 200 includes a distributor 10 (first distributor), an amplifier 11 (first amplifier), a matching circuit 20, a CRLH line 18, a distributor 22 (second distributor), an amplifier 13a (third amplifier) ​​and an amplifier 13b (fourth amplifier), and a load modulation circuit 24 (synthesizer). Amplifier 11 is connected in parallel with amplifiers 13a and 13b between the input terminal Tin and the output terminal Tout.

[0083] Amplifier 11 is a control amplifier. Amplifier 11 is connected to one output terminal of distributor 10. The line between distributor 10 and amplifier 11 is designated as line 12 (first line). A bias circuit 16-1 is provided on line 12. The bias circuit 16-1 supplies a bias voltage to amplifier 11.

[0084] Amplifiers 13a and 13b are balanced amplifiers. The line from distributor 10 to amplifiers 13a and 13b is designated as line 14 (second line). CRLH line 18 and distributor 22 are located on line 14.

[0085] The distributor 22 is, for example, a hybrid coupler, having terminals 22a, 22b, 22c, and 22d. Terminals 22a and 22d are diagonally opposite to each other. Terminals 22b and 22c are diagonally opposite to each other. Terminal 22a of the distributor 22 is connected to the output of the distributor 10. A CRLH line 18 is connected between the distributor 10 and terminal 22a of the distributor 22. In the second embodiment, the CRLH line 18 has capacitors C1 and C2, inductors L1 and L2, but no bias power supply or capacitor C3. Terminal 22b of the distributor 22 is terminated by a reference load Ro. Amplifier 13a is connected to terminal 22c. Amplifier 13b is connected to terminal 22d.

[0086] A bias circuit 16-2 is connected between terminal 22c of distributor 22 and amplifier 13a. A bias circuit 16-3 is connected between terminal 22d and amplifier 13b. Bias circuit 16-2 supplies bias voltage to amplifier 13a. Bias circuit 16-3 supplies bias voltage to amplifier 13b. Figure 3 In the diagram, bias circuits 16-1, 16-2, and 16-3 are illustrated in blocks. Each of these bias circuits has the same configuration as bias circuit 16 in Figure 1.

[0087] The load modulation circuit 24 is, for example, a hybrid coupler, having terminals 24a (first terminal), 24b (second terminal), 24c (third terminal), and 24d (fourth terminal). Terminals 24a and 24d are diagonally opposite terminals. Terminals 24b and 24c are diagonally opposite terminals. Amplifier 13a is connected to terminal 24a. Amplifier 13b is connected to terminal 24b.

[0088] Amplifier 11 is connected to terminal 24c. Matching circuit 20 is provided between amplifier 11 and terminal 24c. Matching circuit 20 matches the impedance from amplifier 11 to matching circuit 20 to the impedance from matching circuit 20 to load modulation circuit 24. Output terminal Tout is connected to terminal 24d. Output terminal Tout is grounded via load resistor RL. Load resistor RL is, for example, 50Ω.

[0089] The input signal Si is received from the input terminal Tin. The distributor 10 divides the signal Si into signal Si1 (first signal) and signal Si2 (second signal). Signal Si1 propagates in line 12 and is amplified by amplifier 11. The amplified signal Si1 passes through the matching circuit 20 and is output to terminal 24c of the load modulation circuit 24.

[0090] Signal Si2 passes through CRLH line 18 and is output to terminal 22a of distributor 22. Distributor 22 distributes signal Si2 into signal Si2a (third signal) and signal Si2b (fourth signal). The phase of signal Si2b lags the phase of signal Si2a by 90°.

[0091] Signal Si2a is output from terminal 22c and amplified by amplifier 13a. The amplified signal Si2a is then output to terminal 24a of the load modulation circuit 24. Signal Si2b is output from terminal 22d and amplified by amplifier 13b. The amplified signal Si2b is then output to terminal 24b of the load modulation circuit 24. Output signal So is output from terminal 24d of the load modulation circuit 24 to the output terminal Tout.

[0092] Amplifier 11 operates in Class AB or Class B mode. Amplifiers 13a and 13b operate in Class C mode. When the power of the input signal Si is low, amplifier 11 primarily amplifies the input signal Si. When the power of the input signal Si is high, amplifiers 11, 13a, and 13b amplify the peak value of the input signal Si. Thus, amplifiers 11, 13a, and 13b amplify the input signal Si.

[0093] When the power of the input signal Si is low and amplifiers 13a and 13b are not operating, the signal Si1 input from terminal 24c to the load modulation circuit 24 is split into two signals Si1a and distributed to terminals 24a and 24b. The phase of signal Si1a propagating from terminal 24c to terminal 24b lags by 90° compared to the phase of signal Si1a propagating to terminal 24a. Signal Si1a is reflected at terminals 24a and 24b. The phase of signal Si1a reflected at terminal 24a lags by 90° compared to the phase of signal Si1a reflected at terminal 24b. The phases of the two signals Si1a are aligned at terminal 24d. The two signals Si1a are combined at terminal 24d. The combined signal is output as the output signal So to the output terminal Tout. The reflection coefficients from amplifiers 13a and 13b to the load modulation circuit 24 are greater than 1, and the load impedances of amplifiers 13a and 13b are substantially high.

[0094] When the input signal Si has high power and amplifiers 13a and 13b are operating, the phase of signal Si2b amplified by amplifier 13b lags behind the phase of signal Si2a amplified by amplifier 13a by 90°. CRLH line 18 adjusts the phase of signal Si2. At terminal 24a of the load modulation circuit 24, signals Si1a and Si2a are in phase. At terminal 24b, signals Si1a and Si2b are in phase. The signal Si1a+Si2a synthesized at terminal 24a and the signal Si1a+Si2b synthesized at terminal 24b are synthesized at terminal 24d. The signal synthesized at terminal 24d is output as the output signal So.

[0095] At this point, the reflection coefficient of the load modulation circuit 24 viewed from amplifiers 13a and 13b is less than 1, and the larger the amplitude of signals Si2a and Si2b, the smaller the reflection coefficient. Therefore, the load impedance of amplifiers 13a and 13b is substantially lower. The load modulation circuit 24 modulates the load impedance viewed from amplifiers 13a and 13b according to the amplitude of signals Si2a and Si2b.

[0096] As an example different from the above-described operating example, amplifiers 13a and 13b could also operate in Class AB or Class B mode. Alternatively, amplifier 11 could operate in Class C mode. When the power of the input signal Si is low, amplifiers 13a and 13b primarily amplify the input signal Si. When the power of the input signal Si is high, amplifiers 11, 13a, and 13b amplify the peak value of the input signal Si. Thus, amplifiers 11, 13a, and 13b amplify the input signal Si.

[0097] Alternatively, high-order harmonic processing circuits can be installed between amplifier 11 and matching circuit 20, between amplifier 13a and load modulation circuit 24, and between amplifier 13b and load modulation circuit 24. These circuits suppress higher-order harmonic components, such as the second harmonic component, in the signal.

[0098] According to the second embodiment, the amplifier circuit 200 is an LMBA (Low-bandwidth amplifier) ​​that operates over a wide bandwidth. The phase delay of the high-frequency signal varies depending on the frequency. To achieve broadband operation, the phase of the signal can be optimized for each frequency. Figure 3 As shown, amplifier circuit 200 has CRLH line 18. (As...) Figure 2A As shown, the phase dispersion of the CRLH line 18 includes a nonlinear component, thus offering high freedom in phase design. Using the CRLH line 18, phase optimization can be achieved over a wide bandwidth. The line length of the CRLH line 18 can be maintained. This enables miniaturization and widening of the amplifier circuit 200.

[0099] Amplifier circuit 200 is an LMBA, for example, used in mobile communication base stations. Compared to a Doherty amplifier circuit, an LMBA can widen the operating frequency band. According to the second embodiment, in an LMBA, by adjusting the phase over a wide bandwidth, the operating frequency band can be further widened.

[0100] exist Figure 3 In this example, a CRLH line 18 is provided on line 14 between distributor 10 and distributor 22. The phase of signal Si2 is adjusted via the CRLH line 18. The phase-adjusted signal Si2 is distributed by distributor 22. The distributed signals Si2a and Si2b are then combined. This allows the phase of the combined signal to be close to optimal over a wide bandwidth. Over a wide bandwidth, this improves the characteristics of the amplifier circuit 200, such as drain efficiency.

[0101] like Figure 3 As shown, a CRLH line 18 is provided in the pre-stage of amplifiers 13a and 13b. The signal before amplification propagates in the CRLH line 18, and its phase is adjusted. The phase-adjusted signal is then amplified. The amplified signal is not lost due to the CRLH line 18.

[0102] Amplifier circuit 200 includes load modulation circuit 24. Signal Si2a is input to terminal 24a of load modulation circuit 24. Signal Si2b is input to terminal 24b. Signal Si1 is input to terminal 24c. Load modulation circuit 24 synthesizes the signals and outputs signal So. Through CRLH line 18, the phase of the synthesized signal is close to optimal in a wide bandwidth, thus achieving broadband operation of amplifier circuit 200.

[0103] CRLH line 18 includes capacitors C1 and C2, inductor L1, and inductor L2. Capacitor C1 is connected in series with line 14 between distributor 10 and distributor 22 to block DC signals. It is possible to omit the need for a separate capacitor for DC blocking in line 14, thus enabling miniaturization of the amplifier circuit 200.

[0104] <Third Implementation Method>

[0105] Figure 4 This is a circuit diagram illustrating the amplifier circuit 300 according to the third embodiment. The amplifier circuit 300 has three CRLH lines. Figure 4 In the diagram, the CRLH circuit of a unit is represented by a box. Descriptions of configurations identical to those in the first or second embodiment are omitted.

[0106] like Figure 4As shown, CRLH lines 18-1, 18-2, and 18-3 are sequentially arranged on line 14, starting from the side closest to distributor 10. Each CRLH line is connected to... Figure 3 The CRLH line 18 also has an inductor L1 and a capacitor C1 connected in series, and an inductor L2 and a capacitor C2 connected in a branch circuit. Three CRLH lines are designed to optimize the phase.

[0107] (Comparative Example)

[0108] Figure 5 This is a circuit diagram illustrating a comparative example amplifier circuit 110. Amplifier circuit 110 does not have a CRLH line, but has a transmission line 19. Transmission line 19 is, for example, a microstrip line, located at line 14.

[0109] Figure 6A This diagram illustrates the phase, showing the phase of the signal at each frequency calculated in the comparative example and the third embodiment. The horizontal axis represents the signal frequency. The vertical axis represents the phase of the signal after passing through the line. The dashed line represents the comparative example. The phase delay in transmission line 19 of the comparative example is approximately 130°. The solid line represents the third embodiment. In each CRLH line, L1 = 0.7nH, L2 = 1.4nH, C1 = 0.56pF, and C2 = 0.28pF are set. The characteristic impedance of each CRLH line is 50Ω. Figure 6A The dots in the diagram represent the optimal phase for signal frequencies of 3.2 GHz, 3.7 GHz, and 4.2 GHz.

[0110] In the comparative example, the phase of a signal at a frequency of 3.7 GHz can be optimized. However, the phase deviates from the optimal value on both the low-frequency and high-frequency sides of 3.7 GHz. The further the frequency is from 3.7 GHz, the greater the deviation from the optimal phase. By setting the phase delay of transmission line 19 to 490°, phase optimization can be achieved across the frequency band from 3.2 GHz to 4.2 GHz. However, transmission line 19 becomes longer, and amplifier circuit 110 becomes larger.

[0111] like Figure 6A As shown, in the third embodiment, by using three CRLH lines, the signal phase can be optimized across the frequency band from 3.2 GHz to 4.2 GHz. The three CRLH lines are shorter than the 490° transmission line 19. Therefore, the amplifier circuit 300 can be miniaturized.

[0112] Figure 6BThis is a graph illustrating drain efficiency. The horizontal axis represents the power Pout of the signal amplified by amplifiers 13a and 13b. The vertical axis represents the drain efficiency DE of the amplifier. The signal frequency ranges from 3.2 GHz to 4.2 GHz. Circles and solid lines represent an example at 3.2 GHz. Diamonds and dotted lines represent an example at 3.4 GHz. Triangles and dashed lines represent an example at 3.6 GHz. Squares and single-dotted lines represent an example at 3.8 GHz. Double circles and dashed lines represent an example at 4.0 GHz. Asterisks and solid lines represent an example at 4.2 GHz.

[0113] At any frequency, the drain efficiency increases with increasing power. For example... Figure 6A Thus, the phase of the signal is optimized in the range of 3.2 GHz to 4.2 GHz, thereby, as Figure 6B That would improve drain efficiency. According to the third embodiment, both improved drain efficiency and miniaturization of the amplifier circuit 300 can be achieved.

[0114] Figure 6C This is a top view illustrating the transmission line 19. A wiring pattern 32 is provided on the surface of the substrate 30. The substrate 30 includes, for example, a dielectric. A ground pattern (not shown) is provided on the back side of the substrate 30 at a position overlapping with the wiring pattern 32. The substrate 30, the wiring pattern 32, and the ground pattern form the transmission line 19 (microstrip line). The length of the transmission line 19 is set to X1. When the phase delay is set to 130°, the length X1 is 23 mm. However, phase adjustment is difficult. When the phase delay is set to 490°, the length X1 is 71 mm. The transmission line 19 becomes longer, and the amplifier circuit 110 becomes larger.

[0115] Figure 6D This is an example top view of a CRLH line 18. A wiring pattern 34, multiple wiring patterns 35, and multiple chip components 36 are provided on the substrate 30. Figure 6D In this example, chip component 36 is marked with a diagonal line. Wiring pattern 34, together with a ground pattern (not shown), forms a microstrip line. This microstrip line, for example, is... Figure 5 Corresponding to line 14. Multiple wiring patterns 35 are separated from each other and from wiring pattern 34. Chip components 36 are connected to the multiple wiring patterns 35. Chip components 36 and parasitic components correspond to the inductors or capacitors of CRLH line 18. The length of CRLH line 18 x 2 is, for example, 13 mm. The total length of the three CRLH lines is approximately 39 mm.

[0116] According to the third embodiment, three CRLH lines are provided in line 14 of the amplifier circuit 300. For example... Figure 6AAs shown, phase optimization can be achieved, for example, in a wide bandwidth of around 1 GHz. For instance, three CRLH lines can be used instead of transmission line 19, which has a delay of 490°. Compared to the example with transmission line 19, the amplifier circuit 300 can be miniaturized.

[0117] The number of CRLH lines set on line 14 can be two, three or more, four or more, or even five or more. Phase adjustment can be performed in a wide frequency band above 1 GHz.

[0118] <Fourth Implementation>

[0119] Figure 7 This is a circuit diagram illustrating the amplifier circuit 400 of the fourth embodiment. A CRLH line 18 is provided on line 12. No CRLH line is provided on line 14.

[0120] According to the fourth embodiment, a CRLH line 18 is provided in line 12, thus adjusting the phase of signal Si1. This allows the phase of the synthesized signal to approach its optimal value over a wide bandwidth. It also enables miniaturization and widening of the amplifier circuit 400.

[0121] Multiple CRLH lines can also be located on line 12. For example, by setting three CRLH lines on line 12, it is possible to... Figure 6A That way, the phase can be close to the optimal value in the 1GHz frequency band.

[0122] A capacitor C1 is provided in line 12. Capacitor C1 has a DC blocking function. Therefore, it is not necessary to provide a separate capacitor for DC blocking in line 12, which allows for miniaturization of the amplifier circuit 400.

[0123] A bias power supply Vgc is connected to inductor L2 in CRLH line 18. The bias power supply Vgc supplies bias voltage to amplifier 11. No additional bias circuit is needed in line 12, thus enabling miniaturization of amplifier circuit 400.

[0124] <Fifth Implementation>

[0125] Figure 8 This is a circuit diagram illustrating the amplifier circuit 500 according to the fifth embodiment. The amplifier circuit 500 has a CRLH line 18a (first CRLH line) and a CRLH line 18b (second CRLH line). The CRLH line 18a is provided on line 12.

[0126] CRLH line 18a has capacitors C1a, C2a, and C3a, inductor L1a, and inductor L2a. A bias power supply Vgc is connected to inductor L2a. CRLH line 18b has capacitors C1b and C2b, inductor L1b, and inductor L2b.

[0127] According to the fifth embodiment, a CRLH line 18a is provided in line 12, thus adjusting the phase of signal Si1. A CRLH line 18b is provided in line 14, thus adjusting the phase of signal Si2. This allows the phase of the synthesized signal to be close to optimal over a wide bandwidth. It enables miniaturization and widening of the amplifier circuit 500.

[0128] As shown in the second to fifth embodiments, at least one of line 12 and line 14 is provided with a CRLH line. Figure 8 In the example, CRLH lines are provided on both lines 12 and 14. Therefore, as described below, the amplifier circuit 500 can be miniaturized.

[0129] The capacitor C1a of CRLH line 18a is connected in series with line 12, providing DC blocking functionality. CRLH line 18a has a bias power supply Vgc. The bias voltage is supplied to amplifier 11 from the bias power supply Vgc of CRLH line 18a. A capacitor and bias circuit for DC blocking can be provided in line 12 without being independent of CRLH line 18a. The capacitor C1b of CRLH line 18b is connected in series with line 14, providing DC blocking functionality. A capacitor for DC blocking can be provided in line 14 without being independent of capacitor C1b. This allows for miniaturization of the amplifier circuit 500.

[0130] The embodiments disclosed herein should be considered exemplary rather than limiting in all respects. The scope of this disclosure is not indicated by the foregoing meaning but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. An amplifier circuit, comprising: The first distributor divides the input signal into a first signal and a second signal; The first amplifier amplifies the first signal; The second amplifier amplifies the second signal; The synthesizer combines the first signal and the second signal, and outputs the synthesized signal as the output signal. as well as A composite left-hand CRLH circuit is connected to at least one of a first line connecting the first distributor to the first amplifier and a second line connecting the first distributor to the second amplifier, and adjusts the phase of at least one of the first signal flowing through the first line and the second signal flowing through the second line.

2. The amplifier circuit according to claim 1, wherein, The synthesizer is a load modulation circuit that modulates the load of the second amplifier. The amplifier circuit is a load-modulated balanced amplifier.

3. The amplifier circuit according to claim 2, wherein, Equipped with a second distributor located on the second line, The second distributor distributes the second signal into a third signal and a fourth signal. The second amplifier includes a third amplifier and a fourth amplifier. The third amplifier amplifies the third signal. The fourth amplifier amplifies the fourth signal. The CRLH line is connected to at least one of the first line and the second line, between the first distributor and the second distributor.

4. The amplifier circuit according to claim 3, wherein, The synthesizer has a first end, a second end, a third end, and a fourth end. The third signal, amplified by the third amplifier, is input to the first terminal. The fourth signal, amplified by the fourth amplifier, is input to the second terminal. The first signal, amplified by the first amplifier, is input to the third terminal. The output signal is output from the fourth terminal.

5. The amplifier circuit according to claim 3 or 4, wherein, It has multiple of the aforementioned CRLH lines. The plurality of said CRLH lines are connected to at least one of the first line and the second line, between the first distributor and the second distributor.

6. The amplifier circuit according to claim 5, wherein, The number of the aforementioned CRLH lines is three or more.

7. The amplifier circuit according to claim 1 or 2, wherein, The CRLH circuit includes a first inductor, a first capacitor, a second inductor, and a second capacitor. When the CRLH line is located on the first line, the first inductor and the first capacitor are connected in series on the first line, and the second inductor and the second capacitor are connected separately between the first capacitor and the first amplifier. When the CRLH line is located on the second line, the first inductor and the first capacitor are connected in series on the second line, and the second inductor and the second capacitor are connected in a branch line between the first capacitor and the second amplifier.

8. The amplifier circuit according to claim 7, wherein, The second inductor is connected to the bias power supply. When the CRLH line is located on the first line, the bias power supply supplies a bias voltage to the first amplifier. When the CRLH line is located on the second line, the bias power supply supplies a bias voltage to the second amplifier.

9. The amplifier circuit according to claim 1 or 2, wherein, It has two lines, a first CRLH line and a second CRLH line, which serve as the CRLH line. The first CRLH line is located on the first line. The second CRLH line is located on the second line.

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