Signal generation circuit, chip and electronic equipment
The clock signal and ready signal are generated by the comparison and logic processing module in the signal generation circuit, which solves the signal loss problem caused by comparator metastability and ensures the normal operation of the system.
Patent Information
- Application Number
- CN202511009167.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-12-12
AI Technical Summary
During the comparison of differential input signals, the comparator is prone to metastability, which causes the generated signal to lose pulse edges and affects the normal operation of the system.
The first clock signal and the ready signal are generated by the comparison processing module in the signal generation circuit, and the second ready signal is generated by the logic processing module in the metastable state according to the ready control signal, so as to avoid the loss of pulse edge.
In metastable conditions, signal pulse edge loss is avoided, ensuring normal system operation.
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Figure CN121124784A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, specifically to a signal generation circuit, chip, and electronic device. Background Technology
[0002] The comparison process of differential input signals can be implemented by a comparator. The comparison result of the comparator may be in a metastable state. Metastable state refers to the intermediate state in which the output of the comparator cannot reach a stable logic level (0 or 1) under certain conditions. At this time, the comparison result will oscillate around the threshold voltage or remain at an uncertain level.
[0003] In metastable conditions, the signal generated based on the comparator's comparison result will lose its pulse edge, resulting in an incomplete signal and affecting the subsequent normal operation of the system. Summary of the Invention
[0004] In view of the above problems, embodiments of this application provide a signal generation circuit, chip, and electronic device to solve the technical problem that the signal generated based on the comparison result will lose its pulse edge due to metastability.
[0005] In a first aspect, embodiments of this application provide a signal generation circuit, which includes a comparison processing module and a logic processing module. The comparison processing module is used to generate a first clock signal and a first ready signal based on a differential input signal. The logic processing module is used to generate a second ready signal based on the first clock signal, the first ready signal, and a ready control signal, and to generate the second ready signal according to the ready control signal when the first ready signal loses a pulse edge.
[0006] Secondly, embodiments of this application also provide a chip that includes the signal generation circuit described above.
[0007] Thirdly, embodiments of this application also provide an electronic device, which includes the signal generating circuit or chip described above.
[0008] The signal generation circuit, chip, and electronic device provided in this application embodiment generate a first clock signal and a first ready signal based on a differential input signal through a comparison processing module. The logic processing module generates a second ready signal based on the first clock signal, the first ready signal, and a ready control signal. When the first ready signal loses its pulse edge, the second ready signal is generated according to the ready control signal. In metastable conditions, the second ready signal can be generated based on the ready control signal instead of the comparison result, thereby avoiding the situation where the second ready signal loses its pulse edge due to metastability, which is beneficial to the normal operation of subsequent work.
[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 A schematic block diagram of the signal generation circuit provided in an embodiment of this application is shown.
[0012] Figure 2 The schematic diagram of the logic processing module is shown.
[0013] Figure 3 The schematic diagram of the first logic unit is shown.
[0014] Figure 4 The circuit schematic of the first logic subunit is shown.
[0015] Figure 5 The circuit schematic of the second logic subunit is shown.
[0016] Figure 6 The circuit schematic of the third logic subunit is shown.
[0017] Figure 7 The circuit schematic of the fourth logic subunit is shown.
[0018] Figure 8 The circuit schematic of the second logic unit is shown.
[0019] Figure 9 A block diagram of the comparison processing module is shown.
[0020] Figure 10 The first timing diagram of the signal generation circuit is shown.
[0021] Figure 11 A second timing diagram of the signal generation circuit is shown.
[0022] Figure 12 The third timing diagram of the signal generation circuit is shown.
[0023] Figure 13 The fourth timing diagram of the signal generation circuit is shown.
[0024] Figure 14 A schematic diagram of the chip structure provided in an embodiment of this application is shown.
[0025] Figure 15A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation
[0026] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0027] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0028] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0029] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0030] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0031] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0032] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0033] like Figure 1 As shown, this application embodiment provides a signal generation circuit 100, which includes a comparison processing module 10 and a logic processing module 20. The comparison processing module 10 is used to generate a first clock signal clk2 and a first ready signal rdy_dly based on differential input signals (Vip, Vin). The logic processing module 20 is used to generate a second ready signal Data_Ready based on the first clock signal clk2, the first ready signal rdy_dly, and the ready control signal rdy_cfg, and to generate the second ready signal Data_Ready according to the ready control signal rdy_cfg when the first ready signal rdy_dly loses its pulse edge.
[0034] It is understood that the signal generation circuit 100 provided in this application embodiment generates a first clock signal clk2 through the comparison processing module 10 and generates a first ready signal rdy_dly based on the differential input signal. The logic processing module 20 generates a second ready signal Data_Ready based on the first clock signal clk2, the first ready signal rdy_dly, and the ready control signal rdy_cfg. When the first ready signal rdy_dly loses its pulse edge, the second ready signal Data_Ready is generated according to the ready control signal rdy_cfg. In the case of metastability, the second ready signal Data_Ready can be generated according to the ready control signal rdy_cfg instead of the comparison result, thereby avoiding the situation where the second ready signal Data_Ready loses its pulse edge due to metastability, which is beneficial to the normal operation of subsequent work.
[0035] It should be noted that the pulse edge can be at least one of a rising edge and a falling edge.
[0036] In some embodiments, such as Figure 2As shown, the logic processing module 20 includes a first logic unit 21 and a second logic unit 22. The first logic unit 21 is used to generate a second clock signal da_clk based on a first clock signal clk2, a quantization indicator signal comp_en, a system clock signal sar_clk, and a ready control signal rdy_cfg. The second logic unit 22 is used to generate a second ready signal Data_Ready based on the first ready signal rdy_dly and the second clock signal da_clk, and to generate the second ready signal Data_Ready according to the ready control signal rdy_cfg when the first ready signal rdy_dly loses its pulse edge.
[0037] It should be noted that the first logic unit 21 is connected to the comparison processing module 10 to receive the first clock signal clk2, and the second logic unit 22 is connected to both the first logic unit 21 and the comparison processing module 10 to receive the second clock signal da_clk and the first ready signal rdy_dly, respectively. The first logic unit 21 generates an anti-interference second clock signal da_clk by integrating the first clock signal clk2, the quantization indicator signal comp_en, the system clock signal sar_clk, and the ready control signal rdy_cfg. The second logic unit 22 generates the final second ready signal Data_Ready based on the first ready signal rdy_dly and the second clock signal da_clk. When a pulse edge loss (metastable characteristic) of the first ready signal rdy_dly is detected, the ready control signal rdy_cfg is immediately activated using a hardware redundancy mechanism to generate the second ready signal Data_Ready, thereby achieving seamless switching in metastable scenarios and reducing or avoiding the pulse edge loss rate of the second ready signal Data_Ready.
[0038] In some embodiments, such as Figure 3 As shown, the first logic unit 21 includes a first logic subunit 211, a second logic subunit 212, a third logic subunit 213, and a fourth logic subunit 214. The first logic subunit 211 is used to delay the first clock signal clk2 and improve its driving capability to generate a third clock signal clk3. The second logic subunit 212 is used to generate a fourth clock signal clk1 based on the logical operation result of the quantization indicator signal comp_en and the system clock signal sar_clk. The third logic subunit 213 is used to perform an inversion operation on the ready control signal rdy_cfg. The fourth logic subunit 214 is used to generate a second clock signal da_clk based on the logical operation result of the third clock signal clk3, the fourth clock signal clk1, and the inverted ready control signal rdy_cfg.
[0039] It should be noted that the first logic subunit 211 is connected to the comparison processing module 10 to receive the first clock signal clk2, and the third logic subunit 213 is connected to the first logic subunit 211 and the second logic subunit 212 to receive the third clock signal clk3 and the fourth clock signal clk1, respectively. The first logic subunit 211 performs delay matching and drive enhancement on the first clock signal clk2 and outputs the optimized third clock signal clk3. The second logic subunit 212 performs logical operations on the quantization indicator signal comp_en and the system clock signal sar_clk to generate the fourth clock signal clk1 with a widened duty cycle. The third logic subunit 213 performs an inversion operation on the ready control signal rdy_cfg. The fourth logic subunit 214 integrates the third clock signal clk3, the fourth clock signal clk1, and the inverted ready control signal rdy_cfg, and arbitrates the output of the final second clock signal da_clk based on the level state of the ready control signal rdy_cfg. This improves the duty cycle of the second clock signal da_clk and significantly enhances the timing fault tolerance capability.
[0040] In some embodiments, such as Figure 4 As shown, the first logic subunit 211 includes an even number of serially connected first NOT gates, which are connected to a first clock signal clk2 and output a third clock signal clk3.
[0041] It should be noted that the even number of serially connected first NOT gates not only delay the phase of the first clock signal clk2 to meet timing requirements, but also shape the first clock signal clk2, increasing the slope of the pulse edge and thus improving the driving capability of the third clock signal clk3. The number of first NOT gates can be 2 (e.g., N11 and N12), 4, 6, 8, 10, or more, which can be set according to the delay requirements. In other embodiments, the first NOT gates can also be used as first inverters.
[0042] In some embodiments, such as Figure 5 As shown, the second logic subunit 212 includes a second NOT gate N2 and a first NOR gate ON1. The second NOT gate N2 is connected to the quantization indicator signal comp_en. The first input terminal of the first NOR gate ON1 is connected to the output terminal of the second NOT gate N2. The second input terminal of the first NOR gate ON1 is connected to the system clock signal sar_clk. The output terminal of the first NOR gate ON1 outputs the fourth clock signal clk1.
[0043] It should be noted that the second NOT gate N2 inverts the quantization indicator signal comp_en, and the first NOR gate ON1 performs a NOR operation on the inverted quantization indicator signal comp_en and the system clock signal sar_clk to generate the fourth clock signal clk1.
[0044] In some embodiments, such as Figure 6 As shown, the third logic subunit 213 includes a third NOT gate N3, the input of which is connected to the ready control signal rdy_cfg; the first input of the second NOR gate ON2 is connected to the output of the fourth logic subunit 214.
[0045] It should be noted that the third NOT gate N3 performs an inverted operation on the ready control signal rdy_cfg.
[0046] In some embodiments, such as Figure 7 As shown, the fourth logic sub-unit 214 includes a second NOR gate ON2. The first input terminal of the second NOR gate ON2 is connected to the output terminal of the third NOT gate N3. The second input terminal of the second NOR gate ON2 is connected to the third clock signal clk3. The third input terminal of the second NOR gate ON2 is connected to the fourth clock signal clk1. The output terminal of the second NOR gate ON2 outputs the second clock signal da_clk.
[0047] It should be noted that the second NOR gate ON2 performs a NOR operation on the ready control signal rdy_cfg after the inversion operation and the third clock signal clk3 and the fourth clock signal clk1 to generate the second clock signal da_clk.
[0048] In some embodiments, such as Figure 8 As shown, the second logic unit 22 includes a third NOR gate ON3 and a fourth NOT gate N4. The first input of the third NOR gate ON3 is connected to the output of the second NOR gate ON2, and the second input of the third NOR gate ON3 is connected to the first ready signal rdy_dly. The input of the fourth NOT gate N4 is connected to the output of the third NOR gate ON3, and the output of the fourth NOT gate N4 generates the second ready signal Data_Ready.
[0049] It should be noted that the third NOR gate ON3 directly receives the first ready signal rdy_dly and the second clock signal da_clk as inputs. Its output is inverted by the fourth NOT gate N4 to generate the second ready signal Data_Ready. When the first ready signal rdy_dly is abnormal due to metastability, the second clock signal da_clk is automatically filled in by the NOR gate logic, ensuring the integrity of the pulse edge of the second ready signal Data_Ready. This embodiment uses the third NOR gate ON3 and the fourth NOT gate N4 to form a simple and efficient fault-tolerant mechanism, which can prevent the loss of the pulse edge of the second ready signal Data_Ready caused by metastability.
[0050] In some embodiments, such as Figure 9 As shown, the comparison processing module 10 is used to generate a first clock signal clk2 based on the quantization indication signal comp_en and the system clock signal sar_clk, and generate a differential output signal based on the differential input signal under the control of the first clock signal clk2, and generate a first ready signal rdy_dly and a data signal Data based on the differential output signal and the system enable signal sar_en; wherein, the second ready signal Data_Ready is used to trigger the acquisition of the data signal Data.
[0051] It should be noted that, by avoiding the loss of the pulse edge of the second ready signal Data_Ready, the triggering loss of the acquisition of the data signal Data due to metastability can be avoided, thereby achieving complete acquisition of the data signal Data.
[0052] Figure 9 The signal generation circuit 100 shown can be applied to, but is not limited to, an analog-to-digital converter (ADC), which can be a differential input ADC, such as a successive approximation ADC (SAR ADC).
[0053] In the comparison processing module 10, the fifth NOT gate N5 inverts the quantization indicator signal comp_en, and the fourth NOR gate ON4 performs a NOR operation between the inverted quantization indicator signal comp_en and the system clock signal sar_clk. The resulting signal is then level-converted by the level converter LS to generate the first clock signal clk2. The buffer BUF buffers the first clock signal clk2 and controls the comparison and reset of the comparator CMP. For example, the rising and falling edges of the first clock signal clk2 are used sequentially to trigger the comparator CMP to compare and reset the differential input signals.
[0054] The comparison result output by the comparator CMP is a differential output signal (Outp, Outn). Two cascaded sixth NOT gates, such as N61 and N62, delay Outp and improve its driving capability before being connected to the first NAND gate AN1 to perform a NAND operation with the system enable signal sar_en. Two cascaded seventh NOT gates, such as N71 and N72, delay Outn and improve its driving capability before being connected to the second NAND gate AN2 to perform a NAND operation with the system enable signal sar_en.
[0055] Among them, the number of the sixth NOT gate can be an even number, and the number of the seventh NOT gate can be an even number.
[0056] The third NAND gate AN3 performs a NAND operation on the output signals of the first NAND gate AN1 and the second NAND gate AN2 to generate an initial ready signal "ready". After being delayed by the delay unit DLY, it generates a first ready signal "rdy_dly". The delay duration of the delay unit DLY can be controlled by the delay control signal "dy_adj" to meet different application requirements.
[0057] The fourth NAND gate AN4 performs a NAND operation on the output signal of the first NAND gate AN1 and the output signal of the fifth NAND gate AN5. The fifth NAND gate AN5 performs a NAND operation on the output signal of the second NAND gate AN2, the system enable signal sar_en, and the output signal of the fourth NAND gate AN4. The eighth NOT gate N8 inverts the output signal of the fourth NAND gate AN4 to generate the data signal Data.
[0058] It should be noted that in the analog-to-digital converter (ADC), the high level of the quantization indicator signal `comp_en` is used to instruct the ADC to perform quantization. The readiness control signal `rdy_cfg` is the control signal for the second readiness signal `Data_Ready`. When the readiness control signal `rdy_cfg` is high, it ensures that the pulse edge of the second readiness signal `Data_Ready` will not be lost if metastability occurs; when the readiness control signal `rdy_cfg` is low, the logic processing module 20 will not affect the generation result of the second readiness signal `Data_Ready`. The system enable signal `sar_en` is used to control whether the ADC enters the working state; for example, a high level is used as the effective level to trigger the ADC to enter the working state. The high level of the sampling signal is used to instruct the ADC to perform sampling. The differential input signal (Vip / Vin) is the output signal of the digital-to-analog converter (DAC). The rising edge of the second readiness signal `Data_Ready` can trigger the sampling or acquisition of the data signal `Data`.
[0059] The analog-to-digital converter can be an ADC with a synchronous clock.
[0060] The following analysis does not consider the delay of each logic gate and comparator CMP. For example... Figure 10 The diagram shows the ideal timing without considering metastability. When the system enable signal sar_en switches to high, the ADC starts working; the system clock signal sar_clk emits a corresponding pulse, and the ADC samples while the sampling signal is high. After the quantization indicator signal comp_en switches to high, the first falling edge of the system clock signal sar_clk corresponds to the first rising edge of the first clock signal clk2, the third clock signal clk3, and the fourth clock signal clk1. The pulse of Outp corresponds to the odd-numbered pulse of either the first clock signal clk2 or the third clock signal clk3, and the pulse of Outn corresponds to the even-numbered pulse of either the first clock signal clk2 or the third clock signal clk3. The pulse of the initial ready signal ready corresponds to the combination of the pulses of Outp and Outn. The pulse of the first ready signal rdy_dly has a corresponding delay compared to the pulse of the initial ready signal ready. The high level of the second ready signal Data_Ready triggers the sampling of the data signal Data.
[0061] If the ready control signal rdy_cfg is low and the second clock signal da_clk is low, the generation of the second ready signal Data_Ready is entirely dependent on the output signals of the comparator CMP, namely Outp and Outn. When the system enable signal sar_en is low, the initial level of the data signal Data is high, and the initial levels of the initial ready signal ready, the first ready signal rdy_dly, and the second ready signal Data_Ready are all low.
[0062] Figure 11 and Figure 10 The difference is that if the comparator CMP has a metastable state problem, the levels of Outp and Outn may not reach a stable state within half a cycle, causing the second ready signal Data_Ready to lose a rising edge.
[0063] and Figure 10 The difference is, Figure 12 The ready control signal rdy_cfg is high. The second clock signal da_clk is a widened clock signal (increased duty cycle) obtained by ORing the third clock signal clk3 and the fourth clock signal clk1. The initial level of the second ready signal Data_Ready is high, and its falling edge depends on the falling edge of the second clock signal da_clk, while its rising edge depends on the rising edge of the first ready signal rdy_dly.
[0064] and Figure 12 The difference is, Figure 13 If the comparator CMP experiences metastability, the levels of Outp and Outn may not reach a stable state within half a cycle. The initial ready signal ready and the first ready signal rdy_dly are both low. Then, the falling edge and rising edge of the second ready signal Data_Ready depend on the second clock signal da_clk, thus avoiding the loss of a rising edge of the second ready signal Data_Ready, and thus avoiding the problem of pulse edge loss caused by metastability.
[0065] like Figure 14 As shown, this application embodiment also provides a chip 200, which includes the signal generation circuit 100 described above. The chip 200 is also called an integrated circuit (IC), and it can be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip. For example, the chip 200 can be, but is not limited to, an analog-to-digital converter or a microprocessor unit (MCU).
[0066] It is understood that, since the chip 200 provided in this application embodiment includes a signal generation circuit 100, it can also generate a first clock signal clk2 and a first ready signal rdy_dly based on the differential input signal through the comparison processing module 10. The logic processing module 20 generates a second ready signal Data_Ready based on the first clock signal clk2, the first ready signal rdy_dly, and the ready control signal rdy_cfg. When the first ready signal rdy_dly loses its pulse edge, it generates the second ready signal Data_Ready according to the ready control signal rdy_cfg. In the case of metastability, it can avoid generating the second ready signal Data_Ready based on the comparison result instead of the ready control signal rdy_cfg, thereby avoiding the situation where the second ready signal Data_Ready loses its pulse edge due to metastability, which is beneficial to the normal operation of subsequent work.
[0067] like Figure 15As shown in the illustration, this application also provides an electronic device 300, which includes a device body and the aforementioned signal generating circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.
[0068] It is understood that, since the electronic device 300 provided in this application embodiment includes a signal generation circuit 100 or a chip 200, it can also generate a first clock signal clk2 and a first ready signal rdy_dly based on the differential input signal through the comparison processing module 10. The logic processing module 20 generates a second ready signal Data_Ready based on the first clock signal clk2, the first ready signal rdy_dly, and the ready control signal rdy_cfg. When the first ready signal rdy_dly loses its pulse edge, it generates the second ready signal Data_Ready according to the ready control signal rdy_cfg. In the case of metastability, it can avoid generating the second ready signal Data_Ready based on the comparison result instead of the ready control signal rdy_cfg, thereby avoiding the situation where the second ready signal Data_Ready loses its pulse edge due to metastability, which is conducive to the normal operation of subsequent work.
[0069] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A signal generation circuit, characterized in that, The signal generation circuit includes: The comparison processing module is used to generate a first clock signal and a first ready signal based on the differential input signal; The logic processing module is configured to generate a second ready signal based on the first clock signal, the first ready signal, and the ready control signal, and generate the second ready signal according to the ready control signal when the first ready signal loses its pulse edge.
2. The signal generation circuit as described in claim 1, characterized in that, The logic processing module includes: The first logic unit is configured to generate a second clock signal based on the first clock signal, the quantization indication signal, the system clock signal, and the ready control signal. The second logic unit is configured to generate the second ready signal based on the first ready signal and the second clock signal, and to generate the second ready signal according to the ready control signal when the first ready signal loses its pulse edge.
3. The signal generation circuit as described in claim 2, characterized in that, The first logic unit includes: The first logic subunit is used to delay the first clock signal and improve its driving capability to generate a third clock signal; The second logic subunit is used to generate a fourth clock signal based on the logical operation result of the quantization indication signal and the system clock signal; The third logic subunit is used to perform an inversion operation on the ready control signal; The fourth logic subunit is used to generate the second clock signal based on the logical operation result of the third clock signal, the fourth clock signal, and the ready control signal after inversion.
4. The signal generation circuit as described in claim 3, characterized in that, The first logic sub-unit includes an even number of serially connected first NOT gates, which are connected to the first clock signal and output the third clock signal.
5. The signal generation circuit as described in claim 3, characterized in that, The second logic subunit includes: The second NOT gate is connected to the quantization indication signal; The first NOR gate has its first input connected to the output of the second NOT gate, its second input connected to the system clock signal, and its output outputting the fourth clock signal.
6. The signal generation circuit as described in claim 3, characterized in that, The third logic subunit includes a third NOT gate, the input of which is connected to the ready control signal, and the output of which is connected to the input of the fourth logic subunit.
7. The signal generation circuit as described in claim 3, characterized in that, The fourth logic subunit includes a second NOR gate, the first input of the second NOR gate is connected to the output of the third logic subunit, the second input of the second NOR gate is connected to the third clock signal, the third input of the second NOR gate is connected to the fourth clock signal, and the output of the second NOR gate outputs the second clock signal.
8. The signal generation circuit as described in claim 7, characterized in that, The second logic unit includes: The third NOR gate has its first input connected to the output of the second NOR gate, and its second input connected to the first ready signal. The fourth NOT gate has its input connected to the output of the third NOR gate, and its output generates the second ready signal.
9. The signal generation circuit according to any one of claims 1 to 8, characterized in that, The comparison processing module is used to generate the first clock signal based on the quantization indication signal and the system clock signal, and generate a differential output signal based on the differential input signal under the control of the first clock signal, and generate the first ready signal and the data signal based on the differential output signal and the system enable signal. The second ready signal is used to trigger the acquisition of the data signal.
10. A chip, characterized in that, The chip includes the signal generation circuit as described in any one of claims 1 to 9.
11. An electronic device, characterized in that, The electronic device includes a device body and a signal generating circuit as described in any one of claims 1 to 9 or a chip as described in claim 10 disposed on the device body.