Signal receiving circuit and receiver
By introducing first and second decision feedback equalizers and digital filters into the receiver, the problem that decision feedback equalizers cannot eliminate crosstalk between adjacent channels is solved, thereby improving the crosstalk cancellation effect and anti-interference performance of the receiver.
Patent Information
- Application Number
- CN202411717310.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-12-12
AI Technical Summary
The decision feedback equalizer in the existing technology cannot effectively eliminate crosstalk between adjacent channels, resulting in poor crosstalk cancellation performance of the receiver.
A signal receiving circuit including a first decision feedback equalizer and at least one second decision feedback equalizer is used. Crosstalk signals are extracted and eliminated through the second decision feedback equalizers corresponding to adjacent channels. Signal processing is performed in combination with digital filters to achieve crosstalk elimination between adjacent channels.
It improves the crosstalk cancellation effect of the receiver, enhances the eye diagram output quality, reduces the load on high-speed nodes of the circuit, increases the analog bandwidth, and optimizes the crosstalk signal from analog to digital to enhance anti-interference capability.
Smart Images
Figure CN121125402A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of communication, and in particular to a signal receiving circuit and a receiver. BACKGROUND
[0002] In the related art, a receiver performs inter-symbol interference cancellation through a decision feedback equalizer. The decision feedback equalizer is used to restore the original shape and quality of a signal, and subtracts an input signal from a decision signal after digital filtering, so as to cancel the post-cursor inter-symbol interference. However, as the integration requirement increases, the density of a high-speed interconnection interface is higher and higher, and there are many parallel channels in the output interface of the high-speed interconnection interface, which causes serious crosstalk between adjacent channels. The decision feedback equalizer in the related art can only cancel the inter-symbol interference, and cannot cancel the crosstalk between adjacent channels, which leads to poor crosstalk cancellation effect of the receiver. SUMMARY
[0003] Embodiments of the present application provide a signal receiving circuit and a receiver including a first decision feedback equalizer and at least one second decision feedback equalizer, to solve the problem that the decision feedback equalizer in the related art can only cancel the inter-symbol interference, and cannot cancel the crosstalk between adjacent channels, which leads to poor crosstalk cancellation effect of the receiver.
[0004] To solve the above technical problems, the present application is implemented as follows:
[0005] In a first aspect, embodiments of the present application provide a signal receiving circuit, which includes a first decision feedback equalizer and at least one second decision feedback equalizer, and the first decision feedback equalizer includes:
[0006] a first processing circuit, which includes a first input end and at least one second input end, the first input end is connected with a first channel, and each second input end is connected with an output end of a corresponding second decision feedback equalizer through a first filter circuit of the corresponding second decision feedback equalizer in a one-to-one correspondence, and the second decision feedback equalizer is a decision feedback equalizer corresponding to an adjacent channel of the first channel;
[0007] The first filter circuit is configured to extract crosstalk signals of the first channel from a channel corresponding to the second decision feedback equalizer, and the first processing circuit is configured to cancel the crosstalk signals of the first channel from the adjacent channel.
[0008] Optionally, the first decision feedback equalizer further includes a first decision device and a second filter circuit.
[0009] The first processing circuit further includes a third input terminal, which is connected to the output terminal of the first decision device through the second filtering circuit. The output terminal of the first processing circuit is connected to the first decision device, and the input terminal of the first decision device is connected to the output terminal of the first processing circuit.
[0010] The first decision unit is used to decide the output signal of the first processing circuit to output a digital signal, the second filtering circuit is used to extract the inter-symbol interference signal of the first channel, and the first processing circuit is also used to eliminate the inter-symbol interference signal of the first channel.
[0011] Optionally, the first decision feedback equalizer further includes a third filtering circuit, and each of the second decision feedback equalizers includes a second processing circuit.
[0012] The second processing circuit includes a fourth input terminal and a fifth input terminal. The fourth input terminal is connected to the corresponding second channel, and the fifth input terminal is connected to the output terminal of the first decision device through the third filter circuit of the first decision feedback equalizer.
[0013] Wherein, the second channel and the first channel are adjacent channels, the third filtering circuit is used to extract the crosstalk signal of the first channel to the second channel, and the second processing circuit is used to eliminate the crosstalk signal of the first channel to the second channel.
[0014] Optionally, the first filtering circuit is a digital filter; and / or,
[0015] The third filtering circuit is a digital filter.
[0016] Optionally, each of the second decision feedback equalizers further includes:
[0017] Second decision-making device;
[0018] Fourth filter circuit;
[0019] The second processing circuit also includes a sixth input terminal, which is connected to the output terminal of the second decision device belonging to the same second decision feedback equalizer through a fourth filter circuit belonging to the same second decision feedback equalizer. The output terminal of the second processing circuit is connected to the second decision device belonging to the same second decision feedback equalizer.
[0020] The second decision unit is used to decide the output digital signal of the output signal of the second processing circuit belonging to the same second decision feedback equalizer. The fourth filter circuit is used to extract the inter-symbol interference signal of the second channel. The second processing circuit is also used to eliminate the inter-symbol interference signal of the second channel.
[0021] Optionally, each of the second decision feedback equalizers further includes the first filtering circuit;
[0022] The input terminal of the second decision device is connected to the output terminal of the second processing circuit belonging to the same second decision feedback equalizer, and the output terminal of the second decision device is connected to the first processing circuit of the first decision feedback equalizer through the first filter circuit belonging to the same second decision feedback equalizer.
[0023] The first filtering circuit is used to extract the crosstalk signal of the second channel to the first channel from the output signal of the second decision device belonging to the same second decision feedback equalizer, and input the extracted crosstalk signal into the first processing circuit.
[0024] Optionally, the sampling clock used by the first decision feedback equalizer is half the data transmission rate of the signal receiving circuit.
[0025] Optionally, the signal receiving circuit further includes a first analog front-end circuit, and the first input terminal of the first processing circuit is connected to the first channel through the first analog front-end circuit;
[0026] The first analog front-end circuit is used to perform analog front-end processing on the signal of the first channel and input the processed analog signal into the first processing circuit.
[0027] Optionally, the output signal of the first processing circuit is the difference between the input signal of the first input terminal of the first processing circuit and the target signal, wherein the target signal is the sum of the input signals of at least one second input terminal of the first processing circuit and the input signal of the third input terminal of the first processing circuit.
[0028] Secondly, embodiments of this application provide a receiver, which includes the signal receiving circuit described in the first aspect.
[0029] In this embodiment, the signal receiving circuit includes a first decision feedback equalizer and at least one second decision feedback equalizer. The first decision feedback equalizer includes a first processing circuit, which includes a first input terminal and at least one second input terminal. The first input terminal is connected to a first channel. Each second input terminal is connected to the output terminal of a corresponding second decision feedback equalizer through a first filtering circuit of that second decision feedback equalizer. The second decision feedback equalizer is a decision feedback equalizer corresponding to an adjacent channel of the first channel. The first filtering circuit is used to extract crosstalk signals from the channel corresponding to the second decision feedback equalizer to the first channel, and the first processing circuit is used to eliminate crosstalk signals from the adjacent channels to the first channel. Thus, by using the second decision feedback equalizer corresponding to the adjacent channel for crosstalk cancellation, and filtering the output of the second decision feedback equalizer corresponding to the adjacent channel, the crosstalk signal output by the second decision feedback equalizer corresponding to the adjacent channel is input to the first processing circuit of the first decision feedback equalizer for crosstalk cancellation of the adjacent channels. This eliminates the crosstalk signals from the adjacent channels to the first channel, thereby improving the crosstalk cancellation effect of the receiver. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is one of the structural schematic diagrams of a signal receiving circuit provided in the embodiments of this application;
[0032] Figure 2 This is a second schematic diagram of a signal receiving circuit provided in an embodiment of this application;
[0033] Figure 3a This is a schematic diagram of the structure of a decision feedback equalizer in related technologies;
[0034] Figure 3b This is a schematic diagram of the structure of a receiver in related technologies;
[0035] Figure 3c yes Figure 3b The diagram shows the channel impulse response of the receiver.
[0036] Figure 4 This is the third schematic diagram of a signal receiving circuit provided in the embodiments of this application;
[0037] Figure 5aIt is one of the interface display diagrams for signal simulation;
[0038] Figure 5b This is the second screenshot of the signal simulation interface.
[0039] Figure 5c This is the third screenshot of the signal simulation interface.
[0040] Figure 5d This is the fourth screenshot of the signal simulation interface. Detailed Implementation
[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0042] In this application embodiment, a signal receiving circuit and receiver are proposed to solve the problem that decision feedback equalizers in related technologies can only eliminate inter-symbol interference but cannot eliminate crosstalk between adjacent channels, resulting in poor crosstalk cancellation effect of the receiver.
[0043] The signal receiving circuit and receiver provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.
[0044] like Figure 1 and Figure 2 As shown, this application embodiment provides a signal receiving circuit, which includes a first decision feedback equalizer 10 and at least one second decision feedback equalizer 20. The first decision feedback equalizer 10 includes:
[0045] The first processing circuit 101 includes a first input terminal and at least one second input terminal. The first input terminal is connected to the first channel. Each second input terminal is connected to the output terminal of the corresponding second decision feedback equalizer 20 through the first filter circuit 201 of the corresponding second decision feedback equalizer 20. The second decision feedback equalizer 20 is a decision feedback equalizer corresponding to the adjacent channel of the first channel.
[0046] The first filtering circuit 201 is used to extract the crosstalk signal between the channel corresponding to the second decision feedback equalizer 20 and the first processing circuit 101 is used to eliminate the crosstalk signal between the adjacent channel and the first channel.
[0047] The first filtering circuit 201 can be a digital filter. For example, it can be a finite impulse response (FIR) filter, such as a low-pass filter, high-pass filter, band-pass filter, or band-stop filter. This application does not limit the specific structure of the first filtering circuit 201. The type of the first filtering circuit can be determined based on the signal characteristics of the second channel. For example, a high-pass filter can be selected when low-frequency signals need to be filtered out, and a low-pass filter can be selected when high-frequency signals need to be filtered out.
[0048] The first processing circuit 101 can be a circuit for summation, such as a summation circuit.
[0049] The at least one second input terminal can be connected to the output terminal of the second decision unit 203 of the at least one second decision feedback equalizer 20 through the first filter circuit 201 of the at least one second decision feedback equalizer 20. For example... Figure 1 As shown, the second input terminal is connected to the output terminal of the second decision circuit 203 of the second decision feedback equalizer 20 through the first filter circuit 201 of the second decision feedback equalizer 20. Figure 2 As shown, taking m second decision feedback equalizers 20 as an example, the first processing circuit 101 includes m second input terminals. Second input terminal A1 is connected to the output terminal of the second decision equalizer 203 of the second decision feedback equalizer B1 through the first filter circuit 201 of the second decision feedback equalizer B1; second input terminal A2 is connected to the output terminal of the second decision equalizer 203 of the second decision feedback equalizer B2 through the first filter circuit 201 of the second decision feedback equalizer B2; ...; second input terminal A m Through the second decision feedback equalizer B m The first filter circuit 201 and the second decision feedback equalizer B m The output of the second decision unit 203 is connected.
[0050] It should be noted that the decision unit in the signal receiving circuit (such as the first decision unit and / or the second decision unit) can be used to determine the value of each symbol. The decision unit quantizes the input signal, converting the analog signal into a digital signal. The output value of the decision unit can also be used to calculate the error between the actual received signal and the decision output.
[0051] In one embodiment, the receiver includes the signal receiving circuit, and the receiver may be a receiver with a high-speed interface SerDes.
[0052] SerDes are a crucial component of the physical interconnect interface for Graphics Processing Units (GPUs). Within the GPU interconnect protocol, they belong to the Packed Memory Array (PMA) sublayer of the physical layer, primarily converting parallel circuits into series circuits. SerDes consist of transmitters (TX) and receivers (RX). Each pair of TX and RX forms a lane. GPU output interfaces typically have multiple ports, each composed of multiple lanes. The quality of these lanes determines the performance of the GPU interconnect, meaning the performance of SerDes directly impacts the high-speed interconnect performance between GPU cards.
[0053] As integration requirements increase, the density of high-speed interconnect interfaces is becoming higher and higher. The output interfaces of high-speed interconnect interfaces have many parallel channels, which leads to serious crosstalk problems between adjacent channels.
[0054] In related technologies, crosstalk cancellation can be achieved using adjacent channel crosstalk cancellation (XTC) circuits. These circuits typically employ a subtraction of the input signal and the crosstalk signal. While this achieves crosstalk cancellation, it increases the circuit load and reduces analog bandwidth at high-speed nodes. In this embodiment, the sampling clock used by the first decision feedback equalizer can be half the data transmission rate of the signal receiving circuit. Therefore, this embodiment improves anti-interference capabilities by performing crosstalk cancellation at half the low frequency and using a digital signal scheme.
[0055] In related technologies, crosstalk cancellation is achieved through decision feedback equalization (DFE). The working principle of a decision feedback equalization (DFE) is as follows: Figure 3a As shown, DFE equalization technology is used to restore the original shape and quality of the signal. The input signal is subtracted from the decision signal after digital filtering, which can eliminate the inter-symbol interference (ISI). That is, the feedback part can eliminate the inter-symbol interference that is ahead in time (the preamble interference of the following symbol to the current symbol) and the inter-symbol interference that is lagging in time.
[0056] High-speed transceiver DFEs can use a half-rate architecture for equalization. However, as SerDes rates increase, interface packaging density increases, and adjacent channel density also increases, leading to stronger inter-channel crosstalk. Figure 3bAs shown, the two-phase clock divides the input data into odd and even modes, reducing the output node data rate to half that of the input. This structure, with the input signal passing through the channel and analog front-end (DFE), can only eliminate the tailing of the impulse response and interference between preceding and following codes, but cannot eliminate crosstalk between adjacent channels, resulting in poor eye diagram quality at the receiver RX. Figure 3c As shown.
[0057] In this embodiment, the sampling clock used by the first decision feedback equalizer can be half the data transmission rate of the signal receiving circuit. Therefore, this embodiment proposes a decision feedback equalizer with crosstalk cancellation based on a half-rate architecture. By embedding the crosstalk cancellation circuit within the decision feedback equalizer, the eye diagram output quality (such as eye height and eye width opening) can be enhanced, the load on high-speed nodes of the circuit can be reduced, and the receiver's analog bandwidth can be increased.
[0058] In this embodiment, a first processing circuit 101 includes a first input terminal and at least one second input terminal. The first input terminal is connected to a first channel. Each second input terminal is connected to the output terminal of a corresponding second decision feedback equalizer 20 through a first filtering circuit 201 of the second decision feedback equalizer 20. The second decision feedback equalizer 20 is a decision feedback equalizer corresponding to an adjacent channel of the first channel. The first filtering circuit 201 is used to extract crosstalk signals from the channel corresponding to the second decision feedback equalizer 20 to the first channel, and the first processing circuit 101 is used to eliminate the crosstalk signals from the adjacent channels to the first channel. Thus, by using the second decision feedback equalizer corresponding to the adjacent channel for crosstalk cancellation, and filtering the output of the second decision feedback equalizer 20 corresponding to the adjacent channel, the crosstalk signal output by the second decision feedback equalizer 20 is input to the first processing circuit 101 of the first decision feedback equalizer 10 for crosstalk cancellation of the adjacent channels. This eliminates the crosstalk signals from the adjacent channels to the first channel, thereby improving the crosstalk cancellation effect of the receiver.
[0059] Optionally, the first decision feedback equalizer 10 further includes a first decision unit 102 and a second filter circuit 103;
[0060] The first processing circuit 101 also includes a third input terminal;
[0061] The third input terminal is connected to the output terminal of the first decision device 102 through the second filter circuit 103, and the output terminal of the first processing circuit 101 is connected to the first decision device 102.
[0062] The first decision unit 102 is used to decide to output a digital signal based on the output signal of the first processing circuit 101, the second filtering circuit 103 is used to extract the inter-symbol interference signal of the first channel, and the first processing circuit 101 is also used to eliminate the inter-symbol interference signal of the first channel.
[0063] The second filtering circuit 103 can be a digital filter. For example, the second filtering circuit 103 can be an FIR filter, such as a low-pass filter, high-pass filter, band-pass filter, or band-stop filter. This application embodiment does not limit the specific structure of the second filtering circuit 103. The type of the second filtering circuit 103 can be determined based on the signal characteristics of the first channel. For example, a high-pass filter can be selected when low-frequency signals need to be filtered out, and a low-pass filter can be selected when high-frequency signals need to be filtered out.
[0064] In this embodiment, the third input terminal is connected to the output terminal of the first decision device 102 through the second filter circuit 103, and the output terminal of the first processing circuit 101 is connected to the first decision device 102. The first processing circuit 101 eliminates the inter-symbol interference signal extracted by the second filter circuit 103 from the signal of the first channel, thereby eliminating the inter-symbol interference of the first channel and further improving the crosstalk cancellation effect of the receiver.
[0065] Optionally, the first decision feedback equalizer 10 further includes a third filter circuit 104, and each of the second decision feedback equalizers 20 includes a second processing circuit 202.
[0066] The second processing circuit 202 includes a fourth input terminal and a fifth input terminal. The fourth input terminal is connected to the corresponding second channel, and the fifth input terminal is connected to the output terminal of the first decision device 102 through the third filter circuit 104 of the first decision feedback equalizer 10.
[0067] Wherein, the second channel and the first channel are adjacent channels, and the third filter circuit 104 is used to extract the crosstalk signal of the first channel to the second channel;
[0068] The second processing circuit 202 is used to eliminate crosstalk signals from the first channel to the second channel.
[0069] The second processing circuit 202 can be a circuit for summation, such as a summation circuit.
[0070] The third filtering circuit 104 can be a digital filter. For example, the third filtering circuit 104 can be an FIR filter, such as a low-pass filter, high-pass filter, band-pass filter, or band-stop filter. This application embodiment does not limit the specific structure of the third filtering circuit 104. The type of the third filtering circuit 104 can be determined based on the signal characteristics of the first channel. For example, a high-pass filter can be selected when low-frequency signals need to be filtered out, and a low-pass filter can be selected when high-frequency signals need to be filtered out.
[0071] In this embodiment, the second processing circuit 202 includes a fourth input terminal and a fifth input terminal. The fourth input terminal is connected to the second channel, and the fifth input terminal is connected to the output terminal of the first decision device 102 through the third filter circuit 104 of the first decision feedback equalizer 10. In this way, the crosstalk signal output by the first decision device 102 of the first decision feedback equalizer 10 after filtering is input into the second processing circuit 202 of the second decision feedback equalizer 20 to cancel crosstalk between adjacent channels. This can eliminate the crosstalk signal from the first channel to the second channel, thereby further improving the crosstalk cancellation effect of the receiver.
[0072] Optionally, the first filtering circuit 201 is a digital filter; and / or,
[0073] The third filter circuit 104 is a digital filter.
[0074] In this embodiment, the first filtering circuit 201 is a digital filter, and the third filtering circuit 104 is a digital filter. The transmission of crosstalk signals is optimized from analog signals to digital signals. The digital signal transmission process has stronger anti-interference capabilities and can improve the anti-interference performance of the receiver.
[0075] Optionally, each of the second decision feedback equalizers 20 further includes:
[0076] Second decision-making device 203;
[0077] Fourth filter circuit 204;
[0078] The second processing circuit 202 also includes a sixth input terminal, which is connected to the output terminal of the second decision device 203 belonging to the same second decision feedback equalizer through the fourth filter circuit 204 belonging to the same second decision feedback equalizer. The output terminal of the second processing circuit 202 is connected to the second decision device 203 belonging to the same second decision feedback equalizer.
[0079] The second decision unit 203 is used to decide and output a digital signal based on the output signal of the second processing circuit 202 belonging to the same second decision feedback equalizer.
[0080] The fourth filtering circuit 204 is used to extract the inter-symbol interference signal of the second channel;
[0081] The second processing circuit 202 is also used to eliminate inter-symbol interference signals of the second channel.
[0082] The fourth filtering circuit 204 can be a digital filter. For example, the fourth filtering circuit 204 can be an FIR filter, such as a low-pass filter, high-pass filter, band-pass filter, or band-stop filter. This application does not limit the specific structure of the fourth filtering circuit 204. The type of the fourth filtering circuit 204 can be determined based on the signal characteristics of the second channel. For example, a high-pass filter can be selected when low-frequency signals need to be filtered out, and a low-pass filter can be selected when high-frequency signals need to be filtered out.
[0083] In this embodiment, the second processing circuit 202 is connected to the output terminal of the second decision unit 203 through the fourth filter circuit 204. The output terminal of the second processing circuit 202 is connected to the second decision unit 203. The inter-symbol interference signal is eliminated by the second processing circuit 202 of the second decision feedback equalizer 20, which can further improve the crosstalk cancellation effect of the receiver.
[0084] Optionally, each of the second decision feedback equalizers 20 further includes the first filter circuit 201;
[0085] The input terminal of the second decision device 203 is connected to the output terminal of the second processing circuit 202 belonging to the same second decision feedback equalizer, and the output terminal of the second decision device 203 is connected to the first processing circuit 101 of the first decision feedback equalizer 10 through the first filter circuit 201 belonging to the same second decision feedback equalizer.
[0086] The first filtering circuit 201 is used to extract the crosstalk signal of the second channel to the first channel from the output signal of the second decision device 203 belonging to the same second decision feedback equalizer, and input the extracted crosstalk signal into the first processing circuit 101.
[0087] In this embodiment, the crosstalk signal output by the second decision unit 203 of the second decision feedback equalizer 20 after filtering is input into the first processing circuit 101 of the first decision feedback equalizer 10 to cancel crosstalk between adjacent channels, which can improve the crosstalk cancellation effect of the receiver.
[0088] Optionally, the sampling clock used by the first decision feedback equalizer 10 is half the data transmission rate of the signal receiving circuit.
[0089] In addition, the sampling clock used by the second decision feedback equalizer 20 can be half of the data transmission rate of the signal receiving circuit.
[0090] Taking the signal receiving circuit used in a receiver as an example, the sampling clock used by the decision feedback equalizer in the receiver is half the data transmission rate of the receiver. The receiver down-converts the signal into two paths using a half-rate architecture. The sampling clock used by the receiver's decision feedback equalizer is half the data rate, which is the Nyquist frequency clock frequency, and can be alternately sampled using inverted clocks clk and clkb respectively. Compared to full frequency, operating at half rate allows for operation at lower frequencies, reducing the design burden of high-speed node circuits and, to some extent, improving the high-frequency node bandwidth of the receiver.
[0091] In this embodiment, the sampling clock used by the first decision feedback equalizer 10 is half the data transmission rate of the signal receiving circuit, thereby enabling the conversion of high-frequency signals into low-frequency signals and using the low-frequency signals for crosstalk cancellation in adjacent channels. This reduces the design burden of high-speed node circuits and can improve the high-frequency node bandwidth of the receiver to a certain extent.
[0092] Optionally, the signal receiving circuit further includes a first analog front-end circuit, and the first input terminal of the first processing circuit 101 is connected to the first channel through the first analog front-end circuit;
[0093] The first analog front-end circuit is used to perform analog front-end processing on the signal of the first channel and input the processed analog signal into the first processing circuit 101.
[0094] The first analog front-end circuit can be an analog front-end (AFE) circuit.
[0095] In addition, the signal receiving circuit may also include a second analog front-end circuit, and the fourth input terminal of the second processing circuit 202 is connected to the second channel through the second analog front-end circuit; the second analog front-end circuit is used to perform analog front-end processing on the signal of the second channel and input the processed analog signal into the second processing circuit 202.
[0096] In this embodiment, the first input terminal of the first processing circuit 101 is connected to the first channel through the first analog front-end circuit, so that the input signal of the first input terminal of the first processing circuit 101 can be processed by the first analog front-end circuit and then crosstalk cancellation processing can be performed, thereby optimizing the input analog signal and further improving the crosstalk cancellation effect.
[0097] Optionally, the output signal of the first processing circuit 101 is the difference between the input signal of the first input terminal of the first processing circuit 101 and the target signal, wherein the target signal is the sum of the input signals of at least one second input terminal of the first processing circuit 101 and the input signals of the third input terminal of the first processing circuit 101.
[0098] For example, taking a second input terminal as an example, the output signal of the output terminal of the first processing circuit 101 can be described as follows:
[0099]
[0100] Where x1(n) is the output signal of the first processing circuit 101, y1(n) is the input signal of the first input of the first processing circuit 101, and W i (i = 1, 2, ..., k, where k is the total number of taps) is the coefficient of the i-th tap, W XTC(i) (i = 1, 2, ..., k, where k is the total number of taps) is the i-th tap coefficient of crosstalk cancellation (XTC). The input signal is the third input terminal. d(ni) is the input signal at the second input terminal. d(ni) is the decision signal delayed by i delay units. d1(ni) is the decision signal output by the first decision unit 102 delayed by i delay units, and d2(ni) is the decision signal output by the second decision unit 203 delayed by i delay units.
[0101] In this embodiment, the output signal of the first processing circuit 101 is the difference between the input signal of the first input terminal of the first processing circuit 101 and the target signal. The target signal is the sum of the input signals of at least one second input terminal of the first processing circuit 101 and the input signal of the third input terminal of the first processing circuit 101. This can eliminate inter-symbol interference of the receiver and eliminate crosstalk between adjacent channels of the receiver, thereby optimizing the signal output characteristics of the receiver.
[0102] Optionally, the output signal of the output terminal of the second processing circuit 202 is the difference between the input signal of the fourth input terminal of the second processing circuit 202 and the first signal, wherein the first signal is the sum of the input signal of the fifth input terminal of the second processing circuit 202 and the input signal of the sixth input terminal of the second processing circuit 202.
[0103] The output signal at the output terminal of the second processing circuit 202 can be described as follows:
[0104]
[0105] Where x2(n) is the output signal of the output terminal of the second processing circuit 202, y2(n) is the input signal of the fourth input terminal of the second processing circuit 202, and W i (i = 1, 2, ..., k, where k is the total number of taps) is the coefficient of the i-th tap, W XTC(i) (i = 1, 2, ..., k, where k is the total number of taps) is the i-th tap coefficient of crosstalk cancellation (XTC). The input signal is the sixth input terminal. This is the input signal at the fifth input terminal. d(ni) is the decision signal delayed by i delay units. d1(ni) is the decision signal output by the first decision unit 102 delayed by i delay units, and d2(ni) is the decision signal output by the second decision unit 203 delayed by i delay units.
[0106] Optionally, the input signal at the second input terminal of the first processing circuit 101 is the crosstalk signal between the channel corresponding to the second decision feedback equalizer 20 and the first channel.
[0107] In this embodiment, the at least one second input terminal is connected to the output terminal of the second decision device 203 of the at least one second decision feedback equalizer 20 through the first filter circuit 201 of the at least one second decision feedback equalizer 20. The crosstalk signal of the adjacent channel (such as the second channel) to the first channel can be extracted through the first filter circuit 201 and the second decision device 203, thereby enabling the crosstalk cancellation of the adjacent channel.
[0108] Optionally, the input signal at the third input terminal of the first processing circuit 101 is the inter-symbol interference signal of the first channel.
[0109] In this embodiment, the third input terminal is connected to the output terminal of the first decision device 102 through the second filter circuit 103, and the inter-symbol interference signal of the first channel can be extracted through the second filter circuit 103 and the first decision device 102, thereby eliminating inter-symbol interference.
[0110] This application also provides a receiver, which includes the signal receiving circuit described in this application.
[0111] The decision feedback equalizer with crosstalk cancellation proposed in this application embodiment can be used in the receiver (RX) section of a high-speed interface SerDes.
[0112] The crosstalk cancellation described in this application mainly involves extracting and eliminating crosstalk between adjacent channels and between symbols after the receiver has reduced the received data speed. The receiver uses a half-rate architecture to down-frequency the signal into two paths, such as... Figure 4As shown, ODD and EVEN represent odd and even numbers, respectively. The sampling clock used by the receiver's decision feedback equalizer is half the data rate, which is the Nyquist frequency. Odd and even numbers are sampled alternately using inverted clocks clk and clkb, respectively. Compared to full frequency, operating at half the data rate allows for operation at lower frequencies, reducing the design burden of high-speed node circuits and potentially increasing the bandwidth of the receiver's high-frequency nodes.
[0113] Figure 4 This is a schematic diagram of the crosstalk cancellation circuit structure according to an embodiment of this application, which is a... Figure 3c An improvement to the DFE circuit structure without XTC technology. CLK_ODD is a comparator, also known as a decision unit, used to determine the value of each symbol. The decision unit quantizes the input signal, converting the analog signal into a digital signal. The output value of this decision unit is also used to calculate the error between the actual received signal and the decision output. This error signal can be used to adjust the tap coefficients of the DFE. The crosstalk cancellation circuit in this embodiment adds a digital filter for the crosstalk signal at the output of the DFE decision unit, sending the crosstalk signal to the DFE of the adjacent channel, which can be used to eliminate the trailing crosstalk.
[0114] The feedback subtraction section is a transverse filter structure. The decision breaker introduces nonlinearity to prevent the DFE from amplifying noise and crosstalk. y(n) and x(n) represent the signals before and after crosstalk cancellation, respectively, and W... i (i = 1, 2, ..., k, where k is the total number of taps) is the coefficient of the i-th tap, W XTC(i) (i = 1, 2, ..., k, where k is the total number of taps) represents the coefficient of the i-th tap of the XTC. d(n) is the decision signal obtained by the decision maker from the crosstalk-cancelled signal x(n). The crosstalk-cancelled signal is calculated using the following formula:
[0115]
[0116]
[0117] Where d(ni) is the decision signal delayed by i delay units. x1(n) and x2(n) are signals obtained by integrating the decision output signals between adjacent channels and the decision output signals of their own channels. For a single channel, they can not only eliminate inter-symbol interference, but also eliminate crosstalk between channels and optimize signal output characteristics.
[0118] like Figure 2 As shown, the formula for canceling crosstalk between m adjacent channels is as follows:
[0119]
[0120] The simulation results of crosstalk cancellation using the crosstalk cancellation circuit are shown in Table 1.
[0121] Table 1
[0122] No DFE DFE No XTC DFE With XTC Eye height (V) 0.804 0.913 1.025 Eye width (UI) 0.46 0.50 0.53
[0123] In Table 1, "no DFE" means that the receiver does not have a DFE; "with DFE but no XTC" means that the receiver has a DFE but the DFE does not have a crosstalk cancellation circuit for eliminating crosstalk between adjacent channels (i.e., the DFE in the related art); "with DFE and XTC" means that the receiver has a DFE and the DFE has a crosstalk cancellation circuit for eliminating crosstalk between adjacent channels (i.e., the DFE provided in the embodiments of this application).
[0124] Taking a 20G (speed not limited to 20G) NRZ signal (not limited to NRZ signal) as an example, Figure 5a , Figure 5b , Figure 5c and Figure 5d Table 1 shows the simulation results for a 20G NRZ signal. The channel loss at the Nyquist frequency is -6.09 dB, the near-end crosstalk (NEXT) is -8.58 dB, and both the DFE equalization and XTC tap count are 1. According to the simulation results, adding XTC technology increases the DFE eye height by 12.3% and the eye width by 6%.
[0125] The receiver in this application uses low-frequency signals for adjacent channel crosstalk cancellation, which can reduce the design burden of high-speed node circuits and improve the high-frequency node bandwidth of the receiver to a certain extent. In addition, the receiver in this application optimizes the transmission of crosstalk signals from analog signals to digital signals. The digital signal transmission process has stronger anti-interference capabilities and can improve the anti-interference performance of the receiver.
[0126] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects.
[0127] In the description of this application, it should be understood that the terms "length", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0128] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0129] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0130] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
[0131] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A signal receiving circuit, characterized in that, The signal receiving circuit includes a first decision feedback equalizer and at least one second decision feedback equalizer, wherein the first decision feedback equalizer includes: The first processing circuit includes a first input terminal and at least one second input terminal. The first input terminal is connected to a first channel. Each second input terminal is connected to the output terminal of the corresponding second decision feedback equalizer through a first filter circuit of a corresponding second decision feedback equalizer. The second decision feedback equalizer is a decision feedback equalizer corresponding to an adjacent channel of the first channel. The first filtering circuit is used to extract the crosstalk signal between the channel corresponding to the second decision feedback equalizer and the first channel, and the first processing circuit is used to eliminate the crosstalk signal between the adjacent channels and the first channel.
2. The signal receiving circuit as described in claim 1, characterized in that, The first decision feedback equalizer also includes a first decision unit and a second filter circuit; The first processing circuit further includes a third input terminal, which is connected to the output terminal of the first decision device through the second filtering circuit. The output terminal of the first processing circuit is connected to the first decision device, and the input terminal of the first decision device is connected to the output terminal of the first processing circuit. The first decision unit is used to decide the output signal of the first processing circuit to output a digital signal, the second filtering circuit is used to extract the inter-symbol interference signal of the first channel, and the first processing circuit is also used to eliminate the inter-symbol interference signal of the first channel.
3. The signal receiving circuit as described in claim 2, characterized in that, The first decision feedback equalizer further includes a third filtering circuit, and each of the second decision feedback equalizers includes a second processing circuit. The second processing circuit includes a fourth input terminal and a fifth input terminal. The fourth input terminal is connected to the corresponding second channel, and the fifth input terminal is connected to the output terminal of the first decision device through the third filter circuit of the first decision feedback equalizer. Wherein, the second channel and the first channel are adjacent channels, the third filtering circuit is used to extract the crosstalk signal of the first channel to the second channel, and the second processing circuit is used to eliminate the crosstalk signal of the first channel to the second channel.
4. The signal receiving circuit as described in claim 3, characterized in that, The first filtering circuit is a digital filter; and / or, The third filtering circuit is a digital filter.
5. The signal receiving circuit as described in claim 3, characterized in that, Each of the second decision feedback equalizers further includes: Second decision-making device; Fourth filter circuit; The second processing circuit also includes a sixth input terminal, which is connected to the output terminal of the second decision device belonging to the same second decision feedback equalizer through a fourth filter circuit belonging to the same second decision feedback equalizer. The output terminal of the second processing circuit is connected to the second decision device belonging to the same second decision feedback equalizer. The second decision unit is used to decide the output digital signal of the output signal of the second processing circuit belonging to the same second decision feedback equalizer. The fourth filter circuit is used to extract the inter-symbol interference signal of the second channel. The second processing circuit is also used to eliminate the inter-symbol interference signal of the second channel.
6. The signal receiving circuit as described in claim 5, characterized in that, Each of the second decision feedback equalizers also includes the first filter circuit; The input terminal of the second decision device is connected to the output terminal of the second processing circuit belonging to the same second decision feedback equalizer, and the output terminal of the second decision device is connected to the first processing circuit of the first decision feedback equalizer through the first filter circuit belonging to the same second decision feedback equalizer. The first filtering circuit is used to extract the crosstalk signal of the second channel to the first channel from the output signal of the second decision device belonging to the same second decision feedback equalizer, and input the extracted crosstalk signal into the first processing circuit.
7. The signal receiving circuit as described in any one of claims 1-6, characterized in that, The sampling clock used by the first decision feedback equalizer is half the data transmission rate of the signal receiving circuit.
8. The signal receiving circuit as described in any one of claims 1-6, characterized in that, The signal receiving circuit further includes a first analog front-end circuit, and the first input terminal of the first processing circuit is connected to the first channel through the first analog front-end circuit. The first analog front-end circuit is used to perform analog front-end processing on the signal of the first channel and input the processed analog signal into the first processing circuit.
9. The signal receiving circuit as described in any one of claims 2-6, characterized in that, The output signal of the first processing circuit is the difference between the input signal of the first input terminal of the first processing circuit and the target signal. The target signal is the sum of the input signals of at least one second input terminal of the first processing circuit and the input signal of the third input terminal of the first processing circuit.
10. A receiver, characterized in that, The receiver includes the signal receiving circuit according to any one of claims 1-9.