Transistor device

Abstract

The invention provides a transistor device. The transistor device comprises a drain layer, a main body layer, a source N region, at least one groove and a doped region, the drain electrode layer has a first conductive type, and the main body layer is arranged above the drain electrode layer and has a second conductive type opposite to the first conductive type; the source N region is arranged in the main body layer and has a first conduction type; the trench penetrates through parts of the source N region, the main body layer and the drain electrode layer, a gate electrode is arranged in the trench, and a dielectric layer is arranged around the gate electrode so as to isolate the gate electrode from the main body layer and the drain electrode layer; the doped region is arranged in the drain electrode layer and aligned to the lower portion of the gate electrode, the doped region is of the second conduction type, and a gap is formed between the doped region and the groove. According to the transistor device, the doped region is independently arranged in the drift layer and is aligned to the lower part of the gate electrode, so that the doped region and the gate electrode are kept at a certain distance, and the electric field of the corner region of the gate electrode is effectively reduced through the doped region, so that the service life of the transistor device is prolonged.

Description

Technical Field

[0001] This invention relates to a transistor device, and more particularly to a trench MOSFET device. Background Technology

[0002] Compared to planar silicon-oxide-semiconductor (MOSFET) technology, trench MOSFETs, by etching elongated trench structures on the wafer surface, allow for smoother current flow within the transistor, thus reducing on-resistance (Ron) and current loss. Compared to planar silicon carbide (SiC) MOSFETs with the same resistance, trench MOSFETs can have a smaller wafer size. This allows for manufacturing with smaller wafers to meet the same power and performance requirements, thereby reducing costs.

[0003] Existing trench-type metal-oxide-semiconductor field-effect transistors typically have a trench with a vertical bend at the bottom. When a voltage is applied to the trench to conduct and create an electric field, the conduction current deflects in the region of the vertical bend, causing a large potential energy change in that region. This creates a strong electric field (the corresponding formula is J = σE, σ = 1 / ρ, where J is the current density, σ is the conductivity, and ρ is the resistivity). This field has an adverse effect on the gate oxide layer in the vertical bend region, thus reducing the transistor's lifespan. Summary of the Invention

[0004] The main objective of this invention is to provide a transistor device comprising a drain layer, a host layer, a source electrode layer, at least one source N-region, at least one trench, and a doped region. The drain layer has a first conductivity type. The host layer is disposed above the drift layer and has a second conductivity type opposite to the first conductivity type. The source electrode layer is disposed above the host layer. The source N-region is disposed in the upper region of the host layer and has the first conductivity type. The trench passes through portions of the source N-region, the host layer, and the drain layer, and a gate is disposed within the trench. A dielectric layer is disposed around the gate to isolate the gate from the host layer and the drain layer. The doped region is disposed inside the drain layer and aligned below the gate. The doped region has the second conductivity type, and a gap exists between the doped region and the trench.

[0005] In one embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0006] In one embodiment of the present invention, the doped region is disposed in a drift layer of the drain layer.

[0007] In one embodiment of the present invention, the interval between the doped region and the trench is formed by trench etching after epitaxy.

[0008] In one embodiment of the present invention, the gap between the doped region and the trench is formed by ion implantation.

[0009] In one embodiment of the present invention, the doped region is formed by ion implantation.

[0010] In one embodiment of the present invention, the doped region is formed by high-temperature impurity diffusion.

[0011] In one embodiment of the present invention, the drift layer exists between the doped region and the trench.

[0012] In one embodiment of the present invention, when the conduction current passes through the drift layer near the doped region, a drift layer depletion region is generated, and the interval is smaller than the width of a depletion region of the drift layer.

[0013] In one embodiment of the present invention, another doped region of the same first conductivity type as the drift layer but with a higher concentration is provided on the left and right sides of the doped region located inside the drift layer and below the gate.

[0014] In one embodiment of the present invention, the difference between the thickness of the other doped region and the thickness of the doped region is within + / - 70% of the thickness of the doped region.

[0015] In one embodiment of the present invention, the other doped region is formed by ion implantation.

[0016] In one embodiment of the present invention, the other doped region is formed by high-temperature impurity diffusion.

[0017] In one embodiment of the present invention, the spacing between the doped region and / or the other doped region and the trench is formed by trench etching after epitaxy.

[0018] In one embodiment of the present invention, the interval between the doped region and / or the other doped region and the trench is formed by ion implantation.

[0019] In one embodiment of the present invention, when the conduction current passes near the doped region, a depletion region of the other doped region is generated, and the width of the other doped region is wider than the width of the depletion region of the other doped region.

[0020] In one embodiment of the present invention, the interval is 0.01 μm to 5 μm.

[0021] In one embodiment of the present invention, the interval is 2 μm to 5 μm.

[0022] In one embodiment of the present invention, the interval is 1 μm to 2 μm.

[0023] In one embodiment of the present invention, the interval is 0.01 μm to 1 μm.

[0024] In one embodiment of the present invention, the materials included in the transistor device include: silicon (Si), silicon germanide (SiGe), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), gallium antimonide (GaSb), gallium oxide (Ga2O3), diamond (Diamond C), or indium antimonide (InSb).

[0025] In one embodiment of the present invention, the transistor device is an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS).

[0026] In summary, the transistor device of the present invention, by independently setting a doped region in the drift layer and placing it below the gate, that is, maintaining a certain distance between the doped region and the gate, can effectively reduce the electric field in the gate corner region, avoid abnormal discharge in the gate corner region, and reduce the impact on the gate oxide layer, thereby extending the service life of the transistor device of the present invention.

[0027] The transistor device of the present invention can be used in the field of high-frequency and high-voltage products, such as inverters, rectifiers, electric vehicles, PHEVs, charging stations, smart grids, energy storage and rail transportation. Attached Figure Description

[0028] Figures 1A-1C This is a schematic diagram of a planar structure of a transistor device according to the first embodiment of the present invention.

[0029] Figure 2A This is a partial coordinate diagram of an existing transistor device.

[0030] Figure 2B According to Figure 2A This diagram shows the electric field strength in the corner section at the bottom of the trench of an existing transistor device.

[0031] Figure 2C For Figure 2B A magnified view of a portion of the image.

[0032] Figure 3A This is a partial coordinate schematic diagram of the transistor device according to the first embodiment of the present invention.

[0033] Figure 3B According to Figure 3A This diagram shows the electric field strength of the transistor device at the corner section at the bottom of the trench according to the first embodiment of the present invention.

[0034] Figure 3C For Figure 3B A magnified view of a portion of the image.

[0035] Figure 4A This is a flowchart illustrating the steps of a first method for forming a transistor device according to a first embodiment of the present invention.

[0036] Figure 4B According to Figure 4A A schematic diagram of the formation process of a transistor device according to the first embodiment of the present invention.

[0037] Figure 4C This is a flowchart illustrating the steps of a second method for forming a transistor device according to the first embodiment of the present invention.

[0038] Figure 4D According to Figure 4C A schematic diagram of the formation process of a transistor device according to the first embodiment of the present invention.

[0039] Figures 5A-5B This is a schematic diagram of a planar structure of a transistor device according to a second embodiment of the present invention.

[0040] Figure 6A This is a flowchart illustrating the steps of a first method for forming a transistor device according to a second embodiment of the present invention.

[0041] Figure 6B For as a basis Figure 6A A schematic diagram of the formation process of a transistor device according to a second embodiment of the present invention.

[0042] Figure 6C This is a flowchart illustrating the steps of a second method for forming a transistor device according to a second embodiment of the present invention.

[0043] Figure 6D This is a schematic diagram of the formation process of a transistor device according to a second embodiment of the present invention (6C).

[0044] Figure 7This table illustrates the width of the depletion region in the second embodiment and the first embodiment without a second doped region, for comparison purposes.

[0045] The diagram is marked as follows:

[0046] 100 transistor devices

[0047] 200 transistor devices

[0048] 1. Drain layer

[0049] 11 Drain electrode layer

[0050] 12 Drain N-region

[0051] 13 Drift Layer

[0052] 13a Drift layer

[0053] 2. Main body layer

[0054] 21 Source N-region

[0055] 22 First P Zone

[0056] 23 Second P Zone

[0057] 3. Source electrode layer

[0058] 31 First dielectric layer

[0059] 4. Trench

[0060] 41 Bottom edge

[0061] 41a Corner Section

[0062] 42 gate

[0063] 43 Second dielectric layer

[0064] 5-Doped Region / First Doped Region

[0065] 6 Second doped region

[0066] AP1 Area

[0067] AP2 Area

[0068] C. Conducting current

[0069] C1 current

[0070] CH conductive channel

[0071] D interval

[0072] E1 Electric field strength range

[0073] E2 electric field strength range

[0074] Length of F

[0075] Width of B

[0076] Contact area O

[0077] Width of L1

[0078] Width of L2

[0079] Thickness of T1

[0080] Thickness of T2

[0081] W , , ,

[0082] ,

[0085] ,

[0084] , Figure 1A ,

[0083] , , W Drift2 , W 第二掺杂区 Width of depletion region Detailed implementation manners

[0082] Refer to Figure 1A , the transistor device 100 of the first embodiment of the present invention includes a drain layer 1, a body layer 2, a source electrode layer 3, a plurality of source N regions 21, a plurality of trenches 4, and a doped region 5. The body layer 2 is located above the drain layer 1, the source electrode layer 3 is disposed above the body layer 2, the source N regions 21 have a first conductivity type and are disposed in the body layer 2 and located in an upper region within the body layer 2; each of the trenches 4 penetrates through a part of the source N regions 21, the body layer 2, and the drain layer 1, and the doped region 5 is disposed inside the drain layer 1 and directly below the aligned trenches 4. The detailed structures of each layer and the relative relationship with each other will be described in detail below. Among them, in this embodiment, for the convenience of description, the first conductivity type is set as N type, and the second conductivity type is P type; however, in practice, the first conductivity type can also be set as P type, and the second conductivity type is N type, and these variations of the embodiments are not limited in the present invention.

[0083] The drain layer 1 has a first conductivity type, and the drain layer 1 has a drain electrode layer 11, a drain N region 12, and a drift layer 13. The drain N region 12 is disposed above the drain electrode layer 11, and the drift layer 13 is formed above the drain N region 11. [[ID=?]]

[0084] The body layer 2 is disposed above the drift layer 13 and has a second conductivity type opposite to the first conductivity type. The body layer 2 has a plurality of first P regions​​Each trench 4 passes through the source N-region 21, the main body layer 2, and a portion of the drift layer 13. Between every two trenches 4, there are two source N-regions 21, one first P-region 22, and one second P-region 23. At the bottom edge 41 of each trench 4, two opposing corner sections 41a are formed, and in this embodiment, these corner sections 41a are each an arc angle. A gate 42 is disposed within each trench 4, and a second dielectric layer 43 is disposed around the gate 42 to isolate it from the main body layer 2 and the drift layer 13 of the drain layer 1.

[0086] The source electrode layer 3 is disposed above the main body layer 2. A first dielectric layer 31 is formed in the source electrode layer 3 and is located above the trench 4 and the local source N region 21. The first dielectric layer 31 separates the source electrode layer 3 from the gate 42 to avoid leakage current or mutual interference.

[0087] The doped region 5 is disposed inside the drain layer 1. More specifically, the doped region 5 is disposed in the drift layer 13 and aligned below the gate 42. The doped region 5 has a second conductivity type, and there is a gap D between the doped region 5 and the trench 4, which separates the doped region 5 from the gate 42 by a certain distance. That is, there is a drift layer 13 between the doped region 5 and the trench 4. In addition, the gap D can be formed by trench etching after epitaxy (for example, in this embodiment, the drift layer 13 is formed by epitaxy, then the main layer 2 is formed, and finally the main layer 2 and part of the drift layer 13 are trench etched). Or, in other embodiments, the gap D can be formed by ion implantation (that is, the doped region 5 is formed by ion implantation in the drift layer 13, and the gap D is correspondingly formed between the trench 4 and the doped region 5 due to the generation of the doped region 5).

[0088] When a voltage is applied to the gate 42, a conductive channel CH is formed, and the conduction current C can flow from the source electrode layer 3 to the drain layer 1. The doped regions 5 are formed intermittently in the drift layer 13 and are located below the gate 42. When the conduction current C contacts the doped region 5, it applies a reverse bias voltage to the doped region 5, causing the outer edge of the doped region 5 to form an expanding depletion region. This depletion region can prevent the conduction current C from turning to the lower part of the gate 42. The electric field of the corner section 41a of the trench 4 is effectively reduced, thereby avoiding abnormal discharge of the corner section 41a, that is, avoiding the generation of a strong electric field in the corner section 41a.

[0089] The formula for calculating the reverse bias applied to doped region 5 is as follows: V 掺杂区 =V DS –I×(R 接触区 +R 源极N区 +R ch +R Drift1 ), where V掺杂区 V is the voltage of doped region 5. DS R is the voltage from source N-region 21 to drain N-region 12, I is the current from source N-region 21 to drain N-region 12, and R is the voltage across the source N-region 21 to drain N-region 12. 接触区 R is the resistance value of contact area O. 源极N区 R is the resistance value of source N-region 21. ch R is the resistance value of the conductive channel CH. Drift1 It is the resistance value of the drift layer 13 section between the junction of the conductive channel CH and the drift layer 13 next to the gate 42 and the doped region 5.

[0090] The total depletion region width W can be divided into the depletion region width W of the doped region 5. 掺杂区 and the width W of the depletion region of the drift layer 13a between the two doped regions 5. Drift2 The formula for calculating the width W of the total vacancy region is: Where, N 漂移层 The doping concentration of drift layer 13, N 掺杂区 V represents the doping concentration of doped region 5. bi The built-in electric field is the Fermi level difference between the p-type semiconductor (first P-region 22) and the n-type semiconductor (source N-region 21) before they bond. 掺杂区 This represents the voltage of doped region 5.

[0091] The width W of the depletion region of doped region 5 掺杂区 The calculation formula is: W 掺杂区 =N 漂移层 ×W / (N 漂移层 +N 掺杂区 W is the width of the total vacancy region, N 漂移层 The doping concentration of drift layer 13, N 掺杂区 This represents the doping concentration of doped region 5. The location of the depletion region in doped region 5 is as follows: Figure 1C The area shown is located between the two rectangular dashed lines.

[0092] The width W of the depletion region of the drift layer 13a between the two doped regions 5 Drift2 The calculation formula is: W Drift2 =N 掺杂区 ×W / (N 漂移层 +N 掺杂区 ), N 掺杂区 Where N is the doping concentration of doped region 5, W is the depletion region width W of the total depletion region, and N is the doping concentration of doped region 5. 漂移层 This represents the doping concentration of drift layer 13. In this embodiment, the spacing D is smaller than the width W of the depletion region of drift layer 13a. Drift2 .

[0093] Reference Figure 1B , further, a three-dimensional schematic range of the drift layer 13a between the two doping regions 5 is marked in Figure 1B (this calculation method is calculated without considering the reverse bias state applied by the doping region 5). The simple calculation formula for the resistance of the drift layer 13a to a vertically downward current C1 is: R Drift2 = ρ Drift2 × T1 / Area = ρ Drift2 ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​~1.4×10 06 V / cm, clearly the electric field strength of the corner section 41a of the present invention is reduced.

[0096] Furthermore, the doped region 5 can be formed by ion implantation or by high-temperature impurity diffusion. No restrictions are placed on the formation method of the doped region 5.

[0097] In this embodiment, the width L1 of the doped region 5 is equal to the width L2 of the trench 4. However, in other embodiments of the present invention, the width L1 of the doped region 5 may be less than or greater than the width L2 of the trench 4, as long as most of the doped region 5 is aligned and disposed below the trench 4, the electric field of these corner sections 41a can be reduced.

[0098] In one embodiment of the present invention, the interval D ranges from 0.01 μm to 5 μm. However, in other embodiments of the present invention, the range of the interval can be set according to requirements, for example, the interval can be selectively between 2 μm and 5 μm, 1 μm and 2 μm, or 0.01 μm and 1 μm.

[0099] The present invention further provides a first method for forming the transistor device 100 according to the first embodiment, see below. Figure 4A Step flowchart and Figure 4B A schematic diagram of the formation process, firstly, as shown in the diagram. Figure 4B As shown in (01), in step S01: a drain layer 1 without a drain electrode layer 11 is provided, and a drain N region 12 of a first conductivity type and a drift layer 13 of a first conductivity type are formed sequentially from bottom to top; as Figure 4B (02) As shown, in step S02: the area to be doped 5 is exposed by photoresist layer, barrier layer and photolithography, and a doped region 5 is formed inside the drift layer 13 by high-temperature impurity diffusion or ion implantation, and then lattice repair is performed by appropriate high temperature (the appropriate high temperature referred to in this step can be based on the temperature control according to the material or structure factors); such as Figure 4B As shown in (03), in step S03, the thickness of the drift layer 13 is increased by epitaxy, and then a host layer 2 having the second conductivity type is formed on the drift layer 13; as Figure 4B As shown in (04), in step S04, the area of ​​the main layer 2 where the trench 4 is to be formed is defined by a photoresist layer, a blocking layer, and an exposure lithography layer. The main layer 2 is etched by etching to form at least one trench 4 on the surface of the main layer 2, such that the trench 4 and the doped region 5 have a gap D; Figure 4BIn step (05), a thin second dielectric layer 43 is formed in the trench 4 (the morphology of the trench 4 still exists at this time), and then a gate 42 (the thin second dielectric layer 43 is insulating and non-conductive) is formed in the trench 4 with the thin second dielectric layer 43, so that the gate 42 is isolated from the main body layer 2 and the drift layer 13 by the second dielectric layer 43. Figure 4B As shown in (06), in step S06, a first dielectric layer 31 is formed to cover the surfaces of the main body layer 2 and the gate 42 (the first dielectric layer 31 is also insulating and non-conductive). The contact area O between the source electrode layer 3 and the main body layer 2 is defined and etched by photolithography and etching before the source electrode layer 3 is formed (the source electrode layer 3 can be formed by metal sputtering or other suitable processes). Figure 4B As shown in (07), in step S07, a drain electrode layer 11 is formed by crystal back grinding and crystal back metal sputtering.

[0100] The present invention also provides a second method for forming the transistor device 100 of the first embodiment, see reference. Figure 4C Step flowchart and Figure 4D A schematic diagram of the formation process, firstly, as shown in the diagram. Figure 4D As shown in (01a), in step S01A: a drain layer 1 without a drain electrode layer 11 is provided, and a drain N region 12 of a first conductivity type and a drift layer 13 of a first conductivity type are formed sequentially from bottom to top; as Figure 4D As shown in (02a), in step S02A: a main layer 2 having the second conductivity type is formed on the drift layer 13; as Figure 4D As shown in (03a), in step S03A: the area of ​​the main layer 2 where the trench 4 is to be formed is defined by the photoresist layer, the blocking layer, and the photolithography, and the main layer 2 is etched by etching to form at least one trench 4 in the main layer 2; Figure 4D As shown in (04a), in step S04A: the trench 4 is exposed by photoresist layer, barrier layer and photolithography etching, and a doped region 5 with a spacing D from the trench 4 is formed by high-energy ion implantation, and then lattice repair is performed by a suitable high-temperature process (the suitable high temperature referred to in this step can be based on the temperature control according to the material or structure factors). Figure 4D As shown in (05a), in step S05A, a thin second dielectric layer 43 is formed in the trench 4 (the trench morphology still exists at this time), and then a gate 42 (the second dielectric layer 43 is insulating and non-conductive) is formed in the trench 4 with the thin second dielectric layer 43 to isolate the gate 42 from the main body layer 2 and the drift layer 13 through the second dielectric layer 43. Figure 4DAs shown in (06a), in step S06A, a first dielectric layer 31 is provided to cover the surfaces of the body layer 2 and the gate 42 (the first dielectric layer 31 is insulating and non-conductive). After defining and etching the contact region O between the source electrode layer 3 and the body layer 2 through exposure lithography and etching, the source electrode layer 3 is formed (the source electrode layer 3 is formed by metal sputtering or other suitable processes). As Figure 4D As shown in (07a), in step S07A, backside grinding of the wafer and backside metal sputtering are performed to form a drain electrode layer 11.

[0101] Referring Figure 5A to, the transistor device 200 in the second embodiment of the present invention includes a drain layer 1, a body layer 2, a source electrode layer 3, a plurality of source N regions 21, a plurality of trenches 4, a first doping region 5, and a plurality of second doping regions 6. That is, compared with the first embodiment, this embodiment includes one doping region (the first doping region 5) and another doping region (the second doping region 6). For the convenience of description, the first conductivity type is set as N-type and the second conductivity type is set as P-type; however, in practice, the first conductivity type can also be set as P-type and the second conductivity type can be set as N-type. These variations of the embodiments are not limited in the present invention.

[0102] Specifically, similar to the first embodiment, the drain layer 1 has a first conductivity type, and the drain layer 1 has a drain electrode layer 11, a drain N region 12, and a drift layer 13. The drain N region 12 is disposed above the drain electrode layer 11, and the drift layer 13 is formed above the drain N region 11. The body layer 2 is disposed above the drift layer 13 and has a second conductivity type opposite to the first conductivity type. The body layer 2 has a plurality of first P regions 22 and a plurality of second P regions 23. The source N regions 21 are disposed in the upper region within the body layer 2. The source N regions 21 and the first P regions 22 are adjacent to each other and arranged alternately, and the second P regions 23 are located below each source N region 21 and each first P region 22. Each of the trenches 4 penetrates through partial regions of the source N regions 21, the body layer 2, and the drift layer 13. Between every two trenches 4, there are two of the source N regions 21, one of the first P regions 22, and one of the second P regions 23. At the bottom edge 41 of each trench 4, two opposite corner segments 41a are formed, and in this embodiment, these corner segments 41a are respectively an arc angle. A gate 42 is disposed within the trench 4, and a dielectric layer 43 is disposed around the gate 42 to isolate the gate 42 from the drift layer 13 of the body layer 2 and the drain layer 1. The source electrode layer 3 is disposed above the body layer 2 and has the first conductivity type. A first dielectric layer 31 is formed within the source electrode layer 3 and is located above the trenches 4 and partial source N regions 21. The source electrode layer 3 is separated from the gate 42 by the first dielectric layer 31 to prevent leakage current or mutual interference.

[0103] As described above, the first doped region 5 is disposed in the drift layer 13 and aligned below the gate 42 located in the trench 4. The first doped region 5 has a second conductivity type, and there is a gap D between the first doped region 5 and the trench 4, which allows it to be separated from the gate 42 by a certain distance. That is, there is a drift layer 13 between the first doped region 5 and the trench 4. These second doped regions 6 are respectively disposed on the left and right sides of the first doped region 5, and each second doped region 6 and the drift layer 13 have the same first conductivity type, but the concentration of the second doped region 6 is higher than that of the drift layer 13. In this invention, preferably, the concentration of the second doped region 6 is 4 times or more than 4 times the doping concentration of the drift layer 13. By disposing second doped regions 6 on both sides of the first doped region 5, it is possible to effectively prevent the outward expansion depletion regions that may be generated on both sides of the first doped region 5 from squeezing the conduction current between the source electrode layer 3 and the drain layer 1 when conduction occurs, and at the same time, it is possible to effectively avoid abnormal discharge in the corner section 41a.

[0104] To reiterate, one feature of this second embodiment is that the conduction current C contacts the first doped region 5 and applies a reverse bias voltage to the first doped region 5, while the second doped region 6 suppresses the depletion regions (such as those extending outward from the left and right outer edges of the first doped region 5) from the outer edges. Figure 5B As shown (within the area selected by the two rectangular dashed lines), the formula for calculating the reverse bias applied to the first doped region 5 is: V 第一掺杂区 =V DS –I×(R 接触区 +R 源极N区 +R ch +R Drift1 ), where V 第一掺杂区 V is the voltage of the first doped region 5. DS R is the voltage from source N-region 21 to drain N-region 12, I is the current from source N-region 21 to drain N-region 12, and R is the voltage across the source N-region 21 to drain N-region 12. 接触区 R is the resistance value of contact area O. 源极N区 R is the resistance value of source N-region 21. ch R is the resistance value of the conductive channel CH. Drift1 This is the resistance value of the drift layer 13 section between the junction of the conductive channel CH and the drift layer 13 next to the gate 42 and the doped region 5. It should be noted that, to clearly indicate the location of the second doped region 6, [the following text is missing from the original]... Figure 5A The diagram only shows the relative relationship between the first doped region 5 on one side and the conduction current C1.

[0105] As mentioned above, the calculation formula for the drift layer between the two previously expanded first doped regions 5 is W. Drift2 =N 第一掺杂区 ×W / (N 漂移层 +N 第一掺杂区 ), N 第一掺杂区N is the doping concentration of the first doped region 5, W is the width of the depletion region W (see the description of W in the first embodiment), and N is the doping concentration of the first doped region 5. 漂移层 The doping concentration of drift layer 13 is then adjusted to the depletion region width W of the second doped region 6. 第二掺杂区 Its calculation formula is W 第二掺杂区 =N 第一掺杂区 ×W / (N 第二掺杂区 +N 第一掺杂区 ), N 第一掺杂区 N is the doping concentration of the first doped region 5, W is the depletion region width W of the total depletion region (see the description of W in the first embodiment for details), and N is the doping concentration of the first doped region 5. 第二掺杂区 This represents the doping concentration of the second doped region 6. In this embodiment, the width of the second doped region 6 is wider than the depletion region width W of the depletion region of the second doped region 6. 第二掺杂区 Since the concentration of the second doped region 6 is higher than that of the drift layer 13, therefore W 第二掺杂区 <W 漂移层 Therefore, the squeezing current C caused by the first doped region 5 can be alleviated. And under suitable N... 第二掺杂区 W at concentration 漂移层 The width is N 第二掺杂区 Limitations, considering the effect of the reverse bias applied to the second doped region 5, such as Figure 5B As shown, the depletion region resistance of the drift layer 13a between the two first doped regions 5 will change as shown in the following calculation formula: F2=(F-2×W 第二掺杂区 ), R 漂移层 =ρ 漂移层 ×T1 / Area=ρ 漂移层 ×T1 / ((F-2×W 第二掺杂区 ()×B), F is the length of the drift layer 13a in the first embodiment, W 第二掺杂区 R is the width of the depletion region of the second doped region 6. 漂移层 The resistance value of drift layer 13, ρ 漂移层 Let T1 be the resistivity of the drift layer 13a, T1 be the thickness of the drift layer 13a, Area be the area, and B be the width of the drift layer 13a in this embodiment. Figure 5B The resistance value of the cuboid region shown is higher than that of the other region. Figure 1C The marked cuboid region has a small resistance value.

[0106] The materials contained in the motor body device 100 of the first embodiment and the transistor device 200 of the second embodiment of the present invention, taking silicon carbide (SiC) as an example, can be calculated according to the above formula as follows: Figure 7 As shown in the table, the second doped region 6 can make W 漂移层 When the source voltage increases, the effect of the reverse bias voltage on the first doped region 5 decreases (i.e., W without the second doped region 6). 漂移层W with a diameter of 10 μm and a second doped region of 6 漂移层 The W value is 0.95 μm, indicating a clear second doped region at time 6. 漂移层 (Width reduced).

[0107] In this embodiment, preferably, the difference between the thickness T2 of the second doped region 6 and the thickness T1 of the first doped region 5 is within + / -70% of the thickness of the first doped region 5 (i.e., -70%×T1≦T2-T1≦+70%×T1).

[0108] Furthermore, this embodiment is the same as the first embodiment, where the width L1 of the first doped region 5 is equal to the width L2 of the trench 4. However, in other embodiments of the present invention, the width L2 of the first doped region 5 relative to the trench 4 can be adjusted, which will not be described in detail here.

[0109] Furthermore, the first doped region 5 and / or the second doped region 6 may be formed by ion implantation or by high-temperature impurity diffusion, respectively. There are no restrictions on the formation methods of the first doped region 5 and the second doped region 6.

[0110] The present invention provides a first method for forming a transistor device 200 according to a second embodiment, see reference. Figure 6A Step flowchart and Figure 6B A schematic diagram of the formation process, firstly, as shown in the diagram. Figure 6B As shown in (11), in step S11: a drain layer 1 without a drain electrode layer 11 is provided, and a drain N region 12 and a drift layer 13 with a first conductivity type are formed sequentially from bottom to top; as Figure 6B As shown in (12), in step S12, the area to be doped 5 is exposed by photoresist layer, barrier layer and photolithography, and a first doped region 5 is formed inside the drift layer 13 by high-temperature impurity diffusion or ion implantation (the first doped region 5 has a second conductivity type opposite to the first conductivity type); as Figure 6B As shown in (13), in step S13, the area where the second doped region 6 is to be formed is exposed by photoresist layer, barrier layer and exposure microlithography etching. The second doped region 6 is formed on the left and right sides of the first doped region 5 by high-temperature impurity diffusion or ion implantation (the second doped region 6 and the drift layer 13 are of the same first conductivity type but the concentration is higher than that of the drift layer 13). Then, lattice repair is performed by a suitable high-temperature process (the suitable high temperature referred to in this step can be based on the temperature control according to the material or structure factors); such as Figure 6B As shown in (14), in step S14, the thickness of the drift layer 13 is increased epitaxially, and then a host layer 2 having the second conductivity type is formed on the drift layer 13; as Figure 6BAs shown in (15), in step S15, at least one trench 4 is formed above the first doped region 5 and in the main body layer 2, such that the trench 4 and the first doped region 5 have a gap D; Figure 6B As shown in (16), in step S16, a thin second dielectric layer 43 is provided in the trench 4, and then a gate 42 (the second dielectric layer 43 is insulating and non-conductive) is provided in the trench 4 with the thin second dielectric layer 43, so that the gate 42 is isolated from the main body layer 2 and the drift layer 13 by the second dielectric layer 43. Figure 6B As shown in (17), in step S17, a first dielectric layer 31 is formed, which covers the surface of the main body layer 2 and the gate 42 (the first dielectric layer 31 is insulating and non-conductive). After defining and etching the contact area O between the source electrode layer 3 and the main body layer 2 by photolithography, the source electrode layer 3 in contact with the main body layer 2 is formed (the source electrode layer 3 can be formed by metal sputtering or other suitable processes). Figure 6B As shown in (18), in step S18, a back-side grinding and back-side metal sputtering are performed to form a drain electrode layer 11.

[0111] The present invention also provides a second method for forming a transistor device 200 according to a second embodiment, see below. Figure 6C Step flowchart and Figure 6D A schematic diagram of the formation process, firstly, as shown in the diagram. Figure 6D As shown in (11a), in step S11A: a drain layer 1 without a drain electrode layer 11 is provided, and a drain N region 12 and a drift layer 13 with a first conductivity type are formed sequentially from bottom to top; as Figure 6D As shown in (12a), in step S12A: a host layer 2 having the second conductivity type is formed on the drift layer 13; as Figure 6D As shown in (13a), in step S13A: at least one trench 4 is formed in the main body layer 2; as Figure 6D As shown in (14a), in step S14A: the trench 4 is exposed by photoresist layer, barrier layer and photolithography etching, and a first doped region 5 with a spacing D from the trench 4 is formed by high-energy ion implantation (the first doped region 5 has a second conductivity type); Figure 6D As shown in (15a), in step S15A: a specific area of ​​the trench 4 is exposed by photoresist layer, blocking layer and photolithography, and multiple second doped regions 6 are implanted with high-energy ions. These second doped regions 6 are formed on both sides of the first doped region 5 (the concentration of the second doped regions 6 is higher than that of the drift region 13 and has a first conductivity mode), and then lattice repair is performed by a suitable high-temperature process. Figure 6DAs shown in (16a), in step S16A, a thin second dielectric layer 43 is formed in the trench 4 (the morphology of the trench 4 still exists at this time), and then a gate 42 (the second dielectric layer 43 is insulating and non-conductive) is formed in the trench 4 with the thin second dielectric layer 43, so that the gate 42 is isolated from the main body layer 2 and the drift layer 13 by the second dielectric layer 43. Figure 6D As shown in (17a), in step S17A, a first dielectric layer 31 is formed to cover the surfaces of the main body layer 2 and the gate 42 (the first dielectric layer 31 is insulating and non-conductive). After defining and etching the contact area O between the source electrode layer 3 and the main body layer 2 through photolithography and etching, the source electrode layer 3 in contact with the main body layer 2 is formed (the source electrode layer 3 can be formed by metal sputtering or other suitable processes). Figure 6D As shown in (18a), in step S18A, a drain electrode layer 11 is formed by back grinding and back metal sputtering.

[0112] The materials contained in the transistor device of the present invention (including the transistor device 100 of the first embodiment and the transistor device 200 of the second embodiment mentioned above) include: silicon (Si), silicon germanide (SiGe), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), gallium antimonide (GaSb), gallium oxide (Ga2O3), diamond (Diamond C) or indium antimonide (InSb).

[0113] The transistor device 100 in the first embodiment and the transistor device 200 in the second embodiment of the present invention may be an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS).

[0114] In summary, the transistor device of the present invention, by independently setting a doped region in the drift layer and placing it below the gate, that is, maintaining a certain distance between the doped region and the gate, can effectively reduce the electric field in the gate corner region, avoid abnormal discharge in the gate corner region, and reduce the impact on the gate oxide layer, thereby extending the service life of the transistor device of the present invention.

[0115] The present invention has been described in detail above. The above description is only one preferred embodiment of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A transistor device, characterized in that, include: The first absorber layer has the first type of conductivity. A main body layer is disposed above the drain layer and has a second conductivity type opposite to the first conductivity type; A source electrode layer is disposed above the main body layer; At least one source N-region is disposed in an upper region within the main body layer and has the first conductivity type; and At least one trench passes through a portion of the source N region, the main body layer, and the drain layer, and a gate is disposed within the trench. A dielectric layer is disposed around the gate to isolate the gate from the main body layer and the drain layer. as well as A doped region is disposed inside the drain layer and aligned below the gate, the doped region having the second conductivity type, and a gap is provided between the doped region and the trench.

2. The transistor device according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

3. The transistor device according to claim 1, characterized in that, The doped region is disposed in a drift layer of the drain layer.

4. The transistor device according to claim 1, characterized in that, The spacing between the doped region and the trench is formed by trench etching after epitaxy.

5. The transistor device according to claim 1, characterized in that, The gap between the doped region and the trench is formed by ion implantation.

6. The transistor device according to claim 1, characterized in that, The doped region is formed by ion implantation.

7. The transistor device according to claim 1, characterized in that, The doped region is formed by high-temperature impurity diffusion.

8. The transistor device according to claim 3, characterized in that, The drift layer exists between the doped region and the trench.

9. The transistor device according to claim 3, characterized in that, When a current passes through the drift layer near the doped region, a drift layer depletion region is generated, and the interval is smaller than the width of the drift layer depletion region.

10. The transistor device according to claim 8, characterized in that, Inside the drift layer and below the gate, on the left and right sides of the doped region, there is another doped region of the same first conductivity type as the drift layer but with a higher concentration.

11. The transistor device according to claim 10, characterized in that, The difference between the thickness of the other doped region and the thickness of the doped region is within + / - 70% of the thickness of the doped region.

12. The transistor device according to claim 10, characterized in that, The other doped region is formed by ion implantation.

13. The transistor device according to claim 10, characterized in that, The other doped region is formed by high-temperature impurity diffusion.

14. The transistor device according to claim 10, characterized in that, The spacing between the doped region and / or the other doped region and the trench is formed by trench etching after epitaxy.

15. The transistor device according to claim 10, characterized in that, The spacing between the doped region and / or the other doped region and the trench is formed by ion implantation.

16. The transistor device according to claim 10, characterized in that, When the conduction current passes near the doped region, a depletion region is generated in the other doped region, and the width of the other doped region is wider than the width of the depletion region of the other doped region.

17. The transistor device according to claim 1, characterized in that, The interval is from 0.01 μm to 5 μm.

18. The transistor device according to claim 1, characterized in that, The interval is 2μm to 5μm.

19. The transistor device according to claim 1, characterized in that, The interval is 1 μm to 2 μm.

20. The transistor device according to claim 1, characterized in that, The interval is from 0.01 μm to 1 μm.

21. The transistor device according to claim 1, characterized in that, The materials contained in the transistor device include: silicon, silicon germanide, germanium, silicon carbide, gallium nitride, gallium arsenide, gallium antimonide, gallium oxide, diamond, or indium antimonide.

22. The transistor device according to claim 1, characterized in that, The transistor device is an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, a metal-insulator-semiconductor field-effect transistor, or a vertically double-diffused metal-oxide-semiconductor field-effect transistor.

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