Semiconductor structure and its fabrication method

Abstract

This invention provides a semiconductor structure and its fabrication method, belonging to the semiconductor field. The semiconductor structure fabrication method includes: providing a substrate and forming a functional layer within the substrate; wherein the functional layer includes a first doped region and a second doped region spaced apart, and an isolation structure disposed between the first doped region and the second doped region; fabricating a gate structure on the first doped region and the second doped region respectively, the gate structure including a gate oxide layer, a gate, and gate sidewalls; fabricating an ion blocking layer, the ion blocking layer exposing at least the source and drain fabrication regions in the first doped region; fabricating a buffer layer, the buffer layer at least covering the gate structure of the first doped region, the buffer layer being a porous structure; and performing ion implantation on the buffer layer to convert the surface layer of the buffer layer into a reinforcement layer. The buffer layer and reinforcement layer formed by this method can effectively protect the gate structure and prevent damage to the gate structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, and particularly relates to a semiconductor structure and its fabrication method. Background Technology

[0002] Existing complementary metal-oxide-semiconductor (CMOS) devices typically include: a substrate, a PMOS region and an NMOS region formed on the substrate, a gate structure formed on the PMOS region and the NMOS region, a source, and a drain. The gate structure includes a gate and a gate sidewall, and a gate oxide layer is disposed between the gate and the PMOS region and between the gate and the NMOS region.

[0003] See Figures 1 to 3 In fabricating existing CMOS devices, an isolation structure 113 is first fabricated between a first doped region 111 (e.g., a PMOS region) and a second doped region 112 (e.g., an NMOS region). Then, the first doped region 111 and the second doped region 112 in the functional layer 11 are fabricated on the surface of the substrate 10 via ion implantation. Subsequently, a gate oxide layer 121 is fabricated sequentially on the surfaces of the first doped region 111 and the second doped region 112, and a gate 122 and a gate sidewall 123 are fabricated on the gate oxide layer 121. After fabricating the gate structure 12 (see...),... Figure 1 The structure involves fabricating a first source 114 and a first drain 115. The first source 114 and the first drain 115 are also formed by ion implantation, with an ion-blocking layer 13 (i.e., a photoresist layer) used to cover areas where ion implantation is not required (see [reference]). Figure 2 The structure shown in the figure (dashed lines indicate the direction of ion implantation) exposes the regions where the first source 114 and the first drain 115 are formed, thereby forming the first drain 115 and the first source 114 in the first doped region 111. By repeating the above source and drain fabrication steps, a second source and a second drain (not shown in the figure) are formed in the second doped region 112, thus forming a CMOS device.

[0004] However, in advanced manufacturing processes, the gate structure is relatively small. During ion implantation, elements with larger molecular weights, accelerated by a high-energy electric field, carry a large amount of energy and impact the gate. Smaller gate structures are more susceptible to damage under ion energy impact (see...). Figure 3 Furthermore, since the channel needs to be isolated by the gate sidewall (silicon nitride sidewall) when forming the source / drain through ion implantation, the stress generated by the difference in thermal expansion coefficients between the silicon nitride sidewall and the gate will worsen under the high-energy impact of ions, affecting gate stability and thus exacerbating gate collapse (see...). Figure 3 ). Summary of the Invention

[0005] This invention provides a semiconductor structure and its fabrication method, which can prevent damage or detachment of the gate structure during the fabrication of the source and drain.

[0006] In a first aspect, a method for fabricating a semiconductor structure is provided, comprising:

[0007] A substrate is provided, and a functional layer is formed therein; wherein the functional layer includes a first doped region and a second doped region disposed at intervals, and an isolation structure disposed between the first doped region and the second doped region;

[0008] A gate structure is fabricated on a first doped region and a second doped region, respectively. The gate structure includes a gate oxide layer, a gate, and a gate sidewall.

[0009] An ion barrier layer is fabricated on the second doped region, wherein the ion barrier layer exposes at least the source and drain fabrication regions in the first doped region.

[0010] A buffer layer is fabricated, wherein the buffer layer at least covers the gate structure of the first doped region, and the buffer layer has a porous structure.

[0011] Ion implantation is performed on the buffer layer to transform the surface of the buffer layer into a reinforcement layer.

[0012] Optionally, the steps for creating the buffer layer include:

[0013] At least the gate structure surface of the first doped region is coated with a first organic solvent by spin coating; wherein the first organic solvent is formed by mixing a polymer and a template agent;

[0014] The first organic solvent is heated to form an organic thin film;

[0015] A second organic solvent is used to remove the template agent from the organic film, forming a buffer layer with a porous structure.

[0016] Alternatively, the polymer may include polyvinylidene fluoride or polymethyl methacrylate.

[0017] Optionally, the template agent comprises 20% to 80% polystyrene by mass.

[0018] Optionally, the second organic solvent includes cyclohexane or ethyl acetate.

[0019] Optionally, ion implantation is performed on the buffer layer, including:

[0020] Using P or As as the implanted element, the implantation dose is 1×10 14 Atom / cm 2 ~1×10 16 Atom / cm2 Ion implantation was performed on the buffer layer using an injection energy of 5keV~30keV.

[0021] Optionally, a gate structure is fabricated on the surface of the first doped region and / or the second doped region, including:

[0022] A gate oxide layer is formed on the surface of the first doped region and / or the second doped region;

[0023] A gate is fabricated on the surface of the gate oxide layer on the surface of the first doped region and / or the second doped region;

[0024] A low-pressure chemical vapor deposition process is used to fabricate the gate sidewall on the gate side.

[0025] In a second aspect, the present invention provides a semiconductor structure, comprising:

[0026] The substrate has a functional layer, the functional layer including a first doped region and a second doped region disposed at intervals, and an isolation structure disposed between the first doped region and the second doped region;

[0027] A gate structure is formed on the first doped region and the second doped region, respectively, and the gate structure includes a gate oxide layer, a gate, and a gate sidewall;

[0028] An ion barrier layer is formed on the second doped region, and the ion barrier layer exposes at least the source and drain fabrication regions of the first doped region.

[0029] A buffer layer, wherein the buffer layer at least covers the gate structure of the first doped region or the second doped region, and the buffer layer is a porous structure;

[0030] The reinforcement layer is formed on the surface of the buffer layer by an ion implantation process.

[0031] Optionally, the buffer layer is a polymer layer, which includes a polyvinylidene fluoride layer or a polymethyl methacrylate layer.

[0032] Optionally, the reinforcing layer is any one of a polyvinylidene fluoride layer containing phosphorus (P), a polyvinylidene fluoride layer containing aspartate (As), a polymethyl methacrylate layer containing phosphorus (P), or a polymethyl methacrylate layer containing aspartate (As).

[0033] Optionally, the thickness ratio of the buffer layer to the reinforcing layer is 5:1 to 50:1.

[0034] Optionally, the thickness of the buffer layer is less than or equal to a thickness threshold, wherein the thickness threshold ranges from 900 angstroms to 1100 angstroms.

[0035] Optionally, the thickness of the reinforcing layer is 1 nm to 10 nm.

[0036] Thirdly, a semiconductor device is provided, said semiconductor device being manufactured using the method described in any of the preceding claims.

[0037] The unexpected technical effects of the technical solution provided by this invention are:

[0038] This invention provides a method for fabricating a semiconductor structure. A gate structure is formed in a first doped region and a second doped region, and after forming an ion barrier layer on the second doped region, a buffer layer and a reinforcement layer are fabricated on the surface of the gate structure in the first doped region. The buffer layer at least covers the gate structure and has a porous structure. An unexpected technical effect is that when the porous buffer layer is placed on top of the reinforcement layer, the high expansion coefficient of the buffer layer effectively absorbs the impact of ion energy on the gate structure during the formation of the source and drain electrodes in the first doped region via ion implantation, preventing damage to the gate structure. Furthermore, the high expansion coefficient of the buffer layer can alleviate the stress on the gate sidewalls under ion energy impact to some extent, further ensuring that the gate structure is not damaged. In addition, the porous buffer layer further avoids the influence of the buffer layer on the source and drain electrode fabrication process in the first doped region. To ensure the protective effect of the buffer layer on the gate structure, the area covered by the buffer layer is set relatively large, and the buffer layer may cover both the source and drain electrode fabrication areas in the first doped region. Because the buffer layer has a porous structure, it has little impact on the ion implantation process when the source and drain are formed through ion implantation, which facilitates the formation of the source and drain in the first doped region.

[0039] A portion of the buffer layer is fixed to form a reinforcement layer through ion implantation. An unexpected technical effect is that after ion implantation, the surface cross-linking degree of the buffer layer increases, producing amorphous carbon, thereby increasing mechanical strength and forming the reinforcement layer. The reinforcement layer is doped with elements, forming hydrogen bonds with the underlying polymer layer (buffer layer), preventing it from detaching during high-energy ion impacts. When the buffer layer is used alone, although it can absorb the impact force of ions on the gate structure, the gate structure will still tilt along the direction of ion energy (e.g., if the ion energy direction is from the upper right to the lower left, after the ions hit the gate structure surface, the gate structure will also tend to tilt from the upper right to the lower left). If the impact force of the ions on the gate structure is large, the tilting tendency will be greater. Under the protection of the buffer layer, the gate structure itself will not be damaged. However, the interface between the gate structure and the first doped region is not protected by the buffer layer. With the gate structure tilting, there is a tendency for the gate structure to separate from the first doped region, which may eventually lead to separation. By adding a reinforcement layer, the gate structure can be further fixed, the tilting tendency of the gate structure can be alleviated, thereby protecting the gate structure and preventing the gate structure from separating from the first doped region.

[0040] With the combined effect of the buffer layer and the reinforcement layer, the gate structure is ensured not to break under ion energy impact, while also ensuring a relatively stable bond between the gate structure and the first doped region. Ultimately, after the source and drain are formed in the first doped region, it is still ensured that the gate structure on the surface of the first doped region will not break or detach, thereby ensuring the quality of the final semiconductor device. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 A schematic diagram of a semiconductor structure provided for related technologies;

[0043] Figure 2 A schematic diagram of another semiconductor structure provided for related technologies;

[0044] Figure 3 A schematic diagram of another semiconductor structure provided for related technologies;

[0045] Figure 4 A schematic diagram of a semiconductor structure provided by the present invention;

[0046] Figure 5 A flowchart of a method for fabricating a semiconductor structure provided by the present invention;

[0047] Figure 6 A flowchart illustrating a method for fabricating a semiconductor device provided by the present invention;

[0048] Figure 7 This invention provides a schematic diagram of the structure of a semiconductor device during its fabrication process;

[0049] Figure 8 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0050] Figure 9 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0051] Figure 10 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0052] Figure 11 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0053] Figure 12 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0054] Figure 13 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0055] Figure 14 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0056] Figure 15 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0057] Figure 16 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0058] Figure 17 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0059] Figure 18 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0060] Figure 19 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0061] Figure 20 A schematic diagram of the fabrication process of another semiconductor device provided by the present invention;

[0062] Figure 21 This is a schematic diagram of the structure of a semiconductor device provided by the present invention.

[0063] The attached figures are labeled as follows:

[0064] 10: Substrate;

[0065] 11: Functional layer; 111: First doped region; 112: Second doped region; 113: Isolation structure; 114: First source; 115: First drain; 116: Second source; 117: Second drain;

[0066] 12: Gate structure; 121: Gate oxide layer; 122: Gate; 123: Gate sidewall;

[0067] 13: Ion blocking layer;

[0068] 14: Buffer structure; 141: Buffer layer; 142: Reinforcing layer. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0070] Figure 4 A schematic diagram of a semiconductor structure provided by the present invention. See also... Figure 4 ,include:

[0071] Substrate 10, the substrate 10 having a functional layer 11, the functional layer 11 including a first doped region 111 and a second doped region 112 spaced apart, and an isolation structure 113 disposed between the first doped region 111 and the second doped region 112;

[0072] A gate structure 12 is formed on the first doped region 111 and the second doped region 112, respectively. The gate structure 12 includes a gate oxide layer 121, a gate 122 and a gate sidewall 123.

[0073] An ion barrier layer 13 is formed on the second doped region 112, and the ion barrier layer 12 exposes at least the source preparation region and the drain preparation region of the first doped region 111.

[0074] A buffer layer 141 is provided, which at least covers the gate structure of the first doped region 111. The buffer layer 141 has a porous structure. The coverage area of ​​the buffer layer 141 can be selectively determined. The buffer layer 141 can also simultaneously cover the first doped region 111 and the ion barrier layer 13, etc., so that the interface between the buffer layer 141 and other structures is relatively large. The relatively large interface gives the buffer layer 141 a certain fixing effect (that is, the effect of fixing the gate in place, which to some extent helps to alleviate the tilting of the gate under the impact of ion energy). However, since the buffer layer is relatively soft, this fixing effect is relatively limited.

[0075] The reinforcement layer 142 is formed on the surface of the buffer layer 141 by an ion implantation process. The reinforcement layer formed on the surface of the buffer layer 141 is to further improve the fixation effect, thereby significantly mitigating the tendency of the gate structure 12 to tilt under ion energy impact.

[0076] This invention provides a semiconductor structure in which a gate structure is formed in a first doped region and a second doped region, and after forming an ion barrier layer on the second doped region, a buffer layer and a reinforcement layer are fabricated on the surface of the gate structure in the first doped region. The buffer layer at least covers the gate structure and is porous. An unexpected technical effect is that, with the porous buffer layer, when the source and drain are formed in the first doped region via ion implantation, the high expansion coefficient of the buffer layer can effectively absorb the impact force of ion energy on the gate structure, preventing damage to the gate structure under ion energy impact. Furthermore, the high expansion coefficient of the buffer layer can alleviate the stress on the gate sidewalls to some extent under ion energy impact, further ensuring that the gate structure is not damaged. In addition, the porous buffer layer further avoids the influence of the buffer layer on the source and drain fabrication processes in the first doped region. To ensure the protective effect of the buffer layer on the gate structure, the area covered by the buffer layer is set relatively large, and the buffer layer may cover both the source and drain fabrication regions in the first doped region. Because the buffer layer has a porous structure, it has little impact on the ion implantation process when the source and drain are formed through ion implantation, which facilitates the formation of the source and drain in the first doped region.

[0077] A portion of the buffer layer is fixed to form a reinforcement layer through ion implantation. An unexpected technical effect is that after ion implantation, the surface cross-linking degree of the buffer layer increases, producing amorphous carbon, thereby increasing mechanical strength and forming the reinforcement layer. The reinforcement layer is doped with elements, forming hydrogen bonds with the underlying polymer layer, preventing it from detaching during high-energy ion impacts. While the buffer layer alone can absorb the impact force of ions on the gate structure, the gate structure will still tilt along the direction of ion energy (e.g., if the ion energy direction is from the upper right to the lower left, the gate structure will tend to tilt from the upper right to the lower left after impact). The greater the impact force of the ions, the greater the tilting tendency. Under the protection of the buffer layer, the gate structure itself will not be damaged. However, the interface between the gate structure and the first doped region is not protected by the buffer layer. With the gate structure tilting, there is a tendency for separation between the gate structure and the first doped region, which may eventually lead to separation. By adding a reinforcement layer, the gate structure can be further fixed, the tilting tendency of the gate structure can be alleviated, thereby protecting the gate structure and preventing the gate structure from separating from the first doped region.

[0078] With the combined effect of the buffer layer and the reinforcement layer, the gate structure is ensured not to break under ion energy impact, while also ensuring a relatively stable bond between the gate structure and the first doped region. Ultimately, after the source and drain are formed in the first doped region, it is still ensured that the gate structure on the surface of the first doped region will not break or detach, thereby ensuring the quality of the final semiconductor device.

[0079] It is worth noting that, Figure 4 This provides the structure of a semiconductor device (CMOS device) during its fabrication process.

[0080] In this embodiment, substrate 10 is a Si substrate.

[0081] In other embodiments, the substrate may be made of semiconductor material, insulating material, conductive material, or any combination thereof. For example, silicon-germanium (SiGe) substrate, silicon-germanium-carbon (SiGeC) substrate, silicon-carbide (SiC) substrate, gallium-arsenide (GaAs) substrate, indium-arsenide (InAs) substrate, indium-phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type and thickness of the substrate should not limit the scope of this disclosure.

[0082] In this embodiment, the first doped region 111 is a PMOS region and the second doped region 112 is an NMOS region.

[0083] In other embodiments, the first doped region 111 can be an NMOS region and the second doped region 112 can be a PMOS region.

[0084] In this embodiment, the PMOS region refers to the region doped with trivalent impurity elements, such as boron (B), gallium (Ga), etc.

[0085] In this embodiment, the NMOS region refers to the region doped with pentavalent impurity elements, such as phosphorus (P) or arsenic (As).

[0086] In this embodiment, the isolation structure 113 can be a shallow trench isolation (STI) structure, that is, after forming a shallow trench in the substrate 10, an oxide layer is filled in the shallow trench to form the isolation structure 113.

[0087] In this embodiment, the first source 114 and the first drain 115 are disposed in the first doped region 111. If the first doped region 111 is a PMOS region, the first source 114 and the first drain 115 are formed by P-type doping, that is, doped with trivalent impurity elements. If the first doped region 111 is an NMOS region, the first source 114 and the first drain 115 are formed by N-type doping, that is, doped with pentavalent impurity elements.

[0088] The second source 116 and the second drain 117 can be referenced to the doping process of the first source 114 and the first drain 115.

[0089] In this embodiment, the gate oxide layer 121 in the gate structure 12 can be formed using SiO2; of course, the gate oxide layer 121 can also be formed using other oxides, and this application does not limit this.

[0090] In this embodiment, the gate 122 can be formed of polysilicon or a metal material, wherein the metal material can be any one of TiN, TaN, W, etc.

[0091] In this embodiment, the gate sidewall 123 is a silicon nitride layer.

[0092] When the source and drain are formed in the first doped region using ion implantation, the ion blocking layer 13 is used to block ions, ensuring that ions are implanted controllably into the source preparation region (i.e., the region corresponding to the source) and the drain preparation region (i.e., the region corresponding to the drain), and avoiding ion implantation into non-target regions.

[0093] Of course, in other embodiments, the ion blocking layer 13 may also be formed of other materials, and the present invention does not limit this.

[0094] In this embodiment, the buffer layer 141 and the reinforcement layer 142 form a buffer structure 14.

[0095] In this embodiment, the buffer layer 141 is a polymer layer, which includes a polyvinylidene fluoride layer or a polymethyl methacrylate layer.

[0096] For example, the buffer layer 141 is a polymer layer, which includes a polymethyl methacrylate layer.

[0097] In this embodiment, a polymer layer is used as a buffer layer. On the one hand, polymers are relatively soft and have a good buffering effect. On the other hand, polymer layers facilitate the subsequent formation of a reinforcing layer and allow the buffer layer to form a porous structure.

[0098] In this embodiment, the reinforcing layer 142 is any one of the following: a polyvinylidene fluoride layer containing phosphorus (P), a polyvinylidene fluoride layer containing arsenic (As), a polymethyl methacrylate layer containing phosphorus (P), and a polymethyl methacrylate layer containing arsenic (As).

[0099] For example, the reinforcing layer 142 is a polymethyl methacrylate layer containing P.

[0100] In this embodiment, the reinforcing layer 142 is a polymer layer after ion implantation. After ion implantation, the surface cross-linking degree of the polymer increases, producing amorphous carbon and improving mechanical strength, thus forming the reinforcing layer 142. The reinforcing layer 142 is doped with F or N elements, which forms hydrogen bonds with the underlying polymer layer (i.e., with the buffer layer 141), making the buffer layer 141 and the reinforcing layer 142 more tightly bonded and preventing the reinforcing layer 142 from falling off during high-energy ion bombardment.

[0101] In this embodiment, the thickness ratio of the remaining buffer layer 141 to the reinforcing layer 142 is 5:1 to 50:1.

[0102] For example, the thickness ratio of the buffer layer 141 to the reinforcing layer 142 is 10:1.

[0103] In this embodiment, while ensuring the fixing effect of the reinforcement layer, the buffer layer is made relatively thick, thereby ensuring the overall protection effect of the buffer structure 14 on the gate structure. Since the reinforcement layer is a hardened layer, if the reinforcement layer is made too thick, it will be detrimental to the buffering effect of the buffer structure 14; if the reinforcement layer is made too thin, it will result in a weaker fixing effect.

[0104] In this embodiment, the thickness of the buffer layer 141 is less than or equal to a thickness threshold, and the thickness threshold ranges from 900 angstroms to 1100 angstroms.

[0105] For example, the thickness threshold is 1000 angstroms.

[0106] In this embodiment, the thickness of the buffer layer 141 should not be too thick, as this would increase manufacturing costs. Conversely, the thickness of the buffer layer should not be too thin, as this would negatively impact the buffering effect. By using a buffer layer within the aforementioned thickness range, both buffering effectiveness and manufacturing cost can be balanced.

[0107] In this embodiment, the thickness of the reinforcing layer 142 is 1 nm to 10 nm.

[0108] For example, the thickness of the reinforcing layer 142 is 5 nm.

[0109] In this embodiment, the thickness of the reinforcing layer should not be too thick. Excessive thickness would result in a high proportion of the reinforcing layer in the buffer structure, making the overall buffer structure too rigid and reducing its buffering effect. Conversely, the thickness of the reinforcing layer should not be too thin, as this would lead to poor fixation. The buffer structure needs to balance both buffering and reinforcing effects to effectively protect the gate structure.

[0110] Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure provided by this invention. See also... Figure 5 ,include:

[0111] S101. A substrate is provided, and a functional layer is formed in the substrate; wherein the functional layer includes a first doped region and a second doped region disposed at intervals, and an isolation structure disposed between the first doped region and the second doped region.

[0112] In one example, step S101 includes:

[0113] Step 1, Provide a substrate.

[0114] Figure 7 This is a schematic diagram illustrating the structure of a semiconductor device during its fabrication process, as provided by the present invention. Figure 7 The substrate 10 is shown in detail.

[0115] In this embodiment, substrate 10 is a Si substrate.

[0116] In other embodiments, the substrate may be made of semiconductor material, insulating material, conductive material, or any combination thereof. For example, silicon-germanium (SiGe) substrate, silicon-germanium-carbon (SiGeC) substrate, silicon-carbide (SiC) substrate, gallium-arsenide (GaAs) substrate, indium-arsenide (InAs) substrate, indium-phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type and thickness of the substrate should not limit the scope of this disclosure.

[0117] Step 2: Create the isolation structure.

[0118] In this embodiment, the isolation structure 113 can be a shallow trench isolation (STI) structure, that is, after forming a shallow trench in the substrate 10, an oxide layer is filled in the shallow trench to form the isolation structure 113.

[0119] Step 3: Form a first doped region and a second doped region in the substrate.

[0120] The first doped region 111 and the second doped region 112 can be formed by ion implantation.

[0121] In this embodiment, the first doped region 111 is a PMOS region and the second doped region 112 is an NMOS region.

[0122] In other embodiments, the first doped region 111 can be an NMOS region and the second doped region 112 can be a PMOS region.

[0123] In this embodiment, the PMOS region refers to the region doped with trivalent impurity elements, such as boron (B), gallium (Ga), etc.

[0124] In this embodiment, the NMOS region refers to the region doped with pentavalent impurity elements, such as phosphorus (P) or arsenic (As).

[0125] It should be noted that the first doped region 111 and the second doped region 112 are formed by two ion implantations.

[0126] Figure 8 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 8 Specifically, the first doped region 111, the second doped region 112, and the isolation structure 113 are shown.

[0127] S102. A gate structure is fabricated on the first doped region and the second doped region, the gate structure including a gate oxide layer, a gate, and a gate sidewall.

[0128] In one example, step S102 includes:

[0129] The first step is to fabricate the gate oxide layer.

[0130] In this embodiment, the gate oxide layer can be formed by thermal oxidation. A SiO2 layer is formed on the surface of the substrate 10 by thermal oxidation, and the SiO2 layer is etched to finally form the gate oxide layer.

[0131] Figure 9 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 9 Specifically, the completed gate oxide layer 121 is shown.

[0132] The second step is to fabricate gates on the surfaces of the first doped region and the second doped region.

[0133] In this embodiment, the gate 122 can be formed of polysilicon or a metal material, wherein the metal material can be TiN, TaN, W, etc.

[0134] In this embodiment, if the gate is made of polycrystalline silicon, it can be formed by chemical vapor deposition. After depositing the polycrystalline silicon layer, ion implantation is performed on the polycrystalline silicon layer to dope it with impurities (P-type doping or N-type doping) to reduce resistance and adjust the work function. Finally, the doped polycrystalline silicon layer is etched to form the gate.

[0135] In this embodiment, if the gate 122 is a metal material, the gate can be formed by physical vapor deposition or atomic layer deposition. After depositing the metal layer, the metal layer is etched to form the gate.

[0136] Figure 10 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 10 Specifically, the completed gate 122 is shown.

[0137] The third step is to fabricate the gate sidewall 123 on the side of the gate 122 using a low-pressure chemical vapor deposition process.

[0138] For example, dichlorosilane (DCS) and NH3 are used as raw materials, with a DCS to NH3 ratio of 2:1 to 8:1. The reaction is carried out at an environment of 500 to 900°C to form a silicon nitride layer. The silicon nitride layer is then etched to form a gate sidewall.

[0139] In this embodiment, the gate sidewall is fabricated using a low-pressure chemical vapor deposition process, which ensures that there is tensile stress between the gate sidewall and the gate. Combined with the high expansion coefficient of the polymer in the buffer layer, the tensile stress between the gate sidewall and the gate can be effectively released.

[0140] Figure 11 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 11 Specifically, the gate sidewall 123 is shown.

[0141] S103, an ion barrier layer 13 is formed on the second doped region 112, wherein the ion barrier layer 13 exposes at least the source preparation region and the drain preparation region of the first doped region 111.

[0142] In one example, step S103 includes:

[0143] The steps of coating photoresist, exposure, and development are performed sequentially to form an ion blocking layer 13 on the second doped region 112.

[0144] It should be noted that the statement that the ion barrier layer at least exposes the source and drain fabrication regions of the first doped region means that the ion barrier layer can be formed not only on the first doped region, but also extended into the first doped region or the isolation structure. However, the ion barrier layer needs to reserve windows corresponding to the source and drain fabrication regions in the first doped region for forming the first source and first drain in the first doped region.

[0145] Figure 12 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 12 Specifically, the ion blocking layer 13 is shown.

[0146] S104. A buffer layer 141 is formed that at least covers the gate structure 12 of the first doped region 111, and the buffer layer 141 is a porous structure.

[0147] In one example, step S104 includes:

[0148] Step 1: At least the surface of the gate structure 12 in the first doped region 111 is coated with a first organic solvent, which is formed by mixing a polymer and a template agent.

[0149] In one example, step 1 includes:

[0150] A first organic solvent containing a polymer and a template agent is spin-coated onto the surface of the gate structure 12 of the first doped region 111; wherein the spin-coating speed is 100 rpm to 2000 rpm.

[0151] For example, the spin coating speed is 1000 rpm.

[0152] In this embodiment, the polymer includes polyvinylidene fluoride or polymethyl methacrylate.

[0153] In this embodiment, using the above-mentioned material as a polymer is beneficial for the subsequent formation of a porous buffer layer and ensures that the formed buffer layer has a high coefficient of expansion, thereby ensuring the buffering effect of the subsequently formed buffer layer.

[0154] In this embodiment, the template agent comprises polystyrene with a mass fraction of 20% to 80%.

[0155] For example, the template agent comprises 40% polystyrene by mass.

[0156] Step 2: The coated material is heated with the first organic solvent to form an organic film.

[0157] In one example, step 2 includes:

[0158] In an environment with a temperature of 100~300℃, the first organic solvent is heated for 10~60 minutes to form an organic film.

[0159] For example, an organic thin film is formed by heating a first organic solvent at a temperature of 200°C for 40 minutes.

[0160] Step 3: Use a second organic solvent to remove the template agent from the organic film to form a buffer layer with a porous structure.

[0161] In this embodiment, the second organic solvent includes cyclohexane or ethyl acetate.

[0162] Figure 13 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 13 Specifically, buffer layer 141 is shown.

[0163] S105. Ion implantation is performed on the buffer layer 141 to convert the surface of the buffer layer 141 into a reinforcement layer 142.

[0164] In one example, step S105 includes:

[0165] Using P or As as the implanted element, the implantation dose is 1×10 14 Atom / cm 2 ~1×10 16 Atom / cm 2 Ion implantation was performed on the buffer layer using an injection energy of 5keV~30keV.

[0166] For example, with P as the injected element, the injected dose is 5 × 10⁻⁶. 14 Atom / cm 2 Ion implantation was performed on the buffer layer at an injection energy of 10 keV.

[0167] In this embodiment, the injection dosage and energy affect the thickness of the reinforcement layer; the higher the dosage and energy, the thicker the reinforcement layer. By using the above parameters to fabricate the reinforcement layer, it can be ensured that the thickness of the reinforcement layer is within a suitable range.

[0168] In this embodiment, P or As elements are ion implanted onto the surface of the buffer layer to form a reinforcing layer on the surface of the buffer layer, thereby enhancing its resistance to energy shocks. After ion implantation, the surface cross-linking degree of the polymer increases, producing amorphous carbon, which improves mechanical strength and forms a reinforcing layer. The reinforcing layer is doped with P or As elements, which form hydrogen bonds with the underlying polymer layer, preventing the reinforcing layer and the buffer layer from detaching during high-energy ion shocks.

[0169] Figure 14 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 14 Specifically, the reinforcement layer 142 is shown.

[0170] Figure 6 A flowchart illustrating a method for fabricating a semiconductor device according to the present invention. See also... Figure 6 ,include:

[0171] S201. A substrate is provided, and a functional layer is formed in the substrate; wherein the functional layer includes a first doped region and a second doped region disposed at intervals, and an isolation structure disposed between the first doped region and the second doped region.

[0172] See step S101.

[0173] S202. A gate structure is fabricated on the first doped region and the second doped region respectively. The gate structure includes a gate oxide layer, a gate, and a gate sidewall.

[0174] See step S102.

[0175] S203. An ion barrier layer is formed on the second doped region, wherein the ion barrier layer exposes at least the source and drain fabrication regions of the first doped region.

[0176] See step S103.

[0177] S204. A buffer layer is formed that at least covers the gate structure on the first doped region, and the buffer layer is a porous structure.

[0178] See step S104.

[0179] S205. Ion implantation is performed on the buffer layer to convert the surface of the buffer layer into a reinforcement layer.

[0180] See step S105.

[0181] S206. Fabricate the first source and the first drain in the first doped region.

[0182] The source and drain electrodes can be formed through ion implantation.

[0183] In this embodiment, the first source 114 and the first drain 115 are disposed in the first doped region 111. If the first doped region 111 is a PMOS region, the first source 114 and the first drain 115 are formed by P-type doping, that is, doped with trivalent impurity elements. If the first doped region 111 is an NMOS region, the first source 114 and the first drain 115 are formed by N-type doping, that is, doped with pentavalent impurity elements.

[0184] Figure 15 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 15 Specifically, the first source 114 and the first drain 115 are shown.

[0185] S207. Remove the reinforcement layer, buffer layer and ion barrier layer in sequence.

[0186] In one example, step S207 includes:

[0187] The reinforcement layer, buffer layer, and ion barrier layer are removed by a combination of dry and wet etching.

[0188] Dry etching is a common ashing process that uses gases such as O2, N2, H2, CF4, and CH4. Wet etching uses a sulfuric acid-hydrogen peroxide mixture (SPM process), with the sulfuric acid temperature at 90~190℃ and the volume ratio of sulfuric acid to hydrogen peroxide at 10:1~1:2.

[0189] Figure 16 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 16 The structure after removing the reinforcement layer, buffer layer, and ion barrier layer is shown.

[0190] S208. An ion barrier layer 13 is formed on the first doped region 111, wherein the ion barrier layer 13 exposes at least the source and drain fabrication regions of the second doped region 112.

[0191] The steps for fabricating the ion barrier layer are described in step S103, but the difference between step S103 and step S103 is that the formation region of the ion barrier layer 13 is different.

[0192] Figure 17 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 17 Specifically, it shows the fabrication of an ion barrier layer 13 on the first doped region 111.

[0193] S209. A buffer layer 141 is formed to at least cover the gate structure 12 of the second doped region 112, and the buffer layer 141 is a porous structure.

[0194] See step S104. The difference between step S104 and step S104 is that the formation area of ​​the buffer layer 141 is different.

[0195] Figure 18 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 18 The diagram shows the structure after the buffer layer has been created.

[0196] S210. Ion implantation is performed on the buffer layer 141 to convert the surface of the buffer layer 141 into a reinforcement layer 142.

[0197] See step S105. The difference between step S105 and step S105 is that the areas where the buffer layer 141 and the reinforcing layer 142 are formed are different.

[0198] Figure 19 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 19 Specifically, the buffer layer 141 and the reinforcement layer 142 that are prepared to cover the gate 12 on the second doped region 112 are shown.

[0199] S211, a second source and a second drain are formed in the second doped region 112.

[0200] The second source and the second drain can be formed by ion implantation.

[0201] In this embodiment, the second source 116 and the second drain 117 are disposed in the second doped region 112. If the second doped region 112 is an NMOS region, the second source 116 and the second drain 117 are formed by N-type doping, that is, doped with pentavalent impurity elements. If the second doped region 112 is a PMOS region, the second source 116 and the second drain 117 are formed by P-type doping, that is, doped with trivalent impurity elements.

[0202] Figure 20 A schematic diagram illustrating the fabrication process of another semiconductor device provided by this invention. See also... Figure 20 Specifically, the second source 116 and the second drain 117 are shown.

[0203] S212. Remove the reinforcement layer, buffer layer and ion barrier layer in sequence.

[0204] See step S207.

[0205] Figure 21 This is a schematic diagram of the structure of a semiconductor device provided by the present invention. See also... Figure 21 This shows the structure after removing the hardening layer, buffer layer, and ion barrier layer, which is the final semiconductor device (CMOS device).

[0206] This invention provides a method for fabricating a semiconductor structure, comprising forming a gate structure in a first doped region and a second doped region, and forming an ion barrier layer on the second doped region, followed by forming a buffer layer and a reinforcement layer on the surface of the gate structure in the first doped region. The buffer layer at least covers the gate structure and is porous. An unexpected technical effect is that, with the porous buffer layer, when the source and drain are formed in the first doped region via ion implantation, the high expansion coefficient of the buffer layer can effectively absorb the impact force of ion energy on the gate structure, preventing damage to the gate structure under ion energy impact. Furthermore, the high expansion coefficient of the buffer layer can alleviate the stress on the gate sidewalls to some extent under ion energy impact, further ensuring that the gate structure is not damaged. In addition, the porous buffer layer further avoids the influence of the buffer layer on the source and drain fabrication processes in the first doped region. To ensure the protective effect of the buffer layer on the gate structure, the area covered by the buffer layer is set relatively large, and the buffer layer may cover both the source and drain fabrication areas in the first doped region. Because the buffer layer has a porous structure, it has little impact on the ion implantation process when the source and drain are formed through ion implantation, which facilitates the formation of the source and drain in the first doped region.

[0207] A portion of the buffer layer is fixed to form a reinforcement layer through ion implantation. An unexpected technical effect is that after ion implantation, the surface cross-linking degree of the buffer layer increases, producing amorphous carbon, thereby increasing mechanical strength and forming the reinforcement layer. The reinforcement layer is doped with elements, forming hydrogen bonds with the underlying polymer layer, preventing it from detaching during high-energy ion impacts. While the buffer layer alone can absorb the impact force of ions on the gate structure, the gate structure will still tilt along the direction of ion energy (e.g., if the ion energy direction is from the upper right to the lower left, the gate structure will tend to tilt from the upper right to the lower left after impact). The greater the impact force of the ions, the greater the tilting tendency. Under the protection of the buffer layer, the gate structure itself will not be damaged. However, the interface between the gate structure and the first doped region is not protected by the buffer layer. With the gate structure tilting, there is a tendency for separation between the gate structure and the first doped region, which may eventually lead to separation. By adding a reinforcement layer, the gate structure can be further fixed, the tilting tendency of the gate structure can be alleviated, thereby protecting the gate structure and preventing the gate structure from separating from the first doped region.

[0208] With the combined effect of the buffer layer and the reinforcement layer, the gate structure is ensured not to break under ion energy impact, while also ensuring a relatively stable bond between the gate structure and the first doped region. Ultimately, after the source and drain are formed in the first doped region, it is still ensured that the gate structure on the surface of the first doped region will not break or detach, thereby ensuring the quality of the final semiconductor device.

[0209] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The application relates to a substrate and a functional layer formed in the substrate, wherein the functional layer comprises first and second doped regions arranged at intervals and an isolation structure arranged between the first and second doped regions; a gate structure is formed on the first and second doped regions respectively, and the gate structure comprises a gate oxide layer, a gate and a gate sidewall; an ion blocking layer is formed on the second doped region, and the ion blocking layer exposes at least a source preparation area and a drain preparation area in the first doped region; a buffer layer is formed, and the buffer layer covers at least the gate structure of the first doped region, wherein the buffer layer is a porous structure; and the surface layer of the buffer layer is converted into a reinforced layer through ion implantation. The step of forming the buffer layer comprises the following steps: a first organic solvent is coated on at least the surface of the gate structure of the first doped region, wherein the first organic solvent is formed by mixing a polymer and a template agent; the first organic solvent is subjected to a heating treatment to form an organic thin film; and a second organic solvent is used to remove the template agent in the organic thin film to form the buffer layer with a porous structure. The polymer comprises polyvinylidene fluoride or polymethyl methacrylate. The template agent comprises polystyrene with a mass fraction of 20%-80%. The second organic solvent comprises cyclohexane or ethyl acetate. The application relates to a substrate and a functional layer formed in the substrate, wherein the functional layer comprises first and second doped regions arranged at intervals and an isolation structure arranged between the first and second doped regions; a gate structure is formed on the first and second doped regions respectively, and the gate structure comprises a gate oxide layer, a gate and a gate sidewall; an ion blocking layer is formed on the second doped region, and the ion blocking layer exposes at least a source preparation area and a drain preparation area in the first doped region; a buffer layer is formed, and the buffer layer covers at least the gate structure of the first doped region, wherein the buffer layer is a porous structure; and the surface layer of the buffer layer is converted into a reinforced layer through ion implantation.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The buffer layer is a polymer layer, and the polymer layer comprises a polyvinylidene fluoride layer or a polymethyl methacrylate layer. The reinforced layer is any one of a polyvinylidene fluoride layer containing P, a polyvinylidene fluoride layer containing As, a polymethyl methacrylate layer containing P and a polymethyl methacrylate layer containing As. The thickness ratio of the buffer layer to the reinforced layer is 5:1-50:

1. The thickness of the buffer layer is less than or equal to a thickness threshold value, and the thickness threshold value is in the range of 900 angstroms-1100 angstroms.

3. The method of fabricating a semiconductor structure of claim 2, wherein, ​ 4. The method of fabricating a semiconductor structure of claim 2, wherein, ​ 5. The method of claim 2, wherein ​ 6. A semiconductor structure, characterized by ​ ​ ​ ​ ​ ​ 7. The semiconductor structure of claim 6, wherein, ​ 8. The semiconductor structure of claim 6, wherein, ​ 9. The semiconductor structure according to any one of claims 6 to 8, characterized in that ​ 10. The semiconductor structure of claim 9, wherein, ​

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