Testing methods and apparatus for semiconductor structures

Abstract

This application provides a testing method and apparatus for semiconductor structures. The method includes: applying test voltages to multiple pads and obtaining multiple first current-voltage curves between the pads and ground terminals of the testing apparatus; applying test voltages to multiple groups of pads and obtaining second current-voltage curves for the groups of pads, wherein each group of pads consists of at least two pads connected to the same conductive layer; detecting the second current-voltage curves and the corresponding first current-voltage curves of the pads, and determining the location of defects in the semiconductor structure based on the detection results. The testing method and apparatus for semiconductor structures provided in this application obtain current / voltage curves by applying different voltages to the pads of the testing apparatus, and determine whether there are open vias based on the curve results, thereby reflecting whether there are open vias in the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method and apparatus for testing through-hole defects in semiconductor structures. Background Technology

[0002] With the continuous development of modern high-tech industries, represented by electronic communication technology, the total output value of the world's integrated circuit industry is growing at a rate of over 30% annually. Static Random Access Memory (SRAM), as an important storage device, is widely used in digital and communication circuit design. SRAM is an important component in logic circuits, widely used for data storage due to its advantages such as low power consumption and high read speed.

[0003] As the feature size (CD) of devices gradually decreases, issues such as small clusters and TB_H (two-bit horizontality) caused by open vias are important causes of hard failure in HV (high voltage) SRAM. However, open vias occur at the back end, and current inline detection alone cannot fully monitor them.

[0004] In a small cluster defect caused by a 4-bit HV (high voltage) SRAM, black spots can be found in the electron microscope image of the Physical Failure Analysis (PFA) results. A slice along the vertical direction reveals an open via shared by two NMOS transistors at the ground terminal. This open via cannot be fully detected by online inspection. Furthermore, for static random access memory or other devices with multi-layer vias, multiple adjacent vias on the same layer may be connected to the same conductive layer. Digital volume image correlation (DVC) is required after PFA, but DVC cannot completely cover open vias at the device's ground terminal. Alternatively, during chip probe testing (CP), electrical failure analysis (EFA) / Physical failure analysis (PFA) is needed to detect open vias, which results in many false positives or false negatives, low efficiency, and inefficient monitoring. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a testing method and testing apparatus for semiconductor structures. By applying different voltages to the pads of the testing apparatus, a current / voltage curve is obtained, and the open via phenomenon is determined based on the curve results, thereby reflecting whether there is an open via phenomenon in the semiconductor structure.

[0006] According to a first aspect of the present invention, a testing method for a semiconductor structure is provided, wherein the semiconductor structure and a testing apparatus are formed synchronously, both including a ground terminal located in a substrate, a plurality of pads, multiple conductive channels, and multiple conductive layers, wherein the conductive channels connect two adjacent conductive layers, and the pads are connected to conductive layers in the multiple conductive layers that are away from the substrate via the conductive channels, and at least two conductive layers of the same layer are connected to adjacent conductive layers via the conductive channels, wherein the testing method includes: applying test voltages to the plurality of pads respectively and obtaining a plurality of first current-voltage curves between the pads and the ground terminal of the testing apparatus; applying test voltages to a plurality of pad groups respectively and obtaining a plurality of second current-voltage curves of the pad groups, wherein the pad group is at least two pads connected to the same conductive layer; detecting the second current-voltage curves and the corresponding first current-voltage curves of the pads, and determining the location of defects in the semiconductor structure based on the detection results.

[0007] Optionally, the test voltage is a scan voltage ranging from 0 to the power supply voltage.

[0008] Optionally, the step of applying a test voltage to multiple pad groups and obtaining a second current-voltage curve for multiple pad groups, wherein the pad group is at least two pads connected to the same conductive layer, includes: applying a test voltage to a target pad in the pad group, grounding the other pads, and obtaining a second current-voltage curve between the target pad and at least one grounded pad; changing the target pad and repeating the step of obtaining the second current-voltage curve until at least one second current-voltage curve for all target pads is obtained.

[0009] Optionally, in the first current-voltage curve and the second current-voltage curve, if the current increases linearly with the increase of voltage, then the current path corresponding to the current-voltage curve is normal; if the current increases instantaneously with the increase of voltage exceeding a threshold, then the current path corresponding to the current-voltage curve is abnormal and a short circuit exists; if the current remains 0 or close to 0 with the increase of voltage, then the current path corresponding to the current-voltage curve is abnormal and an open circuit exists.

[0010] Optionally, between the steps of applying test voltages to multiple pads and obtaining multiple first current-voltage curves between the pads and ground of the test device and the steps of applying test voltages to multiple pad groups and obtaining second current-voltage curves of multiple pad groups, the method further includes: obtaining at least one pad group based on the multiple first current-voltage curves.

[0011] Optionally, the step of obtaining at least one pad group based on the plurality of first current-voltage curves includes: determining the target pad based on the relationship between current and voltage in the plurality of first current-voltage curves; determining whether the target pad and other pads are connected to the same conductive layer; if so, at least two pads connected to the same conductive layer constitute a pad group.

[0012] Optionally, the target pad is the pad whose current changes abnormally with voltage in the first current-voltage curve.

[0013] Optionally, in the step of detecting the second current-voltage curve and the first current-voltage curve of the corresponding pad, and determining the location of the defect in the semiconductor structure based on the detection results, if the second current-voltage curve of the target pad is abnormal, the defect location is located between the target pad and the conductive layer jointly connected to the target pad and the ground pad corresponding to the second current-voltage curve; if the second current-voltage curve of the target pad is normal, the defect location is located between the conductive layer jointly connected to the target pad and the ground pad corresponding to the second current-voltage curve and the ground terminal of the test device.

[0014] Optionally, one of the target pads is located in at least one pad group, and at least one pad in different pad groups is different.

[0015] According to another aspect of the present invention, a testing apparatus for a semiconductor structure is provided, the testing apparatus being formed synchronously with the semiconductor structure and having the same structural features as the semiconductor structure, wherein the testing apparatus is used to perform the above-described testing method.

[0016] The unexpected technical effect of this application is:

[0017] The testing method and apparatus for semiconductor structures provided in this application, which are formed synchronously with the semiconductor structure in the chip, test the wiring layers in the testing apparatus by applying different voltages to the pads of the testing apparatus in sequence, thereby obtaining multiple current / voltage curves. The current represents the current between the corresponding pad and the ground terminal when the voltage is applied. The current / voltage curves are used to determine whether an open circuit exists between the pad and the ground terminal in the testing apparatus. If an open circuit exists, there will be no current or the current will always be close to 0, regardless of the voltage applied. This detection method can quickly detect open circuit problems in the semiconductor structure, allowing for timely adjustments to the semiconductor process and reducing defects in the semiconductor structure.

[0018] Furthermore, after sequentially acquiring the current / voltage curves between each pad and the ground terminal in the test device, the method further includes applying a first voltage and a second voltage to two adjacent / arbitrary pads (the two pads are connected to the same conductive layer in the test device) to obtain the current / voltage curves between the two pads. The method then determines whether an open circuit occurs between the two pads based on the change in current versus voltage. If the current / voltage curve between one of the two adjacent pads indicates an open circuit between that pad and the ground terminal, and the current between the two adjacent pads remains close to 0, then the open circuit occurs between the pad and the shared conductive layer. Attached Figure Description

[0019] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of the structure of a storage unit according to an embodiment of the present invention is shown;

[0021] Figure 2 A flowchart of a testing method for a semiconductor structure according to an embodiment of the present invention is shown;

[0022] Figure 3 A schematic diagram of a test apparatus for semiconductor structures according to an embodiment of the present invention is shown;

[0023] Figure 4 A top view of a test apparatus for semiconductor structures according to an embodiment of the present invention is shown.

[0024] Figure 5 A schematic diagram of the dimensions of a test apparatus for semiconductor structures according to an embodiment of the present invention is shown. Detailed Implementation

[0025] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0026] This application may be presented in various forms, some of which will be described below.

[0027] Figure 1 A schematic diagram of the structure of a storage unit according to an embodiment of the present invention is shown.

[0028] in, Figure 1The storage unit shown includes a first transistor PU1, a second transistor PU2, a third transistor PD1, a fourth transistor PD2, a fifth transistor PG1, and a sixth transistor PG2.

[0029] Specifically, the first terminal of the first transistor PU1 is connected to the power supply voltage VDD; the first terminal of the second transistor PU2 is connected to the first terminal of the first transistor PU1, and the second terminal is connected to the control terminal of the first transistor PU1, while the control terminal is connected to the second terminal of the first transistor PU1; the first terminal of the third transistor PD1 is connected to the second terminal of the first transistor PU1, and the second terminal is connected to the ground terminal GND, while the control terminal is connected to the control terminal of the first transistor PU1; the first terminal of the fourth transistor PD2 is connected to the second terminal of the second transistor PU2, and the second terminal is connected to the second terminal of the third transistor PD1, while the control terminal is connected to the control terminal of the second transistor PU2; the first terminal of the fifth transistor PG1 is connected to the bit line BL, and the second terminal is connected to the second terminal of the first transistor PU1, while the control terminal is connected to the word line WL; the first terminal of the sixth transistor PG2 is connected to the complementary bit line BLB, and the second terminal is connected to the second terminal of the second transistor PU2, while the control terminal is connected to the word line WL.

[0030] During a write operation, the word line WL is high, and the fifth transistor PG1 (select transistor) and the sixth transistor PG2 are turned on. By applying opposite levels to the bit line BL and the complementary bit line BLB (e.g., BL is high and BLB is low), data can be written to the memory unit. The first transistor PU1, the second transistor PU2, the third pull transistor PD1, and the fourth transistor PD2 change the level of the memory node according to the bit line level state, thereby storing data.

[0031] During a read operation: the word line WL is activated first, turning on the fifth transistor PG1 and the sixth transistor PG2. The state of the memory cell is read through the bit line BL and the complementary BLB. Because the memory cell has a cross-coupled structure, the stored logic state will generate a voltage difference on the bit line. The stored data is obtained by detecting this voltage difference.

[0032] During hold operation: When the word line WL is low, the fifth transistor PG1 and the sixth transistor PG2 are turned off, the memory cell is disconnected from the bit line, and the level state of the memory node is maintained by the cross-coupled pull-up and pull-down transistors to retain the stored data.

[0033] In the corresponding semiconductor structure, the substrate includes multiple such... Figure 1The stacked memory unit shown is sliced ​​vertically. The semiconductor structure includes a wiring layer, which contains multiple conductive layers located on different horizontal planes and multiple conductive channels located between vertically adjacent conductive layers. The two ends of each conductive channel are electrically connected to two vertically adjacent conductive layers. However, an open circuit may occur between a via-conductive layer shared by two transistors, and this via open circuit cannot be fully monitored by online detection.

[0034] Figure 2 A flowchart of a testing method for a semiconductor structure according to an embodiment of the present invention is shown; Figure 5 and Figure 3 A cross-sectional and top view schematic diagram of a test apparatus for semiconductor structures according to an embodiment of the present invention is shown; Figure 4 A top view of a test apparatus for semiconductor structures according to an embodiment of the present invention is shown. Figure 5 A schematic diagram of the dimensions of a test apparatus for semiconductor structures according to an embodiment of the present invention is shown.

[0035] like Figure 3 and Figure 4 As shown, the test apparatus 100 for semiconductor structures includes a substrate 110, a plurality of doped regions 101-104 located in the substrate 110, and a wiring layer located above the substrate 110. The wiring layer includes a first conductive channel 120, a first conductive layer 130, a second conductive channel 140, a second conductive layer 150, a third conductive channel 160, and pads 170.

[0036] Among them, the test device 100 is a test device that is manufactured synchronously with the chip, physically integrated but electrically independent. It can be directly tested through the probe station without the need for later connection. It is used to monitor the quality of semiconductor process in real time and is a key tool to ensure chip yield and performance.

[0037] like Figure 3 As shown, the first doped region 101 is connected to the ground terminal GND, for example. The second doped region 102, the third doped region 103, and the fourth doped region 104 are respectively connected to the corresponding pads 170 via the first conductive channel 120, the first conductive layer 130, the second conductive channel 140, the second conductive layer 150, and the third conductive channel 160 in the wiring layer. The number of pads 170 is greater than the number of doped regions, resulting in a situation where one conductive layer is connected to multiple conductive channels in the same layer. That is, different pads 170 may ultimately be electrically connected to the same doped region, such as... Figure 3 The second pad 170-2 in Figure 3 The second pad from the left in the middle) and the third pad 170-3 ( Figure 3The third pad from left to right in the middle is electrically connected to the same first conductive layer 130-2 after passing through the wiring layer, and finally electrically connected to the third doped region 103.

[0038] The test apparatus 100 for semiconductor structures is used to represent the semiconductor structure in a chip and has the same circuit structure as the semiconductor structure. Therefore, the semiconductor structure in this application also includes multiple conductive channels and conductive layers, with at least two conductive channels in the same layer connected to the same conductive layer.

[0039] Furthermore, the test apparatus 100 also includes a wire 180, through which the pad 170 is connected to the power supply voltage VDD. A test voltage is supplied to the test apparatus 100 via the wire 180 to obtain a current-voltage (IV) curve of the test apparatus. Based on the change of current with voltage in the curve, the short circuit or open via in the test apparatus 100 is determined. Since the test apparatus 100 is formed synchronously with the semiconductor structure, if there is a defect in the test apparatus 100, the semiconductor structure formed in the corresponding step will also have a defect.

[0040] In one embodiment, a test voltage is supplied to the test device 100 via the conductor 180. In the obtained current-voltage (IV) curve of the test device, if the curve shows that the current gradually increases linearly with the increase of the voltage, it indicates that the test device 100 is normal and the corresponding semiconductor structure is also normal; if the curve shows that the current increases instantaneously with the increase of the voltage and exceeds the threshold (the threshold is the maximum current value under normal semiconductor structure), it indicates that the test device 100 is short-circuited and the corresponding semiconductor structure is also short-circuited; if the curve shows that the current remains at 0 with the increase of the voltage, it indicates that the test device 100 is open-circuited and the corresponding semiconductor structure is also open-circuited.

[0041] Further, refer to Figure 5 The via (conductive channel) size in the testing apparatus 100 can be optimized based on parameters such as via width and via pitch / via space. For example, increasing the via width can reduce the resistance of the conductive channel and improve filling performance, but it will occupy more chip area; while increasing the via pitch can reduce the risk of short circuits, but it will increase the occupied chip area. In this embodiment, the via pitch refers to the distance between the centers of two adjacent vias, such as... Figure 5 In D1, the through-hole width refers to the diameter of the through-hole on the plane, for example... Figure 5 D2 in the middle.

[0042] Table 1 below shows the via widths of multiple vias and several parameters between adjacent vias in a 28nm SRAM device measured at 128 nm, including X0 (via width), X1 (first horizontal distance between adjacent vias), X2 (second horizontal distance between adjacent vias), Y1 (first vertical distance between adjacent vias), and Y2 (second vertical distance between adjacent vias). While there are differences in via dimensions between different SRAM devices, they all fall within the same range.

[0043] Table 1: Test results of via spacing and width in SRAM

[0044]

[0045] Furthermore, Figure 3 Only one embodiment is shown where multiple pads 170 share a common conductive layer. However, it will be understood that as the number of conductive channel layers and the number of layers in a routing layer increases, situations may arise where one pad is connected to the same conductive layer as some other pads, and this pad is connected to another conductive layer along with other pads. For example, Figure 3 Both pad 170-2 and pad 170-3 are connected to the first conductive layer 130-2; in other embodiments, pad 170-3 and pad 170-4 may be connected to the same second conductive layer 150-3.

[0046] refer to Figure 2 In the testing method for semiconductor structures disclosed in this application, the semiconductor structure and the aforementioned testing apparatus are formed simultaneously. The testing apparatus has the same structural features as the semiconductor structure, including a ground terminal, multiple pads, multiple conductive channels, and multiple conductive layers, with at least two conductive channels of the same layer connected to the same conductive layer. The testing apparatus is used to perform the testing method described below. (Reference) Figure 2 and Figure 3 The testing method for semiconductor structures in this application includes the following steps.

[0047] Step S01: Apply test voltages to multiple pads respectively, and obtain multiple first current-voltage curves between the pads and the ground terminal of the test device.

[0048] In this step, refer to Figure 3First, a test voltage is applied to pad 170-1 (the pad connected to conductive Line 1) via wire 180, and then a first current-voltage curve is obtained between pad 170-1 and the ground terminal of the test device 100 (the terminal connected to the first doped region 101 in the substrate 110). Then, a test voltage is applied to pad 170-2 (the pad connected to conductive Line 2) via wire 180, and then a first current-voltage curve is obtained between pad 170-2 and the ground terminal of the test device 100. The above steps are repeated until the first current-voltage curves between all pads 170 and the ground terminal are obtained.

[0049] The test voltage is the scanning voltage from 0 to the power supply voltage VDD. That is, when acquiring the first current-voltage curve, the test voltage applied to the pad 170 increases from 0 until it reaches the power supply voltage VDD, thereby obtaining a first current-voltage curve that changes with voltage.

[0050] In the first current-voltage curve, the presence of defects such as short circuits or open circuits between the corresponding pads and the ground terminal can be determined based on the change in current with voltage. If such defects are found, the semiconductor structure process can be adjusted in a timely manner, thereby improving the yield of the subsequently formed semiconductor structure. Specifically, in the change of current with voltage, if the current increases linearly with the increase of voltage, the current path corresponding to the current-voltage curve is normal, that is, the circuit structure between the pads and the first doped region 101 of the test structure is normal; if the current increases rapidly with the increase of voltage, the current path corresponding to the current-voltage curve is abnormal and a short circuit exists, that is, the circuit structure between the pads and the first doped region 101 of the test structure has a short circuit; if the current remains at 0 or close to 0 with the increase of voltage, the current path corresponding to the current-voltage curve is abnormal and an open circuit exists, that is, the circuit structure between the pads and the first doped region 101 of the test structure has an open circuit.

[0051] Step S02: Obtain at least one pad group based on the plurality of first current-voltage curves.

[0052] In this step, the target pad is determined based on the relationship between current and voltage in multiple first current-voltage curves; then it is determined whether the target pad and other pads are connected to the same conductive layer. If so, at least two pads connected to the same conductive layer form a pad group. Figure 3 For example, pads 170-2 and 170-3 form a pad group; pads 170-4, 170-5, and 170-6 form a pad group.

[0053] The target pad is, for example, the pad whose current changes abnormally with voltage in the corresponding first current-voltage curve. In other embodiments, multiple pad groups can be first formed based on the connection relationship between the pads 170 and the same conductive layer, and then the required pad group can be selected from the multiple pad groups according to the target pad.

[0054] In this embodiment, since the pad group is identified based on the target pad, at least one target pad exists in each pad group. Furthermore, a target pad is located in at least one pad group, and at least one pad differs between different pad groups. Figure 3 As shown, pad 170-4 can be located in two pad groups because it is connected to the first conductive layer 130-3 and the second conductive layer 150-4 together with other pads. One pad group has pad 170-6 and the other does not.

[0055] Step S03: Apply test voltages to multiple pad groups respectively and obtain second current-voltage curves for multiple pad groups, wherein the pad group is at least two pads connected to the same conductive layer.

[0056] In this step, a test voltage is first applied to one target pad in a pad group, while the other pads are grounded. Then, a second current-voltage curve is obtained between the target pad and at least one grounded pad in the pad group. The target pad is replaced, and the step of obtaining the second current-voltage curve is repeated until at least one second current-voltage curve is obtained for all target pads in the pad group. The pad group is then replaced, and the above steps of obtaining the second current-voltage curve are repeated.

[0057] In the second current-voltage curve, if the current increases linearly with the increase of voltage, then the current path corresponding to the current-voltage curve is normal, that is, the circuit structure between the target pad and the ground pad is normal; if the current increases rapidly with the increase of voltage, then the current path corresponding to the current-voltage curve is abnormal and there is a short circuit, that is, there is a short circuit in the circuit structure between the target pad and the ground pad; if the current remains 0 or close to 0 with the increase of voltage, then the current path corresponding to the current-voltage curve is abnormal and there is an open circuit, that is, there is an open circuit in the circuit structure between the target pad and the ground pad.

[0058] Step S04: Detect the second current-voltage curve and the first current-voltage curve of the corresponding pad, and determine the location of the defect in the semiconductor structure based on the detection results.

[0059] In this step, the location of defects in the semiconductor structure is determined based on the changes in current with voltage in the second current-voltage curve and the first current-voltage curve of the corresponding pad.

[0060] Specifically, if the second current-voltage curve of the target pad is abnormal, the defect location is between the target pad and the conductive layer jointly connected to the target pad and the ground pad corresponding to the second current-voltage curve; if the second current-voltage curve of the target pad is normal, the defect location is between the conductive layer jointly connected to the target pad and the ground pad corresponding to the second current-voltage curve and the ground terminal of the test device. Figure 3 As shown, if the first current-voltage curve of pad 170-2 is abnormal, then pad 170-2 is the target pad. When the second current-voltage curve between pad 170-2 and pad 170-3 is normal, it indicates that the circuit structure above the first conductive layer 130-2 is normal. The reason for the abnormal first current-voltage curve of pad 170-2 is located in the first conductive channel 120-2 below the first conductive layer 130-2. When the second current-voltage curve between pad 170-2 and pad 170-3 is abnormal, it indicates that the circuit structure above the first conductive layer 130-2 is abnormal. The reason for the abnormal first current-voltage curve of pad 170-2 is located between the second conductive channel 140-2, the second conductive layer 150-2, and the third conductive channel 160-2 above the first conductive layer 130-2.

[0061] The testing method and apparatus for semiconductor structures provided in this application, which are formed synchronously with the semiconductor structure in the chip, test the wiring layers in the testing apparatus by applying different voltages to the pads of the testing apparatus in sequence, thereby obtaining multiple current / voltage curves. The current represents the current between the corresponding pad and the ground terminal when the voltage is applied. The current / voltage curves are used to determine whether an open circuit exists between the pad and the ground terminal in the testing apparatus. If an open circuit exists, there will be no current or the current will always be close to 0, regardless of the voltage applied. This detection method can quickly detect open circuit problems in the semiconductor structure, allowing for timely adjustments to the semiconductor process and reducing defects in the semiconductor structure.

[0062] Furthermore, after sequentially acquiring the current / voltage curves between each pad and the ground terminal in the test device, the method further includes applying a first voltage and a second voltage to two adjacent / arbitrary pads (the two pads are connected to the same conductive layer in the test device) to obtain the current / voltage curves between the two pads. The method then determines whether an open circuit occurs between the two pads based on the change in current versus voltage. If the current / voltage curve between one of the two adjacent pads indicates an open circuit between that pad and the ground terminal, and the current between the two adjacent pads remains close to 0, then the open circuit occurs between the pad and the shared conductive layer.

[0063] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a semiconductor structure, said semiconductor structure and a testing device being formed in synchronism, each comprising a ground terminal, a plurality of pads, a plurality of conductive levels and a plurality of conductive layers in a substrate, said conductive levels connecting two adjacent conductive layers, said pads being connected to a conductive layer remote from said substrate via said conductive levels, at least two of said conductive layers of the same level being connected to an adjacent conductive layer via said conductive levels, wherein, The test method comprises: applying a test voltage to each of a plurality of pads and obtaining a plurality of first current-voltage curves between the pads and a ground terminal of the test device; applying a test voltage to each of a plurality of pad groups and obtaining a plurality of second current-voltage curves of the pad groups, the pad group being at least two pads connected to the same conductive layer; detecting the second current-voltage curves and the first current-voltage curves of the corresponding pads, and determining the defect position in the semiconductor structure according to the detection result.

2. The test method of claim 1, wherein, The test voltage is a scanning voltage from 0 to a power supply voltage.

3. The test method of claim 2, wherein, The step of applying a test voltage to each of a plurality of pad groups and obtaining a plurality of second current-voltage curves of the pad groups, the pad group being at least two pads connected to the same conductive layer, comprises: applying a test voltage to a target pad in the pad group and grounding the other pads, and obtaining a second current-voltage curve between the target pad and at least one grounded pad; repeating the step of obtaining a second current-voltage curve until at least one second current-voltage curve of all target pads is obtained.

4. The test method of claim 3, wherein, In the first current-voltage curves and the second current-voltage curves, if the current increases linearly with the increase of the voltage, the current path corresponding to the current-voltage curve is normal; if the current increases instantaneously beyond a threshold value with the increase of the voltage, the current path corresponding to the current-voltage curve is abnormal, and there is a short circuit; if the current remains 0 or close to 0 with the increase of the voltage, the current path corresponding to the current-voltage curve is abnormal, and there is an open circuit.

5. The test method of claim 4, wherein, Between the step of applying a test voltage to each of a plurality of pads and obtaining a plurality of first current-voltage curves between the pads and a ground terminal of the test device, and the step of applying a test voltage to each of a plurality of pad groups and obtaining a plurality of second current-voltage curves of the pad groups, the step further comprises: obtaining at least one pad group according to the plurality of first current-voltage curves.

6. The test method of claim 5, wherein, The step of obtaining at least one pad group according to the plurality of first current-voltage curves comprises: determining a target pad according to the relationship between the current and the voltage in the plurality of first current-voltage curves; determining whether the target pad and the other pads are connected to the same conductive layer, and if so, at least two pads connected to the same conductive layer form a pad group.

7. The test method of claim 6, wherein, The target pad is the pad corresponding to the abnormal change of the current with the voltage in the first current-voltage curve.

8. The test method of claim 4, wherein, In the step of detecting the second current-voltage curves and the first current-voltage curves of the corresponding pads, and determining the defect position in the semiconductor structure according to the detection result, if the second current-voltage curve of the target pad is abnormal, the defect position is located between the target pad and the conductive layer to which the target pad and the ground pad corresponding to the second current-voltage curve are commonly connected; if the second current-voltage curve of the target pad is normal, the defect position is located between the conductive layer to which the target pad and the ground pad corresponding to the second current-voltage curve are commonly connected and the ground terminal of the test device.

9. The test method of claim 6, wherein, One of the target pads is located in at least one pad group, at least one pad of different pad groups being different.

10. A test device for a semiconductor structure, the test device being formed in synchronism with the semiconductor structure, having the same structural features as the semiconductor structure, wherein, The test device is for performing a test method as claimed in any of claims 1 to 9.

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