Alignment structure, semiconductor structure, and method of manufacturing a semiconductor structure

Abstract

The application belongs to the field of semiconductor manufacturing, and particularly relates to an alignment structure, a semiconductor structure and a manufacturing method of the semiconductor structure. The alignment structure is arranged on a substrate, and comprises a plurality of first parts arranged at intervals along a first direction and a second part connected between adjacent first parts. The first part comprises a bottom layer and a pattern layer on the bottom layer, the pattern layer comprises a plurality of strip patterns arranged at intervals, the plurality of strip patterns are arranged in an array along a second direction, the height of the second part relative to the substrate is less than the height of the bottom layer relative to the substrate, and the interval between adjacent first parts is greater than the interval between adjacent strip patterns in the first part. The interval between adjacent first parts is greater than the interval between adjacent strip patterns in the first part, that is, a large groove structure is formed between adjacent first parts. Through the design, the contrast of the formed mark pattern is improved, and the overlay error in the semiconductor manufacturing process is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor manufacturing, and particularly relates to an alignment structure, a semiconductor structure and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] In the semiconductor manufacturing process, the exposed and developed pattern (i.e. the current layer) must be aligned with the existing pattern (i.e. the previous layer) on the wafer substrate to ensure the correct connection between devices. The relative position between the exposed pattern and the previous layer is called overlay error. Too large overlay error will cause short circuit or open circuit of the device, affecting the product yield. Through the measurement and analysis of the alignment mark, the lithography system can compensate for the overlay error caused by the previous process.

[0003] With the further reduction of the size of the semiconductor structure, in order to increase the integration density of the semiconductor structure, self-aligned double patterning, self-aligned quadruple patterning and other processes are introduced into the manufacturing process of the semiconductor structure.

[0004] However, under the self-aligned double patterning and self-aligned quadruple patterning processes, the standard mark cannot be formed, and the contrast of the formed mark pattern is poor, which leads to the inability of the lithography system or detection device to accurately identify the mark, and further leads to the increase of the overlay error. SUMMARY

[0005] The purpose of the present application is to provide an alignment structure, a semiconductor structure and a manufacturing method of the semiconductor structure, so as to improve the contrast of the formed mark pattern and reduce the overlay error in the semiconductor manufacturing process.

[0006] In order to achieve the above purpose, the present application provides an alignment structure arranged on a substrate, the alignment structure comprising:

[0007] a plurality of first parts arranged at intervals along a first direction and a second part connected between adjacent first parts;

[0008] The first part comprises a bottom layer and a pattern layer located on the bottom layer, the outer contour of the orthographic projection of the pattern layer on the substrate coincides with the orthographic projection of the bottom layer on the substrate, the pattern layer comprises a plurality of strip patterns arranged at intervals, and a plurality of the strip patterns are arranged in an array along a second direction, the included angle between the second direction and the first direction being 90±5°;

[0009] The height of the second part relative to the substrate is less than the height of the bottom layer relative to the substrate, and the interval between adjacent first parts is greater than the interval between adjacent strip patterns in the first part.

[0010] Optionally, the second portion has a planar surface away from the substrate.

[0011] Optionally, the height difference between the bottom layer and the second portion is greater than or equal to 100 nanometers.

[0012] Optionally, the alignment structure further comprises an etching stop layer, the etching stop layer is located between the bottom layer and the pattern layer and continuously extends between the bottom layer and at least two adjacent strip patterns in the pattern layer, the material of the etching stop layer is different from the material of the pattern layer and the second portion.

[0013] Optionally, the strip patterns extend along a third direction, the third direction intersects the first direction, the first direction, the second direction and the third direction are parallel to the substrate.

[0014] In the plurality of strip patterns: two adjacent strip patterns successively form a pattern pair, the etching stop layer continuously extends between the pattern pair and the bottom layer and discontinuously extends between adjacent pattern pairs, and a gap between adjacent pattern pairs extends to the bottom layer.

[0015] Optionally, the alignment structure further comprises a metal film layer, the metal film layer covers all surfaces of the first portion and the second portion away from the substrate.

[0016] Optionally, the height difference between the area covered by the metal film layer on the first portion and the area covered by the metal film layer on the second portion relative to the substrate is greater than or equal to 150 nanometers.

[0017] Optionally, the metal film layer fills the gap between adjacent strip patterns in the pattern layer.

[0018] Optionally, the area covered by the metal film layer on the second portion has a planar surface away from the substrate.

[0019] The application further provides a semiconductor structure comprising a substrate and the alignment structure disposed on the substrate.

[0020] The application further provides a method for manufacturing a semiconductor structure, comprising:

[0021] providing a substrate, the substrate comprising a substrate and a to-be-etched material layer on the substrate, and a first region and a second region are divided on the to-be-etched material layer, the first region is arranged at intervals along a first direction, and the second region is connected between adjacent first regions;

[0022] forming a patterned mask layer on a side of the material layer to be etched away from the substrate, the patterned mask layer partially covers the first region and exposes the second region, the patterned mask layer on the first region comprises a plurality of first hard masks arranged at intervals, the plurality of first hard masks on the first region are arranged in a second direction, an angle between the second direction and the first direction is 90±5°, a projection of the plurality of first hard masks on the first region on the material layer to be etched is coincident with the first region, a distance between adjacent first hard masks on the first region is less than a distance between adjacent first regions;

[0023] performing first anisotropic etching on the material layer to be etched with the patterned mask layer as a mask, a first region of the material layer to be etched forms a first part, a second region of the material layer to be etched forms a second part, the first part comprises a bottom layer and a pattern layer on the bottom layer, the pattern layer comprises a plurality of strip patterns arranged at intervals, the first hard mask shields a region of the material layer to be etched to form the strip pattern, a height of the second part relative to the substrate is less than a height of the bottom layer relative to the substrate.

[0024] Optionally, the first hard mask extends in a third direction, the third direction intersects the first direction, the first direction, the second direction and the third direction are all parallel to the substrate.

[0025] of the first hard masks in the first region: two adjacent first hard masks successively form a mask pair, the patterned mask layer further comprises a second hard mask between the mask pair and the material layer to be etched, the second hard mask corresponds to the mask pair one by one, an outer contour of a projection of the mask pair on the substrate is coincident with a projection of the second hard mask on the substrate.

[0026] Optionally, a method for forming the patterned mask layer comprises:

[0027] forming a second hard mask material layer and a mandrel material layer successively on a side of the material layer to be etched away from the substrate, patterning the mandrel material layer to form a plurality of mandrel patterns, the plurality of mandrel patterns on the first region extend in the third direction and are arranged in the second direction;

[0028] forming a first hard mask material layer conformally on the patterned mandrel material layer and the second hard mask material layer, performing a second anisotropic etching on the first hard mask material layer, removing the first hard mask material layer outside a certain distance from both sides of the mandrel pattern, and remaining the first hard mask material layer within the certain distance from both sides of the mandrel pattern to form the first hard mask, two first hard masks belonging to the same mask pair are formed on both sides of the same mandrel pattern;

[0029] performing a third anisotropic etching on the second hard mask material layer with the mandrel pattern and the first hard mask as masks, and remaining the second hard mask material layer to form a plurality of second hard masks, the third anisotropic etching also removes the mandrel pattern.

[0030] Optionally, the material layer to be etched includes a first material layer, an etching stop layer and a second material layer stacked in sequence on the substrate, and the etching rate of the first material layer and the second material layer is greater than the etching rate of the etching stop layer in the first anisotropic etching.

[0031] Optionally, the first anisotropic etching includes a first etching, a second etching and a third etching performed in sequence.

[0032] The first etching removes the exposed part of the second material layer, transfers the pattern of the patterned second hard mask material layer to the second material layer, and stops at the etching stop layer.

[0033] The second etching removes part of the exposed second hard mask material layer, transfers the pattern of the patterned first hard mask material layer to the second hard mask material layer, and at least removes the etching stop layer exposed by the second hard mask in the second region, and stops at the second material layer.

[0034] The third etching removes the exposed part of the first material layer and the second material layer, and transfers the pattern of the patterned second hard mask material layer to the first material layer and the second material layer.

[0035] Optionally, the method for manufacturing the semiconductor structure includes:

[0036] After performing the first anisotropic etching, the remaining patterned mask layer is removed.

[0037] A metal film layer is formed on the side of the patterned material layer to be etched away from the substrate, and the metal film layer covers all surfaces of the first part and the second part away from the substrate.

[0038] The alignment structure, the semiconductor structure and the manufacturing method of the semiconductor structure disclosed in the present application have the following advantages:

[0039] In the present application, the alignment structure is arranged on a substrate, the alignment structure comprises a plurality of first parts arranged at intervals along a first direction and a second part connected between adjacent first parts, the first part comprises a bottom layer and a pattern layer on the bottom layer, an outer contour of a normal projection of the pattern layer on the substrate coincides with a normal projection of the bottom layer on the substrate, the pattern layer comprises a plurality of strip patterns arranged at intervals, the plurality of strip patterns are arranged in an array along a second direction, the height of the second part relative to the substrate is less than the height of the bottom layer relative to the substrate, and the interval between adjacent first parts is greater than the interval between adjacent strip patterns in the first part. Thus, a deep groove structure is formed between adjacent first parts, which is designed to improve the contrast of the formed mark pattern and is conducive to reducing overlay errors in the semiconductor manufacturing process.

[0040] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0041] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0042] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present application, and together with the specification serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0043] Figure 1 is a plan view of an alignment mark in an embodiment of the present application.

[0044] Figure 2 is a plan view of an alignment structure in an embodiment of the present application.

[0045] Figure 3 is Figure 2 is a schematic view of the A-A cross section of the alignment structure in

[0046] Figure 4 is a schematic view of an alignment structure comprising a metal film layer in an embodiment of the present application.

[0047] Figure 5 is a flowchart of a manufacturing method of a semiconductor structure in an embodiment of the present application.

[0048] Figure 6 is a schematic view of forming a patterned photoresist layer in an embodiment of the present application.

[0049] Figure 7 This is a schematic diagram of the patterned mandrel material layer in an embodiment of this application.

[0050] Figure 8 This is a schematic diagram of the formation of the first hard mask material layer in an embodiment of this application.

[0051] Figure 9 This is a schematic diagram of the patterned first hard mask material layer in an embodiment of this application.

[0052] Figure 10 This is a schematic diagram of the patterned second hard mask material layer in an embodiment of this application.

[0053] Figure 11 This is a schematic diagram of the patterned first material layer in an embodiment of this application.

[0054] Figure 12 This is a schematic diagram of etching the second hard mask material layer in an embodiment of this application.

[0055] Explanation of reference numerals in the attached figures:

[0056] 100. Base;

[0057] 200. Material layer to be etched; 210. First material layer; 211. Bottom layer; 220. Etching stop layer; 230. Second material layer; 230a. Pattern pair; 231. Strip pattern; 201. First part; 202. Second part; 203. Trench structure; 204. Submerged groove; 20. Alignment structure;

[0058] 300. Patterned mask layer; 310. First hard mask material layer; 311. First hard mask; 320. Second hard mask material layer; 321. Second hard mask; 3211. Strip mask;

[0059] 400. Mandrel material layer; 410. Mandrel pattern;

[0060] 500. Metallic film layer;

[0061] 600, photoresist layer. Detailed Implementation

[0062] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0063] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0064] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0065] See Figures 1 to 3 As shown, in this embodiment, the alignment structure 20 is disposed on the substrate 100. The alignment structure 20 includes a plurality of alignment structures along a first direction ( Figure 2 A first portion 201 and a second portion 202 are arranged at intervals in the second direction (x-direction) and connected between adjacent first portions 201. The first portion 201 includes a base layer 211 and a pattern layer on the base layer 211, the outer contour of the orthographic projection of the pattern layer onto the substrate 100 coinciding with the orthographic projection of the base layer 211 onto the substrate 100. The pattern layer includes a plurality of spaced-apart strip patterns 231, the plurality of strip patterns 231 being arranged along a second direction (x-direction). Figure 2 The array is set in the middle (y direction), and the angle between the second direction and the first direction is 90±5°. That is to say, the orthographic projection of the strip pattern 231 and the area between adjacent strip patterns 231 on the substrate 100 coincides with the orthographic projection of the bottom layer 211 on the substrate 100.

[0066] It should be noted that the extension direction of the bar pattern 231 can be any direction extending along the surface of the substrate 100, such as the angle between the bar pattern 231 and the first direction is 0° to 45°; the bar pattern 231 can be a straight line or a curve; the bar pattern 231 can be part of other complete patterns, such as the bar pattern 231 being part of a rectangular, circular or elliptical pattern; this application does not make any specific limitations.

[0067] The height of the second part 202 relative to the substrate 100 is less than the height of the bottom layer 211 relative to the substrate 100, and the spacing between adjacent first parts 201 is greater than the spacing between adjacent strip patterns 231 in the first part 201. It can be understood that the height refers to the spacing between the surface of the film layer away from the substrate 100 and the substrate 100.

[0068] See Figure 1As shown, one alignment mark can include four alignment structures 20 arranged in a rectangular region on the substrate 100. Among them, the first alignment structure 20 and the second alignment structure 20 are arranged at the upper left corner and the lower right corner of the rectangular region respectively, and the first parts 201 in the first alignment structure 20 and the second alignment structure 20 are arranged in the second direction; the third alignment structure 20 and the fourth alignment structure 20 are arranged at the upper right corner and the lower left corner of the rectangular region respectively, and the first parts 201 in the third alignment structure 20 and the fourth alignment structure 20 are arranged in the first direction. The first part 201 and the second part 202 of the alignment structure 20 are alternately arranged in intervals to form a grating structure, and the alignment mark is a grating-shaped standard mark.

[0069] In the embodiment, the alignment structure 20 is arranged on the substrate 100, the alignment structure 20 includes a plurality of first parts 201 arranged in the first direction and a second part 202 connected between adjacent first parts 201, the first part 201 includes a bottom layer 211 and a pattern layer on the bottom layer 211, the outer contour of the orthographic projection of the pattern layer on the substrate 100 coincides with the orthographic projection of the bottom layer 211 on the substrate 100, the pattern layer includes a plurality of strip patterns 231 arranged in the second direction, the height of the second part 202 relative to the substrate 100 is less than the height of the bottom layer 211 relative to the substrate 100, and the distance between adjacent first parts 201 is greater than the distance between adjacent strip patterns 231 in the first part 201. Thus, a deep groove structure 203 is formed between adjacent first parts 201. This design improves the contrast of the formed mark pattern and is beneficial to reduce the overlay error in the semiconductor manufacturing process.

[0070] In some embodiments, the side of the second part 202 away from the substrate 100 is a plane, that is, the top surface of the second part 202 is a plane. It can be understood that the top surface being a plane means that the curvature of the top surface is within an allowable range.

[0071] The side of the second part 202 away from the substrate 100 is a plane, which can reduce the noise of the bottom surface of the groove structure 203 and improve the contrast of the mark pattern.

[0072] In some embodiments, the height difference between the bottom layer 211 and the second part 202 is greater than or equal to 100 nanometers. The height of the bottom layer 211 is the distance between the side of the bottom layer 211 away from the substrate 100 and the substrate 100, and the height of the second part 202 is the distance between the side of the second part 202 away from the substrate 100 and the substrate 100.

[0073] The height difference between the bottom layer 211 and the second part 202 is greater than or equal to 100 nanometers, which can improve the contrast of the formed mark pattern and reduce the overlay error in the semiconductor manufacturing process.

[0074] In some embodiments, the alignment structure 20 further includes an etch stop layer 220, which is located between the bottom layer 211 and the pattern layer and extends continuously between at least two adjacent strip patterns 231 in the pattern layer and the bottom layer 211. The material of the etch stop layer 220 is different from the material of the pattern layer and the second portion 202, and the material of the bottom layer 211 and the second portion 202 may be the same as or different. That is, there is etch selectivity among the etch stop layer 220, the pattern layer and the second portion 202.

[0075] The material of the etching stop layer 220 is different from that of the pattern layer and the second part 202. When etching to form the bottom layer 211 and the second part 202, a large height difference can be formed between the second part 202 and the bottom layer 211.

[0076] In some embodiments, the etch stop layer 220 may be integrally and continuously formed between the bottom layer 211 and the pattern layer, or it may be broken between some of the strip patterns 231.

[0077] In some embodiments, the strip pattern 231 is along a third direction ( Figure 2 The first direction (z-direction) extends, and the third direction intersects the first direction. The first direction, the second direction, and the third direction are all parallel to the base 100. It should be noted that the strip pattern 231 can extend along the third direction, but is not limited to this. The strip pattern 231 can also extend along the first direction or the second direction, depending on the situation.

[0078] In the patterned layer, among the multiple strip patterns 231: two adjacent strip patterns 231 sequentially form a pattern pair 230a; an etch stop layer 220 extends continuously between the pattern pair 230a and the bottom layer 211 and is interrupted between adjacent pattern pairs 230a; the gap between adjacent pattern pairs 230a extends into the bottom layer 211. That is, there is an etch stop layer 220 below the two strip patterns 231 in the pattern pair 230a, and below the gap between the two strip patterns 231 in the pattern pair 230a; there is no etch stop layer 220 below the gap between adjacent pattern pairs 230a, and the gap between adjacent pattern pairs 230a extends into the bottom layer 211. Figure 2 The structure shown is such that the bottom surface of the sinkhole 204 is at a greater height than the base 100 than the top surface of the second part 202 (i.e., the bottom surface of the trench structure 203) is at a greater height than the base 100.

[0079] When the alignment structure 20 is formed by a self-alignment double patterning or a self-alignment quadruple patterning process, a pattern pair 230a is formed, and when the trench structure 203 is etched, a sunken groove 204 is formed between adjacent pattern pairs 230a and extends to the bottom layer 211. The width of the sunken groove 204 is smaller than the trench structure 203 formed between adjacent first portions 201, and the depth of the sunken groove 204 is smaller than the depth of the trench structure 203, which does not affect the identification of the mark by the photolithography system or detection equipment.

[0080] In some embodiments, referring to Figure 4 As shown, the alignment structure 20 further includes a metal film layer 500 covering the entire surface of the first portion 201 and the second portion 202 away from the substrate 100.

[0081] The metal film layer 500 covers the first portion 201 and the second portion 202 at the same time, forming a grating structure following the ups and downs of the first portion 201 and the second portion 202, and improving the contrast of the formed mark pattern.

[0082] In some embodiments, the thickness of the area covered by the metal film layer 500 on the first portion 201 and the area covered by the metal film layer 500 on the second portion 202 is equal or approximately equal. Since the height of the first portion 201 is greater than the height of the second portion 202, the height difference of the area covered by the metal film layer 500 on the first portion 201 and the area covered by the metal film layer 500 on the second portion 202 relative to the substrate 100 is greater than or equal to 150 nanometers.

[0083] The metal film layer 500 is opaque, the height of the area covered by the metal film layer 500 on the first portion 201 is greater than the height of the area covered by the metal film layer 500 on the second portion 202, and the height difference between the two is greater than or equal to 150 nanometers, which can improve the contrast of the formed mark pattern and is beneficial to reduce the overlay error in the semiconductor manufacturing process.

[0084] In some embodiments, the metal film layer 500 fills the gap between adjacent strip patterns 231 in the pattern layer. The area covered by the metal film layer 500 on the first portion 201 is a plane away from the substrate 100, i.e., the top surface of the area covered by the metal film layer 500 on the first portion 201 is a plane.

[0085] The top surface of the area covered by the metal film layer 500 on the first portion 201 is a plane, which can reduce the noise of the top surface of the area covered by the metal film layer 500 on the first portion 201 and improve the contrast of the mark pattern.

[0086] In some embodiments, the area covered by the metal film layer 500 on the second portion 202 is a plane away from the substrate 100, i.e., the top surface of the area covered by the metal film layer 500 on the second portion 202 is a plane.

[0087] The metal film layer 500 covers the top surface of the second part 202, and the top surface is a plane, which can reduce the noise of the bottom surface of the trench structure 203 and improve the contrast of the mark pattern.

[0088] The application also provides a semiconductor structure, which comprises a substrate 100 and an alignment structure 20 arranged on the substrate 100.

[0089] The semiconductor structure comprises the alignment structure 20, and the alignment structure 20 comprises a plurality of first parts 201 arranged at intervals along a first direction and a second part 202 connected between adjacent first parts 201. The first part 201 comprises a bottom layer 211 and a pattern layer located on the bottom layer 211. The outer contour of the orthographic projection of the pattern layer on the substrate 100 coincides with the orthographic projection of the bottom layer 211 on the substrate 100. The pattern layer comprises a plurality of strip patterns 231 arranged at intervals. The plurality of strip patterns 231 are arranged in an array along a second direction. The height of the second part 202 relative to the substrate 100 is less than the height of the bottom layer 211 relative to the substrate 100. The interval between adjacent first parts 201 is greater than the interval between adjacent strip patterns 231 in the first part 201. Thus, a trench structure 203 with a large depth is formed between adjacent first parts 201. This design improves the contrast of the formed mark pattern and is beneficial to reducing overlay errors in the semiconductor manufacturing process.

[0090] The application also provides a manufacturing method of a semiconductor structure, as shown in Figures 5 to 12 The manufacturing method of the semiconductor structure comprises the following steps.

[0091] S100: providing a substrate, which comprises a substrate 100 and a to-be-etched material layer 200 located on the substrate 100. The to-be-etched material layer 200 is divided into first regions arranged at intervals along a first direction and second regions connected between adjacent first regions.

[0092] S200: forming a patterned mask layer 300 on the side of the to-be-etched material layer 200 away from the substrate 100. The patterned mask layer 300 partially covers the first regions and exposes the second regions. The part of the patterned mask layer 300 located in the first region comprises a plurality of first hard masks 311 arranged at intervals. The plurality of first hard masks 311 in the first region are arranged in an array along a second direction. The angle between the second direction and the first direction is 90±5°. The outer contour of the orthographic projection of the plurality of first hard masks 311 on the to-be-etched material layer 200 coincides with the first region, that is, the orthographic projection of the region between adjacent first hard masks 311 on the to-be-etched material layer 200 coincides with the first region. The interval between adjacent first hard masks 311 in the first region is less than the interval between adjacent first regions.

[0093] S300: performing first anisotropic etching on the to-be-etched material layer 200 by taking the patterned mask layer 300 as a mask, a first region of the to-be-etched material layer 200 forms a first part 201, and a second region of the to-be-etched material layer 200 forms a second part 202, the first part 201 includes a bottom layer 211 and a pattern layer located on the bottom layer 211, the pattern layer includes a plurality of spaced strip patterns 231, the first hard mask 311 shields the region of the to-be-etched material layer 200 to form the strip pattern 231, and the height of the second part 202 relative to the substrate 100 is less than the height of the bottom layer 211 relative to the substrate 100.

[0094] The distance between adjacent first hard masks 311 is less than the distance between adjacent first regions, and the etching load of the first region and the etching load of the second region are different when etching the to-be-etched material layer 200, so that a groove structure 203 with a larger depth can be formed between adjacent first parts 201, the process is simple, the contrast of the formed mark pattern is improved, and the overlay error in the semiconductor structure manufacturing process is reduced.

[0095] In some embodiments, the first hard mask 311 extends along a third direction intersecting the first direction, and the first direction, the second direction and the third direction are all parallel to the substrate 100. Among the plurality of first hard masks 311 in the first region: adjacent two first hard masks 311 successively form a mask pair, the patterned mask layer 300 further includes a second hard mask 321 located between the mask pair and the to-be-etched material layer 200, the second hard mask 321 corresponds to the mask pair one by one, and the outer contour of the orthographic projection of the mask pair on the substrate 100 coincides with the orthographic projection of the second hard mask 321 on the substrate 100. That is, the orthographic projection of the two first hard masks 311 belonging to the same mask pair and the region therebetween on the substrate 100 coincides with the orthographic projection of the second hard mask 321 on the substrate 100.

[0096] The patterned mask layer 300 further includes a second hard mask 321 located between the mask pair and the to-be-etched material layer 200, and the to-be-etched material layer 200 is etched by using two layers of masks, the height difference between the bottom layer 211 and the second part 202 can be increased, thereby improving the contrast of the formed mark pattern, and reducing the overlay error in the semiconductor manufacturing process.

[0097] In some embodiments, the patterned mask layer 300 can be formed by using a self-aligned double patterning or a self-aligned quadruple patterning process. Specifically, the method for forming the patterned mask layer 300 includes:

[0098] A second hard mask material layer 320 and a mandrel material layer 400 are sequentially formed on a side of the material layer 200 to be etched away from the substrate 100, and a patterned photoresist layer 600 is formed on a side of the mandrel material layer 400 away from the substrate 100, so as to pattern the mandrel material layer 400 to form a plurality of mandrel patterns 410, the plurality of mandrel patterns 410 in the first region extending along the third direction and being arranged in an array along the second direction;

[0099] A first hard mask material layer 310 is conformally formed on the patterned mandrel material layer 400 and the second hard mask material layer 320, and a second anisotropic etching is performed on the first hard mask material layer 310, so as to remove a portion of the first hard mask material layer 310 away from the substrate 100 on a side of the mandrel pattern 410 and on both sides of the mandrel pattern 410 (parallel to the substrate 100), and a remaining portion of the first hard mask material layer 310 within a certain distance on both sides of the mandrel pattern 410 forms a first hard mask 311, and two first hard masks 311 in the same mask pair are formed on both sides of the same mandrel pattern 410.

[0100] The mandrel pattern 410 and the first hard mask 311 are used as masks to perform a third anisotropic etching on the second hard mask material layer 320, and a remaining portion of the second hard mask material layer 320 forms a plurality of second hard masks 321, and the third anisotropic etching also removes the mandrel pattern 410.

[0101] The self-aligned double patterning or self-aligned quadruple patterning process can break through the physical limit of the photolithography technology in a relatively economical manner, and realize higher resolution pattern preparation.

[0102] In some embodiments, the material layer 200 to be etched includes a first material layer 210, an etching stop layer 220, and a second material layer 230 sequentially stacked on the substrate 100. The first material layer 210 and the second material layer 230 have etching selectivity with the etching stop layer 220, and the etching rates of the first material layer 210 and the second material layer 230 are both greater than the etching rate of the etching stop layer 220 in the first anisotropic etching.

[0103] The material layer 200 to be etched includes the etching stop layer 220, which is used to stop etching the first material layer 210 when the first material layer 210 and the second material layer 230 are etched, so as to form a large height difference between the second portion 202 and the bottom layer 211.

[0104] In some embodiments, the first anisotropic etching includes a first etching, a second etching and a third etching performed in sequence. It can be understood that the first etching, the second etching and the third etching are all anisotropic etching. The first etching removes the exposed part of the second material layer 230, transfers the pattern of the patterned second hard mask material layer 320 to the second material layer 230, and stops at the etching stop layer 220. In the process of etching the second material layer 230, the first hard mask material layer 310 is partially etched, and the height of the first hard mask 311 is reduced.

[0105] The second etching removes part of the exposed second hard mask material layer 320, transfers the pattern of the patterned first hard mask material layer 310 to the second hard mask material layer 320, and each second hard mask 321 is etched into two strip-shaped masks 3211. The second etching also removes at least the etching stop layer 220 of the second region exposed by the second hard mask 321, and stops at the second material layer 230. The second etching stop layer 220 of the first region between the second hard masks 321 is partially etched when the etching stop layer 220 of the second region is completely etched due to different etching loads. In the process of performing the second etching or after the second etching, the remaining first hard mask material layer 310 is completely etched and removed.

[0106] The third etching removes the exposed part of the first material layer 210 and the second material layer 230, and transfers the pattern of the patterned second hard mask material layer 320 to the first material layer 210 and the second material layer 230. The first material layer 210 under the strip-shaped mask 3211 forms a strip-shaped pattern 231, and the plurality of strip-shaped patterns 231 of the first region form a pattern layer. The second material layer 230 under the pattern layer forms a bottom layer 211, and the second material layer 230 of the second region forms a second part 202. Due to the partial etching of the etching stop layer 220 between the adjacent second hard masks 321 of the first region in the second etching, the depth of the sink groove 204 between the adjacent pattern pairs 230a is smaller than the groove structure 203 formed between the adjacent first parts 201, or the etching stop layer 220 between the adjacent pattern pairs 230a is not completely etched, and the sink groove 204 is not formed. The etching stop layer 220 between the two strip-shaped patterns 231 in the pattern pair 230a is not completely etched.

[0107] The semiconductor structure prepared by the above method can provide an alignment structure, and the method uses fewer masks, has low process cost, and provides an alignment structure with high contrast, which is beneficial to reducing overlay error in the semiconductor manufacturing process.

[0108] In some embodiments, the method for manufacturing a semiconductor structure includes:

[0109] After performing the first anisotropic etching, the remaining patterned mask layer 300 is removed;

[0110] A metal film layer 500 is formed on the side of the patterned material layer 200 to be etched away from the substrate 100, and the metal film layer 500 covers the entire surface of the first portion 201 and the second portion 202 away from the substrate 100.

[0111] The metal film layer 500 covers the first portion 201 and the second portion 202 at the same time, and forms a grating structure with the ups and downs of the first portion 201 and the second portion 202, thereby improving the contrast of the formed mark pattern.

[0112] The terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0113] In the present application, unless otherwise explicitly specified and limited, the terms "assembly", "connection" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0114] In the description of the present application, the description of the terms "some embodiments", "exemplarily" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0115] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application shall be within the scope of the present application.

Claims

1. An alignment structure provided on a substrate, characterized by, The alignment structure comprises: a plurality of first portions arranged along a first direction and a plurality of second portions connecting between adjacent first portions; the first portion comprises a bottom layer and a pattern layer on the bottom layer, an outer contour of a normal projection of the pattern layer on the substrate coincides with a normal projection of the bottom layer on the substrate, the pattern layer comprises a plurality of strip patterns arranged along a second direction, an angle between the second direction and the first direction is 90±5°; a height of the second portion relative to the substrate is less than a height of the bottom layer relative to the substrate, and a distance between adjacent first portions is greater than a distance between adjacent strip patterns in the first portion; the alignment structure further comprises an etching stop layer, the etching stop layer is located between the bottom layer and the pattern layer and continuously extends between at least two adjacent strip patterns in the pattern layer and the bottom layer, a material of the etching stop layer is different from materials of the pattern layer and the second portion, the strip patterns extend along a third direction, the third direction intersects the first direction, and the first direction, the second direction and the third direction are parallel to the substrate; in the pattern layer, two adjacent strip patterns sequentially form a pattern pair, the etching stop layer continuously extends between the pattern pair and the bottom layer and discontinuously extends between adjacent pattern pairs, a gap between adjacent pattern pairs extends to the bottom layer, and a height of a bottom surface of the gap relative to the substrate is greater than a height of the second portion relative to the substrate.

2. The alignment structure of claim 1, wherein a side of the second portion away from the substrate is a plane.

3. The alignment structure of claim 1, wherein a height difference between the bottom layer and the second portion is greater than or equal to 100 nanometers.

4. An alignment structure according to any one of claims 1 to 3, wherein the alignment structure further comprises a metal film layer, the metal film layer covers all surfaces of the first portion and the second portion away from the substrate.

5. The alignment structure of claim 4, wherein, a height difference between an area of the first portion covered by the metal film layer and an area of the second portion covered by the metal film layer relative to the substrate is greater than or equal to 150 nanometers.

6. The alignment structure of claim 4, wherein the metal film layer fills the gap between adjacent strip patterns in the pattern layer.

7. The alignment structure of claim 4, wherein a side of the area of the second portion covered by the metal film layer away from the substrate is a plane.

8. A semiconductor structure, characterized by a semiconductor structure comprises a substrate and an alignment structure as claimed in any one of claims 1 to 7 disposed on the substrate.

9. A method of manufacturing a semiconductor structure, characterized by, a method for manufacturing a semiconductor structure as claimed in claim 8, the method comprising: providing a substrate comprising a substrate and a layer of to-be-etched material on the substrate, and dividing the layer of to-be-etched material into a plurality of first regions arranged along a first direction and a plurality of second regions connecting between adjacent first regions; forming a patterned mask layer on a side of the material layer to be etched away from the substrate, the patterned mask layer partially covers the first region and exposes the second region, the patterned mask layer on the part of the first region comprises a plurality of first hard masks arranged at intervals, the plurality of first hard masks on the first region are arranged in an array along a second direction, an angle between the second direction and the first direction is 90±5°, an outer contour of a normal projection of the plurality of first hard masks on the first region on the material layer to be etched is coincident with the first region, a spacing between adjacent first hard masks on the first region is smaller than a spacing between adjacent first regions; performing first anisotropic etching on the material layer to be etched with the patterned mask layer as a mask, a first region of the material layer to be etched forms a first part, and a second region of the material layer to be etched forms a second part, the first part comprises a bottom layer and a pattern layer on the bottom layer, the pattern layer comprises a plurality of strip patterns arranged at intervals, the first hard mask shields a region of the material layer to be etched to form the strip pattern, and a height of the second part relative to the substrate is smaller than a height of the bottom layer relative to the substrate.

10. The method of manufacturing a semiconductor structure according to claim 9, wherein The first hard mask extends along a third direction, the third direction intersects the first direction, and the first direction, the second direction and the third direction are all parallel to the substrate. Among the plurality of first hard masks of the first region: adjacent two first hard masks successively form a mask pair, the patterned mask layer further comprises a second hard mask between the mask pair and the material layer to be etched, the second hard mask corresponds to the mask pair one by one, and an outer contour of a normal projection of the mask pair on the substrate is coincident with a normal projection of the second hard mask on the substrate.

11. The method of manufacturing a semiconductor structure according to claim 10, wherein The method for forming the patterned mask layer comprises: forming a second hard mask material layer and a mandrel material layer successively on a side of the material layer to be etched away from the substrate, patterning the mandrel material layer to form a plurality of mandrel patterns, and the plurality of mandrel patterns on the first region extend along the third direction and are arranged in an array along the second direction; forming a first hard mask material layer conformally on the patterned mandrel material layer and the second hard mask material layer, performing second anisotropic etching on the first hard mask material layer, removing the first hard mask material layer on a side of the mandrel pattern away from the substrate and a certain distance outside both sides of the mandrel pattern, and the remaining first hard mask material layer within a certain distance on both sides of the mandrel pattern forms the first hard mask, and two first hard masks belonging to the same mask pair are formed on both sides of the same mandrel pattern; performing third anisotropic etching on the second hard mask material layer with the mandrel pattern and the first hard mask as masks, and the remaining second hard mask material layer forms a plurality of second hard masks, and the third anisotropic etching also removes the mandrel pattern.

12. The method of manufacturing a semiconductor structure according to claim 11, wherein The to-be-etched material layer comprises a first material layer, an etching stop layer and a second material layer stacked in sequence on the substrate, and etching rates of the first material layer and the second material layer are both greater than that of the etching stop layer in the first anisotropic etching.

13. The method of manufacturing a semiconductor structure according to claim 12, wherein The first anisotropic etching comprises a first etching, a second etching and a third etching performed in sequence. The first etching removes exposed portions of the second material layer, transfers a pattern of the patterned second hard mask material layer to the second material layer, and stops at the etching stop layer. The second etching removes portions of the second hard mask material layer, transfers a pattern of the patterned first hard mask material layer to the second hard mask material layer, and removes at least the etching stop layer exposed by the second hard mask in the second region, and stops at the second material layer. The third etching removes exposed portions of the first material layer and the second material layer, and transfers a pattern of the patterned second hard mask material layer to the first material layer and the second material layer.

14. The method of manufacturing a semiconductor structure according to one of claims 9 to 13, characterized in that, In the method for manufacturing the semiconductor structure: After the first anisotropic etching is performed, the remaining patterned mask layer is removed. A metal film layer is formed on a side of the patterned to-be-etched material layer away from the substrate, and the metal film layer covers all surfaces of the first portion and the second portion away from the substrate.

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