H2b-based server multi-configuration dynamic loading and adaptive adjustment method and system

Abstract

The application discloses a kind of based on H2B's server multi-configuration dynamic loading and adaptive adjustment method and system, it is related to computer hardware technical field, disclosed based on H2B's server multi-configuration dynamic loading and adaptive adjustment method and system, through firmware control, the dynamic loading and verification of multiple hardware configurations are realized, based on H2B shared space, the collaborative work of BMC and BIOS is realized, hardware resource allocation and configuration update are automatically completed in system startup stage, can realize the dynamic switching of multiple hardware configurations, improve resource configuration efficiency and reduce manual operation risk, while can ensure configuration integrity.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to a method and system for dynamic loading and adaptive adjustment of multiple server configurations based on H2B. Background Technology

[0002] As the core computing unit of a data center, the flexibility and manageability of server hardware configurations are crucial to meeting the needs of different application scenarios. In traditional server design and deployment, hardware configurations are typically fixed during the manufacturing phase or initial deployment, or require complex manual adjustments. When changes to the underlying hardware configuration are needed, these solutions often require system downtime for physical operations or tedious BIOS configuration, which is extremely time-consuming for large-scale server deployments. This inefficiency is particularly pronounced in business environments requiring frequent configuration changes. Furthermore, while servers may be designed for peak loads, resources under that configuration may not be fully utilized most of the time, resulting in waste. Conversely, lower configurations may lead to performance bottlenecks during peak periods. This mismatch between resource configuration and business needs impacts system performance and increases operating costs.

[0003] Furthermore, in the aforementioned solutions, when making multiple complex settings in the BIOS, the probability of system configuration errors increases significantly with the number of configuration parameters, leading to system instability or underperformance. The collaboration between the BMC and BIOS is also typically not for dynamically loading multiple complete hardware configuration files; they lack an effective information transmission mechanism to dynamically adjust hardware resources based on the selected configuration scheme in the very early stages of system startup. Moreover, due to the diversity of configurations, the BIOS often cannot accurately report silkscreen information based on actual hardware resources, requiring a full configuration, which not only involves a large development workload but also makes maintenance difficult.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a method and system for dynamic loading and adaptive adjustment of multiple server configurations based on H2B, which aims to achieve dynamic switching of multiple hardware configurations, improve resource allocation efficiency, and reduce the risk of manual operation.

[0006] To achieve the above objectives, this application proposes a method for dynamic loading and adaptive adjustment of multiple server configurations based on H2B, the method comprising:

[0007] Through firmware control, non-volatile space is set in the BMC's storage medium to store multiple sets of hardware configuration profile data;

[0008] Based on the configuration selection mechanism after BMC startup, target configuration profile data is read from the non-volatile space and its integrity is verified.

[0009] Write the verified complete target configuration profile data to the H2B shared space;

[0010] Based on the BIOS obtaining the target configuration profile data from the H2B shared space during the POST process, the hardware configuration parameters are parsed to obtain the hardware configuration parameters.

[0011] Based on the hardware configuration parameters, dynamic allocation of hardware resources and device initialization are completed, and currently effective hardware configuration information is generated; the hardware configuration information includes hardware resource topology information and the original configuration parameter set;

[0012] The SMBIOS table is updated based on the hardware configuration information, and system control is transferred to the operating system.

[0013] In one embodiment, before the step of reading target configuration profile data from the non-volatile space based on the configuration selection mechanism after BMC startup and verifying its integrity, the method further includes:

[0014] Receive configuration switching instructions through the BMC external interface and obtain the new target configuration profile ID;

[0015] Update the current configuration identifier in the non-volatile space to the new target configuration profile ID;

[0016] Trigger a BMC restart to load the new configuration profile data.

[0017] In one embodiment, the step of setting up non-volatile space in the BMC's storage medium via firmware control to store multiple sets of hardware configuration profile data includes:

[0018] Define multiple sets of hardware configuration profile data structures, each of which includes a profile ID, a CPU configuration parameter set, a memory configuration parameter set, a PCIe channel mapping table, a network configuration parameter set, a storage configuration parameter set, a device enable flag set, and a checksum.

[0019] The hardware configuration profile data structure is written into the non-volatile space via firmware control.

[0020] In one embodiment, the step of reading target configuration profile data from the non-volatile space and verifying its integrity based on the configuration selection mechanism after BMC startup includes:

[0021] Determine the target configuration profile ID based on the current configuration identifier;

[0022] The storage address of the target configuration profile data is located from the profile index table in the non-volatile space based on the target configuration profile ID.

[0023] Read the target configuration profile data and verify its checksum;

[0024] When verification fails, the safe mode configuration data is loaded as the target configuration profile data.

[0025] In one embodiment, the step of obtaining the target configuration profile data from the H2B shared space based on the BIOS during the POST process and parsing it to obtain hardware configuration parameters includes:

[0026] Obtain the complete target configuration profile data from the H2B shared space;

[0027] The CPU core enable status, memory channel allocation mode, PCIe slot channel number allocation rules, and onboard device enable flags in the target configuration profile data are analyzed to generate hardware configuration parameters.

[0028] In one embodiment, the step of dynamically allocating hardware resources and initializing the device based on the hardware configuration parameters to generate currently effective hardware configuration information includes:

[0029] The number of physical channels in the PCIe slots is reallocated according to the PCIe channel mapping table in the hardware configuration parameters.

[0030] Activate or disable a specified onboard device based on the device enable flag set in the hardware configuration parameters;

[0031] Adjust the processor core enable status according to the CPU configuration parameter set in the hardware configuration parameters, and generate dynamically allocated hardware resource topology information;

[0032] The PCIe channel mapping table and device enable flag set in the hardware configuration parameters are used as the original configuration parameter set and merged with the hardware resource topology information to form the hardware configuration information.

[0033] In one embodiment, the step of reallocating the number of physical lanes of a PCIe slot according to the PCIe lane mapping table in the hardware configuration parameters includes:

[0034] Identify the target channel allocation pattern for each physical slot from the PCIe channel mapping table included in the hardware configuration parameters;

[0035] Compare the actual number of channels detected by the current hardware with the target number of channels;

[0036] If the actual number of channels is inconsistent with the target number of channels, the PCIe switch register is rewritten by the CPLD to force the slot to work according to the target number of channels;

[0037] If no device is connected to the slot, the power and clock signals for that slot are disabled to save power.

[0038] In one embodiment, the step of adjusting the processor core enable state according to the CPU configuration parameter set in the hardware configuration parameters and generating dynamically allocated hardware resource topology information includes:

[0039] Based on the core enable flag in the CPU configuration parameter set, selectively activate physical processor cores;

[0040] Configure the operating parameters of the memory controller based on the memory channel allocation mode;

[0041] The hardware resource topology information is constructed by integrating the PCIe channel allocation results and device enable status.

[0042] In one embodiment, the step of updating the SMBIOS table based on the hardware configuration information and transferring system control to the operating system includes:

[0043] A system model identifier is generated based on the hardware resource topology information in the hardware configuration information and written into the system model field of the SMBIOS table;

[0044] Based on the PCIe channel mapping table contained in the original configuration parameter set in the hardware configuration information, update the current channel allocation field of the SMBIOS system slot information table;

[0045] Update the SMBIOS onboard device description entries based on the device enable flag set in the original configuration parameter set.

[0046] Furthermore, to achieve the above objectives, this application also proposes an H2B-based server multi-configuration dynamic loading and adaptive adjustment system. The H2B-based server multi-configuration dynamic loading and adaptive adjustment system includes: a memory, a processor, and an H2B-based server multi-configuration dynamic loading and adaptive adjustment program stored in the memory and executable on the processor. The H2B-based server multi-configuration dynamic loading and adaptive adjustment program is configured to implement the steps of the H2B-based server multi-configuration dynamic loading and adaptive adjustment method.

[0047] The H2B-based server multi-configuration dynamic loading and adaptive adjustment method and system proposed in this application realizes the dynamic loading and verification of multiple hardware configurations through firmware control, realizes the collaborative work of BMC and BIOS based on H2B shared space, and automatically completes hardware resource allocation and configuration update during the system startup phase. It can realize the dynamic switching of multiple hardware configurations, improve resource configuration efficiency and reduce the risk of manual operation, while ensuring configuration integrity. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating an embodiment of the H2B-based server multi-configuration dynamic loading and adaptive adjustment method of this application;

[0051] Figure 2 This is a flowchart illustrating another embodiment of the H2B-based server multi-configuration dynamic loading and adaptive adjustment method of this application;

[0052] Figure 3 For this application Figure 1 A detailed flowchart of step S100;

[0053] Figure 4 For this application Figure 1 A detailed flowchart of step S200;

[0054] Figure 5 For this application Figure 1 Detailed flowchart of step S400;

[0055] Figure 6 For this application Figure 1 A detailed flowchart of step S500;

[0056] Figure 7 For this application Figure 6 A detailed flowchart of step S510;

[0057] Figure 8 For this application Figure 6 A detailed flowchart of step S530;

[0058] Figure 9 For this application Figure 1 A detailed flowchart of step S600;

[0059] Figure 10 This is a schematic diagram of a structural embodiment of the H2B-based server multi-configuration dynamic loading and adaptive adjustment system provided in this application.

[0060] Explanation of icon numbers:

[0061] 10. Memory; 20. Processor.

[0062] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0063] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0064] It should be understood that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0065] In existing technologies, the flexibility and manageability of server hardware configuration face numerous challenges. Early servers relied on physical jumpers or DIP switches for limited parameter settings, which were cumbersome and prone to errors. With technological evolution, BIOS setup tools became mainstream, but they required manual intervention and were ill-suited for large-scale deployments or frequent changes. Deployment tools based on preset configuration files could partially solve batch configuration problems, but lacked the ability to dynamically adjust the allocation of underlying hardware resources. While the BMC (Browser Management Console) has hardware management functions, it lacks a mechanism to work with the BIOS to dynamically load multiple complete configurations. For example, when a server needs to switch between compute-intensive and I / O-intensive configurations, traditional methods require manual adjustments with system shutdown, which is inefficient and prone to errors.

[0066] To address the aforementioned issues, the inventors discovered a disconnect between hardware resource configuration and system startup processes in existing technologies, leading to inefficient configuration switching. Analysis of the server startup process revealed that the BMC runs independently before system startup, possessing the potential to store multiple configurations. Further research showed that establishing a shared data channel between the BMC and BIOS enables early transfer of configuration data. Based on this, a proposal was made to pre-store multiple hardware configurations in the BMC's non-volatile space, dynamically loading them through a collaborative mechanism during the startup phase, thereby avoiding physical operations and manual intervention.

[0067] Based on this, embodiments of this application provide a method for dynamic loading and adaptive adjustment of multiple server configurations based on H2B, referring to... Figure 1 The H2B-based server multi-configuration dynamic loading and adaptive adjustment method includes steps S100 to S600, wherein:

[0068] Step S100: Through firmware control, a non-volatile space is set in the storage medium of the BMC to store multiple sets of hardware configuration profile data.

[0069] Step S200: Based on the configuration selection mechanism after BMC startup, read the target configuration profile data from the non-volatile space and verify its integrity;

[0070] Step S300: Write the verified complete target configuration profile data into the H2B shared space;

[0071] Step S400: Based on the BIOS obtaining the target configuration profile data from the H2B shared space during the POST process, the hardware configuration parameters are parsed to obtain the hardware configuration parameters;

[0072] Step S500: Based on the hardware configuration parameters, complete the dynamic allocation of hardware resources and device initialization, and generate the currently effective hardware configuration information; the hardware configuration information includes hardware resource topology information and the original configuration parameter set;

[0073] Step S600: Update the SMBIOS table according to the hardware configuration information and transfer system control to the operating system.

[0074] In this embodiment, the non-volatile space refers to a storage area in the BMC storage medium that retains its power-off properties. Specifically, it can be implemented using reserved partitions in a flash memory chip, used to persistently store multiple sets of hardware configuration parameter sets. The configuration selection mechanism refers to the logic by which the BMC selects a target configuration based on a preset identifier during startup. This can be achieved by reading the stored configuration index table, ensuring that the specified configuration is loaded each time the system starts. The H2B shared space refers to the shared memory area between the BMC and the host system. Specifically, it can be implemented using a reserved physical memory address segment, serving as an intermediate buffer for configuration data transfer. Dynamic allocation of hardware resources refers to adjusting the state of resources such as the processor core and memory channels according to configuration parameters. This can be achieved by rewriting chipset registers, enabling the hardware to be initialized according to a predetermined mode.

[0075] In this embodiment, during the BMC initialization phase, the firmware reads the current configuration identifier from the non-volatile space to locate the corresponding hardware configuration profile data. After verifying the data integrity through a verification algorithm, the valid data is written to the H2B shared space. When the host system boots up, the BIOS obtains configuration data from the shared space during the POST phase, parses it to generate a parameter set including CPU core enable status and PCIe channel allocation rules. The hardware initialization module reconfigures the number of active processor cores, adjusts the PCIe switch register channel allocation, and generates a configuration record containing resource topology information based on these parameters. The finally updated SMBIOS table provides the operating system with an accurate hardware view, ensuring that subsequent driver loading matches the resource configuration.

[0076] In this embodiment, through the collaborative mechanism between the BMC and BIOS, multiple hardware configurations are dynamically loaded automatically in the early stages of system startup. In existing technologies, the BMC only manages basic functions such as power supply, utilizing its storage and preprocessing capabilities in conjunction with the H2B shared space to achieve efficient transfer of configuration data. Compared to physical operations requiring manual adjustments with system downtime, this solution achieves minute-level configuration switching through software definition, thereby automating server hardware configuration switching and significantly reducing the time required for configuration changes. In various application scenarios, hardware resource allocation modes can be quickly switched according to load requirements, such as prioritizing PCIe lanes for network devices or storage controllers. Through pre-stored verification mechanisms and automated loading processes, manual configuration errors are effectively avoided, ensuring that hardware initialization is strictly consistent with the predetermined configuration. The dynamic update mechanism of the system table structure enables the operating system to accurately identify the current hardware topology, providing a reliable foundation for resource scheduling.

[0077] In one feasible implementation, refer to Figure 2 Before step S200, the method further includes steps S710 to S730, wherein:

[0078] Step S710: Receive configuration switching instructions through the BMC external interface and obtain the new target configuration profile ID;

[0079] Step S720: Update the current configuration identifier in the non-volatile space to the new target configuration profile ID;

[0080] Step S730: Trigger a BMC restart to load the new configuration profile data.

[0081] In this embodiment, the BMC external interface refers to the physical or logical interface through which the baseboard management controller provides communication functions. Specifically, it can be implemented using a network interface, serial interface, or out-of-band management interface, used to receive instruction signals from remote management terminals or local management tools. The configuration switching instruction refers to an operation command containing a target configuration profile identifier, specifically implemented using a predefined format API call or IPMI standard instruction, used to trigger the server hardware configuration switching process. The new target configuration profile ID refers to a unique code identifying the configuration scheme to be activated, specifically implemented using a hexadecimal value or UUID string, used to locate the corresponding configuration data in the non-volatile space. The non-volatile space refers to a storage area in the BMC storage medium with power-off data retention characteristics, specifically implemented using a reserved partition in Flash memory, used to persistently store multiple sets of configuration data and the current configuration identifier. The current configuration identifier refers to a dynamic variable stored in the non-volatile space, specifically implemented using an index number or pointer, used to indicate the location of the currently effective configuration profile data. Triggering a BMC restart refers to re-initializing the baseboard management controller via a software reset command. This can be achieved by writing to the system reset register or by using a watchdog timer trigger mechanism, which is used to make the new configuration flag effective and start the configuration loading process.

[0082] In this embodiment, when a server hardware configuration switch is required, the administrator sends a switch command containing the target configuration profile ID to the BMC via the out-of-band management network. After parsing the command, the BMC updates the current configuration identifier field in the configuration management module of the non-volatile memory area, replacing the original identifier with the new target configuration profile ID. After the identifier update is completed, the BMC performs a soft reset to restart its operating environment. During the restart process, the BMC's configuration loading module reads the corresponding new configuration profile data from the non-volatile space based on the updated current configuration identifier, and then dynamically adjusts the hardware configuration through subsequent processes. This process requires no manual intervention in BIOS settings or physical operations, achieving automated configuration switching.

[0083] In this embodiment, the out-of-band management capabilities of the BMC enable the reception and execution of remote configuration switching commands. Furthermore, a soft reset of the BMC completes the loading of the new configuration, avoiding the time consumption associated with a full system restart. Additionally, the atomicity and traceability of the configuration switching operation are ensured through the current configuration identifier field in the non-volatile space. Thus, this application enables remote one-click switching of server hardware configurations, significantly reducing the time cost and error risk of manual operations. The configuration switching process does not interrupt the host operating system; the identifier update and restart operations are completed only at the BMC level, effectively improving the scheduling flexibility of server resources. Receiving commands through a standardized out-of-band management interface allows this solution to be seamlessly integrated into automated operation and maintenance systems, meeting the dynamic configuration management needs of large-scale server clusters in data centers.

[0084] In one feasible implementation, refer to Figure 3 Step S100 includes steps S110 to S120, wherein:

[0085] Step S110: Define multiple sets of hardware configuration profile data structures. The data structures include profile ID, CPU configuration parameter set, memory configuration parameter set, PCIe channel mapping table, network configuration parameter set, storage configuration parameter set, device enable flag set, and checksum.

[0086] Step S120: The hardware configuration profile data structure is written into the non-volatile space via firmware control.

[0087] In this embodiment, the hardware configuration profile data structure refers to a formatted data set used to describe the configuration of server hardware resources. Specifically, it can be implemented using a structure or binary data block containing multiple fields, each field corresponding to the configuration parameters of a specific hardware module. This data structure ensures a unified data format for different configuration schemes during storage and parsing through standardized field definitions. The profile ID is an encoding used to uniquely identify different hardware configuration schemes, specifically implemented using a 16-bit or 32-bit integer value. This identifier allows for quick location of target data across multiple configurations. The CPU configuration parameter set is a set of processor core enable states and frequency settings. Specifically, it can use a bitmap structure to represent the core enable state, combined with numerical parameters to define the operating frequency, used to dynamically adjust processor resources during the initialization phase. The PCIe channel mapping table is a table showing the correspondence between physical slots and logical channels. Specifically, it can be implemented using a two-dimensional array or key-value pair data structure. Each entry records the slot number and the number of allocated channels, used for reallocating PCIe bandwidth resources. The device enable flag bit set is a set of binary flags controlling the activation state of onboard devices. Specifically, it can be implemented using a bit field structure, with each bit corresponding to the enable state of a specific device, used to quickly enable or disable hardware modules. A checksum is a verification value used to verify the integrity of configuration data. It can be generated using CRC32 or SHA-1 algorithms, and the verification mechanism prevents data from being damaged during storage or transmission.

[0088] In this embodiment, the method creates a dedicated partition in the non-volatile area of ​​the storage medium through BMC firmware, such as dividing an independent storage block in a flash memory chip. Each hardware configuration scheme is encapsulated into a data structure containing fields such as profile ID, CPU parameters, memory parameters, and PCIe mapping table, where the profile ID serves as the index key and a checksum is appended to the end of the data structure. During writing, the firmware stores multiple configuration schemes sequentially according to a predefined data alignment format, while maintaining a profile index table to record the starting address and length of each configuration. When a new configuration needs to be stored, the firmware calculates the storage location based on the data structure size, writes the data to a free area, and updates the index table. During reading, the physical address of the target data is obtained by retrieving the index table using the profile ID, and then integrity verification is performed. For example, in a certain configuration scheme, the CPU configuration parameter set defines the activation of 12 out of 16 physical cores, the PCIe channel mapping table allocates slot 1 to x16 mode, and the device enable flag set disables the onboard RAID controller. These parameters are encapsulated into fixed-length data blocks and appended with a CRC32 checksum when written to the non-volatile space.

[0089] In this embodiment, a predefined data structure containing complete hardware resource descriptions enables centralized storage and rapid location of multiple configurations. Simultaneously, a checksum mechanism ensures the reliability of configuration data during long-term storage, resolving the issues of scattered configuration data and lack of integrity verification in traditional methods. Standardized data structures ensure accurate parsing of configuration parameters for different hardware modules; non-volatile storage and verification mechanisms prevent startup failures due to data corruption; and a profile ID indexing mechanism significantly improves configuration retrieval and loading speed. This allows the server to quickly switch between complete hardware configurations in different application scenarios, while reducing the risk of system failures caused by manual operation or data errors.

[0090] In one feasible implementation, refer to Figure 4 Step S200 includes steps S210 to S240, wherein:

[0091] Step S210: Determine the target configuration profile ID based on the current configuration identifier;

[0092] Step S220: Locate the storage address of the target configuration profile data from the profile index table in the non-volatile space according to the target configuration profile ID;

[0093] Step S230: Read the target configuration profile data and verify its checksum;

[0094] Step S240: When verification fails, load the security mode configuration data as the target configuration profile data.

[0095] In this embodiment, the current configuration identifier refers to an identifier stored in the non-volatile storage area, used to indicate the currently effective configuration profile number. Specifically, it can be implemented using a persistent variable maintained by the BMC firmware, which is updated each time a configuration switch occurs. The profile index table is a data structure stored in the non-volatile space, containing the mapping relationship between each configuration profile ID and its physical storage address. Specifically, it can be implemented using a hash table or fixed offset addressing method, used to quickly locate the storage location of the target configuration data. The checksum is a check value used to verify data integrity, specifically generated using a cyclic redundancy check algorithm or a hash algorithm, used to detect whether the configuration data has been corrupted during storage or transmission. The security mode configuration data refers to the set of basic configuration parameters pre-set in the BMC firmware, specifically using a minimal hardware resource allocation scheme, used to provide a bootable default configuration when an anomaly is detected in the main configuration data.

[0096] In this embodiment, during the BMC startup phase, the firmware first reads the current configuration identifier from the non-volatile memory area and parses out the target configuration profile ID. By querying the profile index table, it determines the physical address range of the configuration data corresponding to this ID in the storage medium. Subsequently, the BMC firmware reads the complete configuration data block from this address and calculates its checksum, comparing it with the stored value. When the checksum matches, the configuration data is deemed complete and valid, and it is transmitted to the H2B shared space; if the checksum fails, the security mode configuration data embedded in the BMC chip is automatically loaded to prevent system startup failure due to data corruption. This process is completed automatically during the BMC initialization phase without manual intervention.

[0097] In this embodiment, by implementing hardware-level data verification during the BMC startup phase, configuration data anomalies can be identified at the initial power-on stage of the system, and the system can automatically switch to safe mode configuration, effectively preventing startup failures caused by corrupted configuration data. For example, when non-volatile memory causes configuration data bits to flip due to electromagnetic interference, existing technologies may directly apply incorrect parameters, resulting in hardware initialization errors. However, this solution can detect and activate backup configurations in a timely manner through a verification mechanism, significantly improving system robustness. Through the above technical solution, this application achieves automated verification and anomaly recovery during the configuration data loading process, solving the system startup failure problem caused by corrupted configuration data in traditional methods. By pre-setting safe mode configuration data, basic hardware initialization parameters can still be provided when a major configuration anomaly is detected, avoiding the need for manual data repair. At the same time, the fast location mechanism based on the profile index table reduces configuration retrieval time, enabling the configuration switching process to be completed efficiently at the hardware level.

[0098] In one feasible implementation, refer to Figure 5 Step S400 includes steps S410 to S420, wherein:

[0099] Step S410: Obtain the complete target configuration profile data from the H2B shared space;

[0100] Step S420: parse the CPU core enable status, memory channel allocation mode, PCIe slot channel number allocation rules and onboard device enable flags in the target configuration profile data to generate hardware configuration parameters.

[0101] In this embodiment, the H2B shared space refers to the shared memory region established between the baseboard management controller and the basic input / output system. Specifically, it can be implemented using dual-port memory or mapped registers to achieve cross-firmware layer data interaction. The target configuration profile data refers to a complete set of parameters containing a specific hardware resource configuration scheme. Specifically, it can be stored in the form of structured data blocks, with each data block containing a check field and a version identifier. Hardware configuration parameters refer to a set of operation instructions that, after parsing, can directly drive the hardware controller. Specifically, it can be generated through binary encoding conversion and includes the register write sequence required for device initialization.

[0102] In this embodiment, during the basic input / output system self-test (BIT) phase of system startup, the shared storage area reserved by the baseboard management controller is accessed through a predefined physical address. After the complete target configuration profile data is read into the BIT's temporary buffer, a structured parsing operation is performed: first, the CPU core enable status field is identified to extract the physical core number to be activated; then, the memory channel allocation mode field is analyzed to determine the channel enable status of each memory controller; next, the PCIe slot channel allocation rules are parsed to generate a channel bandwidth configuration scheme for each physical slot; finally, the onboard device enable flags are read to generate a device initialization whitelist. A step-by-step verification mechanism is used during the parsing process, verifying the data validity immediately after each field is parsed to ensure that the generated hardware configuration parameters meet the physical constraints of the target hardware platform.

[0103] In this embodiment, by pre-setting multiple sets of complete configuration data and dynamically parsing them during the startup phase, on-demand allocation of hardware resources is achieved. Furthermore, by automatically generating configuration parameters through parsing predefined allocation rules, configuration efficiency is significantly improved. In addition, device management is automated through parsing flag sets, enabling automated generation and precise application of hardware configuration parameters, thus solving the problems of low efficiency and error-proneness in traditional manual configuration. When the server needs to switch computing modes, such as from storage-intensive to network-intensive scenarios, the system can automatically parse the new PCIe channel allocation rules and adjust the physical slot bandwidth, ensuring that hardware resource configuration matches business needs in real time. Simultaneously, the structured data parsing mechanism effectively avoids parameter omissions or format errors during manual configuration, improving the reliability of system initialization.

[0104] In one feasible implementation, refer to Figure 6 Step S500 includes steps S510 to S540, wherein:

[0105] Step S510: Reallocate the number of physical channels of the PCIe slot according to the PCIe channel mapping table in the hardware configuration parameters;

[0106] Step S520: Activate or disable the specified onboard device based on the device enable flag set in the hardware configuration parameters;

[0107] Step S530: Adjust the processor core enable state according to the CPU configuration parameter set in the hardware configuration parameters, and generate dynamically allocated hardware resource topology information.

[0108] Step S540: The PCIe channel mapping table and device enable flag set in the hardware configuration parameters are used as the original configuration parameter set and merged with the hardware resource topology information to form the hardware configuration information.

[0109] In this embodiment, the PCIe channel mapping table refers to a data structure that defines the target channel allocation mode for each physical slot. Specifically, it can be implemented using a combination of fields including slot number, number of channels, and operating mode, used to guide the hardware layer in dynamically adjusting the PCIe switch registers. The device enable flag set refers to device control parameters composed of binary bit sequences. Specifically, it can use bitmasks to represent the activation status of onboard network cards, memory controllers, or coprocessors, and implement physical switching through the GPIO control signals of the CPLD. The CPU configuration parameter set refers to a set of parameters including core enable status, frequency strategy, and cache allocation rules. Specifically, it can dynamically configure the core's enable and sleep states through the processor microcode interface. Hardware resource topology information refers to structured data reflecting the currently active hardware connection relationships. Specifically, it can generate a system-level topology view by integrating the number of processor cores, memory channel allocation mode, and PCIe slot status.

[0110] In this embodiment, after the hardware configuration parameters are loaded, the system first parses the PCIe channel mapping table to identify the target channel allocation mode for each physical slot. For example, the target number of channels for PCIe slot number 3 can be 16. If the currently detected connected device only occupies 8 channels, the corresponding switch register is rewritten through the CPLD to force the slot to work in 16-channel mode. For slots without connected devices, their power and clock signals can be turned off to reduce power consumption. At the same time, specific flag bits in the device enable flag set are read. For example, when the 5th bit is 1, the onboard RAID controller is activated, and when it is 0, its function is disabled. After the core enable flag in the CPU configuration parameter set is parsed, physical cores are selectively activated. For example, only 24 cores in a dual-processor system are enabled, and the remaining cores enter a low-power state. After integrating the above configuration results, the system generates topology information containing the number of processor cores, memory channel allocation, and PCIe slot status, and merges it with the original parameters to form complete hardware configuration information.

[0111] In this embodiment, the solution achieves automated resource allocation through predefined configuration profile data and batch control through flag bit sets, avoiding omissions or misoperations. This solution also integrates multi-dimensional configuration parameters to construct a unified view, providing the operating system with an accurate hardware status description. Thus, this application achieves automated control of hardware resource allocation. For example, when switching between compute-intensive and I / O-intensive configurations, PCIe bandwidth adjustment and core enable status synchronization can be completed without manual intervention. The application of device enable flag bit sets reduces the probability of configuration errors; for example, predefined bit sequences ensure strict consistency between onboard device status and configuration scheme. Dynamic generation of hardware resource topology information solves the problem of mismatch between silkscreen information and physical topology in traditional solutions. For example, the system can accurately report the currently enabled number of processor cores and PCIe slot operating modes, avoiding false system information reports due to configuration changes.

[0112] In one feasible implementation, refer to Figure 7 Step S510 includes steps S511 to S514, wherein:

[0113] Step S511: Identify the target channel allocation mode for each physical slot from the PCIe channel mapping table included in the hardware configuration parameters;

[0114] Step S512: Compare the actual number of channels detected by the current hardware with the target number of channels;

[0115] Step S513: If the actual number of channels is inconsistent with the target number of channels, the PCIe switch register is rewritten by the CPLD to force the slot to work according to the target number of channels.

[0116] In step S514, if no device is connected to the slot, the power and clock signals of the slot are disabled to save power.

[0117] In this embodiment, the PCIe channel mapping table refers to a predefined correspondence between physical slots and the target number of channels. This can be implemented using a configuration file stored in the firmware, guiding the system to dynamically adjust PCIe channel allocation. CPLD rewriting of the PCIe switch register refers to real-time configuration of the PCIe switch registers using a complex programmable logic device. This can be implemented using a firmware module programmed with a hardware description language, enabling dynamic modification of channel allocation parameters during system startup. Disabling power and clock signals for unconnected slots means cutting off power and clock input to idle slots. This can be achieved through the coordinated operation of a power management integrated circuit and a clock controller, reducing system power consumption by disabling the physical layer circuitry of unused slots.

[0118] In this embodiment, during system startup, the firmware reads the target configuration's PCIe channel mapping table from non-volatile storage and parses the target channel allocation mode for each physical slot. The hardware detection module obtains the currently connected PCIe devices and their channel counts, comparing them with the target configuration. When the actual channel count is found to be inconsistent with the target value, a register write command is sent to the PCIe switch via the CPLD to forcibly adjust the slot's channel allocation logic. For physical slots without connected devices, the power management module shuts down their power supply lines, and the clock controller synchronously stops the clock signal output for that slot. This process is automatically completed during the BIOS initialization phase, achieving dynamic hardware resource adaptation without manual intervention.

[0119] In this embodiment, automated channel reallocation and power management are implemented through firmware, enabling dynamic switching of hardware configurations early in the system startup process, significantly improving configuration efficiency and accuracy. Simultaneously, the intelligent shutdown mechanism for idle slots effectively reduces system standby power consumption, overcoming the energy waste caused by keeping unused devices powered in traditional solutions. This allows for automated dynamic adjustment of PCIe channel allocation, reducing the risk of manual configuration errors and improving the utilization efficiency of server hardware resources. For scenarios requiring frequent switching between compute-intensive and I / O-intensive configurations, the system can quickly adapt to different channel allocation needs, ensuring that bandwidth resources match the actual load.

[0120] In one feasible implementation, refer to Figure 8 Step S530 includes steps S531 to S533, wherein:

[0121] Step S531: Selectively activate physical processor cores according to the core activation identifier in the CPU configuration parameter set;

[0122] Step S532: Configure the operating parameters of the memory controller based on the memory channel allocation mode;

[0123] Step S533: Integrate the PCIe channel allocation results and device enable status to construct the hardware resource topology information.

[0124] In this embodiment, the core enable flag refers to a set of binary flags stored in the hardware configuration parameters. Each flag corresponds to the activation state of a physical processor core. Specifically, the core can be enabled or disabled by reading the flags through the BIOS firmware and calling the processor microcode interface. This flag allows the server to dynamically adjust the scale of computing resources according to configuration requirements, such as disabling some cores to reduce power consumption in low-load scenarios. The memory channel allocation mode refers to a set of parameters defining the operating mode of the memory controller channels. Specifically, interleaved mode, independent mode, or hybrid mode configuration parameters can be used, and the channel allocation strategy can be dynamically adjusted by writing to the memory controller registers. This mode can optimize memory bandwidth utilization according to configuration requirements, such as enabling full-channel interleaved mode to improve data access efficiency in high-throughput scenarios. Hardware resource topology information refers to structured data describing the connection relationships between processor cores, memory channels, PCIe slots, and onboard devices. Specifically, a topology map can be generated by parsing the core enable state, memory controller register values, and PCIe switch configurations. This information provides the operating system with an accurate hardware view, ensuring that resource scheduling is consistent with the physical configuration.

[0125] In this embodiment, after the BIOS obtains the target configuration profile data during the POST phase, it first parses the core enable flags in the CPU configuration parameter set. For example, if the flag indicates that only the odd-numbered cores in a dual-processor system need to be enabled, the BIOS will call the processor instruction set interface to disable the even-numbered cores. Subsequently, based on the memory channel allocation mode parameters, it configures the channel enable bits and interleaving strategy of the memory controller, for example, configuring eight channels as four groups of dual-channel interleaved modes. After completing the core and memory configuration, the BIOS reads the completed PCIe channel allocation results and device enable status, integrates the processor core activation list, memory channel mapping table, PCIe slot channel number allocation table, and device status table to generate hardware resource topology information containing hierarchical connection relationships. This topology information is written into the ACPI table, allowing the operating system to accurately identify the physical resource distribution during the initialization phase.

[0126] Understandably, existing technologies require manual adjustment of the number of enabled cores in the BIOS settings interface and cannot automatically synchronize memory channel modes and PCIe allocation strategies based on preset configurations, leading to fragmented resource configurations. For example, if a user only modifies the number of cores without simultaneously adjusting the memory channels, some memory bandwidth may not be effectively utilized. This solution, however, ensures coordinated adjustments to core, memory, and peripheral configurations through a structured definition of configuration profile data, eliminating the risk of inconsistencies from manual configuration. Furthermore, the dynamic generation mechanism of hardware resource topology information overcomes the mismatch between traditional fixed topology information and dynamic configurations, such as preventing the operating system from mistakenly determining the availability of disabled PCIe slots.

[0127] Through the above technical solutions, this application achieves on-demand dynamic allocation of processor core resources, avoiding wasted computing power or performance bottlenecks caused by fixed configurations. By coordinating the memory channel allocation mode with the core activation status, the matching degree between memory bandwidth utilization and processor computing efficiency is improved. The dynamic construction mechanism of hardware resource topology information ensures that the operating system accurately identifies the currently effective hardware configuration, avoiding device driver loading errors or resource scheduling conflicts caused by lagging topology information.

[0128] In one feasible implementation, refer to Figure 9 Step S600 includes steps S610 to S630, wherein:

[0129] Step S610: Generate a system model identifier based on the hardware resource topology information in the hardware configuration information and write it into the system model field of the SMBIOS table;

[0130] Step S620: Based on the PCIe channel mapping table contained in the original configuration parameter set in the hardware configuration information, update the current channel allocation field of the SMBIOS system slot information table;

[0131] Step S630: Update the SMBIOS onboard device description entry based on the device enable flag set in the original configuration parameter set.

[0132] In this embodiment, the SMBIOS table refers to a system management information table conforming to the DMTF standard, used to provide hardware configuration information to the operating system. Specifically, it can be implemented using ACPI table structures such as _SM_ and _SMB_ defined in the UEFI specification. Its function is to provide the operating system with accurate hardware topology data. The system model identifier is a string encoding that uniquely identifies the current hardware configuration. Specifically, it can be generated by using a hash algorithm to digest the hardware resource topology information. Its function is to enable the operating system to recognize the currently effective configuration version. The PCIe channel mapping table is configuration data that records the correspondence between physical slots and logical channels. Specifically, it can use a two-dimensional array structure to store the mapping relationship between slot numbers and channel allocation numbers. Its function is to accurately reflect the dynamically adjusted PCIe resource allocation status. The device enable flag set is a binary bit sequence representing the activation status of onboard devices. Specifically, it can use a bitmask method to store the enable status of each device. Its function is to synchronize the physical device status with system management data.

[0133] In this embodiment, after the dynamic allocation of hardware resources is completed, the BIOS converts the generated hardware resource topology information into a data structure conforming to the SMBIOS specification. The system model field generates a unique identifier by combining the number of CPU cores, memory channels, and PCIe slot allocation mode; for example, a string in the format "CPU16_MEM8_PCIe4x4" is written into the system model field. For the PCIe channel mapping table, the BIOS iterates through the current channel allocation number for each physical slot and updates the "Current Usage" field of the SMBIOS system slot information table with the actual number of active channels. The device enable flag set is parsed into independent entries; for example, the SMBIOS entry corresponding to a disabled onboard network card is set to the "Disabled" state.

[0134] In some implementations, when a difference is detected between the PCIe lane allocation mode in the hardware configuration information and the default configuration, the BIOS automatically generates a supplementary descriptor containing dynamic allocation information. For example, a new "Dynamic Allocation" extended field is added to the SMBIOS Type 9 (System Slots) table to record the numerical changes before and after lane reallocation. For disabled onboard devices, the device status field in the SMBIOS Type 41 (Onboard DevicesExtended Information) entry is set to 0x02 (Not Present) to ensure that the operating system does not load the corresponding driver.

[0135] In this embodiment, by synchronizing hardware configuration information and the SMBIOS data structure in real time, the topology information obtained by the operating system is ensured to be completely consistent with the actual hardware state. This eliminates compatibility issues caused by information asynchrony and solves the problem of mismatched system management information after dynamic hardware configuration. This allows the operating system to load drivers and allocate resources based on accurate hardware description information. This solution avoids device identification errors caused by lag in SMBIOS information and improves system stability after configuration switching. Furthermore, by replacing manual maintenance of SMBIOS data with an automated update mechanism, the operational complexity in multi-configuration scenarios is significantly reduced.

[0136] In the embodiments of this application, the H2B-based server multi-configuration dynamic loading and adaptive adjustment method realizes the dynamic loading and verification of multiple hardware configurations through firmware control, realizes the collaborative work of BMC and BIOS based on H2B shared space, and automatically completes hardware resource allocation and configuration update during the system startup phase. It can realize the dynamic switching of multiple hardware configurations, improve resource configuration efficiency and reduce the risk of manual operation, while ensuring configuration integrity.

[0137] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the H2B-based server multi-configuration dynamic loading and adaptive adjustment method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0138] This application also provides an H2B-based server multi-configuration dynamic loading and adaptive adjustment system, see reference. Figure 10 The H2B-based server multi-configuration dynamic loading and adaptive adjustment system includes: a memory 10, a processor 20, and an H2B-based server multi-configuration dynamic loading and adaptive adjustment program stored on the memory 10 and capable of running on the processor 20. The H2B-based server multi-configuration dynamic loading and adaptive adjustment program is configured to implement the steps of the H2B-based server multi-configuration dynamic loading and adaptive adjustment method.

[0139] The H2B-based server multi-configuration dynamic loading and adaptive adjustment system provided in this application, employing the H2B-based server multi-configuration dynamic loading and adaptive adjustment method in the above embodiments, can achieve dynamic switching of multiple hardware configurations, improve resource allocation efficiency, and reduce the risk of manual operation. Compared with the prior art, the beneficial effects of the H2B-based server multi-configuration dynamic loading and adaptive adjustment system provided in this application are the same as those of the H2B-based server multi-configuration dynamic loading and adaptive adjustment method provided in the above embodiments, and other technical features of the H2B-based server multi-configuration dynamic loading and adaptive adjustment system are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0140] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. All equivalent structural transformations made under the technical concept of this application using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A method for dynamic loading and adaptive adjustment of multiple server configurations based on H2B, characterized in that, The method includes: Through firmware control, non-volatile space is set in the BMC's storage medium to store multiple sets of hardware configuration profile data; Based on the configuration selection mechanism after BMC startup, target configuration profile data is read from the non-volatile space and its integrity is verified. Write the verified complete target configuration profile data to the H2B shared space; Based on the BIOS obtaining the target configuration profile data from the H2B shared space during the POST process, the hardware configuration parameters are parsed to obtain the hardware configuration parameters. Based on the hardware configuration parameters, dynamic allocation of hardware resources and device initialization are completed, and currently effective hardware configuration information is generated; the hardware configuration information includes hardware resource topology information and the original configuration parameter set; The SMBIOS table is updated based on the hardware configuration information, and system control is transferred to the operating system. The step of updating the SMBIOS table based on the hardware configuration information and transferring system control to the operating system includes: A system model identifier is generated based on the hardware resource topology information in the hardware configuration information and written into the system model field of the SMBIOS table; Based on the PCIe channel mapping table contained in the original configuration parameter set in the hardware configuration information, update the current channel allocation field of the SMBIOS system slot information table; Update the SMBIOS onboard device description entries based on the device enable flag set in the original configuration parameter set.

2. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 1, characterized in that, Before the step of reading target configuration profile data from the non-volatile space and verifying its integrity based on the configuration selection mechanism after BMC startup, the method further includes: Receive configuration switching instructions through the BMC external interface and obtain the new target configuration profile ID; Update the current configuration identifier in the non-volatile space to the new target configuration profile ID; Trigger a BMC restart to load the new configuration profile data.

3. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 1, characterized in that, The step of setting up non-volatile space in the BMC's storage medium through firmware control to store multiple sets of hardware configuration profile data includes: Define multiple sets of hardware configuration profile data structures, each of which includes a profile ID, a CPU configuration parameter set, a memory configuration parameter set, a PCIe channel mapping table, a network configuration parameter set, a storage configuration parameter set, a device enable flag set, and a checksum. The hardware configuration profile data structure is written into the non-volatile space via firmware control.

4. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 1, characterized in that, The steps of reading target configuration profile data from the non-volatile space and verifying its integrity based on the configuration selection mechanism after BMC startup include: Determine the target configuration profile ID based on the current configuration identifier; The storage address of the target configuration profile data is located from the profile index table in the non-volatile space based on the target configuration profile ID. Read the target configuration profile data and verify its checksum; When verification fails, the safe mode configuration data is loaded as the target configuration profile data.

5. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 1, characterized in that, The step of obtaining the target configuration profile data from the H2B shared space during the POST process based on the BIOS and parsing it to obtain hardware configuration parameters includes: Obtain the complete target configuration profile data from the H2B shared space; The CPU core enable status, memory channel allocation mode, PCIe slot channel number allocation rules, and onboard device enable flags in the target configuration profile data are analyzed to generate hardware configuration parameters.

6. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 1, characterized in that, The steps of dynamically allocating hardware resources and initializing the device based on the hardware configuration parameters, and generating the currently effective hardware configuration information, include: The number of physical channels in the PCIe slots is reallocated according to the PCIe channel mapping table in the hardware configuration parameters. Activate or disable a specified onboard device based on the device enable flag set in the hardware configuration parameters; Adjust the processor core enable status according to the CPU configuration parameter set in the hardware configuration parameters, and generate dynamically allocated hardware resource topology information; The PCIe channel mapping table and device enable flag set in the hardware configuration parameters are used as the original configuration parameter set and merged with the hardware resource topology information to form the hardware configuration information.

7. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 6, characterized in that, The step of reallocating the number of physical lanes in the PCIe slots according to the PCIe lane mapping table in the hardware configuration parameters includes: Identify the target channel allocation pattern for each physical slot from the PCIe channel mapping table included in the hardware configuration parameters; Compare the actual number of channels detected by the current hardware with the target number of channels; If the actual number of channels is inconsistent with the target number of channels, the PCIe switch register is rewritten by the CPLD to force the slot to work according to the target number of channels; If no device is connected to the slot, the power and clock signals for that slot are disabled to save power.

8. The H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in claim 6, characterized in that, The step of adjusting the processor core enable state according to the CPU configuration parameter set in the hardware configuration parameters and generating dynamically allocated hardware resource topology information includes: Based on the core enable flag in the CPU configuration parameter set, selectively activate physical processor cores; Configure the operating parameters of the memory controller based on the memory channel allocation mode; The hardware resource topology information is constructed by integrating the PCIe channel allocation results and device enable status.

9. A server multi-configuration dynamic loading and adaptive adjustment system based on H2B, characterized in that, The H2B-based server multi-configuration dynamic loading and adaptive adjustment system includes: a memory, a processor, and an H2B-based server multi-configuration dynamic loading and adaptive adjustment program stored in the memory and executable on the processor. The H2B-based server multi-configuration dynamic loading and adaptive adjustment program is configured to implement the steps of the H2B-based server multi-configuration dynamic loading and adaptive adjustment method as described in any one of claims 1 to 8.

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