Model storage acceleration system in frequency domain convolution processing engine
By optimizing the memory address translation and control module of the frequency domain convolution processing engine, the problem of limited storage capacity and read bandwidth in frequency domain convolution processing is solved, and efficient storage and fast reading of large-capacity model data are achieved.
Patent Information
- Application Number
- CN202511094855.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-06
- Publication Date
- 2025-12-16
AI Technical Summary
In existing technologies, the frequency domain data of the transmitted model is stored in on-chip RAM during frequency domain convolution processing. This results in problems such as small storage capacity and limited read bandwidth, which makes it impossible to store large-scale model data and the placement and routing timing cannot converge, causing program instability.
The system employs a memory address translation module, an asynchronous signal processing module, a write data processing module, a read/write control module, a memory controller IP core, and a read data cache module to achieve asynchronous clock domain conversion, bit width conversion, and control signal timing optimization of model data, thereby improving memory space utilization and data access bandwidth.
It expands the model data capacity to over 1GB, reduces read latency and improves data access speed, with a maximum read speed of up to 4GB/s, solving the problem of limited storage capacity and read bandwidth.
Smart Images
Figure CN121144004A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of radar signal processing, in particular to a model storage acceleration system in a frequency domain convolution processing engine. BACKGROUND
[0002] In the field of radar signal processing, the receiving end uses pulse compression method to improve the signal-to-noise ratio of the pulse signal, and the essence of the pulse compression method is time domain convolution operation. Large point number time domain convolution will consume a lot of logic operation resources, so the time domain convolution operation is usually converted to the frequency domain for processing to save operation resources. The frequency domain convolution operation mainly includes the following three steps:
[0003] 1. Fourier transform is performed on the input two-way data;
[0004] 2. The transformed two-way frequency domain data is multiplied;
[0005] 3. The result of the multiplication is inverse Fourier transformed.
[0006] In step 2 of the frequency domain convolution processing, one of the multiplication operations is the received processed baseband spectrum data, and the other is the frequency domain data of the sending model stored in the cache in advance.
[0007] The frequency domain data of the sending model in the prior art is mainly stored in the on-chip RAM, and the on-chip RAM capacity of today's programmable logic device FPGA is limited (not more than 100MB) and precious (cross-clock domain processing, layout routing, ILA debugging all need to consume RAM resources), so the RAM that is really used to store model data is extremely limited.
[0008] However, the frequency domain data of the current sending model is stored in the on-chip RAM, which mainly has the following problems:
[0009] 1. The amount of data stored in the model is small.
[0010] Limited by the capacity of the on-chip RAM itself, it is impossible to store model data (more than 10MB);
[0011] 2. The read bandwidth is limited.
[0012] Configuring the on-chip RAM to a large data bit width (512 bits) and running at a high clock frequency (200MHz) will cause the timing of the layout routing to fail to converge and also cause the program to be unstable. SUMMARY
[0013] In view of the above problems, the present application provides a model storage acceleration system in a frequency domain convolution processing engine for overcoming the above problems or at least partially solving the above problems.
[0014] The application provides the following solutions:
[0015] A model storage acceleration system in a frequency domain convolution processing engine, comprising:
[0016] a memory address conversion module, an asynchronous signal processing module, a write data processing module, a read-write control module, a memory controller IP core, and a read-out data buffer module; the memory address conversion module is connected to the asynchronous signal processing module; the asynchronous signal processing module, the write data processing module, and the memory controller IP core are all connected to the read-write control module; and the read-out data buffer module is connected to the memory controller IP core.
[0017] The memory address conversion module is configured to receive configuration parameters and implement the function of converting the configuration parameters into memory addresses.
[0018] The asynchronous signal processing module is configured to implement the conversion of address control signals in the app_clk clock domain into the mig_ui_clk clock domain.
[0019] The write data processing module is configured to receive model data and implement asynchronous clock isolation and bit width conversion.
[0020] The read-write control module is configured to generate the control signal timing required by the memory controller.
[0021] The memory controller IP core is configured to generate the clock and reset signals required by the memory chip, generate the timing of the data, address, and control buses, and calibrate the physical parameters.
[0022] The read-out data buffer module is configured to implement the conversion of address control signals in the mig_ui_clk clock domain into the app_clk clock domain, and implement the buffering of the read-out data from the memory to ensure that one frame of continuous data is output to the application end.
[0023] Preferably, the memory addresses include height data addresses and modulation data addresses; the generation of the start address start_addr_h and the end address end_addr_h of the height data is implemented through the following two formulas:
[0024] start_addr_h=(index_pulse-1)x8(1)
[0025] end_addr_h=(index_pulse-1)x8+H_ADDR_SIZE(2)
[0026] The generation of the start address start_addr_m and the end address end_addr_m of the modulation data is implemented through the following four formulas:
[0027] start_addr_m = ADDR_NUM_H + model_base_addr + model_offset_addr (3) end_addr_m = ADDR_NUM_H + model_base_addr + model_offset_addr
[0028] + ADDR_NUM_M (4)
[0029] model_base_addr = index_freq x ADDR_NUM_M (5)
[0030] model_offset_addr = index_pulse x ADDR_NUM_M (6)
[0031] wherein: index_pulse is a pulse index number; index_freq is a frequency index number; H_ADDR_SIZE is a size of a memory address occupied by a single height data; ADDR_NUM_H is a size of a memory address occupied by all height data; and ADDR_NUM_M is a size of a memory address occupied by 256-point modulation data.
[0032] Preferably, the address conversion method of the memory address conversion module comprises:
[0033] After power-on, the memory address generation state machine is in an idle state; a work enable signal input from outside the module is set high, and the state machine takes a pre-set pulse start index value as an initial value of a pulse index counter;
[0034] When a rising edge of an external input detection signal arrives, the pulse index counter starts to increase by 1;
[0035] According to formulae (1) and (2), the start address and the end address of the height data are started to be calculated, and a timing trigger counter starts to load an initial value and decrease;
[0036] When the timing trigger counter decreases to 0, according to formulae (3), (4), (5) and (6), the start address and the end address of the height data are started to be calculated.
[0037] Preferably, the clock domain conversion mode of the asynchronous signal processing module comprises an asynchronous FIFO.
[0038] Preferably, the bit width conversion comprises converting a clock domain of model data, which is app_clk, into a clock domain of a memory controller, which is mig_ui_clk, and converting 64-bit bit width of the model data into 512-bit bit width of the memory controller IP core.
[0039] Preferably, the read-write control module includes a read-write control flow, and the read-write control flow includes:
[0040] In the idle state, if the write data FIFO is determined to be not empty, the state machine jumps to the write operation state;
[0041] In the write operation state, the state machine generates a write control command and a timing sequence;
[0042] When the file writing is completed, the state machine returns to the idle state, otherwise the write address is increased by 8, and when the write address reaches the maximum value, the write address is cleared, and then the write address and the write command are loaded again;
[0043] In the idle state, if the read trigger rising edge is valid, the state machine jumps to the read operation state;
[0044] In the read operation state, the state machine generates a read control command and a timing sequence
[0045] When the read operation is completed, the state machine judges whether the read address reaches the set value;
[0046] When the delay waiting is completed, the idle state is returned again.
[0047] If the set value is reached, the idle state is returned, otherwise the read address is increased by 8, and then the read address and the read command are loaded again.
[0048] According to the specific embodiments provided by the application, the following technical effects are disclosed:
[0049] The model storage acceleration system in the frequency domain convolution processing engine provided by the embodiment of the application can improve the size of the model data participating in the frequency domain convolution operation, and the capacity of the stored model data can reach 1 GB or more, while the traditional implementation mode is stored in the chip and does not exceed 10 MB; the memory reading process provided can reduce the reading delay (us level), and can also flexibly change the reading speed (the maximum reading speed can reach 4 GB / s); and the designed storage method can improve the space utilization of data in the memory.
[0050] Of course, implementing any product of the application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS
[0051] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0052] Figure 1This is a block diagram of a model storage acceleration system in a frequency domain convolution processing engine provided in an embodiment of the present invention;
[0053] Figure 2 This is a flowchart of the memory address generation algorithm provided in an embodiment of the present invention;
[0054] Figure 3 This is a read / write control flowchart provided in an embodiment of the present invention. Detailed Implementation
[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.
[0056] See Figure 1 This invention provides a model storage acceleration system in a frequency domain convolution processing engine, such as... Figure 1 As shown, the system may include:
[0057] The system includes a memory address translation module, an asynchronous signal processing module, a write data processing module, a read / write control module, a memory controller IP core, and a read data cache module. The memory address translation module is connected to the asynchronous signal processing module. The asynchronous signal processing module, the write data processing module, and the memory controller IP core are all connected to the read / write control module. The read data cache module is connected to the memory controller IP core.
[0058] The memory address translation module is used to receive configuration parameters and perform the function of translating configuration parameters into memory addresses. Specifically, in this embodiment, the memory address may include a height data address and a modulation data address. The start address (start_addr_h) and end address (end_addr_h) of the height data are generated using the following two formulas:
[0059] start_addr_h=(index_pulse-1)x8(1)
[0060] end_addr_h=(index_pulse-1)x8+H_ADDR_SIZE(2)
[0061] The start address start_addr_m and end address end_addr_m of the modulation data are generated using the following four formulas:
[0062] start_addr_m=ADDR_NUM_H+model_base_addr+model_offset_addr(3)end_addr_m=ADDR_NUM_H+model_base_addr+model_offset_addr
[0063] +ADDR_NUM_M(4)
[0064] model_base_addr=index_freqxADDR_NUM_M(5)
[0065] model_offset_addr=index_pulsexADDR_NUM_M(6)
[0066] In the formula: index_pulse is the pulse index number; index_freq is the frequency index number; H_ADDR_SIZE is the memory address size occupied by a single height data; ADDR_NUM_H is the memory address size occupied by all height data; ADDR_NUM_M is the memory address size occupied by 256-point modulation data.
[0067] Furthermore, the address translation method of the memory address translation module includes:
[0068] After power-on, the memory address generation state machine is in an idle state; the external input enable signal of the module is set high, and the state machine uses the preset pulse start index value as the initial value of the pulse index counter;
[0069] When the rising edge of the external input detector signal arrives, the pulse index counter starts to increment by 1.
[0070] The starting and ending addresses of the height data are calculated according to formulas (1) and (2), and the timing trigger counter starts loading the initial value and decrements.
[0071] When the timing trigger counter decrements to 0, the start and end addresses of the height data are calculated according to formulas (3), (4), (5), and (6).
[0072] The asynchronous signal processing module is used to convert the address control signal under the app_clk clock domain to the mig_ui_clk clock domain; specifically, in this application embodiment, the clock domain conversion method of the asynchronous signal processing module may include asynchronous FIFO.
[0073] The write data processing module is used to receive model data and implement asynchronous clock isolation and bit width conversion; in specific implementation, the bit width conversion in this application embodiment can include converting the clock domain where the model data is located, app_clk, to the clock domain where the memory controller is located, mig_ui_clk, and converting the 64-bit bit width model data to the 512-bit bit width of the memory controller IP core.
[0074] The read / write control module is used to generate the control signal timing required by the memory controller; specifically, in this application embodiment, the read / write control flow of the read / write control module may include:
[0075] In the idle state, once the write data FIFO is confirmed to be not empty, the state machine jumps to the write operation state;
[0076] During a write operation, the state machine generates write control commands and timing sequences.
[0077] When the file writing is finished, the state machine returns to the idle state; otherwise, the write address is incremented by 8. When the write address reaches its maximum value, it is cleared to zero, and then the write address and write command are reloaded.
[0078] In the idle state, if the rising edge of the read trigger is valid, the state machine jumps to the read operation state;
[0079] During a read operation, the state machine generates read control commands and timing sequences.
[0080] After a read operation is completed, the status machine will determine whether the read address has reached the set value;
[0081] If the set value is reached, return to the idle state; otherwise, increment the read address by 8 and then reload the read address and read command.
[0082] The memory controller IP core is used to generate the clock and reset signals required by the memory chip, generate the timing of data, address and control buses, and perform physical parameter calibration.
[0083] The read data buffer module is used to convert the address control signal under the mig_ui_clk clock domain to the app_clk clock domain, and to buffer the memory read data to ensure that a continuous frame of data is output to the application.
[0084] The model storage acceleration system in the frequency domain convolution processing engine provided in this application adopts a new data storage method, which improves the utilization of memory space; adopts a new address mapping algorithm, which reduces the processing latency of address mapping; and designs a new memory control process, which reduces the data access processing latency and improves the data access bandwidth.
[0085] The model storage acceleration system in the frequency domain convolution processing engine provided in this application will be described in detail below.
[0086] This application provides a storage acceleration system for radar signal processing, which can improve the processing bandwidth of frequency domain convolution and reduce processing latency.
[0087] like Figure 1 The storage acceleration system shown mainly includes a memory address translation module, an asynchronous signal processing module, a write data processing module, a read / write state machine control module, and a read data cache module.
[0088] 1. Write data formatting module.
[0089] The write data formatting module primarily implements asynchronous clock isolation and bit width conversion. The clock domain of the written model data is app_clk (frequency 62.5MHz), which is converted to the clock domain mig_ui_clk (frequency 200MHz) of the memory controller after processing by the write data formatting module. The written model data is 64 bits wide, which is converted to the 512-bit width of the memory controller IP core after processing by the write data formatting module.
[0090] 2. Memory address translation module.
[0091] The Memory Address Translation module mainly implements the function of converting configuration parameters to memory addresses. The model involves height data addresses and modulation data addresses. The start address start_addr_h and end address end_addr_h of the height data are generated by formulas (1) and (2), while the start address start_addr_m and end address end_addr_m of the modulation data are generated by formulas (3), (4), (5), and (6).
[0092] start_addr_h=(index_pulse-1)x8(1)
[0093] end_addr_h=(index_pulse-1)x8+H_ADDR_SIZE(2)
[0094] start_addr_m=ADDR_NUM_H+model_base_addr+model_offset_addr(3)end_addr_m=ADDR_NUM_H+model_base_addr+model_offset_addr
[0095] +ADDR_NUM_M(4)
[0096] model_base_addr=index_freqxADDR_NUM_M(5)
[0097] model_offset_addr=index_pulsexADDR_NUM_M(6)
[0098] Where index_pulse is the pulse index number; index_freq is the frequency index number; H_ADDR_SIZE is the memory address size occupied by a single height data, with a value of 8; ADDR_NUM_H is the memory address size occupied by all height data, with a value of 4,000,000; and ADDR_NUM_M is the memory address size occupied by 256-point modulation data, with a value of 128.
[0099] like Figure 2 The flowchart of the memory address generation algorithm is shown. After the system is powered on, the memory address generation state machine is in an idle state. The external input enable signal of the module is set high, and the state machine uses the preset pulse start index value as the initial value of the pulse index counter. When the rising edge of the external input detector signal arrives, on the one hand, the pulse index counter starts to increment by 1, and on the other hand, it starts to calculate the start address and end address of the height data according to formulas (1) and (2), while the timing trigger counter starts to load the initial value and decrement. When the timing trigger counter decrements to 0, it starts to calculate the start address and end address of the height data according to formulas (3), (4), (5), and (6).
[0100] 3. Asynchronous signal processing module.
[0101] The asynchronous signal processing module mainly implements the conversion of address control signals in the app_clk clock domain to the mig_ui_clk clock domain, and its main implementation method is asynchronous FIFO.
[0102] 4. Read / write control module.
[0103] The read / write control module is primarily responsible for generating the timing control signals required by the memory controller. For example... Figure 3 The diagram shown is a flowchart of the read / write control module.
[0104] In the idle state, when the write data FIFO is not empty, the state machine transitions to the write operation state. In the write operation state, the state machine generates write control commands and timing sequences. When the file writing is complete, the state machine returns to the idle state; otherwise, the write address is incremented by 8. When the write address reaches its maximum value, it is cleared to zero, and then the write address and write commands are reloaded.
[0105] In the idle state, if a rising edge of the read trigger is valid, the state machine transitions to the read operation state. In the read operation state, the state machine generates read control commands and timing sequences. After a read operation is completed, the state machine checks if the read address has reached a set value. If it has, it returns to the idle state; otherwise, the read address is incremented by 8, and the read address and read command are loaded again.
[0106] 5. Read data caching module.
[0107] The data reading module performs two functions: firstly, it converts the address control signals from the mig_ui_clk clock domain to the app_clk clock domain; secondly, it buffers the data read from memory to ensure that a continuous frame of data is output to the application.
[0108] 6. Memory controller IP core.
[0109] The memory controller IP core is responsible for generating the clock and reset signals required by the memory chip, generating the timing of data, address and control buses, and also for calibrating physical parameters.
[0110] In summary, the model storage acceleration system in the frequency domain convolution processing engine provided in this application can increase the size of the model data participating in the frequency domain convolution operation, and the stored model data capacity can reach more than 1GB, while the traditional implementation method is limited to on-chip storage of no more than 10MB; the provided memory read process can reduce read latency (µs level) and can flexibly change the read speed (maximum read speed can reach 4GB / s); the designed storage method can improve the space utilization of data in memory.
[0111] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0112] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.
[0113] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0114] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A model storage acceleration system in a frequency domain convolution processing engine, characterized in that, It includes a memory address translation module, an asynchronous signal processing module, a write data processing module, a read / write control module, a memory controller IP core, and a read data cache module; the memory address translation module is connected to the asynchronous signal processing module; the asynchronous signal processing module, the write data processing module, and the memory controller IP core are all connected to the read / write control module; the read data cache module is connected to the memory controller IP core; The memory address translation module is used to receive configuration parameters and perform the function of translating configuration parameters into memory addresses; The asynchronous signal processing module is used to convert the address control signal in the app_clk clock domain to the mig_ui_clk clock domain; The write data processing module is used to receive model data and implement asynchronous clock isolation and bit width conversion; The read / write control module is used to generate the control signal timing required by the memory controller; The memory controller IP core is used to generate the clock and reset signals required by the memory chip, generate the timing of data, address and control buses, and perform physical parameter calibration. The read data buffer module is used to convert the address control signal under the mig_ui_clk clock domain to the app_clk clock domain, and to buffer the memory read data to ensure that a continuous frame of data is output to the application.
2. The model storage acceleration system in the frequency domain convolution processing engine according to claim 1, characterized in that, The memory address includes the height data address and the modulation data address; the start address start_addr_h and end address end_addr_h of the height data are generated by the following two formulas: start_addr_h=(index_pulse-1)x8(1) end_addr_h=(index_pulse-1)x8+H_ADDR_SIZE(2) The start address start_addr_m and end address end_addr_m of the modulation data are generated using the following four formulas: start_addr_m=ADDR_NUM_H+model_base_addr+model_offset_addr(3) end_addr_m=ADDR_NUM_H+model_base_addr+model_offset_addr +ADDR_NUM_M(4) model_base_addr=index_freqxADDR_NUM_M(5) model_offset_addr=index_pulsexADDR_NUM_M(6) In the formula: index_pulse is the pulse index number; index_freq is the frequency index number; H_ADDR_SIZE is the memory address size occupied by a single height data; ADDR_NUM_H is the memory address size occupied by all height data; ADDR_NUM_M is the memory address size occupied by 256-point modulation data.
3. The model storage acceleration system in the frequency domain convolution processing engine according to claim 2, characterized in that, The address translation method of the memory address translation module includes: After power-on, the memory address generation state machine is in an idle state; the external input enable signal of the module is set high, and the state machine uses the preset pulse start index value as the initial value of the pulse index counter; When the rising edge of the external input detector signal arrives, the pulse index counter starts to increment by 1. The starting and ending addresses of the height data are calculated according to formulas (1) and (2), and the timing trigger counter starts loading the initial value and decrements. When the timing trigger counter decrements to 0, the start and end addresses of the height data are calculated according to formulas (3), (4), (5), and (6).
4. The model storage acceleration system in the frequency domain convolution processing engine according to claim 1, characterized in that, The clock domain conversion method of the asynchronous signal processing module includes asynchronous FIFO.
5. The model storage acceleration system in the frequency domain convolution processing engine according to claim 1, characterized in that, The bit width conversion includes converting the clock domain of the model data (app_clk) to the clock domain of the memory controller (mig_ui_clk), and converting the 64-bit model data to the 512-bit width of the memory controller IP core.
6. The model storage acceleration system in the frequency domain convolution processing engine according to claim 1, characterized in that, The read / write control process of the read / write control module includes: In the idle state, once the write data FIFO is confirmed to be not empty, the state machine jumps to the write operation state; During a write operation, the state machine generates write control commands and timing sequences. When the file writing is finished, the state machine returns to the idle state; otherwise, the write address is incremented by 8. When the write address reaches the maximum value, the write address is cleared to zero, and then the write address and write command are reloaded. In the idle state, if the rising edge of the read trigger is valid, the state machine jumps to the read operation state; During a read operation, the state machine generates read control commands and timing sequences. After a read operation is completed, the state machine determines whether the read address has reached the set value; Once the delay period is over, it will return to the idle state. If the set value is reached, return to the idle state; otherwise, increment the read address by 8 and then reload the read address and read command.