Data processing circuit, driving chip and LED array driving system

Abstract

The application provides a data processing circuit, a driving chip and an LED array driving system, and relates to the technical field of integrated circuits.The first delay phase-locked loop module is used for detecting the phase difference between the effective edge of the first single-wire data signal and the effective edge of the second single-wire data signal, converting the first reference clock signal based on the first single-wire data signal, and outputting a plurality of first delay clock signals with different phase delays compared with the effective edge of the first reference clock signal based on the phase difference; the data sending module generates the second single-wire data signal based on the input third data signal and the first delay clock signal; after the first delay phase-locked loop module is locked, the effective edge of the second single-wire data signal is aligned with the effective edge of the first single-wire data signal, and the second single-wire data signal, the first reference clock signal and the first single-wire data signal have the same clock frequency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a data processing circuit, a driving chip and an LED array driving system. BACKGROUND

[0002] In related data transmission applications, how to align the effective edges of the output data and the effective edges of the input data and make them the same frequency is a difficult problem.

[0003] In some driving applications of LED display screens, multiple driving chips are cascaded, a control card sends display data SDI to the first driving chip in the cascaded multiple driving chips, and then the first driving chip outputs display data SDO to the next driving chip in the cascade after processing the display data SDI. That is, the display data SDO is both the output data of the current driving chip and the input data of the next driving chip. When each driving chip in the cascade receives the display data, each driving chip drives a plurality of LED beads connected thereto to emit light according to the display data. Whether the display data received by each driving chip in the cascade is the same frequency and the same phase determines whether it can refresh the display data synchronously, which is the key to affecting the display effect. The traditional scheme is usually as shown in Figure 1 In addition to cascading through a data signal line between each driving chip, a clock signal line is also cascaded, the clock signal line transmits a clock signal (i.e. the previous stage driving chip inputs a clock signal CLKI, and then outputs a clock signal CLKO to the next driving chip in the cascade) step by step, so that each driving chip refreshes the data synchronously, however, this driving power consumption is large, and parallel wiring occupies a large area. SUMMARY

[0004] The present application provides a data processing circuit, a driving chip and an LED array driving system, which can align the effective edges of the output data and the effective edges of the input data and make them the same frequency based on single-line transmission, in some high-transmittance display screens such as hole screen, wind-through screen, sound-through screen and the like which have high requirements for the number of wires and higher requirements for synchronous refreshing, not only can the driving chip and the driving chip be cascaded by only one data signal line, saving signal lines such as clock signal lines, but also can ensure that the display data received by each driving chip in the cascade is the same frequency and the same phase, can refresh the display data synchronously with high precision, and saves power consumption.

[0005] To solve the above problems, from a first aspect, the application discloses a data processing circuit, comprising: a first delay-locked loop module and a data sending module, the first delay-locked loop module is used for detecting the phase difference between the active edge of a first single-wire data signal and the active edge of a second single-wire data signal, converting the first single-wire data signal to obtain a first reference clock signal, and outputting a plurality of first delay clock signals with different phase delays compared with the active edge of the first reference clock signal based on the phase difference; the data sending module generates the second single-wire data signal based on the input third data signal and the first delay clock signal; wherein the third data signal is obtained based on the first single-wire data signal; wherein after the first delay-locked loop module is locked, the duty cycle of each clock cycle of the first reference clock signal is fixed, the active edge of the second single-wire data signal is aligned with the active edge of the first single-wire data signal, and the second single-wire data signal, the first reference clock signal and the first single-wire data signal have the same clock frequency.

[0006] Through the data processing circuit provided by the application, after the first delay-locked loop module is locked, the second single-wire data signal, the first reference clock signal and the first single-wire data signal have the same clock frequency, and the active edge of the second single-wire data signal is aligned with the active edge of the first single-wire data signal, so that the embodiment of the application can realize the alignment of the active edge of the output data and the active edge of the input data based on single-wire transmission and the same frequency (i.e. the same clock frequency). Based on different application scenarios, the requirements for aligning the active edge of the output data and the active edge of the input data are different, and the alignment of the active edge of the second single-wire data signal and the active edge of the first single-wire data signal in the application can be: the rising edge of the second single-wire data signal is aligned with the rising edge of the first single-wire data signal; or, the falling edge of the second single-wire data signal is aligned with the falling edge of the first single-wire data signal; or, the rising edge of the second single-wire data signal is aligned with the falling edge of the first single-wire data signal; or, the falling edge of the second single-wire data signal is aligned with the rising edge of the first single-wire data signal.

[0007] Wherein, when applied in the LED display screen, the rising edge of the second single-line data signal is aligned with the rising edge of the first single-line data signal or the falling edge of the second single-line data signal is aligned with the falling edge of the first single-line data signal after the first delay-locked loop module is locked, the same frequency and same phase of the output data (the second single-line data signal) and the input data (the first single-line data signal) can be realized. The first delay-locked loop module (essentially a DLL) is innovatively used to detect the phase difference between the effective edge of the first single-line data signal and the effective edge of the second single-line data signal, and then the phase delay of the plurality of first delay clock signals output by the first delay-locked loop module compared with the effective edge of the first reference clock signal is adjusted according to the phase difference, and then the phase of the second single-line data signal output by the data sending module is changed based on the input third data signal and the first delay clock signal, so that a complete negative feedback loop is formed. Compared with the prior art, the delay caused by the inherent characteristics of some devices in the data processing circuit is reduced or eliminated, the precision of the synchronous refreshing of the display data is improved, and the power consumption can be saved.

[0008] In an embodiment of the present application, the first single-line data signal and the second single-line data signal each include a waveform one representing data 0 and a waveform two representing data 1, and the waveform one and the waveform two each include a segment of high level and unequal duty cycles.

[0009] In an embodiment of the present application, the plurality of first delay clock signals include a first clock signal clk0, a second clock signal clk1 and a third clock signal clk2; wherein, the phase delay time of the first clock signal clk0 compared with the effective edge of the first reference clock signal is t1, the phase delay time of the second clock signal clk1 compared with the effective edge of the first reference clock signal is t2, and the phase delay time of the third clock signal clk2 compared with the effective edge of the first reference clock signal is t3, t1

[0010] In an embodiment of the present application, the first delay-locked loop module includes a data-to-clock module and a voltage-controlled delay chain; the data-to-clock module is used to convert the first single-line data signal or the inverted signal of the first single-line data signal into the first reference clock signal, and adjust the waveform of the converted first reference clock signal according to the input target delay clock signal until the first delay-locked loop module is locked; the voltage-controlled delay chain is used to output a plurality of first delay clock signals with different phase delays compared with the effective edge of the first reference clock signal, and adjust the phase delay time of the first delay clock signal compared with the effective edge of the first reference clock signal according to the input second control signal; wherein, the second control signal is generated based on the phase difference, and the target delay clock signal is any one of the plurality of first delay clock signals.

[0011] In an embodiment of the present application, the target delay clock signal is the second clock signal clk1.

[0012] In an embodiment of the present application, the data sending module comprises a first module and a second module, the first module is configured to sample the third data signal according to the input fourth clock signal clk3, and select the falling edge of the second single-wire data signal to align with the edge of the first clock signal clk0 or the edge of the third clock signal clk2 based on the third data signal, and output a first reset signal data_rn; the second module is configured to sample the high-level signal logic_l according to the fourth clock signal clk3, and reset based on the first reset signal data_rn, and output the second single-wire data signal; wherein the fourth clock signal clk3 is generated by the first delay phase-locked loop module, or the fourth clock signal clk3 is generated based on the first single-wire data signal and the second clock signal clk1.

[0013] In an embodiment of the present application, the data processing circuit further comprises a data recovery module; the data recovery module generates a recovered data signal based on the input first single-wire data signal and the second clock signal clk1, and the third data signal is obtained based on the recovered data signal.

[0014] In an embodiment of the present application, the data processing circuit further comprises a second delay phase-locked loop module and a data recovery module; the second delay phase-locked loop module converts the first single-wire data signal to obtain a second reference clock signal, and outputs a plurality of second delay clock signals with different phase delays compared to the effective edge of the second reference clock signal based on the detected phase difference between the first single-wire data signal and the feedback clock signal thereof; wherein the feedback clock signal is any one of the plurality of second delay clock signals; the data recovery module generates a recovered data signal based on the input first single-wire data signal and the second delay clock signal, and the third data signal is obtained based on the recovered data signal.

[0015] In an embodiment of the present application, the data processing circuit further comprises a logic circuit; wherein the logic circuit inputs the recovered data signal and outputs the third data signal.

[0016] In an embodiment of the present application, the data clock conversion module comprises a frequency division module, a first edge trigger module and a second edge trigger module, wherein the frequency division module performs frequency division based on the first single-line data signal and outputs a frequency division signal; the first edge trigger module samples the frequency division signal based on the first single-line data signal and outputs a first reference clock signal; the second edge trigger module samples a high-level signal according to a target delay clock signal and resets based on the first reference clock signal, and outputs a second reset signal rst to the frequency division module and the first edge trigger module; after the first delay-locked loop module is locked, the second reset signal rst controls the frequency division module and the first edge trigger module to reset in each clock cycle of the first single-line data signal.

[0017] In an embodiment of the present application, the frequency division module comprises N-stage D flip-flop one in cascade, N≥1; in the N-stage D flip-flop one, the data input end and the state inverting output end of each D flip-flop one are connected in common, and the reset end is used for connecting the second reset signal rst; wherein the clock end of the first D flip-flop one is used for connecting the first single-line data signal or the negated signal of the first single-line data signal, the clock end of the remaining D flip-flop one is used for connecting the state inverting output end of the previous D flip-flop one, and the data input end and the state inverting output end of the last D flip-flop one are connected in common to output the frequency division signal.

[0018] In an embodiment of the present application, the first edge trigger module comprises D flip-flop two, the clock end of the D flip-flop two is used for connecting the first single-line data signal or the negated signal of the first single-line data signal, the data input end is used for connecting the frequency division signal, the state output end is used for outputting the first reference clock signal, and the reset end is used for connecting the second reset signal; the second edge trigger module comprises D flip-flop three, the clock end of the D flip-flop three is used for connecting the target delay clock signal, the reset end is used for connecting the first reference clock signal, the data input end is used for connecting the high-level signal, and the state output end outputs the second reset signal or the state output end outputs the second reset signal after being inverted by an inverter one.

[0019] In an embodiment of the present application, the first module comprises a D flip-flop four, an inverter two and an edge detection module, the clock end of the D flip-flop four is configured to receive a fourth clock signal clk3, the data input end is configured to receive a third data signal, the state output end outputs a data signal d0 and the data signal d0 is outputted as a data signal d1 through the inverter two; the edge detection module generates a first low-level pulse signal for aligning with the rising edge of the data signal d0 based on the input first clock signal clk0, generates a second low-level pulse signal for aligning with the rising edge of the data signal d1 based on the input third clock signal clk2, and logically processes the first low-level pulse signal, the second low-level pulse signal, the data signal d0 and the data signal d1, and outputs a first reset signal; the second module comprises a D flip-flop five, the clock end of the D flip-flop five is configured to receive the fourth clock signal clk3, the data input end is configured to receive a high-level signal, the reset end is configured to access the first reset signal, and the state output end outputs a second single-line data signal or the state output end outputs the second single-line data signal through an inverter three.

[0020] In an embodiment of the present application, the first delay phase-locked loop module further comprises a phase detector, a charge pump circuit and a loop filter; the phase detector is configured to detect the phase difference between the valid edge of the first single-line data signal and the valid edge of the second single-line data signal, and output a first control signal; the charge pump circuit outputs a current signal based on the first control signal; and the loop filter charges or discharges based on the current signal to adjust the output second control signal.

[0021] From a second aspect, the present application further provides a driving chip comprising the data processing circuit according to the first aspect of the present application, the driving chip receives the first single-line data signal through one data signal line and / or transmits the second single-line data signal through one data signal line.

[0022] In an embodiment of the present application, the driving chip is a column driving chip or a row driving chip for driving an LED display screen.

[0023] From a third aspect, the present application further provides an LED array driving system comprising H row driving chips cascaded through one data signal line and L column driving chips cascaded through one data signal line, wherein the row driving chip and the column driving chip are both the driving chip according to the second aspect of the present application, and the H row driving chips and the L column driving chips jointly drive an LED array display.

[0024] The present application has the following advantages:

[0025] The data processing circuit provided by the application comprises a first delay phase-locked loop module and a data sending module, wherein the first delay phase-locked loop module can innovatively compare the phase difference between the first single-wire data signal with a variable duty cycle and the second single-wire data signal fed back, and after the first delay phase-locked loop module is locked, the first single-wire data signal or the inverted signal of the first single-wire data signal can be converted into a first reference clock signal with a fixed duty cycle, and a plurality of first delay clock signals are output; the data sending module generates the second single-wire data signal based on the received first delay clock signal and the input third data signal, and feeds back the second single-wire data signal to the first delay phase-locked loop module to form a negative feedback loop, so that the phase of the second single-wire data signal is adjusted based on the phase difference between the first single-wire data signal and the second single-wire data signal, and finally after the first delay phase-locked loop module is locked, the effective edges of the output data (the second single-wire data signal) and the input data (the first single-wire data signal) can be aligned and the same frequency can be achieved.

[0026] When the data processing circuit of the application is applied to some high-transmittance display screens such as hole screen, wind screen, sound screen and the like which require a higher number of lines and a higher synchronous refresh, not only can the data processing circuit realize the single-wire cascade between the driving chips through only one data signal line, saving signal lines such as clock signal lines, but also can ensure the same frequency and phase of the display data received by each driving chip in the cascade, can refresh the display data with high precision and synchronously, and can save power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description.

[0028] Figure 1 is a structural schematic diagram of synchronous refresh of display data of each driving chip in the prior art;

[0029] Figure 2 is a structural schematic diagram of the data processing circuit provided by the embodiment of the application Figure 1 ;

[0030] Figure 3 is a structural schematic diagram of the data processing circuit provided by the embodiment of the application Figure 2 ;

[0031] Figure 4 is a structural schematic diagram of synchronous refresh of display data of each driving chip in the embodiment of the application

[0032] Figure 5 is a waveform schematic diagram of data 1 and data 0 in the single-wire data signal;

[0033] Figure 6is a waveform schematic diagram of a plurality of first delay clock signals provided by the embodiment of the present application;

[0034] Figure 7 is Figure 2 a circuit schematic diagram of the data processing circuit shown in Figure 1 ;

[0035] Figure 8 is Figure 2 a circuit schematic diagram of the data processing circuit shown in Figure 2 ;

[0036] Figure 9 is Figure 2 a circuit schematic diagram of the data processing circuit shown in Figure 3 ;

[0037] Figure 10 is a structural schematic diagram of a data-to-clock module provided by the embodiment of the present application;

[0038] Figure 11 is a circuit schematic diagram of a data-to-clock module provided by the embodiment of the present application;

[0039] Figure 12 is a waveform schematic diagram before a first delay phase-locked loop module is locked;

[0040] Figure 13 is a waveform schematic diagram after the first delay phase-locked loop module is locked;

[0041] Figure 14 is a waveform schematic diagram of generating a recovered data signal provided by the embodiment of the present application;

[0042] Figure 15 is a waveform schematic diagram of generating a data signal d0 and a data signal d1 provided by the embodiment of the present application;

[0043] Figure 16 is a waveform schematic diagram of generating a first reset signal provided by the embodiment of the present application;

[0044] Figure 17 is a waveform schematic diagram of generating a second single-wire data signal provided by the embodiment of the present application;

[0045] Figure 18 is a waveform schematic diagram of realizing the same frequency and the same phase of a second single-wire data signal DO and a first single-wire data signal DI provided by the embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0047] Hereinafter, the terms "second", "first", or "xx-one", "xx-two" and the like are only used for the convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. "Based on" indicates a basic, inspired or considered relationship. It implies that the subsequent action, result or feature is based on, starting point or main basis of the previously mentioned conditions or information, but does not exclude the possibility of adding other factors or other processing. "And / or", which describes the relationship between the associated objects, means that there can be three relationships, for example, A and / or B, which can represent the following cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural.

[0048] The first aspect of the embodiment of the present application provides a data processing circuit, which refers to Figure 2 and Figure 3 The data processing circuit includes a first delay-locked loop module and a data sending module. The first delay-locked loop module is used to detect the phase difference between the active edge of the first single-wire data signal DI and the active edge of the second single-wire data signal DO, convert the first reference clock signal clkr based on the first single-wire data signal DI, and output a plurality of first delay clock signals with different phase delays compared to the active edge of the first reference clock signal clkr based on the phase difference. The data sending module generates the second single-wire data signal DO based on the input third data signal Datao and the first delay clock signal; wherein the third data signal Datao is obtained based on the first single-wire data signal DI; wherein after the first delay-locked loop module is locked, the duty cycle of each clock cycle of the first reference clock signal clkr is fixed, the active edge of the second single-wire data signal DO is aligned with the active edge of the first single-wire data signal DI, and the second single-wire data signal DO, the first reference clock signal clkr and the first single-wire data signal DI have the same clock frequency.

[0049] The data processing circuit provided by the embodiment of the present application can convert the first reference clock signal clkr based on the first single-wire data signal DI (such as converting the received DI into the first reference clock signal clkr or converting the inverted signal of the first single-wire data signal DI into the first reference clock signal clkr), and then output a plurality of first delay clock signals with different phase delays compared to the active edge of the first reference clock signal clkr. All or part of the plurality of first delay clock signals are provided to the data sending module, so that the data sending module generates the second single-wire data signal DO based on the received first delay clock signal and the input third data signal Datao, thereby realizing the process of generating output data (i.e. the second single-wire data signal DO) based on input data (i.e. the first single-wire data signal DI).

[0050] Considering the inherent characteristics of the circuits in the first delay-locked loop module and the data transmitting module (such as the CK-Q delay in the flip-flop used to output the second single-line data signal DO), there can be a large phase error between the active edge of the second single-line data signal DO and the active edge of the first single-line data signal DI. Therefore, in the data processing circuit of the embodiment of the present application, after the data transmitting module generates the second single-line data signal DO, the second single-line data signal DO is also input to the first delay-locked loop module as a feedback signal of the first delay-locked loop module, so that the first delay-locked loop module can detect the phase difference between the active edge of the first single-line data signal DI and the active edge of the second single-line data signal DO, thereby adjusting the phase delay of the plurality of first delay clock signals output by the first delay-locked loop module relative to the active edge of the first reference clock signal clkr, and further changing the phase of the second single-line data signal DO. Through the complete negative feedback loop composed of the first delay-locked loop module and the data transmitting module, after the first delay-locked loop module is locked, the high-precision alignment of the active edge of the output data (the second single-line data signal DO) and the active edge of the input data (the first single-line data signal DI) can be achieved while the clock frequency is the same.

[0051] The data processing circuit of the embodiment of the present application can be applied to a driving chip in the field of LED display driving, for example. Figure 4As shown, the plurality of driving chips can be cascaded by only data signal lines, wherein, except for the last driving chip, the data receiving end of each driving chip is connected with a data signal line to receive the first single-line data signal DI; and the data sending end of each driving chip is connected with a data signal line to send the second single-line data signal DO. The last driving chip in the cascade can have both the data receiving end and the data sending end, or only the data receiving end to receive the first single-line data signal DI. Each driving chip can obtain its display data from the first single-line data signal DI to drive the lamp beads to emit light. Based on the data processing circuit of the embodiment of the present application, in the cascade of the plurality of driving chips, after the first delay phase-locked loop module is locked, the rising edge of the second single-line data signal DO is aligned with the rising edge of the first single-line data signal DI, or the falling edge of the second single-line data signal DO is aligned with the falling edge of the first single-line data signal DI, so that the output data (the second single-line data signal DO) and the input data (the first single-line data signal DI) are the same frequency and in phase. Since the output data of the upper driving chip in the cascade is the input data of the lower driving chip, the input data and the output data of the plurality of driving chips in the cascade are the same frequency and in phase, so that the data synchronization refresh between the plurality of driving chips in the single-line cascade is realized, the refresh delay is eliminated, the signal lines such as the clock signal line between the control card and the driving chip can be saved, and the application is suitable for some high-transmittance display screens such as the hole screen, the air-permeable screen, the sound-permeable screen and the like, which have higher requirements for the number of lines and the synchronization refresh.

[0052] Of course, the data processing circuit of the embodiment of the present application can also be applied to some other application fields to realize that the effective edge of the output data (the second single-line data signal DO) is aligned with the effective edge of the input data (the first single-line data signal DI) and is the same frequency. Based on different application scenarios, the requirements for aligning the effective edge of the output data with the effective edge of the input data are different, and the effective edge of the second single-line data signal (DO) is aligned with the effective edge of the first single-line data signal (DI) in the embodiment of the present application, which can be that the rising edge of DO is aligned with the rising edge of DI; or, the falling edge of DO is aligned with the falling edge of DI; or, the rising edge of DO is aligned with the falling edge of DI; or, the falling edge of DO is aligned with the rising edge of DI.

[0053] It is worth mentioning that the single-wire data signal (DI and DO) is a serial data sequence composed of multiple data 1 and multiple data 0 and encoded by duty cycle, and the duty cycle of each clock cycle of the data sequence is not fixed. The delay phase locked loop (DLL) is a clock adjustment circuit, which can adjust the output of the voltage-controlled delay chain according to the phase difference between the reference clock and the output clock, so that the phase of the output clock is consistent with that of the reference clock after locking. However, the working mechanism of the DLL depends on fixed periodicity and edge regularity, and the traditional DLL can only achieve the same phase of the output clock and the input reference clock, and cannot process the data signal with uncertain duty cycle, that is, the phase of the effective edge of the input data cannot be consistent with that of the output data. The first delay phase locked loop module provided in the embodiment of the present application also specially converts the first single-wire data signal DI or the inverted signal DIf of the first single-wire data signal DI into the first reference clock signal clkr. When the first delay phase locked loop module is locked, the duty cycle of each clock cycle of the first reference clock signal clkr is fixed. In this way, the first single-wire data signal DI with uncertain duty cycle is converted into the first reference clock signal clkr with fixed duty cycle, which not only realizes data conversion, but also provides an internal clock for the data processing circuit to process data, and adapts to the processing logic of the DLL. The converted first reference clock signal clkr is equivalent to the input reference clock of the first delay phase locked loop module, and the feedback clock is equivalent to the second single-wire data signal DO or the inverted signal of the second single-wire data signal DO. After the establishment process of the complete negative feedback loop composed of the first delay phase locked loop module and the data sending module, the problem that the traditional DLL cannot align the effective edges of the data is solved.

[0054] Optionally, the duty cycle of each clock cycle of the first reference clock signal clkr is 50% after the first delay phase locked loop module is locked. Optionally, the duty cycle of each clock cycle of the first reference clock signal clkr is 75% after the first delay phase locked loop module is locked. Of course, other numerical values can also be used, and the present application is not limited in this regard.

[0055] In the embodiment of the present application, the single-wire data signal DI and DO each include a waveform one representing data 0 and a waveform two representing data 1, and the waveform one and the waveform two each include a segment of high level with unequal duty cycles. Figure 5 As shown in the figure, the clock cycle of DI is T, the high level duty cycle of data 1 is 3 / 4 of the clock cycle T, and the high level duty cycle of data 0 is 1 / 4 of the clock cycle T. Alternatively, the high level duty cycle of data 1 is 1 / 4 of the clock cycle T, and the high level duty cycle of data 0 is 3 / 4 of the clock cycle T. The specific duty cycle can also be other numerical values, and the present application is not limited in this regard, as long as the data 0 and the data 1 can be distinguished.

[0056] The first plurality of delayed clock signals outputted by the first delay-locked loop module can include a first clock signal clk0, a second clock signal clk1, and a third clock signal clk2. The first clock signal clk0 has a phase delay of t1 compared to an active edge of a first reference clock signal clkr (hereinafter, the first reference clock signal clkr is referred to as clkr for simplicity in some descriptions below), the second clock signal clk1 has a phase delay of t2 compared to the active edge of the clkr, and the third clock signal clk2 has a phase delay of t3 compared to the active edge of the clkr, where t1 < t2 < t3. For example, referring to Figure 6 , the active edge of the first single-wire data signal DI is a rising edge, the active edge of the clkr is a rising edge, and after the first delay-locked loop module is locked, the first clock signal clk0 has a phase delay of t1 compared to the rising edge of the clkr, the second clock signal clk1 has a phase delay of t2 compared to the rising edge of the clkr, and the third clock signal clk2 has a phase delay of t3 compared to the rising edge of the clkr, where t1 < t2 < t3. For example, if the active edge of the first single-wire data signal DI is a falling edge, the active edge of the clkr is a falling edge, and after the first delay-locked loop module is locked, the first clock signal clk0, the second clock signal clk1, and the third clock signal clk2 all have different phase delays compared to the falling edge of the clkr.

[0057] For the first delay-locked loop module, the first delay-locked loop module according to the embodiment of the present application can specifically include a data-to-clock module and a voltage-controlled delay line (VCDL).

[0058] The first delay-locked loop module can be a DLL triggered by a rising edge or a DLL triggered by a falling edge. When the first delay-locked loop module is a DLL triggered by a rising edge, the first delay-locked loop module can compare whether a rising edge of the DO is aligned with a rising edge of the DI or whether a rising edge of an inverted signal of the DO is aligned with a rising edge of an inverted signal DIf of the DI. When the first delay-locked loop module is a DLL triggered by a falling edge, the first delay-locked loop module can compare whether a falling edge of the DO is aligned with a falling edge of the DI.

[0059] In an embodiment of the present application, the active edge of the first single-wire data signal DI is a rising edge, and the active edge of the second single-wire data signal DO is a rising edge. Referring to Figure 7, the first delay-locked loop module is a DLL triggered by a rising edge, an input end of the first delay-locked loop module inputs DI, and a feedback end inputs DO. The data-to-clock module is used for converting DI into a first reference clock signal clkr, and adjusting a waveform of the converted clkr according to an input target delay clock signal until the first delay-locked loop module is locked; the voltage-controlled delay chain is used for outputting a plurality of first delay clock signals with different phase delays compared with a rising edge of clkr, and adjusting a phase delay time of the first delay clock signals compared with the rising edge of clkr according to an input second control signal; wherein the second control signal is generated based on a phase difference between an active edge of the first single-wire data signal DI and an active edge of the second single-wire data signal DO, and the target delay clock signal is any one of the plurality of first delay clock signals.

[0060] In another embodiment of the present application, the active edge of the first single-wire data signal DI is a falling edge, and the active edge of the second single-wire data signal DO is a falling edge. Referring to Figure 8 , the first delay-locked loop module is a DLL triggered by a rising edge, an input end of the first delay-locked loop module inputs DI, and a feedback end inputs DO. The data-to-clock module is used for converting DI into a first reference clock signal clkr, and adjusting a waveform of the converted clkr according to an input target delay clock signal until the first delay-locked loop module is locked; the voltage-controlled delay chain is used for outputting a plurality of first delay clock signals with different phase delays compared with a rising edge of clkr, and adjusting a phase delay time of the first delay clock signals compared with the rising edge of clkr according to an input second control signal; wherein the second control signal is generated based on a phase difference between an active edge of the first single-wire data signal DI and an active edge of the second single-wire data signal DO, and the target delay clock signal is any one of the plurality of first delay clock signals.

[0061] In another embodiment of the present application, the active edge of the first single-wire data signal DI is a falling edge, and the active edge of the second single-wire data signal DO is a falling edge. Referring to Figure 9, the first delay-locked loop module is a falling edge triggered effective DLL, an input end of the first delay-locked loop module inputs the first single-wire data signal DI, and a feedback end inputs the second single-wire data signal DO. The data-to-clock module is used for converting the first single-wire data signal DI into a first reference clock signal clkr, and adjusting the waveform of the converted clkr according to an input target delay clock signal until the first delay-locked loop module is locked. The voltage-controlled delay chain is used for outputting a plurality of first delay clock signals with different phase delays compared with the falling edge of the clkr, and adjusting the phase delay time of the first delay clock signal compared with the falling edge of the clkr according to an input second control signal. The second control signal is generated based on the phase difference between the effective edge of the first single-wire data signal DI and the effective edge of the second single-wire data signal DO, and the target delay clock signal is any one of the plurality of first delay clock signals.

[0062] As shown in Figure 2 , Figure 3 and Figures 7-9 , the embodiment of the present application sets a data-to-clock module in the traditional DLL module. The data-to-clock module can convert the data-to-clock of DI or the inverted signal DIf of DI, and then output the converted first reference clock signal clkr to the voltage-controlled delay chain. The voltage-controlled delay chain can output a plurality of first delay clock signals with different phase delays compared with the clkr. In this process, one of the plurality of first delay clock signals will be fed back to the data-to-clock module as a target delay clock signal. The data-to-clock module adjusts the waveform of the clkr according to the input target delay clock signal until the first delay-locked loop module is locked. After the first delay-locked loop module is locked, the duty cycle of each clock cycle of the first reference clock signal clkr is fixed.

[0063] Other structures in the first delay-locked loop module can refer to the related prior art of DLL, which is not limited by the present application. For example, continuing to refer to Figures 7-9 , the first delay-locked loop module can further include a phase detector, a charge pump circuit, and a loop filter.

[0064] The phase detector (PD) is used for detecting the phase difference between the effective edge of the first single-wire data signal DI and the effective edge of the second single-wire data signal DO, and outputting a first control signal. Optionally, as shown in Figure 7 , the first delay-locked loop module is a rising edge triggered effective DLL, and the phase detector can detect the phase difference between the rising edge of DI and the rising edge of DO, and then output the first control signal. Optionally, as shown in Figure 8As shown, the first delay-locked loop module is a rising edge triggered DLL, the phase detector can detect the phase difference between the rising edge of the inverted signal DIf of DI and the rising edge of the inverted signal of DO, and then output the first control signal. Optionally, as shown in FIG. 2B, the first delay-locked loop module is a falling edge triggered DLL, the phase detector can detect the phase difference between the falling edge of DI and the falling edge of DO, and then output the first control signal. Figure 9 As shown, the first delay-locked loop module is a rising edge triggered DLL, the phase detector can detect the phase difference between the rising edge of the inverted signal DIf of DI and the rising edge of the inverted signal of DO, and then output the first control signal. Optionally, as shown in FIG. 2B, the first delay-locked loop module is a falling edge triggered DLL, the phase detector can detect the phase difference between the falling edge of DI and the falling edge of DO, and then output the first control signal.

[0065] The charge pump circuit outputs a current signal based on the first control signal. The first control signal is usually a digital pulse signal, so the charge pump circuit converts the first control signal into an analog current signal.

[0066] The loop filter usually includes a capacitor C, and the loop filter charges or discharges based on the current signal to adjust the output second control signal. The second control signal can be a control voltage (V_ctrl), and the loop filter can adjust the voltage of the second control signal by charging or discharging the current signal, and the voltage of the second control signal reflects the accumulated phase error.

[0067] The voltage-controlled delay chain VCDL is the actuator of the DLL, which can be composed of a series of delay units (such as inverters), and the total delay time (T_delay) of the entire chain is controlled by the second control signal. In the embodiment of the present application, the second control signal is generated based on the phase difference between the active edge of the first single-wire data signal and the active edge of the second single-wire data signal, and the voltage-controlled delay chain is used to adjust the phase delay time of the output multiple first delay clock signals compared with the active edge of the first reference clock signal clkr according to the input second control signal.

[0068] The circuit structure and closed-loop feedback of the phase detector, charge pump circuit, loop filter and voltage-controlled delay chain VCDL, as well as the implementation principle of the locking process, can refer to the related explanations of the existing DLL, which are not limited here.

[0069] In a specific circuit framework, the data clock conversion module of the embodiment of the present application can include a frequency division module, a first flip-flop module and a second flip-flop module. The frequency division module performs frequency division based on the first single-line data signal DI and outputs a frequency division signal; the first edge flip-flop module samples the frequency division signal based on the first single-line data signal DI and outputs a first reference clock signal clkr; the second edge flip-flop module is used to sample a high-level signal logic_l according to a target delay clock signal (represented by a second clock signal clk1 in various figures) and reset based on the first reference clock signal clkr, and outputs a second reset signal rst to the frequency division module and the first edge flip-flop module; wherein after the first delay phase-locked loop module is locked, the second reset signal rst controls the frequency division module and the first edge flip-flop module to reset in each clock cycle of the first single-line data signal DI.

[0070] In the embodiment, the frequency division module performs frequency division based on the first single-line data signal DI and the first edge flip-flop module samples the frequency division signal based on the first single-line data signal DI, which can have the following implementation ways: as shown in Figure 10 some implementation ways, the frequency division module performs frequency division on the first single-line data signal DI and outputs a frequency division signal, and the first edge flip-flop module samples the frequency division signal according to the first single-line data signal DI and outputs a first reference clock signal clkr. In other implementation ways (not shown in the figure), the frequency division module performs frequency division on the inverse signal DIf of the first single-line data signal DI and outputs a frequency division signal, and the first edge flip-flop module samples the frequency division signal according to the inverse signal DIf of the first single-line data signal DI and outputs a first reference clock signal clkr.

[0071] In the circuit framework of the data-to-clock module, the second trigger module can be understood as a detection module. The second trigger module samples the high-level signal `logic_l` using the target delayed clock signal to detect the state of the target delayed clock signal, thereby detecting whether the voltage-controlled delay chain (VCDL) is working properly. When the target delayed clock signal is not detected, the second reset signal `rst` output by the second trigger module remains stable, keeping the frequency divider module and the first edge trigger module in their current operating state. When the target delayed clock signal is detected, the second reset signal `rst` output by the second trigger module becomes valid, forcibly resetting the frequency divider module and the first edge trigger module. Since the target delayed clock signal is one of multiple first delayed clock signals output by the first delay phase-locked loop (PLL) module, when the PLL module is locked, the clock period of the target delayed clock signal is fixed (i.e., the same frequency as the clock period of the first single-line data signal DI). Therefore, the target delayed clock signal is detected by the second trigger module once per clock cycle, and the second reset signal `rst` output by the second trigger module becomes valid once per clock cycle to control the frequency divider module and the first edge trigger module to reset. Correspondingly, the first trigger module will periodically generate the first reference clock signal clkr, causing the second edge trigger module to reset once per clock cycle.

[0072] Since the first reference clock signal clkr output by the first edge-triggered module is controlled by the first single-line data signal DI and the second reset signal rst, and the second reset signal rst is inherently affected by the target delayed clock signal, the waveform of the first reference clock signal clkr is determined by the first single-line data signal DI and the target delayed clock signal. Theoretically, without considering the inherent delay of devices such as triggers, after the first delay phase-locked loop module is locked, if the effective edge of DI is a rising edge, then the rising edge of clkr is aligned with the rising edge of DI, and the falling edge of clkr is aligned with the rising edge of the target delayed clock signal.

[0073] Furthermore, some implementation methods can be illustrated with specific circuits such as... Figure 11As shown, the frequency divider module can be implemented using cascaded N-stage D flip-flops, where N ≥ 1. In the N-stage D flip-flops, the data input (D terminal) and the inverted state output (QN terminal) of each stage are connected together, and the reset terminal (RN terminal) is used to connect to the second reset signal rst. The clock terminal (CK terminal) of the first stage D flip-flop is used to connect to the first single-wire data signal DI, and the clock terminals of the remaining stages are connected to the inverted state output of their preceding stages. The last stage D flip-flop, with its data input and inverted state output connected together, outputs the frequency divider signal. There can be one or more D flip-flops, meaning N can be one or more, typically multiple, to detect abnormal operation of the first delay phase-locked loop module. Optionally, N is 3. (Continue to refer to...) Figure 11 The first edge-triggered module may include a second D flip-flop. The clock terminal (CK terminal) of the second D flip-flop is used to connect to the first single-wire data signal DI, the data input terminal (D terminal) is used to connect to the frequency divider signal, the status output terminal (Q terminal) is used to output the first reference clock signal clkr, and the reset terminal (RN terminal) is used to connect to the second reset signal rst. The second edge-triggered module may include a third D flip-flop. The clock terminal (CK terminal) of the third D flip-flop is used to connect to the target delayed clock signal, the reset terminal is used to connect to the first reference clock signal clkr, the data input terminal (D terminal) is used to connect to the high-level signal logic_l, and the status output terminal (Q terminal) outputs the second reset signal rst, or the status output terminal outputs the second reset signal rst after passing through an inverter.

[0074] In some implementations, when the effective edge of the first single-line data signal is a falling edge, the clock input (i.e., the CK input) of the first-stage D flip-flop can be connected to the inverted signal of the first single-line data signal DI, and correspondingly, the clock input (i.e., the CK input) of the second D flip-flop can also be connected to the inverted signal of the first single-line data signal DI. The specific structure can be the same as... Figure 11 Similarly, I will not elaborate further here.

[0075] In embodiments of the present invention, such as Figures 7-11 As shown, the target delayed clock signal can be the second clock signal clk1. That is, the second clock signal clk1 will be fed back to the data-to-clock module, which will adjust the waveform of the first reference clock signal clkr according to the input clk1 until the first delay phase-locked loop module locks. Next, taking the target delayed clock signal as the second clock signal clk1 as an example, [the following section discusses...] Figure 11 The circuit shown is explained.

[0076] Before the first delay phase-locked loop module is locked, clk1 either does not oscillate or does not meet the requirement of being at the same frequency as the first single-wire data signal DI. Here, we take the case where clk1 does not oscillate as an example; the detailed timing diagram is as follows. Figure 12As shown, the three-stage D flip-flops at the DI input all implement a 2-division multiple, meaning out1 is 2 times the first single-line data signal DI, out2 is 2 times the first single-line data signal DI, and out3 is 2 times the first single-line data signal DI. In the second D flip-flop, out3 is sampled on the rising edge of the first single-line data signal DI, so clkr is delayed by one clock cycle compared to out3. Since clk1 is not oscillating and is 0, the third D flip-flop remains in the reset state and outputs 0. This output is then connected to the reset terminals of each of the first and second D flip-flops via an inverter, preventing the first and second D flip-flops from resetting.

[0077] After the first delay phase-locked loop module is locked, its detailed internal timing diagram is as follows: Figure 13 As shown, clk1 and the first single-line data signal DI have the same frequency. The second reset signal rst activates once per clock cycle, causing the 8-fold frequency division implemented by the first three-stage D flip-flop to fail before being reset, resulting in out2 and out3 outputs always being high. Since the rising edge of DI is sampled as a high-level signal to obtain the first reference clock signal clkr, after the first delay-locked loop module is locked, the rising edge of the first reference clock signal clkr is basically aligned with the rising edge of DI. After clkr equals 1, the second D flip-flop is reset. Since the clock period of clk1 is fixed after the first delay-locked loop module is locked, when the rising edge of clk1 arrives, the third D flip-flop outputs the second reset signal rst = 1. After the second reset signal rst = 1, the first and second three-stage D flip-flops are reset, causing clkr to go low. Figure 13 As shown, after the first delay phase-locked loop module is locked, the rising edge of the first reference clock signal clkr is aligned with the first single-line data signal DI, and the falling edge of the first reference clock signal clkr is aligned with the rising edge of clk1, thus achieving the same frequency for clkr and DI, and a duty cycle of 50%.

[0078] In this embodiment of the invention, the data transmission module generates a second single-wire data signal DO based on the input third data signal Datao and the first delayed clock signal. The third data signal Datao is obtained based on the first single-wire data signal DI, and can be obtained based on the following implementation methods:

[0079] In some implementations, such as Figure 2 As shown, the data processing circuit may further include a data recovery module. This data recovery module generates a recovered data signal Ck_data based on the inputs DI and clk1, wherein the third data signal Datao is obtained based on the recovered data signal Ck_data.

[0080] Furthermore, the third data signal Datao can be the recovered data signal Ck_data. Alternatively, the third data signal Datao can also be the processed data from the recovered data signal Ck_data, such as... Figures 7-9 As shown, the data processing circuit may further include a data recovery module and a logic circuit. The data recovery module generates a recovered data signal Ck_data based on the inputs DI and clk1; the logic circuit takes the recovered data signal Ck_data as input and outputs a third data signal Datao.

[0081] In other implementations, such as Figure 3 As shown, the data processing circuit may further include a second delay phase-locked loop (PLL) module and a data recovery module. The second PLL module converts the first single-line data signal to obtain a second reference clock signal, and based on the phase difference between the detected first single-line data signal and its feedback clock signal, outputs multiple second delayed clock signals with different phase delays relative to the effective edges of the second reference clock signal; wherein the feedback clock signal is any one of the multiple second delayed clock signals. The data recovery module generates a recovered data signal Ck_data based on the input first single-line data signal DI and one of the multiple second delayed clock signals (specifically, it can be the second clock signal clk1 among the multiple second delayed clock signals), and the third data signal Datao is obtained based on the recovered data signal Ck_data.

[0082] Figure 3 In the implementation of the framework shown, the third data signal Datao is obtained based on the recovered data signal Ck_data, and there are two specific implementation methods: the first is that the third data signal Datao is the recovered data signal Ck_data; the second is that the third data signal Datao is the processed data of the recovered data signal Ck_data. If the third data signal Datao is the processed data of the recovered data signal Ck_data, optionally, in Figure 3 Within the framework shown, the data processing circuit may also include logic circuits (not shown in the figure). The logic circuits input the recovered data signal Ck_data and output the third data signal Datao. The internal circuit structure of the second delay-locked loop module is basically the same as that of the first delay-locked loop module. Refer to the relevant explanations in the introduction to the structure and principle of the first delay-locked loop module. That is, the second delay-locked loop module also includes a data-to-clock module and a voltage-controlled delay chain (VCDL), etc., which will not be elaborated here.

[0083] Figure 3In the implementation of the framework shown, the clock signal (i.e., multiple second-delayed clock signals) upon which the data recovery of the first single-line data signal DI to generate the third data signal Datao depends has a different source than the clock signal (i.e., the first-delayed clock signal) upon which the data transmission module depends to generate the second single-line data signal DO. The first delay-locked loop module generates multiple first-delayed clock signals based on the first single-line data signal DI, and the second delay-locked loop module generates multiple second-delayed clock signals based on the first single-line data signal DI. Unlike the first delay-locked loop module, the feedback data for phase detection in the second delay-locked loop module is not the second single-line data signal DO, but rather its output feedback clock signal, which is any one of the multiple second-delayed clock signals. By employing both the first and second delay-locked loop modules to achieve the objective of this invention, circuit stability can be improved.

[0084] In the above embodiments, such as Figures 7-9 As shown, the data recovery module can be implemented using a D flip-flop (D flip-flop six).

[0085] exist Figure 7 In the circuit structure shown, the clock input of the D flip-flop six is ​​used to receive the second clock signal clk1, the data input (i.e., the D terminal) is used to receive the first single-line data signal DI, and the state output (i.e., the Q terminal) outputs the recovered data signal Ck_data. The recovered data signal Ck_data is obtained by sampling the first single-line data signal DI based on the rising edge of the second clock signal clk1; its waveform can be referenced. Figure 14 That is, at each rising edge of the second clock signal clk1, if the first single-line data signal DI is low, the recovered data signal Ck_data is low; if the first single-line data signal DI is high, the recovered data signal Ck_data is high.

[0086] exist Figure 8 and Figure 9 In the circuit structure shown, the clock input of the D flip-flop six is ​​used to receive the second clock signal clk1, the data input (i.e., the D input) is used to receive the inverted signal DIf of the first single-wire data signal DI, and the state output (i.e., the Q input) outputs the recovered data signal Ck_data. Its principle is similar to... Figure 7 Similarly, I won't go into details here.

[0087] Continue to refer to Figures 7-9The data transmission module may include a first module and a second module. The first module samples the third data signal Datao based on the input fourth clock signal clk3, and selects whether the falling edge of the second single-wire data signal DO is aligned with the edge of the first clock signal clk0 or the edge of the third clock signal clk2 based on the third data signal Datao, and outputs a first reset signal data_rn. The second module samples the high-level signal logic_l based on the fourth clock signal clk3, resets it based on the first reset signal data_rn, and outputs the second single-wire data signal DO.

[0088] In some implementations, the fourth clock signal clk3 can be directly generated by the first delay phase-locked loop module, such as... Figure 2 , Figure 3 as well as Figures 7-9 As shown. After the first delay-locked loop module locks, the fourth clock signal clk3 can be delayed by exactly one clock cycle compared to the first reference clock signal clkr (understandably, the phase delay time of the effective edge of the fourth clock signal clk3 compared to the first reference clock signal clkr is t4, t4 > t3). For example, if the effective edge of the first single-line data signal DI is a rising edge and the effective edge of the first reference clock signal clkr is a rising edge, the waveform of the fourth clock signal clk3 can be shown as follows. Figure 6 As shown, after the first delay phase-locked loop module is locked, the rising edges of the fourth clock signal clk3 and clkr are aligned. Since the rising edges of clkr and DI are aligned, the rising edges of clk3 are also aligned with the rising edges of DI. For example, if the effective edge of the first single-line data signal DI is a falling edge, then the effective edge of the first reference clock signal clkr is a falling edge. After the first delay phase-locked loop module is locked, the falling edge of the fourth clock signal clk3 is aligned with the falling edge of clkr. Since the falling edges of clkr and DI are aligned, the falling edges of clk3 are also aligned with the falling edges of DI.

[0089] In other embodiments (not shown in the figure), the fourth clock signal clk3 can also be generated based on the first single-line data signal DI and the second clock signal clk1. For example, the rising edge of clk3 is aligned with the rising edge of DI, and the falling edge of clk3 is aligned with the rising edge of clk1. The generation of the fourth clock signal clk3 based on the first single-line data signal DI and the second clock signal clk1 can be implemented using structures such as flip-flops or multi-stage inverters; this embodiment does not impose any limitations.

[0090] Regarding the specific structure of the first and second modules, such as Figure 7As shown, the first module may include a fourth D flip-flop, a second inverter, and an edge detection module, while the second module may include a fifth D flip-flop. The clock input (CK input) of the fourth D flip-flop receives the fourth clock signal clk3, the data input (D input) receives the third data signal Datao, and the state output (Q input) outputs the data signal d0, which is then output as data signal d1 via the second inverter. The edge detection module generates a first low-level pulse signal rn_clk0 based on the input first clock signal clk0, aligned with the rising edge of the data signal d0. It also generates a second low-level pulse signal rn_clk2 based on the input third clock signal clk2, aligned with the rising edge of the data signal d1. The module then performs logical processing on the first low-level pulse signal rn_clk0, the second low-level pulse signal rn_clk2, and the data signals d0 and d1, outputting a first reset signal data_rn.

[0091] In an embodiment, such as Figure 7 As shown, the first clock signal clk0 and the third clock signal clk2 are used to generate data 0 and data 1 in the second single-line data signal DO. When designing and controlling the voltage-controlled delay chain of the first delay phase-locked loop module, t1 and t3 can be determined based on waveform one representing data 0 and waveform two representing data 1. Optionally, 0° < t1 < 180°, 180° < t3 < 360°. Since the first module selects the falling edge of DO to align with the edge of the first clock signal clk0 or the edge of the third clock signal clk2 based on the third data signal Datao, it outputs the first reset signal data_rn. Therefore, the waveform of data_rn represents whether the selection object of the third data signal Datao is the edge of the first clock signal clk0 or the edge of the third clock signal clk2, and thus represents whether data 1 or data 0 in the second single-line data signal DO is generated. This embodiment of the invention corresponds to... Figure 7 The waveform diagrams for generating data signals d0 and d1 are provided as follows: Figure 15 As shown, the waveform of the first reset signal data_rn generated based on data signal d0 and data signal d1 is as follows. Figure 16 As shown.

[0092] The specific implementation circuit for logically processing the first low-level pulse signal rn_clk0, the second low-level pulse signal rn_clk2, and data signals d0 and d1 to output the first reset signal data_rn can be as follows: Figure 7 As shown, the waveform is as follows Figure 16As shown: Data signal d0 actually represents data 0, and data signal d1 actually represents data 1. The first low-level pulse signal rn_clk0 is ORed with data signal d0 to obtain signal A; the second low-level pulse signal rn_clk2 is ORed with data signal d1 to obtain signal B; signals A and B are then ORed with each other to obtain the first reset signal data_rn.

[0093] Continue to refer to Figure 7 The clock input of the D flip-flop 5 is used to receive the fourth clock signal clk3, the data input is used to receive the high-level signal logic_l, the reset input is used to receive the first reset signal data_rn, and the status output outputs the second single-wire data signal DO. The corresponding waveform diagram is shown below. Figure 17 As shown, since the D flip-flop 5 samples the high-level signal logic_l according to the fourth clock signal clk3, when the rising edge of the fourth clock signal clk3 arrives, the high-level signal logic_l is sampled, and the DO output by the state output terminal generates a rising edge. Without considering the inherent delay of the D flip-flop 5, the rising edge of DO is aligned with the rising edge of clk3. Based on the prior knowledge that the rising edge of clk3 is aligned with the rising edge of the first single-line data signal DI, theoretically, the rising edge of DO is aligned with the rising edge of the first single-line data signal DI. Furthermore, since the D flip-flop 5 is reset based on the first reset signal data_rn in each clock cycle, and the waveform of the first reset signal data_rn can generate the falling edge of DO, the generation and output of DO are ultimately realized.

[0094] It is worth emphasizing that, in this embodiment of the invention, since the second single-line data signal DO is also input to the first delay-locked loop module as a feedback signal, the first delay-locked loop module identifies the phase difference between DI and DO, thereby adjusting the phase delay of its output multiple first delayed clock signals relative to the first reference clock signal clkr, and thus adjusting the phase of DO. Therefore, when the first delay-locked loop module is locked, this embodiment of the invention does not only theoretically achieve the effect of aligning the effective edge of the second single-line data signal DO with the effective edge of the first single-line data signal DI at the same clock frequency, but can also achieve this effect in practice, such as aligning the rising edge of the second single-line data signal with the rising edge of the first single-line data signal, or aligning the falling edge of the second single-line data signal with the falling edge of the first single-line data signal. Figure 7 The illustrated embodiment shows a waveform diagram of the second single-line data signal DO and the first single-line data signal DI achieving synchronous frequency and phase. Figure 18 As shown.

[0095] In such Figure 8 and Figure 9In this embodiment, the state output of D flip-flop five outputs a second single-line data signal DO via inverter three. The corresponding waveform is not shown. The relevant structure, principle, and effect can be explained in the preceding text and will not be repeated here. Figure 3 In the implementation of the framework shown, in addition to the second delay-locked loop module, the data processing circuit may also include a data recovery module and a data transmission module. Figure 2 The various embodiments of the circuit shown are basically the same, and will not be described in detail here.

[0096] A second aspect of the present invention provides a driver chip, which includes a data processing circuit as described in the first aspect of the present invention, such as... Figure 4 As shown, the driver chip receives a first single-line data signal DI through a data signal line and / or transmits a second single-line data signal DO through a data signal line. This driver chip can be a column driver chip or a row driver chip used to drive an LED array.

[0097] The third aspect of the present invention provides an LED array driving system (not shown in the figure), which includes H row driving chips cascaded through a single data signal line and L column driving chips cascaded through a single data signal line. The row driving chips and column driving chips are both driving chips of the second aspect of the present invention, and the H row driving chips and L column driving chips jointly drive the LED array display.

[0098] The LED array mentioned in the various embodiments of this invention can specifically be an LED display screen. The LED array is driven by one or more sets of single-line cascaded row driver chips and one set of single-line cascaded column driver chips. However, depending on the actual application scenario of the LED array, the number and structure of the row driver chips used to drive the LED array vary. Specifically, it can be a dot matrix display screen structure or a light strip display screen structure. Regardless of whether the LED array is a dot matrix display screen structure or a light strip display screen structure, compared with the prior art, the single-line cascaded driving structure for both row and column drivers greatly saves wiring space and facilitates control of the display screen's transparency.

[0099] In the dot matrix display structure (not shown in the figure), the LED array is driven by a set of H cascaded row driver chips (shown as row transistors in the figure) and a set of L cascaded column driver chips. In the light strip display structure (not shown in the figure), in the LED array, each column pixel is driven by a set of M cascaded row driver chips (shown as row transistors in the figure) and a corresponding column driver chip.

[0100] The LED array can consist of X rows and L columns of pixels, with each of the L columns of pixels connected to one of the L column driver chips. Each pixel includes m LEDs of different colors, where m ≥ 1. That is, the pixels in this LED array can be monochrome or multi-color pixels. Optionally, m is 3, and each pixel includes three LEDs of different colors: red, green, and blue. One column driver chip simultaneously drives all three colors of LEDs for display.

Claims

1. A data processing circuit, characterized by, The data processing circuit comprises: a first delay-locked loop module configured to detect a phase difference between an active edge of a first single-wire data signal and an active edge of a second single-wire data signal, convert a first reference clock signal based on the first single-wire data signal, and output a plurality of first delay clock signals with different phase delays compared to an active edge of the first reference clock signal based on the phase difference; a data sending module configured to generate the second single-wire data signal based on a third data signal input and the first delay clock signal, wherein the third data signal is obtained based on the first single-wire data signal; after the first delay-locked loop module is locked, a duty cycle of each clock cycle of the first reference clock signal is fixed, the active edge of the second single-wire data signal is aligned with the active edge of the first single-wire data signal, the second single-wire data signal, the first reference clock signal and the first single-wire data signal have the same clock frequency; the first single-wire data signal and the second single-wire data signal each comprise a waveform one representing data 0 and a waveform two representing data 1, and the waveform one and the waveform two each comprise a segment of high level with unequal duty cycles.

2. The data processing circuit according to claim 1, wherein the active edge of the second single-wire data signal is aligned with the active edge of the first single-wire data signal, comprising: a rising edge of the second single-wire data signal is aligned with a rising edge of the first single-wire data signal; or, a falling edge of the second single-wire data signal is aligned with a falling edge of the first single-wire data signal; or, a rising edge of the second single-wire data signal is aligned with a falling edge of the first single-wire data signal; or, a falling edge of the second single-wire data signal is aligned with a rising edge of the first single-wire data signal. the plurality of first delay clock signals comprise a first clock signal, a second clock signal and a third clock signal; 3. The data processing circuit of claim 1, wherein, wherein a phase delay time of the first clock signal compared to the active edge of the first reference clock signal is t1, a phase delay time of the second clock signal compared to the active edge of the first reference clock signal is t2, and a phase delay time of the third clock signal compared to the active edge of the first reference clock signal is t3, t1 < t2 < t3.

4. The data processing circuit according to claim 3, wherein the first delay-locked loop module comprises a data-to-clock module and a voltage-controlled delay chain; the data-to-clock module is configured to convert the first single-wire data signal or an inverted signal of the first single-wire data signal into a first reference clock signal, and adjust a waveform of the converted first reference clock signal according to a target delay clock signal input until the first delay-locked loop module is locked; the voltage-controlled delay chain is configured to output a plurality of first delay clock signals with different phase delays compared to the active edge of the first reference clock signal, and adjust a phase delay time of the first delay clock signal compared to the active edge of the first reference clock signal according to a second control signal input. ​ ​ The second control signal is generated based on the phase difference, and the target delay clock signal is any one of the plurality of first delay clock signals.

5. The data processing circuit of claim 4, wherein wherein The target delay clock signal is the second clock signal.

6. The data processing circuit of claim 3, wherein The data transmitting module comprises: a first module configured to sample the third data signal according to an input fourth clock signal, to select a falling edge of the second single-wire data signal to align with an edge of the first clock signal or an edge of the third clock signal based on the third data signal, and to output a first reset signal; a second module configured to sample a high-level signal according to the fourth clock signal, to reset based on the first reset signal, and to output the second single-wire data signal; wherein the fourth clock signal is generated by the first delay phase-locked loop module, or the fourth clock signal is generated based on the first single-wire data signal and the second clock signal.

7. The data processing circuit of claim 3, wherein The data processing circuit further comprises a data recovery module; The data recovery module generates a recovered data signal based on the input first single-wire data signal and the second clock signal, and the third data signal is obtained based on the recovered data signal. or The data processing circuit further comprises a second delay phase-locked loop module and a data recovery module; The second delay phase-locked loop module converts the first single-wire data signal to obtain a second reference clock signal, and outputs a plurality of second delay clock signals with different phase delays compared to effective edges of the second reference clock signal based on a detected phase difference between the first single-wire data signal and a feedback clock signal of the plurality of second delay clock signals, wherein the feedback clock signal is any one of the plurality of second delay clock signals; The data recovery module generates a recovered data signal based on the input first single-wire data signal and the second delay clock signal, and the third data signal is obtained based on the recovered data signal.

8. The data processing circuit of claim 7, wherein The data processing circuit further comprises a logic circuit; wherein the logic circuit inputs the recovered data signal and outputs the third data signal.

9. The data processing circuit of claim 4, wherein The data conversion clock module comprises: a frequency division module configured to divide the frequency of the first single-wire data signal to output a frequency division signal; a first edge trigger module configured to sample the frequency division signal based on the first single-wire data signal to output the first reference clock signal; a second edge trigger module configured to sample a high-level signal according to the target delay clock signal, to reset based on the first reference clock signal, and to output a second reset signal to the frequency division module and the first edge trigger module. The second reset signal controls the frequency division module and the first edge trigger module to reset in each clock cycle of the first single-wire data signal after the first delay phase-locked loop module is locked.

10. The data processing circuit according to claim 9, characterized in that, the frequency division module comprises N-stage D flip-flops in cascade, N≥1; in the N-stage D flip-flops, the data input end and the state inverse output end of each D flip-flop are connected in common, and the reset end is used for connecting the second reset signal; the clock end of the first-stage D flip-flop is used for connecting the first single-wire data signal or the inverse signal of the first single-wire data signal, the clock end of the rest D flip-flops is used for connecting the state inverse output end of the previous-stage D flip-flop, and the data input end and the state inverse output end of the last-stage D flip-flop are connected in common to output the frequency division signal.

11. The data processing circuit according to claim 9, characterized in that, the first edge trigger module comprises a D flip-flop two, the clock end of the D flip-flop two is used for connecting the first single-wire data signal or the inverse signal of the first single-wire data signal, the data input end is used for connecting the frequency division signal, the state output end is used for outputting the first reference clock signal, and the reset end is used for connecting the second reset signal; the second edge trigger module comprises a D flip-flop three, the clock end of the D flip-flop three is used for connecting the target delay clock signal, the reset end is used for connecting the first reference clock signal, the data input end is used for connecting a high-level signal, and the state output end outputs the second reset signal or outputs the second reset signal after being inverted by an inverter one.

12. The data processing circuit according to claim 6, characterized in that, the first module comprises: a D flip-flop four and an inverter two, the clock end of the D flip-flop four is used for receiving a fourth clock signal, the data input end is used for receiving the third data signal, and the state output end outputs a data signal d0 and outputs a data signal d1 after being inverted by the inverter two; an edge detection module, which generates a first low-level pulse signal for aligning with the rising edge of the data signal d0 based on the input first clock signal, generates a second low-level pulse signal for aligning with the rising edge of the data signal d1 based on the input third clock signal, and logically processes the first low-level pulse signal, the second low-level pulse signal, and the data signal d0 and the data signal d1 to output a first reset signal; the second module comprises: a D flip-flop five, the clock end of which is used for receiving a fourth clock signal, the data input end of which is used for receiving a high-level signal, the reset end of which is used for connecting the first reset signal, and the state output end of which outputs the second single-wire data signal or outputs the second single-wire data signal after being inverted by an inverter three.

13. The data processing circuit according to claim 4, characterized in that, the first delay phase-locked loop module further comprises a phase detector, a charge pump circuit, and a loop filter. The phase detector is configured to detect a phase difference between an active edge of the first single-wire data signal and an active edge of the second single-wire data signal, and output a first control signal; The charge pump circuit is configured to output a current signal based on the first control signal; The loop filter is configured to charge or discharge based on the current signal to adjust the second control signal output.

14. A driver chip, characterized by comprising: The driving chip receives a first single-wire data signal through one data signal line and / or transmits a second single-wire data signal through one data signal line, and comprises the data processing circuit according to any one of claims 1-13.

15. The driver chip of claim 14, wherein, The driving chip is a column driving chip or a row driving chip for driving an LED display screen.

16. An LED array driving system, characterized by, The LED array display comprises H row driving chips cascaded through one data signal line and L column driving chips cascaded through one data signal line, wherein the row driving chips and the column driving chips are both the driving chip according to claim 14, and the H row driving chips and the L column driving chips jointly drive the LED array display.

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