Method for evaluating feature size of semiconductor device

Abstract

The invention relates to the technical field of self-alignment patterning processes, in particular to a method for evaluating the feature size of a semiconductor device. The method comprises the following steps: placing a wafer in a partition chuck, and processing the wafer through a self-alignment patterning process to obtain a plurality of empty slots; in the oxide etching step, the temperature difference between any two subareas of the subarea chuck is greater than zero, the highest temperature is higher than or equal to the reference temperature, and the lowest temperature is lower than or equal to the reference temperature; obtaining the feature size balance degree of each partition corresponding to the wafer; and according to the temperature of each partition of the partition chuck and the corresponding feature size balance degree, the size relation between the feature size of the core area and the feature size of the gap at the reference temperature is determined. According to the semiconductor device feature size evaluation method provided by the invention, the feature size relationship between the core area and the gap of the wafer can be quickly determined, the process debugging efficiency is improved, the process debugging cost is reduced, and the conclusion accuracy is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of self-aligned patterning process, in particular to a method for evaluating feature size of semiconductor device. BACKGROUND

[0002] As advanced multiple lithography technology, SADP (Self-Aligned Double Patterning) process and SAQP (Self-Aligned Quadruple Patterning) process can realize high resolution and small feature size, so as to improve the integration and performance of chips. In actual process debugging, due to the influence of CD (feature size), Open ratio (open hole rate), etch amount (etching amount) and other factors, the Core CD (feature size of core area) and the Gap CD (feature size of gap) may deviate, and finally the feature size imbalance (IMB) of Core and Gap may be poor, so it is very important to determine the CD problem in process debugging, and subsequent IMB improvement needs to be based on this condition.

[0003] In the related art, the CD problem is determined by observing the wafer slice through TEM (Transmission Electron Microscope), which is not only time-consuming and costly. SUMMARY

[0004] The present application aims to provide a method for evaluating feature size of semiconductor device to alleviate the technical problems of long time and high cost in determining the CD problem in the related art.

[0005] The present application provides a method for evaluating feature size of semiconductor device, comprising:

[0006] In the process step, the wafer is placed on a partition chuck, and the wafer is processed by a self-aligned patterning process to obtain a plurality of air slots; in the oxide etching step of the self-aligned patterning process, the temperature difference between any two partitions of the partition chuck is greater than zero, the highest temperature of the partition chuck is higher than or equal to a reference temperature, and the lowest temperature of the partition chuck is lower than or equal to the reference temperature;

[0007] In the acquisition step, the feature size balance of the wafer corresponding to each partition is obtained; wherein the feature size balance is the absolute value of the feature size difference between two adjacent air slots, and the air slot includes a core area and a gap;

[0008] determining the size relationship between the feature size of the core region and the feature size of the gap at the reference temperature according to the temperature of each partition of the partition chuck and the corresponding feature size balance degree.

[0009] Preferably, as an implementable manner, the temperatures of the several partitions gradually decrease or increase from inside to outside along the radial direction from the center of the partition chuck.

[0010] Preferably, as an implementable manner, the temperature of the innermost partition is consistent with the reference temperature.

[0011] Preferably, as an implementable manner, the determining step comprises:

[0012] Under the condition that the temperature of the partition chuck gradually decreases from inside to outside, if the feature size balance degree gradually decreases or first decreases and then increases from the center to the edge of the wafer, it is determined that the feature size of the core region is smaller than the feature size of the gap at the reference temperature; if the feature size balance degree gradually increases from the center to the edge of the wafer, it is determined that the feature size of the core region is larger than the feature size of the gap at the reference temperature.

[0013] Under the condition that the temperature of the partition chuck gradually increases from inside to outside, if the feature size balance degree gradually decreases or first decreases and then increases from the center to the edge of the wafer, it is determined that the feature size of the core region is larger than the feature size of the gap at the reference temperature; if the feature size balance degree gradually increases from the center to the edge of the wafer, it is determined that the feature size of the core region is larger than the feature size of the gap at the reference temperature.

[0014] Preferably, as an implementable manner, the several partitions comprise a center partition, a middle-in partition, a middle-out partition and an edge partition which are sequentially distributed from inside to outside along the radial direction from the center of the partition chuck.

[0015] Preferably, as an implementable manner, the temperature difference between two adjacent partitions of the partition chuck is less than or equal to 5℃.

[0016] Preferably, as an implementable manner, the temperature difference between two adjacent partitions of the partition chuck is 4℃.

[0017] Preferably, as an implementable manner, the obtaining step comprises:

[0018] measuring the feature sizes of the plurality of empty slots and determining the corresponding relationship between the feature size of each empty slot and the measurement position;

[0019] According to the corresponding relationship, two adjacent air slots are divided into a group.

[0020] The characteristic size balance degree and the corresponding position are obtained by respectively subtracting the characteristic size of two air slots in each group and taking the absolute value.

[0021] Preferably, as an implementable manner, the acquisition step comprises:

[0022] The characteristic size of the air slot is measured by a characteristic size scanning electron microscope.

[0023] The present application provides another kind of semiconductor device characteristic size evaluation method, comprising:

[0024] The wafer is placed on the chuck, and the wafer is processed by a self-aligned patterning process to obtain a plurality of air slots; in the oxide etching step of the self-aligned patterning process, the temperature of the chuck is higher or lower than the reference temperature.

[0025] The characteristic size balance degree of the wafer is obtained; wherein the characteristic size balance degree is the absolute value of the difference between the characteristic sizes of two adjacent air slots, and the air slot includes the core area and the gap.

[0026] According to the temperature of the chuck and the characteristic size balance degree, the size relationship between the characteristic size of the core area and the characteristic size of the gap at the reference temperature is determined.

[0027] Compared with the prior art, the present application has the following advantages:

[0028] When the wafer on the partitioned chuck is subjected to oxide etching, the temperature difference between any two partitions of the partitioned chuck is set to be greater than zero. After the self-aligned patterning process is completed, the characteristic size of the gap on the wafer is positively correlated with the temperature of the corresponding partition on the partitioned chuck, while the characteristic size of the core area of each region on the wafer is substantially the same, and is basically consistent with the characteristic size of the core area formed when the partitioned chuck is subjected to oxide etching at the reference temperature.

[0029] By analyzing the IMB trend under different conditions through one experiment, the characteristic size relationship between the core area and the gap of the wafer can be determined, so that the IMB problem at the reference temperature can be quickly located, and the process debugging efficiency is improved; and without needing to observe the wafer slice, the experimental wafer can continue to be processed, and is applied to the subsequent process debugging, thereby reducing the process debugging cost. In addition, by using the partition chuck and setting the temperature gradient, the trend of the IMB changing with the temperature can be better reflected, and especially for the case that the core CD and the gap CD are not much different at the reference temperature, the trend that the IMB first decreases and then increases can be identified, the risk of introducing errors due to the trend reversal of the IMB can be greatly reduced, and the conclusion accuracy is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0031] Figures la-f Process flow chart of self-aligned double patterning technology;

[0032] Figures 2a-e Process flow chart of self-aligned four patterning technology;

[0033] Figure 3a Core and gap schematic diagram after oxide etching in self-aligned double patterning technology;

[0034] Figure 3b Core and gap schematic diagram after completion of self-aligned double patterning technology;

[0035] Figures 4a-b Schematic diagram and slice diagram before removing the top oxide in self-aligned four patterning technology;

[0036] Figure 5 The first schematic flow chart of the evaluation method of the characteristic size of the semiconductor device provided by the embodiment of the present application;

[0037] Figure 6 Influence of chuck temperature change on characteristic size in oxide etching step of self-aligned patterning process;

[0038] Figure 7 Trend distribution diagram of IMB changing with wafer radius in the embodiment of the present application;

[0039] Figure 8A second schematic flowchart of the method for evaluating feature sizes of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The semiconductor industry has been continuously pursuing smaller, faster, and more energy-efficient chip manufacturing processes to meet the ever-increasing demand for performance and power consumption in modern electronic devices. As Moore's Law approaches its limits, traditional photolithography techniques have been unable to meet the demands of chip manufacturing, and SADP and SAQP processes can achieve higher resolution and smaller feature sizes.

[0041] SADP refers to the use of self-alignment technology to form two different patterns in a single photolithography step. The process flow steps are as shown in Figures la-f , Figure la for the pattern formed after single litho-etch, Figure lb for the pattern formed after ALD Oxide deposition, Figure lc for the pattern formed after ALD Ox etching, Figure Id for the pattern formed after Carbon Strip, Figure le for the pattern formed after SiON etching, Figure If for the pattern formed after 2 nd Carbon etching and Top Ox removal. Through this technology, dense lines and spaced lines on the chip can be prepared simultaneously, achieving higher line width resolution, thus SADP process can significantly reduce cost and complexity compared to traditional multiple photolithography processes.

[0042] SAQP refers to the use of self-alignment technology to form four different patterns in a single photolithography step. Based on Figure If , the wafer is further processed, and the subsequent process flow steps are as shown in Figures 2a-e , Figure 2a for the pattern formed after ALD Oxide2 nd deposition, Figure 2b for the pattern formed after ALD Ox etching, Figure 2c for the pattern formed after Carbon Strip, Figure 2d for the pattern formed after SiON etching, Figure 2e for the pattern formed after Top Ox removal. This technology enables more complex structures and patterns on the chip, further improving the integration and performance of the chip, and is typically used to manufacture high-end chips such as processors, memories, and graphics chips.

[0043] Take SADP as an example, Core, Gap are defined as follows: refer to Figure 3a After ALD Ox etching, the area with Carbon is Core, and the rest is Gap; refer to Figure 3b After SADP process, the two adjacent spaces correspond to Core and Gap respectively.

[0044] In the related art, refer to Figure 4a and Figure 4b Before Top Ox removal, the wafer is sliced, and the Core CD and Gap CD at this time are observed by transmission electron microscopy, and the core and gap are distinguished according to the top oxide morphology to determine the CD problem. On the one hand, the slicing identification requires a long time and high cost; on the other hand, after slicing the wafer, the final CD cannot be observed by continuing to flow, the error of the result is large, and when the experimental conditions change, the IMB trend may be reversed, for example: the original conclusion is that the core area CD is 1.5nm smaller than the gap CD, and the IMB is 1.5; after changing the experimental conditions, the core area CD is 2nm larger than the gap area CD, and the IMB is 2, the conclusion is that this condition is not conducive to IMB optimization, however, the actual conclusion should be: this condition has a significant effect on IMB optimization, and the purpose of IMB optimization can be achieved through quantitative experiments.

[0045] Therefore, the present application provides a method and system for determining the balance degree of feature size in a self-aligned patterning process, which uses a 4-zone electrostatic chucking chuck, changes the core CD and gap CD distribution by setting a temperature gradient, quickly locates the IMB problem, improves the efficiency of process debugging, and reduces the cost of process debugging; and the experimental wafer can continue to flow, which is applied to subsequent process debugging, and reduces the error caused by sample preparation / quantitative measurement and other environments.

[0046] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0047] The present application will be described in further detail below with reference to specific examples and in conjunction with the drawings.

[0048] Figure 5 A method for evaluating the feature size of a semiconductor device is provided for an embodiment of the present application, and the method comprises:

[0049] S102, a processing step, placing the wafer on a partitioned chuck, and processing the wafer by a self-aligned patterning process to obtain a plurality of empty slots; in the oxide etching step of the self-aligned patterning process, the temperature difference between any two partitions of the partitioned chuck is greater than zero, the highest temperature of the partitioned chuck is higher than or equal to the reference temperature, and the lowest temperature of the partitioned chuck is lower than or equal to the reference temperature;

[0050] In the oxide etching step, the oxide film is etched. Figure lb After the wafer is processed by the step, the structure shown in the figure can be formed. Figure lc After the wafer is processed by the step, the structure shown in the figure can be formed. Figure 2a After the wafer is processed by the step, the structure shown in the figure can be formed. Figure 2b The wafer can be processed by a self-aligned patterning process using an inductively coupled plasma etching machine (ICP), and the temperature of the partitioned chuck can be set in the process recipe. The reference temperature is the chuck temperature in the oxide etching step under the original process conditions.

[0051] S104, an acquisition step, acquiring the characteristic size balance degree of each partition of the wafer; wherein the characteristic size balance degree is the absolute value of the difference between the characteristic sizes of two adjacent empty slots, and the empty slots include core regions and gaps;

[0052] S106, a determination step, determining the size relationship between the characteristic size of the core region and the characteristic size of the gap under the reference temperature according to the temperature of each partition of the partitioned chuck and the corresponding characteristic size balance degree.

[0053] In process debugging, there is a relatively linear relationship between temperature and organic mask bottom feature size (Line CD): as the temperature rises, the side wall protection adhesion decreases, the lateral etching increases, and the Line CD decreases; on the contrary, as the temperature decreases, the side wall protection adhesion increases, the lateral etching decreases, and the Line CD increases. The qualitative relationship is applied to the oxide etching step in SADP or SAQP, and the process schematic diagram is shown in Figure 6 The wafer finally obtained in the process shown in the figure can draw the following conclusions: after the temperature decreases, the Core CD remains unchanged and the Gap CD becomes smaller; correspondingly, after the temperature rises, the Core CD remains unchanged and the Gap CD becomes larger. Figure 6

[0054] According to the above conclusions, when the wafer placed on the partitioned chuck is subjected to oxide etching, the temperature difference between any two partitions of the partitioned chuck is set to be greater than zero. After the wafer is processed by the self-aligned patterning process, the characteristic size of the gap on the wafer is positively correlated with the temperature of the corresponding partition on the partitioned chuck, while the characteristic size of the core region of each region on the wafer is substantially the same and basically consistent with the characteristic size of the core region formed when the partitioned chuck is subjected to the oxide etching step at the reference temperature.​

[0055] The relationship between the characteristic size of the core region and the characteristic size of the gap at the reference temperature can be determined in the following cases:

[0056] A, when the highest temperature of the zoned chuck is equal to the reference temperature, the zones of the zoned chuck are sorted in order of temperature from high to low, the temperature gradually decreases, the core CD remains unchanged and the gap CD gradually decreases.

[0057] If the IMB gradually decreases, i.e., the absolute value of the difference between the characteristic sizes of the adjacent two empty grooves gradually decreases, it indicates that the core CD is smaller and the gap CD is larger at the reference temperature, so that the IMB is optimized after the gap CD decreases.

[0058] If the IMB gradually increases, i.e., the absolute value of the difference between the characteristic sizes of the adjacent two empty grooves gradually increases, it indicates that the core CD is larger and the gap CD is smaller at the reference temperature, so that the IMB becomes worse after the gap CD decreases.

[0059] If the IMB first decreases and then increases, i.e., the absolute value of the difference between the characteristic sizes of the adjacent two empty grooves first decreases and then increases, it indicates that the core CD is smaller and the gap CD is larger at the reference temperature, but the difference between them is not large, so that the IMB is optimized after the gap CD decreases, but when the chuck temperature decreases to a certain lower temperature, the gap CD is too small, causing the absolute value of the difference between the characteristic sizes of the adjacent two empty grooves to gradually increase, and the IMB becomes worse and worse.

[0060] B, when the lowest temperature of the zoned chuck is equal to the reference temperature, the zones of the zoned chuck are sorted in order of temperature from low to high, the temperature gradually increases, the core CD remains unchanged and the gap CD gradually increases.

[0061] If the IMB gradually decreases, i.e., the absolute value of the difference between the characteristic sizes of the adjacent two empty grooves gradually decreases, it indicates that the core CD is larger and the gap CD is smaller at the reference temperature, so that the IMB is optimized after the gap CD increases.

[0062] If the IMB gradually increases, i.e., the absolute value of the difference between the characteristic sizes of the adjacent two empty grooves increases, it indicates that the core CD is smaller and the gap CD is larger at the reference temperature, so that the IMB becomes worse after the gap CD increases.

[0063] If the IMB first decreases and then increases, i.e., the absolute value of the difference between the feature sizes of the adjacent two empty grooves first decreases and then increases, it indicates that at the reference temperature, the core CD is relatively large and the gap CD is relatively small, but the difference between the core CD and the gap CD is not large, thus, after the gap CD becomes large, the IMB is optimized, but when the chuck temperature rises to a certain higher temperature, the gap CD is too large, which causes the absolute value of the difference between the feature sizes of the adjacent two empty grooves to gradually increase, and the IMB becomes worse and worse.

[0064] C, in the case that the reference temperature is between the lowest temperature and the highest temperature, the partitions of the partitioned chuck are sorted in the order of temperature from low to high, the temperature gradually increases, and the core CD is unchanged while the gap CD gradually increases.

[0065] If the IMB gradually decreases, i.e., the absolute value of the difference between the feature sizes of the adjacent two empty grooves decreases, it indicates that at the reference temperature, the core CD is relatively large and the gap CD is relatively small, thus, after the gap CD becomes large, the IMB is optimized.

[0066] If the IMB gradually increases, i.e., the difference between the feature sizes of the adjacent two empty grooves increases, it indicates that at the reference temperature, the core CD is relatively small and the gap CD is relatively large, thus, after the gap CD becomes large, the IMB becomes worse.

[0067] If the IMB gradually decreases between the lowest temperature and the reference temperature and gradually increases between the reference temperature and the highest temperature, i.e., the absolute value of the difference between the feature sizes of the adjacent two empty grooves gradually decreases between the lowest temperature and the reference temperature and gradually increases between the reference temperature and the highest temperature, it indicates that at the reference temperature, the core CD and the gap CD are comparable in size, thus, no matter whether the gap CD becomes large or small, the IMB will become worse.

[0068] As can be seen from the above, by using the above method, the feature size relationship between the core region and the gap of the wafer can be determined through one experiment, so that the IMB problem at the reference temperature can be quickly located, and the efficiency of process debugging is improved; and wafer slicing is not required, the experimental wafer can continue to be processed, and is applied to subsequent process debugging, thereby reducing the process debugging cost. In addition, by using the partitioned chuck and setting the temperature gradient, the trend of the IMB changing with the temperature can be better reflected, especially for the case that the core CD and the gap CD are comparable in size at the reference temperature, the trend that the IMB first decreases and then increases can be identified, the risk of introducing errors due to the trend reversal of the IMB can be greatly reduced, and the accuracy of the conclusion is improved.

[0069] When the relationship between Core CD and Gap CD is clarified, the IMB performance can be optimized by etching gas ratio / temperature. For example, after the IMB problem is clarified as Core CD > Gap CD, the process tuning direction is to reduce Core CD or increase Gap CD. By reducing the sidewall protection gas or increasing the temperature in the oxide etching step, Gap CD can be increased to optimize IMB.

[0070] Preferably, the several partitions of the partitioned chuck are arranged to be radially distributed from the center, and the temperature of the several partitions is set to gradually decrease or increase from the inside to the outside, so that the trend of IMB change with wafer radius can be analyzed according to the measured location of the empty slot, and the measurement data of the feature size of the empty slot can be conveniently summarized and analyzed.

[0071] Each chip will leave some measurement patterns in the corner during lithography, which are used for the feature size and depth measurement of the empty slot to avoid directly taking the device area to affect the chip yield. The more data that can be measured near the edge of the wafer, the less data that can be measured near the center of the wafer. Therefore, the temperature of the innermost partition of the partitioned chuck is preferably set to be consistent with the reference temperature, and only a small amount of measurement data is needed to qualitatively analyze and determine that the performance of the center matches the reference. That is, there is no need to quantitatively analyze the measurement data of the innermost partition to determine the trend of IMB change, which can avoid the data error caused by the small amount of measurement data. In other partitions of the partitioned chuck, more measurement data can be obtained, which is conducive to obtaining more significant IMB change trend and realizing accurate positioning of the IMB problem under the reference temperature.

[0072] The above determination step can specifically include: under the condition that the temperature of the partitioned chuck gradually decreases from the inside to the outside, the feature size of the core area of each part of the wafer is basically consistent, and the feature size of the gap gradually decreases from the center of the wafer to the edge. If the feature size balance gradually decreases or first decreases and then increases from the center of the wafer to the edge, it can be determined that the feature size of the core area is smaller than that of the gap under the reference temperature, so that the IMB is optimized after the feature size of the gap decreases. If the feature size balance gradually increases from the center of the wafer to the edge, it can be determined that the feature size of the core area is larger than that of the gap under the reference temperature, so that the IMB becomes worse after the feature size of the gap decreases. In this way, the relationship between the feature size of the core area and the gap of the wafer can be quickly determined, so that the IMB problem under the reference temperature can be quickly positioned.

[0073] The determining step can further include: under the condition that the temperature of the partition chuck gradually increases from the inside to the outside, the feature size of the core region of each part of the wafer is substantially uniform, and the feature size of the gap gradually increases from the center to the edge of the wafer. If the feature size balance gradually decreases from the center to the edge of the wafer or first decreases and then increases, it is determined that the feature size of the core region is larger than that of the gap at the reference temperature, and therefore, the IMB is optimized after the feature size of the gap increases. If the feature size balance gradually increases from the center to the edge of the wafer, it is determined that the feature size of the core region is larger than that of the gap at the reference temperature, and therefore, the IMB becomes worse after the feature size of the gap increases. In this way, the relationship between the feature sizes of the core region and the gap of the wafer can be quickly determined, and the IMB problem at the reference temperature can be quickly located.

[0074] The several partitions of the partition chuck can include an inner zone, a middle inner zone, a middle outer zone, and an outer zone distributed from the center in a radial direction from the inside to the outside. Such a partition chuck can not only accurately locate the IMB problem at the reference temperature, but also will not cause interference between adjacent two zones due to too many partitions. In addition, the hardware configuration is less difficult, and mass production is facilitated.

[0075] Generally, the wafer corresponding to the center zone of the partition chuck has about 4-8 measurable patterns, the middle inner zone has about 6-15 measurable patterns, the middle outer zone has about 15-26 measurable patterns, and the edge zone has about 27-35 measurable patterns.

[0076] Specifically, the temperature difference between adjacent two partitions of the partition chuck can be set to be less than or equal to 5℃ to adapt to the configuration of the chuck hardware (such as electrostatic chuck heater and cooling system) in the related art.

[0077] Preferably, the temperature difference between adjacent two partitions of the partition chuck is set to 4℃ to balance the actual capacity of the chuck hardware and more significant experimental results. Figure 7 For the IMB trend distribution graph under the following temperature conditions: the reference temperature is 50℃, the temperature of each partition of the partition chuck is 50℃; the temperature of the center zone is 50℃, the temperature of the middle inner zone is 46℃, the temperature of the middle outer zone is 42℃, and the temperature of the edge zone is 38℃; wherein the vertical coordinate is the value of the IMB, and the horizontal coordinate represents the wafer radius corresponding to the IMB. Test IMB is the IMB under the temperature conditions of the present embodiment, and Baseline IMB is the IMB at the reference temperature. From the above, it can be seen that the IMB of the wafer under the temperature conditions of the present embodiment is smaller than the IMB at the reference temperature, and the IMB of the wafer under the temperature conditions of the present embodiment is smaller than the IMB at the reference temperature. Figure 7It can be seen that, from the center of the wafer to the edge, the IMB increases with the decrease of the temperature, indicating that the Gap CD gradually increases from the center of the wafer to the edge, the problem of the IMB is that the Gap CD is larger than the Core CD, and the process adjustment direction is to increase the Core CD or reduce the Gap CD, which can be realized by increasing the sidewall protection gas or reducing the temperature in the oxide etching step to reduce the Gap CD, so as to optimize the IMB.

[0078] The obtaining step can specifically include: measuring the characteristic size of the plurality of air slots, and determining the corresponding relationship between the characteristic size of each air slot and the measurement position; according to the corresponding relationship, two adjacent air slots are divided into a group; the characteristic sizes of the two air slots in each group are subtracted and the absolute values are taken to obtain a plurality of characteristic size balance degrees and corresponding positions. The above method is used for data measurement, statistics and analysis, and the efficiency is higher.

[0079] Specifically, the characteristic size results of the plurality of air slots obtained by measurement can be with coordinates, and when subsequent data arrangement is performed, it can be determined which one of the center partition, the middle inner partition, the middle outer partition and the edge partition of the data partition chuck is, and the characteristic size balance degree of each partition is calculated accordingly.

[0080] Specifically, the characteristic size of the air slot can be measured by a characteristic size scanning electron microscope, the data measurement accuracy is higher, and the IMB problem at the reference temperature can be accurately positioned.

[0081] The partition chuck specifically is an electrostatic chuck.

[0082] Figure 8 An evaluation method of a characteristic size of a semiconductor device is provided for an embodiment of the present application, and the method comprises:

[0083] S202, a processing step, placing a wafer on a chuck, and processing the wafer by a self-aligned patterning process to obtain a plurality of air slots; in the oxide etching step of the self-aligned patterning process, the temperature of the chuck is higher or lower than the reference temperature;

[0084] S204, an obtaining step, obtaining the characteristic size balance degree of the wafer; wherein the characteristic size balance degree is the absolute value of the difference between the characteristic sizes of two adjacent air slots, and the air slot includes a core region and a gap;

[0085] S206, a determining step, determining the size relationship between the characteristic size of the core region and the characteristic size of the gap at the reference temperature according to the temperature of the chuck and the characteristic size balance degree.

[0086] The size relationship between the characteristic size of the core region and the characteristic size of the gap at the reference temperature can be determined according to the following cases:

[0087] A, in the case that the temperature of the chuck is lower than the reference temperature.

[0088] If the IMB after temperature adjustment is lower than the IMB at the reference temperature, that is, the absolute value of the difference between the characteristic sizes of the adjacent two grooves becomes smaller, it indicates that the core CD is smaller and the gap CD is larger at the reference temperature, and thus the IMB is optimized after the gap CD becomes smaller.

[0089] If the IMB after temperature adjustment is higher than the IMB at the reference temperature, that is, the absolute value of the difference between the characteristic sizes of the adjacent two grooves becomes smaller, it indicates that the core CD is larger and the gap CD is smaller at the reference temperature, and thus the IMB becomes worse after the gap CD becomes smaller.

[0090] A, in the case where the temperature of the chuck is higher than the reference temperature.

[0091] If the IMB after temperature adjustment is lower than the IMB at the reference temperature, that is, the absolute value of the difference between the characteristic sizes of the adjacent two grooves gradually becomes smaller, it indicates that the core CD is larger and the gap CD is smaller at the reference temperature, and thus the IMB is optimized after the gap CD becomes larger.

[0092] If the IMB after temperature adjustment is higher than the IMB at the reference temperature, that is, the absolute value of the difference between the characteristic sizes of the adjacent two grooves becomes larger, it indicates that the core CD is smaller and the gap CD is larger at the reference temperature, and thus the IMB becomes worse after the gap CD becomes larger.

[0093] In summary, the above method can quickly determine the characteristic size relationship between the core region and the gap of the wafer, thereby quickly positioning the IMB problem at the reference temperature, improving the efficiency of process debugging, and reducing the cost of process debugging.

[0094] One embodiment of the present application provides a machine readable storage medium, which stores machine executable instructions, and the machine executable instructions cause a processor to implement the above-mentioned self-alignment patterning process characteristic size balance degree determination method when the machine executable instructions are called and executed by the processor.

[0095] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-mentioned device and apparatus can refer to the corresponding process in the foregoing method embodiments, which will not be described herein.

[0096] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the prior art that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0097] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0098] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0099] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of evaluating a feature size of a semiconductor device, characterized by, The method comprises: A processing step of placing a wafer on a partitioned chuck, processing the wafer through a self-aligned patterning process to obtain a plurality of empty slots; in the oxide etching step of the self-aligned patterning process, the temperature difference between any two partitions of the partitioned chuck is greater than zero, the highest temperature of the partitioned chuck is higher than or equal to a reference temperature, and the lowest temperature of the partitioned chuck is lower than or equal to the reference temperature; An acquisition step of acquiring a characteristic size balance degree of each partition corresponding to the wafer; wherein the characteristic size balance degree is the absolute value of the characteristic size difference between two adjacent empty slots, and the empty slots include a core area and a gap; A determination step of determining the size relationship between the characteristic size of the core area and the characteristic size of the gap at the reference temperature according to the temperature of each partition of the partitioned chuck and the corresponding characteristic size balance degree.

2. The method of claim 1, wherein A plurality of partitions are distributed radially from the center of the partitioned chuck outward, and the temperature of a plurality of partitions gradually decreases or increases from the inside to the outside.

3. The method of claim 2, wherein The temperature of the innermost partition is consistent with the reference temperature.

4. The method of claim 3, wherein The determination step comprises: Under the condition that the temperature of the partitioned chuck gradually decreases from the inside to the outside, if the characteristic size balance degree gradually decreases or first decreases and then increases from the center to the edge of the wafer, it is determined that the characteristic size of the core area is smaller than the characteristic size of the gap at the reference temperature; if the characteristic size balance degree gradually increases from the center to the edge of the wafer, it is determined that the characteristic size of the core area is greater than the characteristic size of the gap at the reference temperature; Under the condition that the temperature of the partitioned chuck gradually increases from the inside to the outside, if the characteristic size balance degree gradually decreases or first decreases and then increases from the center to the edge of the wafer, it is determined that the characteristic size of the core area is greater than the characteristic size of the gap at the reference temperature; if the characteristic size balance degree gradually increases from the center to the edge of the wafer, it is determined that the characteristic size of the core area is greater than the characteristic size of the gap at the reference temperature.

5. The method of claim 1 to 4, wherein A plurality of partitions include a center partition, a middle-in partition, a middle-out partition, and an edge partition, which are sequentially distributed radially from the center of the partitioned chuck outward.

6. The method of claim 1-5, wherein, The temperature difference between two adjacent partitions of the partitioned chuck is less than or equal to 5℃.

7. The method of claim 6, wherein the method further comprises: The temperature difference between two adjacent partitions of the partitioned chuck is 4℃.

8. The method of claim 1 to 7, wherein The acquisition step comprises: Measuring the characteristic sizes of a plurality of empty slots and determining the correspondence between the characteristic sizes of each empty slot and the measurement position; According to the correspondence, two adjacent empty slots are divided into a group; The absolute values of the differences between the characteristic sizes of two empty slots in each group are obtained to obtain a plurality of characteristic size balance degrees and corresponding positions.

9. The method of claim 8, wherein the method further comprises: The acquisition step comprises: The characteristic sizes of the empty slots are measured by a characteristic size scanning electron microscope.

10. A method of evaluating a feature size of a semiconductor device, characterized by, The method comprises: A processing step of placing a wafer on a partitioned chuck, processing the wafer through a self-aligned patterning process to obtain a plurality of empty slots; in the oxide etching step of the self-aligned patterning process, the temperature of the partitioned chuck is higher or lower than a reference temperature; An acquisition step of acquiring a feature size balance degree of the wafer; wherein the feature size balance degree is an absolute value of a feature size difference between two adjacent empty slots, and the empty slots include the core area and the gap; A determination step of determining a size relationship between the feature size of the core area and the feature size of the gap at the reference temperature according to the temperature of the chuck and the feature size balance degree.

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