General digital variable sampling filtering method based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a general digital variable sampling filtering method based on an FPGA, and the method comprises the following steps: obtaining target filtering parameters which comprise a variable sampling rate and a filter coefficient; based on the target filtering parameter, configuring a digital filtering data path which is preset in the FPGA and is based on a universal cyclic shift register array; based on a variable sampling rate, adaptively adjusting a handshake protocol time sequence of input and output data streams of the configurable digital filtering data path so as to realize data synchronization with upstream and downstream modules; and filtering an input data stream by using the configured configurable digital filtering data path to obtain an output data stream conforming to the target filtering parameter. According to the invention, the technical problem of deep coupling of filter hardware and specific sampling rate parameters is solved, and high multiplexing of a single design source code is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital signals, in particular to a universal digital variable sampling filter method based on FPGA. BACKGROUND

[0002] In modern communication, radar and software radio systems, a digital variable sampling filter is a key component for realizing sampling rate conversion between different processing modules. For example, it is often used to connect a high-speed sampling rate radio frequency front-end and a low-speed sampling rate baseband processing unit, and through decimation or interpolation operation, the data throughput rates of the two are matched. In the FPGA-based implementation scheme, the design of such a filter is usually static and fixed. Specifically, the designer will design the structure and coefficients of the filter according to a certain sampling rate conversion factor (such as decimation rate or interpolation rate) and the desired frequency response. These design parameters are fixed during the hardware description language coding stage, and after synthesis, layout and routing, a special hardware circuit for this specific sampling rate conversion function is finally generated on the FPGA.

[0003] However, with the evolution and diversification of communication protocols, a single device often needs to support multiple working modes or communication standards, such as switching between 4G, 5G and wireless local area network (WLAN), and the corresponding radio frequency and baseband sampling rates of each mode may be different. Under the above static design idea, whenever the system needs to adapt to a new sampling rate, the HDL source code of the filter must be modified, and a complete set of complex and time-consuming design verification procedures must be re-executed. The original verified hardware module cannot be directly reused for new parameter requirements, which leads to a long design process, high research and development cost, and difficulty in quickly responding to changing application requirements. SUMMARY

[0004] In order to solve the technical problem of deep coupling between filter hardware and specific sampling rate parameters, and to realize high reuse of a single design source code, the present application provides a universal digital variable sampling filter method based on FPGA.

[0005] The universal digital variable sampling filter method based on FPGA provided by the present application adopts the following technical scheme: A universal digital variable sampling filter method based on FPGA, comprising the following steps: S1. Obtain target filter parameters, wherein the target filter parameters include variable sampling rate and filter coefficients; S2. Based on the target filter parameters, configure a digital filter data path based on a universal circular shift register array preset in the FPGA; S3. adaptively adjust handshake protocol timing of input and output data stream of the configurable digital filtering data path based on the variable sampling rate, to realize data synchronization with upstream and downstream modules; S4. filter the input data stream by using the configured configurable digital filtering data path, to obtain the output data stream conforming to the target filtering parameter.

[0006] By adopting the technical solution, the configurable digital filtering data path preset in the FPGA is directly reconstructed in physical structure according to the target filtering parameter. Specifically, the data path is built based on a general cyclic shift register array, and the data path connection relationship, register depth and parallel processing branch number in the data path are not fixed. When the new variable sampling rate parameter is obtained, the parameter is directly input to the generate statement or array instantiation in the hardware description language, to guide the synthesis tool of the FPGA to generate a physically optimal circuit structure. For example, an N times decimation rate parameter enables the data path to be embodied as an N-phase polyphase filter structure, so that the original high-speed serial operation is decomposed into N low-speed parallel operations. The direct mapping mechanism from the parameter to the hardware structure is the basis for realizing the single design source code reuse, so that the filters with different functions can be generated by the same logic.

[0007] After the data path is configured according to the parameter, a rate counter dynamically set by the parameter is built in the output control logic of the module, and the same variable sampling rate parameter can be used to synchronously control the data stream of the interface. The rate counter takes the system clock as a reference, and the count value directly determines the minimum interval between two valid assertions of the output data valid signal TVALID. For example, when the N times decimation rate parameter is loaded, the rate counter ensures that the TVALID signal is valid once only after N input sampling periods are processed internally. In this way, the internal rate of the data processing core is accurately materialized as the timing behavior of the external interface signal. The mechanism of internally binding the internal operation rhythm and the external handshake timing enables the data throughput rate of the module to be automatically announced to the system downstream, thereby realizing reliable data stream synchronization without external intervention.

[0008] Optionally, the S2 further includes: Before the configurable digital filtering data path is configured, the reading operation on the input first-in-first-out buffer is stopped, wherein the first-in-first-out buffer is used to receive and store the input data stream; After the configurable digital filtering data path is configured, the reading operation on the first-in-first-out buffer is started.

[0009] By adopting the technical scheme, before performing the data path configuration, the method first suspends the reading operation on the input first-in-first-out buffer. This enables the buffer to continue receiving and accumulating data from the upstream data generation end during the internal reconstruction of the data path, thereby decoupling the transient configuration process of the data path from the continuity of the upstream data flow.

[0010] After the data path configuration is completed, the method then starts the reading operation on the buffer, so that the previously accumulated data and subsequent real-time data can be continuously processed by the configured data path. The coordinated control process of suspension and start ensures the integrity of the input data during the entire period of parameter switching of the filter module, avoiding data loss or upstream link blocking that may be caused by module reconstruction.

[0011] Optionally, the S2 further includes: When suspending the reading operation on the first-in-first-out buffer, record the current data amount in the first-in-first-out buffer as a transition data amount; The S4 further includes: After starting the reading operation on the first-in-first-out buffer, insert a preset transition state identifier into the corresponding output data stream for a batch of data samples read from the first-in-first-out buffer, the number of which is equal to the transition data amount.

[0012] By adopting the technical scheme, at the moment when the buffer reading operation is suspended, the method accurately records the data amount stored in the buffer at that moment as a transition data amount. Then, when the data path completes the configuration and starts processing data again, the method inserts a preset transition state identifier into the output for a batch of initial data samples read from the buffer, the number of which is equal to the recorded transition data amount. The coordinated operation of recording and inserting the identifier embeds metadata into the data stream itself, enabling the data to carry its own historical state information when passing through the system, so that the downstream data receiving end can unambiguously identify which data is buffered during parameter change.

[0013] Optionally, the S1 includes: Obtain a transition data processing mode parameter; The S4 includes: According to the transition data processing mode parameter, perform one of the following preset operations on the data sample to which the transition state identifier is inserted: Output the data sample and the transition state identifier; or discard the data sample without output.

[0014] By adopting the technical scheme, the method first acquires a transition data processing mode parameter for decision-making. In subsequent filtering processing steps, data samples identified as transition states are selectively output or directly discarded.

[0015] The principle of the scheme is to collect the disposal right of transition data into the module and set its behavior as configurable. It upgrades a passive state marking function to an active, policy-based data flow management function. By providing the option of discarding data samples, the method enables the filter module to present an externally simplified standard flow interface with no data output during reconstruction, thereby eliminating the burden of additional logic for downstream modules to parse and process transition state identification. The scheme fundamentally reduces the complexity of system integration and improves the compatibility and ease of use of the general module in different system architectures.

[0016] Optionally, the S1 comprises: acquiring a coefficient set selection index, wherein the FPGA stores a plurality of coefficient sets corresponding to the coefficient set selection index; The S2 further comprises: determining a target coefficient set from the plurality of stored coefficient sets according to the coefficient set selection index, and configuring the configurable digital filtering data path with the target coefficient set.

[0017] By adopting the technical scheme, S1 first acquires a coefficient set selection index with a very small amount of data, and S2's configuration process directly determines and retrieves a target coefficient set from the plurality of coefficient sets stored in the FPGA according to the index, to configure the data path. By pre-setting the coefficient set and simplifying the external control input to an index, the original external bus communication process that may involve a large amount of data throughput is converted into a high-speed on-chip memory addressing operation. This mechanism greatly shortens the time required to reconfigure the filter, solves the problem of excessive configuration delay caused by loading a large amount of coefficient data, and thus realizes fast and deterministic switching between different preset filtering modes.

[0018] Optionally, the memory storing the plurality of coefficient sets is a readable and writable random access memory; The FPGA-based general digital variable sampling and filtering method further comprises: receiving and overwriting at least one coefficient set in the random access memory via a configuration interface.

[0019] By adopting the technical scheme, the static coefficient set originally fixed in the hardware logic is converted into a software resource that can be dynamically updated externally. This enables the device to adapt to new technical standards or working modes through software updates without re-combining and deploying the hardware.

[0020] Optionally, the random access memory comprises at least two independent coefficient storage areas; The step of receiving and overwriting at least one coefficient set in the random access memory via a configuration interface comprises the following sub-steps: One of the at least two independent coefficient storage areas is designated as an online area for the configurable digital filter data path to read coefficients, and one is designated as an offline area; The overwriting operation on the coefficient set is performed, wherein the overwriting operation on the coefficient set is only performed in the offline area; After the overwriting operation in the offline area is completed, the offline area is switched to the online area.

[0021] By adopting the above technical solution, the coefficient memory is first partitioned into an online area and an offline area which are independent of each other, and the coefficient overwriting operation is strictly limited to be performed in the offline area, thereby isolating the coefficient updating action and the real-time reading action of the filter in the physical storage space. After the overwriting operation is safely completed, the method performs a switching operation again to designate the updated offline area as a new online area. The principle of the series of steps lies in building a conflict-free updating mechanism which ensures that the filter data path reads a complete and consistent set of coefficients at any moment, and eliminates the possibility of reading part of the updated data. This solution solves the technical problem of data disorder and system crash caused by concurrent reading and writing in real-time updating of the read-write memory.

[0022] In summary, the present application includes at least one of the following beneficial technical effects: 1. By parameterizing the configuration of the general hardware architecture and matching the adaptive interface timing control, the technical problem of deep coupling between the filter hardware and the specific sampling rate parameter is solved, the high reuse of a single design source code is realized, the development cycle for different application requirements is significantly shortened, and the research and development cost is reduced.

[0023] 2. By introducing data buffering, transient data identification and a configurable handling mechanism, the problems of data loss and unclear data timeliness in the dynamic reconstruction process are solved, and the integrity of the data stream and the determinacy of the system behavior during parameter switching are ensured.

[0024] 3. By adopting the read-write coefficient storage area and the safe overwriting switching mechanism, the technical problem of function solidification and non-expandability of the pre-storage scheme is solved, so that the function of the filter can be updated and upgraded online after the device is deployed, and the design flexibility and the product technical life cycle are enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1A program block diagram of a general digital variable sampling filter method based on FPGA in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] The present application is further described in detail by reference to the following drawings.

[0027] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the inventive concept. As part of the description, some of the diagrams in the present disclosure are represented in block diagram form to avoid obscuring the disclosed principles. Some features of actual implementations can not be described in detail if it is determined that it will aid in understanding the present disclosure. Also, the language used in the present disclosure has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the inventive subject matter, resort to the claims being necessary to determine such inventive subject matter. Reference in the specification to "one implementation" or "an implementation" means that a particular feature, structure, or characteristic described is included in at least one implementation, and multiple references to "one implementation" or "an implementation" do not necessarily all refer to the same implementation.

[0028] The terms "one," "a," and "the" are not intended to refer to singular entities, but include the general class of which a specific example can be used for illustration. The use of the terms "one" or "a" can mean any number of including "one," "one or more," "at least one," and "one or more than one." The term "or" means any one of the alternatives, as well as any combination of the alternatives, including all of the alternatives, unless the alternatives are expressly indicated to be mutually exclusive. The phrase "at least one of" in combination with a list of items means that at least one of the individual items in the list is present, or any combination of the items in the list is present, unless expressly indicated to the contrary.

[0029] In modern digital communication, software radio, radar signal processing, and other high performance signal processing systems based on field programmable gate array (FPGA), digital filters are widely used to perform key tasks such as channel selection, anti-aliasing, interference suppression, pulse shaping, etc., whose performance metrics directly affect the functionality and reliability of the whole system.

[0030] Among the many types of digital filters, digital resampling filters are a composite functional module that combines the functions of frequency selective filtering and sampling rate conversion. Its basic function is to change the sampling rate of the signal while filtering the input digital signal. The change of the sampling rate includes decimation, i.e. reducing the sampling rate of the signal by a certain proportion, and interpolation, i.e. increasing the sampling rate of the signal by a certain proportion. Its working principle is usually based on a finite impulse response filter structure, and the core operation is a series of multiply-accumulate operations. Specifically, the filter multiplies a series of input digital signal sample values by a set of pre-set filter coefficients representing the frequency response characteristics of the filter, and then adds all the products to generate an output sample value. In the resampling process, the ratio between the rate at which input samples are consumed and the rate at which output samples are generated is determined by the set resampling rate parameter.

[0031] Modern communication and signal processing systems usually require a single hardware platform to support multiple different communication protocols or different working modes under the same protocol. For example, a software radio base station may need to switch between different communication standards such as 5G NR, LTE or Internet of Things according to business needs; and within the 5G NR standard, it also needs to support multiple different channel bandwidth configurations such as 20 megahertz and 100 megahertz. Each communication standard or working mode corresponds to a complete set of unique signal processing parameters, including but not limited to signal bandwidth, symbol rate and sampling rate. As a core component of the signal processing chain, the digital resampling filter must be able to adapt to these changes.

[0032] However, traditional FPGA-based digital filters usually adopt a fixed or hard-coded design scheme. Its key functional parameters, such as resampling rate, filter coefficient set defining its frequency response, and internal data path structure (such as the number of parallel processing branches), are determined during the hardware design phase. These parameters are written directly into the hardware description language code as constants, and through synthesis and layout tools, they are finally fixed as the logical circuit connection relationship inside the FPGA. The product of this design method is a dedicated filter hardware module that is bound one-to-one with a specific application scenario, and all its resources are configured to achieve the optimal performance under this set of fixed parameters.

[0033] The variable sampling rate of the filter directly determines the shift register depth and the number of parallel branches of the data path, and the filter coefficients are fixed in the memory cells or combinational logic. This deep coupling results in extremely low reusability of hardware modules. In modern multi-mode application scenarios, when the system needs to switch to a new communication mode with different variable sampling rates or passband characteristics, the original filter hardware module customized for the old mode cannot adapt to the new parameter requirements. The developer must return to the design source, modify the hardware description language code, and re-execute the complete hardware development process including logic synthesis, implementation, timing analysis, and functional verification. This process not only consumes a large amount of engineering resources and time, but also cannot meet the demand for online, dynamic reconfiguration of modern communication systems.

[0034] Therefore, an FPGA-based general digital variable sampling filter method is disclosed in the embodiments of the present application. Referring to Figure 1 , the method comprises the following steps S1-S4.

[0035] S1. Obtain target filter parameters, wherein the target filter parameters include a variable sampling rate and filter coefficients.

[0036] S2. Based on the target filter parameters, configure a general cyclic shift register array-based digital filter data path preset in the FPGA.

[0037] S3. Based on the variable sampling rate, adaptively adjust the handshake protocol timing of the input and output data streams of the configurable digital filter data path to realize data synchronization with upstream and downstream modules.

[0038] S4. Filter the input data stream using the configured configurable digital filter data path to obtain an output data stream that meets the target filter parameters.

[0039] The method realizes the decoupling of filter function parameters and hardware physical structure through the cooperative mechanism of parameterized data paths and adaptive interface control. The hardware structure inside the configurable digital filter data path, such as the number of parallel processing branches or data shift logic, is adjustable and determined by the target filter parameters obtained by S1. This allows the same set of physical hardware resources to perform different specifications of core filtering operations according to different parameter configurations. The adaptive interface controller reads the variable sampling rate and other information in the target filter parameters and dynamically adjusts the control timing of the output data interface, such as the generation rate of the output data valid signal, so that the filtered data can be smoothly transmitted to the downstream processing module at the correct data flow rate that matches the current configuration.

[0040] To implement the foregoing method, the embodiments of the present application further provide a corresponding hardware device, which comprises a configuration interface module, a parameter register group, a first-in-first-out buffer, a coefficient storage module, a configurable digital filter data path, and an adaptive interface controller, etc.

[0041] The configuration interface module and the parameter register group are used to perform S1 in the foregoing method, i.e., obtaining the target filter parameters. Specifically, the configuration interface module provides a standard bus interface, such as an AXI4-Lite bus interface, facing an external system, to receive all target filter parameters issued by upper-layer software or a processor. The module internally comprises a parameter register group, which adopts a memory mapping design. Each dynamically configurable parameter, such as a variable sampling rate, a coefficient set selection index for selecting a specific filter coefficient set, and a transition data processing mode to be described later, is assigned a unique and fixed bus address. When the external system writes parameter data into the specified address through a bus write operation, the configuration interface module locks the data in the corresponding parameter register. The output of the parameter register group is a set of parallel and stable parameter signals before the completion of each reconstruction, which are distributed to all other modules inside the device that need these parameters for work.

[0042] After obtaining the new target filter parameters through the configuration interface, the related modules inside the hardware device, especially the configurable digital filter data path, need a limited transient time to complete the reconstruction of the internal operation structure. During this period, the data path cannot correctly process data. To ensure the continuity and integrity of the data flow during the online reconstruction process, the embodiments of the present application comprise a first-in-first-out buffer. To solve the problem of data integrity during the online reconstruction process, in a preferred embodiment, between S1 and S2, the method further comprises: during the transient process of configuring the configurable digital filter data path according to the new target filter parameters, using a first-in-first-out buffer to cache the external input data stream to prevent data loss.

[0043] The FIFO buffer is equivalent to a data stream reservoir during the transient process of parameter reconfiguration of the system. The input end can be implemented as a standard AXI-Stream data stream interface to facilitate connection with the standard data generation end module upstream; the output end is a standard FIFO interface for reading by the internal configurable digital filtering data path, and the storage depth of the FIFO buffer needs to be set according to the longest reconfiguration time that the system may experience and the highest rate of input data to ensure that there is enough space to cache real-time data continuously input during reconfiguration. The reading enable signal of the FIFO buffer is precisely controlled by the adaptive interface controller. When the controller starts a reconfiguration process, it temporarily prohibits reading operations on the FIFO buffer to pause the data flow to the data path; after reconfiguration is completed, the controller resumes its reading operation. In this way, the decoupling between the continuous data generation process upstream and the transient reconfiguration process inside the device is achieved, effectively avoiding data loss.

[0044] The hardware device of the embodiment of the application further includes a coefficient storage module for storing and providing one or more sets of filter coefficients required by the configurable digital filtering data path when performing operations. The coefficient storage module can pre-embed multiple different coefficient sets to correspond to multiple preset filtering modes, and accordingly, the target filtering parameters obtained in S1 include a coefficient set selection index, that is, the filter coefficients in the target filtering parameters are obtained by looking up a preset coefficient storage module according to a coefficient set selection index. The input interface of the module receives the coefficient set selection index from the parameter register group as a read address, and according to the index, outputs the corresponding coefficient set data as an output to the configurable digital filtering data path. This implementation can be based on a read-only memory (ROM) or a random access memory (RAM) loaded during system initialization.

[0045] To support on-site updating or adaptive filtering, in a preferred embodiment, the coefficient storage module is designed to be online-updatable. Specifically, the coefficient storage module is a read-write random access memory (RAM), and the method further includes: updating the filter coefficients stored in the random access memory online through a configuration interface. This means that in addition to providing a coefficient reading channel to the data path, the module also includes a write data channel connected to the aforementioned configuration interface module, allowing upper-layer software to write a completely new coefficient set into the storage module through bus operation during system operation.

[0046] To solve the read-write conflict problem that may occur in the process of online updating coefficients, and to guarantee the instantaneousness and reliability of coefficient switching, in a more preferred embodiment, the random access memory comprises at least two independent storage areas, and the method further comprises: while one storage area provides the current coefficients for the digital filtering data path, the updated coefficients are written to the other storage area through the configuration interface to realize online conflict-free coefficient updating. The two storage areas, i.e. one working area and one standby area, realize the physical isolation of read-write operations. When the system is working normally, the data path always reads stable and valid coefficients from the working area. At the same time, the upper software can safely write the new coefficient set to the standby area through the configuration interface. After the new coefficients are completely written, the controller can switch the standby area to the new working area through an atomic operation, thereby realizing the disturbance-free and instantaneous switching of the filter characteristics.

[0047] In addition, in a preferred embodiment, the hardware device further comprises a configurable digital filtering data path. The input interface of the data path is connected with the output end of the first-in-first-out buffer and the output end of the coefficient storage module respectively, to receive data samples and filter coefficients; and the output end of the data path sends the calculated filtered data to the subsequent adaptive interface controller for processing.

[0048] The physical structure of the configurable digital filtering data path is not fixed for specific parameters, but is constructed based on a general and parameterizable circular shift register array. The structural characteristics of the data path, such as the number of parallel processing branches, the logic of data shifting, and the resource call of multipliers and adders, are all directly determined by the target filtering parameters, especially the variable sampling rate parameters, obtained from the parameter register group. This determination mechanism can either generate an optimized hardware instance for specific needs by parameter transmission during FPGA synthesis, or adjust the data path by dynamic configuration signals during system operation.

[0049] In addition, in a preferred embodiment, the hardware device further comprises an adaptive interface controller, and the output data processing module is used to perform final processing on the original filtering result from the configurable digital filtering data path, and format it as a standard AXI-Stream data stream output to the downstream module. Specifically, the adaptive interface controller reads the currently effective variable sampling rate parameter from the parameter register group, and dynamically controls the handshake protocol timing of the output AXI-Stream interface according to the parameter. For example, it can accurately adjust the generation rate of the output data valid signal to ensure that the data samples are output at the correct time interval according to the target sampling rate, thereby maintaining synchronization with the downstream module.

[0050] The adaptive interface controller is also used to process the transition data generated during the parameter reconstruction to ensure the determinacy of the data stream. In a preferred embodiment, S4 further comprises: a preset transition state identifier is inserted into the corresponding output data stream for the data samples read from the FIFO buffer in an amount equal to the amount of transition data. That is, after the transient process ends, the data cached in the FIFO buffer is output as transition data, and a transition state identifier is attached when the transition data is output. To achieve this function, the controller is built-in a counter, which can record the amount of data cached in the FIFO buffer at the beginning of the reconstruction. When the reconstruction is completed and the cached data is processed and output in turn, the controller attaches a specific transition state identifier to the data through a sideband signal, such as the TUSER signal in the AXI-Stream interface.

[0051] To provide flexible processing capability for the transition data, in a more preferred embodiment, the target filter parameters further comprise a transition data processing mode, and the foregoing method further comprises: performing a preset disposal operation on the transition data with the transition state identifier according to the transition data processing mode, the disposal operation comprising outputting the data samples and the transition state identifier; or discarding the data samples without outputting. The transition data processing mode parameter is set by the upper-layer software through the configuration interface. The adaptive interface controller performs the corresponding disposal operation on the marked transition data according to the set value of the parameter. For example, when the mode is set to discard, the controller will suppress the valid output of the data valid signal when outputting the part of data; when the mode is set to normal output, it will be normally output.

[0052] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0053] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A general digital variable sampling filtering method based on FPGA, characterized in that, Includes the following steps: S1. Obtain the target filtering parameters, which include the variable sampling rate and filter coefficients; S2. Based on the target filtering parameters, configure a digital filtering data path pre-set in the FPGA and based on a general-purpose circular shift register array; S3. Based on the variable sampling rate, the handshake protocol timing of the input and output data streams of the configurable digital filter data path is adaptively adjusted to achieve data synchronization with upstream and downstream modules; S4. The input data stream is filtered using the configured configurable digital filter data path to obtain an output data stream that conforms to the target filter parameters.

2. The general digital variable sampling filtering method based on FPGA according to claim 1, characterized in that, S2 further includes: Before configuring the digital filter data path, the read operation on the first-in-first-out buffer is stopped, wherein the first-in-first-out buffer is used to receive and store the input data stream; After configuring the digital filter data path, start the read operation on the first-in-first-out buffer.

3. The general digital variable sampling filtering method based on FPGA according to claim 2, characterized in that, S2 further includes: When the read operation on the first-in-first-out buffer is terminated, the current data volume in the first-in-first-out buffer is recorded as the transition data volume; S4 further includes: After initiating the read operation on the first-in-first-out buffer, a preset transition state identifier is placed in the corresponding output data stream for the data samples read from the first-in-first-out buffer in quantities equal to the amount of transition data.

4. The general digital variable sampling filtering method based on FPGA according to claim 3, characterized in that, S1 includes: Obtain parameters for a transitional data processing mode; S4 includes: Based on the transition data processing mode parameters, perform one of the following preset operations on the data sample with the transition state identifier: Output the data sample and the transition state identifier; or discard the data sample and do not output it.

5. The general digital variable sampling filtering method based on FPGA according to claim 1, characterized in that, S1 includes: Obtain a coefficient set selection index, wherein the FPGA stores multiple sets of coefficient sets corresponding to the coefficient set selection index; S2 further includes: Based on the coefficient set selection index, a target coefficient set is determined from the multiple sets of stored coefficient sets, and the configurable digital filter data path is configured with the target coefficient set.

6. The general digital variable sampling filtering method based on FPGA according to claim 5, characterized in that, The memory storing the multiple sets of coefficients is a read-write random access memory; The FPGA-based general digital variable sampling filtering method also includes: At least one set of coefficients in the random access memory is received and overwritten via a configuration interface.

7. The general digital variable sampling filtering method based on FPGA according to claim 6, characterized in that, The random access memory includes at least two independent coefficient storage areas; The step of receiving and overwriting at least one set of coefficients in the random access memory via a configuration interface includes the following sub-steps: Designate one of the at least two independent coefficient storage areas as an online area for the configurable digital filter data path to read coefficients, and designate the other as an offline area; Perform an overwrite operation on the coefficient set, wherein the overwrite operation on the coefficient set is performed only in the offline area; After the overwrite operation in the offline area is completed, the offline area is switched to the online area.

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