Unified probability graph-based multi-task computing architecture implementation method and device, equipment and medium

Abstract

The application discloses a multi-task computing architecture implementation method and device based on a unified probability graph, equipment and a medium, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; the unified signal model is represented as a unified probability graph model; message passing between variable nodes and check nodes in the unified probability graph model is set to determine an iterative operation unit; and the baseband signal processing task is processed by multiplexing the iterative operation unit in a hardware circuit and a processor. In summary, the application can be widely applied in baseband signal processing.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a method, apparatus, device, and medium for implementing a multi-task computing architecture based on a unified probabilistic graph. Background Technology

[0002] For differentiated signal processing tasks, it is often necessary to design elements and customize algorithms for different tasks, which limits chip flexibility and becomes a bottleneck for full task coverage in the 6G era. Baseband signal processing, as a core component of a communication system, involves multiple differentiated communication elements, which collectively determine the efficiency, reliability, and adaptability of signal transmission. For example, in signal modulation, different digital modulation techniques are selected according to different communication scenarios to adapt to different bandwidth requirements and anti-interference capabilities; in coding schemes, differentiated error correction coding strategies can improve signal fault tolerance in noisy environments, and so on.

[0003] Current technologies lack exploration of a unified baseband signal processing architecture. Optimizing individual signal processing units independently makes it difficult to achieve optimal overall energy efficiency in general-purpose baseband signal processing. The underlying theoretical reason lies in the multidimensional heterogeneity of each signal processing unit across time (processing timing, duration, etc.), space (computing power, storage resources, etc.), and processing architecture. The nonlinear coupling between baseband power consumption and the time and space dimensions of each processing unit, along with the difficulty of optimizing local unit modules, makes it challenging to achieve an optimal balance between power consumption and performance under multiple constraints. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, in response to the above-mentioned problems, the object of the present invention is to provide a method, apparatus, device, and medium for implementing a multi-task computing architecture based on a unified probabilistic graph, capable of fusing and representing different signal processing functions based on a single model.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a method for implementing a multi-task computing architecture based on a unified probabilistic graph, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; representing the unified signal model as a unified probabilistic graph model; setting up message passing between variable nodes and verification nodes in the unified probabilistic graph model, and determining iterative operation units; and realizing the processing of the baseband signal processing tasks by reusing the iterative operation units in hardware circuits and processors.

[0007] Secondly, the present invention also provides an implementation device for a multi-task computing architecture based on a unified probabilistic graph, comprising: a signal model establishment unit configured to establish a unified signal model based on the common characteristics of baseband signal processing tasks; a probabilistic graph model establishment unit configured to represent the unified signal model as a unified probabilistic graph model; a message passing unit configured to set up message passing between variable nodes and verification nodes in the unified probabilistic graph model and determine an iterative operation unit; and a task processing unit configured to process baseband signal processing tasks by reusing the iterative operation unit.

[0008] Thirdly, the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the method described thereon.

[0009] Fourthly, the present invention also provides a computer-readable storage medium for storing one or more programs, said one or more programs including computer instructions for causing a computer to perform the method.

[0010] This invention, by adopting the above technical solutions, has the following characteristics: 1. Starting from the common characteristics of baseband signal processing tasks, this invention uses probabilistic graphical theory to uniformly represent baseband signal processing elements as a unified probabilistic graphical model, realizing the fusion representation of multiple signal processing functions by a single model, laying a mathematical foundation for unified optimization of terminal signal processing power consumption. 2. This invention, through its iterative computing unit, can flexibly adapt to multiple types of signal processing tasks, support dynamic processor reconfiguration, achieve "multi-functionality with a single hardware component," and the estimation accuracy of unknown variables can approach the performance limit. In summary, this invention can be widely applied to baseband signal processing tasks. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. In the drawings:

[0012] Figure 1 This is a schematic diagram of baseband signal multitasking according to an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram illustrating the unified representation of differentiated baseband signal processing tasks based on probabilistic graphs according to an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of the time-parallel processing architecture of the in-memory computing device according to an embodiment of the present invention;

[0015] Figure 4 This is a schematic diagram of the time-serial processing architecture of the in-memory computing integrated device according to an embodiment of the present invention;

[0016] Figure 5 This is a schematic diagram illustrating the connection relationship between the verification node and each variable node in the probabilistic graphical model of this invention. Detailed Implementation

[0017] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0018] To address the problem that traditional algorithms struggle to adapt to diverse task requirements in baseband signal processing, this invention provides a method, apparatus, device, and medium for implementing a multi-task computing architecture based on a unified probabilistic graph. The method includes: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; representing the unified signal model as a unified probabilistic graph model; setting up message passing between variable nodes and verification nodes in the unified probabilistic graph model to determine iterative computation units; and realizing the processing of baseband signal processing tasks by reusing the iterative computation units in hardware circuits and processors. Therefore, this invention starts with the common characteristics of baseband signal processing tasks, establishes a unified representation model of baseband signal processing elements based on probabilistic graphs, and achieves the fusion representation of multiple signal processing functions using a single model.

[0019] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0020] Example 1: This example provides a method for implementing a multi-task computing architecture based on a unified probabilistic graph, including:

[0021] S1. Establish a unified signal model based on the common characteristics of baseband signal processing tasks.

[0022] In this embodiment, the baseband signal processing tasks include applications such as channel decoding, channel detection, channel estimation, multi-antenna detection, and image recognition. This is just one example, and is not limited to this.

[0023] Specifically, such as Figure 1 As shown, the baseband signal processing tasks in this embodiment include: Task 1: multi-antenna detection task; Task 2: channel decoding task; Task 3: channel estimation task; Task 4: multi-user identification task.

[0024] like Figure 2 As shown, based on the common characteristics of baseband signal processing tasks, a unified signal model is established as follows: ,in, For unknown variables, For observed variables, For given and The correlation mapping matrix between them This is unknown disturbance noise. Each is a certain unknown variable. Each of these represents a specific observed variable.

[0025] It should be noted that the parameters of the unified signal model have different meanings when facing different baseband signal processing tasks. For example, in a multi-antenna detection task: This is the characteristic matrix of a multi-antenna channel. For the transmitted symbol to be estimated, For the mixed signal observed by the receiver from multiple antennas, continuous, continuous, For unknown discrete variables; in channel decoding tasks: This is the codeword verification matrix. For the transmitted bits to be estimated, The bit sequence received by the receiving end. Discrete, continuous, For unknown discrete variables; in channel estimation tasks: For pilot structure matrix, For the communication channel to be estimated, The pilot signal observed at the receiving end. continuous, For unknown continuous variables; in multi-user detection tasks, For the perception matrix, The device is in an active state. The signal observed by the receiver is a superimposed signal from multiple users. continuous, continuous, It is an unknown continuous variable.

[0026] S2. Based on probabilistic graphical theory, the unified signal model is represented as a unified probabilistic graphical model.

[0027] In this embodiment, the unified probabilistic graphical model includes multiple variable nodes, multiple verification nodes, and multiple undirected edges. Undirected edges connect variable nodes and verification nodes that have a connection relationship. Each variable node corresponds to an association mapping matrix. A column vector, where each verification node corresponds to an association mapping matrix. A row vector in the associated mapping matrix The number of rows is Association mapping matrix The number of columns is For example: association mapping matrix The Middle Row vector is represented as , For the correlation mapping matrix No. Line number The elements of the column are represented as validation nodes. With variable nodes The relationship between them, if the association mapping matrix middle If the element is 1, then the variable node With verification node If there is a connection relationship, such as an association mapping matrix of If the element is 0, then the variable node... With verification node No connection exists.

[0028] Furthermore, the set of unknown variable states in the baseband signal processing task is unified into variable nodes in the probabilistic graphical model, and the coupling law of signal sequence in the baseband signal processing task is unified into verification nodes. Verification nodes are used to characterize the coupling relationship between unknown variables, observed variables, and correlation mapping matrices. Here, the coupling law of signal sequence refers to the combined effect of verification nodes and correlation laws in the probabilistic graphical model.

[0029] Furthermore, based on the preceding formal transformation, each signal processing problem in the baseband signal processing task is transformed into a problem of estimating unknown variables based on observed variables and correlation patterns. The signal state of a certain task is the variable to be estimated. The set of possible values ​​for states, in this embodiment, is assumed to have K states, denoted as follows: For example, in a decoding scenario, K states represent the values ​​of the transmitted bits. In LDPC decoding...K =2, =1, =0, the specific application of which will be explained in subsequent embodiments, and will not be repeated here.

[0030] S3. Design a unified probabilistic graphical model for message passing, determine the iterative operation unit, and realize the propagation and diffusion of local probability messages to global probability messages through mutual message passing between verification nodes and variable nodes, so as to approximate the maximum posterior probability of the variable to be estimated and approximately achieve the optimal estimate.

[0031] In this embodiment, as Figure 2 As shown, the message passing mechanism of the unified probabilistic graphical model is designed, and the iterative computation unit is determined. The specific process is as follows:

[0032] 1) Construct the probability configuration function.

[0033] In this embodiment, the first Probability configuration function for each verification node This is used to characterize the differences in probabilistic iterative messages from the check node to the variable node in different baseband signal processing tasks. A probabilistic configuration function is constructed based on different tasks. They are all different, the verification node and the probability configuration function The quantities are in a one-to-one correspondence. Specifically, the probability allocation function... Essentially, it represents a given correlation mapping matrix. With unknown variables After about the observed variables The posterior probability satisfies It is used to characterize the differentiated constraint rules between tasks. The core objective of unified probabilistic graphical computation is to maximize the posterior probability, i.e. The variable to be estimated is passed Obtain, among which, Represents the set of states of a variable node.

[0034] Furthermore, this embodiment effectively addresses the problem of significant algorithmic differences between communication signal processing elements / units by fusing and representing signal processing elements and unifying the inference architecture, thus laying a mathematical model foundation for joint power consumption optimization across elements. Appropriate probability configuration functions are set during specific signal processing. It can achieve flexible switching of baseband signal processing functions, and the probability configuration function can be adjusted according to different baseband signal processing tasks. They are also different. The following explanation focuses on different baseband signal processing tasks, using this as an example, but is not limited to:

[0035] Multi-antenna detection tasks Configured as follows:

[0036] ;

[0037] Channel estimation task Configured as follows:

[0038] ;

[0039] Channel decoding task Configured as follows:

[0040] ;

[0041] in, Indicates the noise variance. H represents the received signal, and H represents the matrix transpose. Represents the association mapping matrix The first in row vectors This indicates the remainder calculation. This indicates that the remainder is inverted.

[0042] 2) Construct message passing between the verification node and the variable node as the iterative calculation unit.

[0043] In this embodiment, the implementation process of the iterative operation unit is as follows:

[0044] Posterior propagation unit (backpropagation): Each verification node uses prior messages from neighboring variable nodes to calculate posterior messages and broadcasts the results to connected variable nodes.

[0045] Prior propagation unit (forward propagation): Each variable node updates its prior confidence message using the posterior message from its neighboring check nodes and propagates the update to all connected check nodes.

[0046] Based on the aforementioned iterative computation unit, the propagation and diffusion of local probability messages to global probability messages are achieved through mutual message passing between verification nodes and variable nodes, approximating the maximum posterior probability of the variable to be estimated and approximately reaching the optimal estimate.

[0047] Furthermore, the specific computational form of the iterative operation unit is not limited and can be determined according to actual needs. In this embodiment, the specific implementation form of the posterior propagation unit is as follows:

[0048]

[0049] in, This represents the states contained in the variable node. For verification nodes To the variable node Passed variables The state value is The message (essentially representing the verification node) To the variable node The message about the first Variables about The confidence level is the posterior probability. for The probability configuration function, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, Indicates and verifies the node There are connections, except for variable nodes. The combination of all variable node states except for It is a set The number of candidate vectors is . M Candidate vectors are unknown variables One of the elements, Indicates and verifies the node Connected and variable nodes Values The combination of all variable node states, express From the verification node A set of indexes of variable nodes with connections Take the value from; It concerns the transmission of messages from the variable node to the verification node. The function, the specific calculation method includes but is not limited to , Represents variable nodes To the verification node The message conveyed about The news.

[0050] The specific implementation of the prior propagation unit in this embodiment is as follows:

[0051]

[0052] In the formula, Represents variable nodes To the verification node Variables passed between The state value is Messages (essentially variable nodes) to the inspection point The message about the first Variables about The confidence level (i.e., the prior probability) Represents variable nodes To the verification node The message is from the verification node. Other than variable nodes Connected verification nodes The message generation is given, where: Taking this as an example, but not limited to this, For verification nodes To the variable node Passing information about variables The state value is The news.

[0053] S4. Flexible processing of multiple tasks is achieved by reusing iterative operation units in hardware circuits and processors.

[0054] In this embodiment, the iterative operation unit realizes the message passing between the verification node and the variable node in multiple signal processing tasks. Facing the corresponding baseband signal processing task, the iterative operation unit is deployed and multiplexed in the hardware circuit and processor. In each iteration, the two coupled stages perform posterior and prior propagation, enabling flexible processing of multiple tasks. Different baseband processing tasks can be handled simply by switching... The configuration allows for signal processing of the corresponding task. Therefore, this invention can flexibly adapt to various types of signal processing tasks and meet diverse task requirements.

[0055] The following detailed embodiments illustrate the specific application of the multi-task computing architecture implementation method based on unified probabilistic graphs of the present invention.

[0056] In the baseband signal processing task, each signal processing problem is transformed into a problem of estimating unknown variables based on observation vectors and correlation patterns. The message passing process from each verification node to the variable node is completed on the in-memory computing device. The core of the in-memory computing device-driven probabilistic graph computation lies in the iterative message update and confidence propagation between the variable node and the verification node. Posterior and prior propagation are performed through two coupled stages in each iteration.

[0057] In this embodiment, for any verification node in the unified probabilistic graphical model, each variable node connected to the verification node via undirected edges can be determined, as can the undirected edges between the verification node and each variable node. This is based on each undirected edge and the association mapping matrix. Construct the node state matrix corresponding to each undirected edge, with the total number of node state matrices corresponding to the total number of undirected edges. Based on the unified probabilistic graphical model, the 1st... i The message passing of all variable nodes connected by undirected edges to each verification node is represented as a unified signal processor architecture for vector-matrix multiplication (VMM) operations:

[0058] .

[0059] The unified signal processor architecture includes a node state matrix. driving vector and state value probability vector The specific implementation of the above formula is as follows:

[0060] .

[0061] Based on the unified signal processor architecture described above, the operations involved in the probabilistic graph calculation are implemented using continuous physical operators (voltage and current). Specifically, the node state matrix is ​​pre-stored in a memory-computing characteristic device; the input of the memory-computing characteristic device is set to a voltage value vector proportional to the driving vector, for example:

[0062] The output of the in-memory computing device is a current value. Through Kirchhoff's laws, a weighted sum of probability products is used to obtain the state value probability vector. .

[0063] Specifically, the unified signal processor architecture based on in-memory computing devices will be described in this embodiment using only memristors as an example, and is not limited to this. A memristor is the fourth basic circuit element after resistors, capacitors, and inductors. Its resistance is determined by the excitation and changes continuously. It features high integration density, fast operation speed, low power consumption, and non-volatility. A memristor cross array can complete vector and matrix multiplication and accumulation operations within one cycle. The multiplication factors are directly stored in the memristor array, eliminating the need for separate storage units.

[0064] The memristor in this embodiment includes a large memristor array, which is composed of... (Association mapping matrix) The graph is composed of subarrays (containing the number of non-zero elements), and the number of subarrays corresponds to the number of undirected edges in the probability graph. For example, when using memristor subarrays... During calculation, the formula can be equivalently transformed into the vector-matrix multiplication form described above, and the verification nodes can be checked. To the variable node The subarray number corresponding to the message passing is denoted as For the first Subarrays, Perform subsequent calculations:

[0065] .

[0066] In practical use, the memristor subarray has a pre-set node state matrix:

[0067]

[0068] Set the voltage to The input is given to the rows of the memristor subarray, where... This refers to... Array number The voltage of the row input is proportional to the voltage in the set. (Indicates the relationship with the verification node) There are connections, except for variable nodes. The combination of all variable node states except those of other variables) m vectors probability , It concerns the transmission of messages from the variable node to the verification node. The function, and its specific calculation method includes but is not limited to:

[0069] .

[0070] Column output current of memristor subarray .

[0071] The current output by the memristor cross array is iteratively updated to obtain the message transmission from each variable node to each check node, which is then used as the input to the memristor cross array, thus completing the iterative process until the iteration ends.

[0072] In this embodiment, each variable node uses posterior messages from neighboring verification nodes. Update prior confidence messages The update will then be propagated to all connected verification nodes. Specifically, the message passing from the variable calculation node to the verification node involves: .

[0073] In a preferred embodiment of the present invention, a DAC module and an ADC module are further provided. The ADC module is used to convert the current value output by the memristor array into a digital signal for calculating the message passing from the variable node to the test node. The calculation process can be implemented using an existing FPGC, which will not be described in detail here. The DAC module is used to convert the calculation result of the message passing from the variable node to the test node into a voltage signal and input it into the memristor array for iterative calculation, which will not be described in detail here.

[0074] In a preferred embodiment of the present invention, the computing architecture of the in-memory computing device is configured in two modes: a time-parallel processing architecture and a time-serial processing architecture. For example... Figure 3 The diagram shows a time-parallel processing architecture where each subarray is independently disconnected. For example, decoding can be performed using each memristor subarray by simultaneously inputting the input voltage into all subarrays and reading out the current for iterative calculation. Figure 4 The diagram illustrates a time-serial processing architecture, where subarrays are connected. For example, various memristor subarrays can be combined into a large memristor array for decoding. This is achieved by sequentially inputting voltages to the corresponding subarrays according to time slots. Each subarray then sequentially reads the corresponding input voltage and current, and then inputs them again according to time slots for iterative calculation. It's important to note that the array values ​​and sizes are exactly the same in both methods. In the time-parallel processing architecture, the subarrays are independently disconnected, while in the time-serial processing architecture, the subarrays are not disconnected; however, the subarrays can be arranged and connected sequentially.

[0075] The following example uses Turbo decoding as a baseband processing task to illustrate the specific application of the circuit implementation method based on the unified probabilistic graph computing architecture of the present invention.

[0076] The circuit implementation method based on a unified probabilistic graphical computing architecture for processing Turbo decoding tasks proposed in this embodiment should be noted that the correlation mapping matrix in Turbo decoding is an extended parity-check matrix. The specific process includes:

[0077] S101. Obtain the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded.

[0078] In this embodiment, the Turbo code to be decoded is the received Turbo code sent by the sender that needs to be decoded. The extended parity-check matrix is ​​a parity-check matrix created based on the Turbo code to be decoded and used for decoding the Turbo code. The encoder can encode the original K bit information codewords into N codewords using a Turbo encoder. Then, based on BPSK as an example, N symbols s are modulated and sent to the decoding end. Due to noise interference during transmission, the decoding end in this embodiment receives N symbols. The decoding task at the decoding end is to... The initial K codewords, i.e., the original bit information, are restored. The probabilistic graphical model is a unified probabilistic graphical model corresponding to the extended parity-check matrix, used for decoding the Turbo code to be decoded. Each variable node corresponds to a column vector in the extended parity-check matrix, and each parity node corresponds to a row vector in the extended parity-check matrix. If the row order in the extended parity-check matrix is ​​equal to... i Column order equals j If the element is 1, then the order of the first node is equal to... iThe order of the verification node and the second node is equal to j The variable nodes have a connection relationship. If the row order in the extended parity matrix is ​​equal to... i Column order equals j If the element is 0, then the order of the first node is equal to... i The order of the verification node and the second node is equal to j The variable nodes have no connection relationship. The first node's order is the sequence number of the check node among all check nodes, and the second node's order is the sequence number of the variable node among all variable nodes.

[0079] To better illustrate the relationship between the extended parity-check matrix and the probabilistic graphical model in this embodiment, as well as the relationship between variable nodes, parity nodes, and undirected edges, it is specifically explained as follows: When the extended parity-check matrix is ​​an I-row, J-column matrix, and its third row vector is [0, 1, 1, 1, 0, 0], the probabilistic graphical model includes I parity nodes and J variable nodes (in this case, J is 6). The third parity node in the probabilistic graphical model... i (at this time, i 3) The connection relationships between the variables and the nodes are as follows: Figure 5 As shown in the diagram, the 2nd, 3rd, and 4th elements of this row vector are 1, and the 1st, 5th, and 6th elements are 0. Therefore, the 3rd check node is connected to the 2nd, 3rd, and 4th variable nodes via undirected edges, while the 3rd check node is not connected to the 1st, 5th, and 6th variable nodes. It should be noted that... Figure 5 Except for the third check node, the connection relationships between other check nodes and variable nodes are not shown. These connections can be understood by referring to the connection relationship between the third check node and variable nodes described above. Furthermore, the initial probability of the state value of each variable node can include the first and second initial probabilities, given that the original Turbo codewords corresponding to the variable node are 1 and 0 respectively, under the condition that the extended codewords corresponding to the variable node are known.

[0080] S102. Propagate the initial probability of the state value of each variable node to each verification node connected by an undirected edge. For any variable node, propagate the initial probability of its state value to different verification nodes. It is understood that the variable node will only pass messages to verification nodes with which it has a connection, and will not pass messages to verification nodes with which it does not have a connection.

[0081] S103. For any verification node, construct the node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each target variable node connected to it, and the extended verification matrix.

[0082] In this embodiment, a target variable node is a variable node connected to a verification node via an undirected edge. A target undirected edge is the undirected edge connecting the verification node and the target variable node. Specifically, for any verification node in the probabilistic graphical model, this embodiment can determine each target variable node connected to the verification node via an undirected edge, and determine the target undirected edges between the verification node and each target variable node. Based on each target undirected edge and the extended verification matrix, a node state matrix corresponding to each target undirected edge is constructed. The node state matrix is ​​a matrix used to configure the node states in the in-memory computing device. It can be understood that this embodiment can construct the node state matrix corresponding to each target undirected edge connected to a verification node. Therefore, this embodiment can construct the node state matrix corresponding to each undirected edge based on each undirected edge in the probabilistic graphical model, and the total number of node state matrices corresponds to the total number of undirected edges.

[0083] S104. Construct the driving vector corresponding to each target undirected edge.

[0084] In this embodiment, for any verification node in the probabilistic graphical model, a driving vector corresponding to each target undirected edge can be constructed based on each target undirected edge connected to the verification node and the message passing between each target variable node and the verification node. It can be understood that this embodiment can construct the driving vector corresponding to each target undirected edge for each target undirected edge connected to a certain verification node. Therefore, this embodiment can construct a driving vector corresponding to each undirected edge based on each undirected edge in the probabilistic graphical model, and the total number of driving vectors corresponds to the total number of undirected edges.

[0085] S105. Configure the in-memory computing characteristic device based on the node state matrix corresponding to each undirected edge to obtain the in-memory computing characteristic device subarray corresponding to each undirected edge.

[0086] In this embodiment, for any node state matrix corresponding to an undirected edge, the state of each node in the initial state of the in-memory computing device can be configured according to the node state matrix corresponding to the undirected edge, thereby obtaining the in-memory computing device subarray corresponding to the undirected edge. It can be understood that in this embodiment, for any undirected edge in the probabilistic graphical model, a corresponding in-memory computing device subarray can be configured.

[0087] S106. Based on the driving vector, the in-memory computing characteristic device subarray, and the state value probability vector corresponding to each undirected edge, the original Turbo code and the original bit information corresponding to the Turbo code to be decoded are obtained.

[0088] Specifically, in this embodiment, the Turbo code to be decoded can be obtained by using the driving vector corresponding to each undirected edge in the probabilistic graphical model, the in-memory computing characteristic device subarray, and the state value probability vector, to obtain the original Turbo code (such as the N codes mentioned above). The original Turbo code and the original bit information (such as the K codewords mentioned above) are obtained. The Turbo decoding method based on in-memory computing devices in this embodiment can be achieved by constructing an extended parity-check matrix and a probabilistic graphical model. Based on the extended parity-check matrix and the probabilistic graphical model, the in-memory computing device subarray and voltage vector corresponding to each undirected edge are configured. Based on the in-memory computing device subarray, driving vector, and state value probability vector corresponding to each undirected edge, the Turbo code to be decoded is decoded to obtain the original Turbo code and the original bit information.

[0089] Specifically, when the in-memory computing characteristic device uses a memristor, the node state matrix is ​​a node resistance state matrix. In this case, step S103 includes: obtaining the number t of target undirected edges, determining the internal order of each target undirected edge among all target undirected edges; constructing multiple candidate vectors obtained by arranging and combining t target binary characters; for any candidate vector, if the element order of the target binary characters in the candidate vector is equal to the internal order of the target undirected edge, then establishing an association between the target binary characters in the candidate vector and the target variable nodes connected by the target undirected edge; sequentially traversing each target undirected edge; for the a-th target undirected edge traversed, dividing the multiple candidate vectors into multiple first candidate vectors and multiple second candidate vectors to be processed; constructing the node resistance state matrix corresponding to the target undirected edge based on each first candidate vector, second candidate vector, association relationship, and extended parity check matrix; wherein the a-th element in the first candidate vector is 1, and the a-th element in the second candidate vector is 0.

[0090] Optionally, the above-mentioned construction of the node resistance matrix corresponding to the target undirected edge based on each first candidate vector, second candidate vector, association relationship, and extended check matrix includes: for any candidate vector to be processed, constructing a zero vector with a total number of elements equal to the total number of variable nodes; determining the node order of the target variable nodes associated with each target binary character in the candidate vector to be processed as the unique order to be arranged for each target binary character; replacing each zero element in the zero vector whose position order is equal to the order to be arranged with the target binary character uniquely corresponding to the order to be arranged, to obtain the processed candidate vector; wherein, the candidate vector to be processed is either the first candidate vector or the second candidate vector; when the candidate vector to be processed is the first candidate vector, the processed candidate vector is the first processed candidate vector; when the candidate vector to be processed is the second candidate vector, the processed candidate vector is the first processed candidate vector; when the candidate vector to be processed is the first candidate vector, the processed candidate vector is the second processed candidate vector. When the second candidate vector is selected, the processed candidate vector becomes the second processed candidate vector. The target row vector uniquely corresponding to the verification node is determined in the extended verification matrix. For any first processed candidate vector, the target row vector is moduloed by the first processed candidate vector to obtain the corresponding first value. The first value is then inverted to obtain the first inverted value. Each first inverted value is arranged to obtain the first node resistance column vector. For any second processed candidate vector, the target row vector is moduloed by the second processed candidate vector to obtain the corresponding second value. The second value is then inverted to obtain the second inverted value. Each second inverted value is arranged to obtain the second node resistance column vector. The first node resistance column vector and the second node resistance column vector are horizontally concatenated to obtain the node resistance matrix corresponding to the target undirected edge.

[0091] To better illustrate the above execution process, this embodiment describes the process as follows: This embodiment applies to any verification node i The verification node can be determined in the probabilistic graphical model. i Connecting the target variable nodes and the target undirected edges. For example... Figure 5 As shown, when iWhen t is 3, the target variable nodes connected to the 3rd check node are the 2nd, 3rd, and 4th variable nodes, respectively. In this case, the number of target undirected edges t equals 3, and each target undirected edge is an undirected edge connecting the 3rd check node to the 2nd, 3rd, and 4th variable nodes. The internal order of each target undirected edge among all target undirected edges is 1, 2, and 3. Target binary characters include 0 and 1. When t equals 3, multiple candidate vectors are constructed by permuting and combining the 3 target binary characters. The number of candidate vectors is 2 to the power of 3, i.e., 8 candidate vectors, namely (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0), and (1, 1, 1). It can be understood that the number of elements in the candidate vectors is the same as the number of target undirected edges. The first, second, and third target binary characters in the candidate vectors are associated with the target variable nodes connected by the undirected edges of the target nodes in the internal order 1, 2, and 3, respectively. This means that the first, second, and third target binary characters in the candidate vectors are associated with the second, third, and fourth variable nodes, respectively. 'a' represents the internal order of the undirected edges. The first, second, and third undirected edges are traversed sequentially. Upon reaching each undirected edge, the eight candidate vectors are divided into first and second candidate vectors. For example, when traversing to the third undirected edge, 'a' equals 3. If the third element in the candidate vector is 1, it is determined as the first candidate vector; if the third element is 0, it is determined as the second candidate vector. The first candidate vectors at this point include (0,0,1), (0,1,1), (1,0,1), and (1,1,1), while the second candidate vectors include (0,0,0), (0,1,0), (1,0,0), and (1,1,0). Each of the first and second candidate vectors mentioned above is used as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is used as a candidate vector to be processed, a zero vector (0, 0, 0, 0, 0, 0) with a total number of elements equal to the total number of variable nodes (6) is first constructed. The first, second, and third target binary characters in the first candidate vector are associated with the second, third, and fourth variable nodes, respectively. Therefore, in this embodiment, the second, third, and fourth zero elements in the zero vector can be replaced with the first, second, and third target binary characters in the first candidate vector, respectively, to obtain the corresponding first processed candidate vector (0, 0, 1, 1, 0, 0). At this point, when this embodiment traverses to the third target undirected edge, four first processed candidate vectors and four second processed candidate vectors can be obtained based on this target undirected edge. Then, in this embodiment, the target row vector uniquely corresponding to the third verification node can be determined in the extended verification matrix, that is, the third row vector in the extended verification matrix.For any first-processed candidate vector, perform a modulo operation between the target row vector and the first-processed candidate vector to obtain a corresponding first value. Invert this first value to obtain a first inverted value. This results in four corresponding first inverted values. Arrange these four first inverted values ​​vertically to obtain the first node resistance column vector. For any second-processed candidate vector, perform a modulo operation between the target row vector and the second-processed candidate vector to obtain a corresponding second value. Invert this second value to obtain a second inverted value. This results in four corresponding second inverted values. Arrange these four second inverted values ​​vertically to obtain the second node resistance column vector. Concatenate the first and second node resistance column vectors horizontally to obtain the node resistance matrix corresponding to the third target undirected edge.

[0092] Optionally, when the in-memory computing characteristic device is a memristor, the driving vector is a voltage vector. In this case, step S104 includes: when traversing to the a-th target undirected edge, deleting the a-th element in each candidate vector to obtain multiple first vectors; deduplicating multiple first vectors to obtain multiple second vectors; for any second vector, determining the target confidence level corresponding to each target binary character in the second vector; multiplying the target confidence levels corresponding to each target binary character in the second vector to obtain the product corresponding to the second vector; arranging the products corresponding to each second vector to obtain the voltage vector corresponding to the target undirected edge; wherein, the target confidence level corresponding to the target binary character in the second vector is: the confidence level of the target variable node associated with the target binary character, which transmits its own state value equal to the target binary character to the verification node. 'a' represents the internal order of each target undirected edge connected to the 3rd verification node. When a is 3, the eight candidate vectors created in this embodiment are (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0), and (1, 1, 1). In this case, the third element of each candidate vector can be deleted to obtain eight first vectors: (0, 0), (0, 0), (0, 1), (0, 1), (1, 0), (1, 0), (1, 1), and (1, 1). After deduplication, the remaining four second vectors are obtained: (0, 0), (0, 1), (1, 0), and (1, 1). For any of the second vectors, such as the second vector (0, 1), this embodiment can determine the target confidence level corresponding to each target binary character in the second vector. The confidence level corresponding to the first target binary character in the second vector is: the confidence level of the target variable node (i.e., the second variable node) associated with the target binary character transmitting the message with its own state value equal to 0 to the third verification node. The confidence level corresponding to the second target binary character in the second vector is: the confidence level of the target variable node (i.e., the third variable node) associated with the target binary character transmitting the message with its own state value equal to 1 to the third verification node. Multiplying the two determined confidence levels yields one product corresponding to the second vector. Four products are calculated for the four second vectors. Arranging these four products vertically yields the voltage vector corresponding to the third target undirected edge.

[0093] The voltage vector corresponding to the target undirected edge constructed in this embodiment can be represented as:

[0094]

[0095] Among them, with Let's take an example to explain the meaning of each character. Indicates the first i The verification node and the first jUndirected edges between nodes with variables The subscript 2 indicates the candidate vector set. M The second candidate vector was obtained. For The voltage value of the second row of the array input is proportional to the voltage value of the candidate vector. m vectors The probability of.

[0096] Optionally, when the in-memory computing characteristic device is a memristor, the in-memory computing characteristic device subarray is a memristor subarray. In this case, step S105 includes: for any undirected edge corresponding to a node resistance state matrix, obtaining the corresponding initial memristor subarray based on the number of rows and columns of elements in the node resistance state matrix, where the number of rows and columns of nodes in the initial memristor subarray corresponds to the number of rows and columns of elements; for any target element at any position in the node resistance state matrix, determining the corresponding target node in the initial memristor subarray based on the target element's position in the node resistance state matrix; if the target element is 1, setting the target node's resistance state to a low resistance state; if the target element is 0, setting the target node's resistance state to a high resistance state; in this embodiment, when describing the construction of the above-mentioned node resistance state matrix, the first node resistance state column vector and the second node resistance state column vector are horizontally concatenated to obtain the node resistance state matrix corresponding to the third target undirected edge. Specifically, in Figure 5 In the memristor subarray corresponding to the third target undirected edge, the resistance state of each node in the first node column is configured according to each element in the first node resistance state column vector, and the resistance state of each node in the second node column is configured according to each element in the second node resistance state column.

[0097] The memristor subarray corresponding to the target undirected edge constructed in this embodiment can be represented as a matrix:

[0098]

[0099] in, Indicates the first i The verification node and the first j Undirected edges between variable nodes Each represents a candidate vector after the first processing described above. Each of these represents a candidate vector after the second processing described above. The first column on the left of this matrix is ​​essentially the first node's resistance state column vector, representing the values ​​obtained by multiplying the target row vector by the corresponding candidate vector after the first processing. The second column on the left of this matrix is ​​essentially the second node's resistance state column vector, representing the values ​​obtained by multiplying the target row vector by the corresponding candidate vector after the second processing. (Memristor subarray) This is obtained by configuring the resistance states based on the elements in the node resistance state matrix, and the elements of the node resistance state matrix can be configured as follows: , The negation operator is 'NOT', and mod is the modulo operator. For the extended parity check matrix, the first row vectors. Indicates according to the first The verification node and the first The above-mentioned processed candidate vector is constructed from the undirected edges between the variable nodes.

[0100] Optionally, the memristor subarray corresponding to the undirected edge includes a first node column and a second node column. The first node column corresponds to the case where the variable node connected to the undirected edge has a state value of 1, and the second node column corresponds to the case where the variable node connected to the undirected edge has a state value of 0. In the decoding scenario, K states represent the values ​​of the transmitted bits. In LDPC decoding, K=2. u 1=1, u K = 0, the number of columns in the node resistance matrix corresponding to each undirected edge is the same as the value of K, and the number of rows in the node resistance matrix corresponding to each undirected edge is the same as the number of candidate vectors. Since K = 2 in this embodiment, Figure 5 If the verification node 3 has 3 target undirected edges, then the number of candidate vectors is . .

[0101] At this point, step S106 includes: for any undirected edge, according to each voltage element in the voltage vector corresponding to the undirected edge, inputting a voltage equal to the magnitude of the voltage element to each row node in the memristor subarray corresponding to the undirected edge, and reading the first current value of the first node column and the second current value of the second node column in the memristor subarray respectively; according to the first current value and the second current value in each memristor subarray, updating the state value of each variable node to be transmitted to each verification node, and updating the new probability of the state value of each variable node; determining whether the new probability of the state value of each variable node meets the set conditions; if the new probability of the state value of each variable node does not meet the set conditions, then taking the new confidence of each variable node to be transmitted to each verification node as the current confidence, and returning to step S104 until the set conditions are met; if the set conditions are met, then determining the original Turbo code according to the new probability of the state value of each variable node; deciphering the original Turbo code to obtain the corresponding original bit information.

[0102] Optionally, the update to obtain the new probability of the state value of each variable node includes: for any variable node, determining each undirected edge connected to the variable node, multiplying the first current value in the memristor subarray corresponding to each undirected edge connected to the variable node with the square of the first initial probability in the initial probability of the variable node's state value to obtain the new probability that the variable node's own state value is equal to 1, multiplying the second current value in the memristor subarray corresponding to each undirected edge connected to the variable node with the square of the second initial probability in the initial probability of the variable node's state value to obtain the new probability that the variable node's own state value is equal to 0; determining whether the new probability of the state value of each variable node satisfies the set conditions includes: performing a hard decision on the new probability of the state value of each variable node to obtain a codeword vector; performing a modulo operation on the extended parity check matrix and the codeword vector to obtain the operation result; if the operation result is equal to 0, it is determined that the set conditions are satisfied; if the operation result is not equal to 0, it is determined that the set conditions are not satisfied; determining the original Turbo code based on the new probability of the state value of each variable node includes: selecting the first N elements in the latest codeword vector and determining them as the original Turbo code.

[0103] To better illustrate the above execution process, this embodiment will continue to provide a detailed description. For example... Figure 5 As shown, the node resistance matrix constructed in this embodiment has The voltage vector has The current read is .in, This represents the memristor subarray corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Indicates the first The verifiable node and the first node with a connection relationship The undirected edges between the target variable nodes correspond to the memristor subarrays. It should be noted that... and It does not refer to the second node order of the variable node, but rather to the order of the target variable node connected to the verification node among all target variable nodes connected to that verification node. This represents the voltage vector corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Indicates the first The verifiable node and the first node with a connection relationship The voltage vector corresponding to the undirected edge between the target variable nodes. This includes the first and second current values ​​in the memristor subarray corresponding to the undirected edge between the first verification node and the first target variable node with which it is connected. Including the first The verifiable node and the first node with a connection relationship The first and second current values ​​in the memristor subarray corresponding to the undirected edges between the target variable nodes. For example, in this embodiment, the undirected edge can be used as a reference. Each voltage element in the array is transmitted via the DAC module to the memristor subarray corresponding to the undirected edge. Each row of nodes in the array receives a voltage equal to the size of the voltage element; for example, this voltage is input to the memristor subarray. The first row of nodes in the input and... A voltage equal to the magnitude of the first voltage element is applied to the memristor subarray. The second row of nodes in the input is the same as the input. A voltage equal to the second voltage element is applied until the last row of nodes in the memristor subarray is input. The voltage is equal to the value of the last voltage element. Then, in this embodiment, the first and second current values ​​in the memristor subarray can be read. The data is digitized using an ADC module for subsequent updates. For the node resistance matrices, voltage vectors, and current vectors corresponding to other undirected edges, this embodiment can perform parallel processing following the above process, and will not be elaborated further.

[0104] The operation process performed in the memristor subarray is represented in matrix multiplication form as follows:

[0105]

[0106] in, T This is the matrix transpose symbol. and middle, ij Indicates the first The verification node and the first Undirected edges between nodes of variable type. (The text in parentheses is incomplete and likely refers to a separate topic.) =1 indicates the first column. (The text in parentheses is incomplete and likely refers to a specific column or section.) =1 indicates the second column. Indicates the first The verification node and the first The first current value in the memristor subarray corresponding to the undirected edge between each variable node. Indicates the first The verification node and the first The second current value in the memristor subarray corresponding to the undirected edges between the variable nodes. It should be noted that the message passing between the variable nodes and the check node, i.e., the update process of the variable node transmitting its own state value to the check node, will not be elaborated further. In this embodiment, after constructing the memristor subarray corresponding to each undirected edge in the probabilistic graphical model, the memristor subarrays corresponding to each undirected edge can be connected into a large memristor array, which is then used to implement Turbo decoding. In this embodiment, the various memristor subarrays can be spliced ​​together to obtain the large memristor array.

[0107] In summary, the multi-task computing architecture implementation method based on a unified probabilistic graph proposed in this embodiment innovatively configures hardware resources. It reconstructs the connection topology between verification nodes and variable nodes as needed based on the association mapping matrix, and loads probability function configuration functions corresponding to different application scenarios, enabling a single hardware platform to adaptively support multiple types of signal processing tasks, achieving "multi-purpose single hardware" and improving the chip's scenario adaptability. Furthermore, the probabilistic graph inference power optimization method based on in-memory computing devices proposed in this invention can significantly reduce the power consumption of terminal baseband signal processing through single-chip structure optimization.

[0108] Furthermore, the ultra-low-power inference architecture of the probabilistic graphical analog domain based on the laws of circuit physics of this invention, with a unified message passing process (message passing from the verification node to the variable node) exhibiting multiplication-accumulation characteristics, has a mathematical computational complexity of O(N), which is proportional to the square of the node size. During the message passing phase, the node state matrix can be encoded as memristor conductance values. Different tasks employ different formulas for calculation, which are then stored in a memristor cross array, transforming traditional discrete computation into instantaneous synthesis of physical quantities in the analog domain. This invention sharply reduces the computational complexity from O(N) to O(1). The core gain stems from the parallel current integration mechanism of the memristor cross array, enabling multiplication-accumulation operations on nodes of arbitrary size to be completed with only a single-step simulation operation, significantly reducing inference energy consumption.

[0109] Example 2: Following the method provided in Example 1 for implementing a multi-task computing architecture based on a unified probabilistic graph, this example provides an apparatus for implementing a multi-task computing architecture based on a unified probabilistic graph, comprising: a signal model establishment unit configured to establish a unified signal model based on the common characteristics of baseband signal processing tasks; a probabilistic graph model establishment unit configured to represent the unified signal model as a unified probabilistic graph model; a message passing unit configured to set up message passing between variable nodes and verification nodes in the unified probabilistic graph model and determine iterative operation units; and a task processing unit configured to process the baseband signal processing tasks by multiplexing the iterative operation units in hardware circuits and a processor.

[0110] Example 3: This example provides an electronic device corresponding to the implementation method of multi-task computing architecture based on unified probabilistic graphs provided in Example 1. The electronic device can be an electronic device for client use, such as a mobile phone, laptop, tablet computer, desktop computer, etc., to execute the method of Example 1.

[0111] Example 4: This example provides a computer-readable storage medium for storing one or more programs, the one or more programs including computer instructions, which, when executed by a computer, cause the computer to perform the method provided in Example 1 above.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for implementing a multi-task computing architecture based on a unified probabilistic graph, characterized in that, include: Based on the common characteristics of baseband signal processing tasks, a unified signal model is established; wherein, the unified signal model is: ,in, For unknown variables, For observed variables, For given and The correlation mapping matrix between them This is unknown disturbance noise. Each is a certain unknown variable. For each of the observed variables, The number of rows in the association mapping matrix. The number of columns in the association mapping matrix; The baseband signal processing tasks include multi-antenna detection tasks, channel estimation tasks, or channel decoding tasks, wherein: In the multi-antenna detection task: This represents the multi-antenna channel characteristic matrix, where the unknown variable is the transmitted symbol to be estimated, and the observed variable is the multi-antenna mixed signal observed at the receiver. In the channel estimation task: This represents the pilot structure matrix, where the unknown variable is the channel to be estimated, and the observed variable is the pilot signal observed by the receiver. In the channel decoding task: This represents the codeword parity check matrix, where the unknown variable is the transmitted bit to be estimated, and the observed variable is the signal received by the receiver. The unified signal model is represented as a unified probabilistic graphical model, and the specific process is as follows: The unified probabilistic graphical model includes variable nodes, verification nodes, and undirected edges, wherein the undirected edges are used to connect variable nodes and verification nodes that have a connection relationship. The variable node represents the unknown variable; The verification node represents the coupling relationship between the unknown variable, the observed variable, and the correlation mapping matrix, and sets a probability configuration function based on the correlation mapping matrix. This is used to characterize the differential constraint rules among the baseband signal processing tasks; Set up message passing between variable nodes and verification nodes in the unified probabilistic graphical model, and determine the iterative computation unit; By multiplexing the iterative operation unit in the hardware circuit and processor, the baseband signal processing task can be processed.

2. The method for implementing a multi-task computing architecture based on a unified probabilistic graph according to claim 1, characterized in that, Depending on the baseband signal processing task, the probability configuration function The specific configuration is as follows: The multi-antenna detection task Configured as follows: ； The channel estimation task Configured as follows: ； The channel decoding task Configured as follows: ； in, Indicates the noise variance. H represents the received signal, and H represents the matrix transpose. Represents the association mapping matrix The first in row vectors This indicates the remainder calculation. This indicates that the remainder is inverted.

3. The method for implementing a multi-task computing architecture based on a unified probabilistic graph according to claim 1 or 2, characterized in that, The iterative operation unit includes: The posterior propagation unit is configured to compute a posterior message for each verification node using prior messages from neighboring variable nodes and broadcast the result to the connected variable nodes. The prior propagation unit is configured to update the prior confidence message for each variable node using the posterior message from the neighboring check node, and propagate the update to all connected check nodes.

4. The method for implementing a multi-task computing architecture based on a unified probabilistic graph according to claim 3, characterized in that, The specific implementation of the iterative operation unit is as follows: ； ； in, Representing variables The included states, For verification nodes To the variable node Passed variables The state value is The news for The probability configuration function, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Indicates and verifies the node Connected and variable nodes Values The combination of all variable node states, Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, express From the verification node i A set of indexes of variable nodes with connections Take the value from; It concerns the transmission of messages from the variable node to the verification node. The function, Represents variable nodes To the verification node The message conveyed about The message; Represents variable nodes To the verification node Variables passed between The state value is The news Represents variable nodes To the verification node The message is from the verification node. Other than variable nodes Connected verification nodes Provide message generation, For verification nodes To the variable node Passing information about variables The state value is The news.

5. A device for implementing a multi-task computing architecture based on a unified probabilistic graph, characterized in that, include: The signal model building unit is configured to build a unified signal model based on the common characteristics of baseband signal processing tasks, wherein the unified signal model is: ,in, For unknown variables, For observed variables, For given and The correlation mapping matrix between them This is unknown disturbance noise. Each is a certain unknown variable. For each of the observed variables, The number of rows in the association mapping matrix. The number of columns in the correlation mapping matrix; the baseband signal processing task includes a multi-antenna detection task, a channel estimation task, or a channel decoding task, wherein: in the multi-antenna detection task: This represents the multi-antenna channel characteristic matrix, where the unknown variable is the transmitted symbol to be estimated, and the observed variable is the multi-antenna mixed signal observed at the receiver; in the channel estimation task: The pilot structure matrix represents the unknown variable, which is the channel to be estimated, and the observed variable is the pilot signal observed at the receiver; in the channel decoding task: This represents the codeword parity check matrix, where the unknown variable is the transmitted bit to be estimated, and the observed variable is the signal received by the receiver. The probabilistic graphical model building unit is configured to represent the unified signal model as a unified probabilistic graphical model, and the specific process is as follows: The unified probabilistic graphical model includes variable nodes, verification nodes, and undirected edges, wherein the undirected edges are used to connect variable nodes and verification nodes that have a connection relationship. The variable node represents the unknown variable; The verification node represents the coupling relationship between the unknown variable, the observed variable, and the correlation mapping matrix, and sets a probability configuration function based on the correlation mapping matrix. This is used to characterize the differential constraint rules among the baseband signal processing tasks; The message passing unit is configured to set up message passing between variable nodes and verification nodes in the unified probabilistic graphical model and to determine the iterative operation unit; The task processing unit is configured to process the baseband signal processing task by multiplexing the iterative operation unit in the hardware circuit and the processor.

6. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the method according to any one of claims 1-4.

7. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include computer instructions for causing a computer to perform the method according to any one of claims 1-4.

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