IGBT device and preparation method thereof
By employing a combination of silicon nitride and silicon oxide passivation layer design on the surface of IGBT devices and setting circular holes at the corners, the problem of easy cracking of silicon nitride is solved, thereby improving the stability and reliability of the devices.
Patent Information
- Application Number
- CN202511274068.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-08
- Publication Date
- 2025-12-16
AI Technical Summary
The surface of IGBT devices is easily affected by external factors. The silicon nitride passivation layer is prone to cracking due to high stress, which leads to stress accumulation during high-frequency switching and affects stability and reliability.
The design employs a combination of silicon nitride and silicon oxide or silicon-rich silicon nitride passivation layer, combined with low-temperature process materials to fill the metal gaps, and circular holes are set at the corners of the passivation layer to buffer stress, thereby increasing adhesion and buffering effect.
This improves the moisture resistance and reliability of IGBT devices, reduces the risk of passivation layer cracking, and enhances the stability and durability of the devices.
Smart Images
Figure CN121152227A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductors, specifically relating to an IGBT device and its fabrication method. Background Technology
[0002] IGBT device surfaces are susceptible to external influences, such as gaseous impurities, moisture, and water vapor, which directly affect the device's electrical performance and severely reduce its stability and reliability. Therefore, a surface passivation technology is needed to effectively shield IGBT devices from the influence of the external environment and improve their moisture resistance, reliability, and stability. Silicon nitride is the most common passivation layer material, offering advantages such as uniform material structure, good chemical stability (it does not react with other inorganic acids except hydrofluoric acid), strong corrosion resistance, resistance to thermal shock, and high oxidation resistance.
[0003] However, silicon nitride films are subject to high stress, and thicker silicon nitride films are very prone to cracking. Furthermore, its step coverage is weak, making it difficult to form a complete, seamless, continuous film when the steps are large. This causes cracks to easily appear at the metal steps when the IGBT device is subjected to stress. During the switching control of high voltage and high current, significant losses are unavoidable. These losses are converted into heat energy and dissipated into the surrounding environment. As a result, stress accumulates continuously towards the center of the chip during high-frequency switching of the IGBT device, generating huge stress in the passivation layer film. This leads to severe cracking of the passivation layer, affecting the stability and reliability of the IGBT device. Summary of the Invention
[0004] Purpose of the invention: The purpose of this invention is to provide an IGBT device with a passivation layer that is not prone to cracking. Another purpose of this invention is to provide a method for fabricating an IGBT device with a passivation layer that is not prone to cracking.
[0005] Technical solution: The IGBT device of the present invention includes a wafer substrate, a terminal region and an active region on the wafer substrate, an emitter metal and a gate metal on the active region, a passivation layer for protecting the chip surface deposited on the surface of the emitter metal and the gate metal, the disconnected area of the emitter metal and the gate metal being filled with an insulating material flush with the metal surface, and the passivation layer including a first passivation layer located around the bonding area and a second passivation layer covering the boundary of the bonding area.
[0006] The second passivation layer includes an inner boundary covering the edge of the pressure bonding area and an outer boundary covering the edge of the first passivation layer.
[0007] The first passivation layer is made of silicon nitride, and the second passivation layer is made of silicon oxide or silicon-rich silicon nitride.
[0008] In this case, the solder joints etched on the first passivation layer are all rounded rectangles.
[0009] The thickness of the first passivation layer is 0.1–0.5 μm, and the thickness of the second passivation layer is 0.05–0.2 μm.
[0010] The second passivation layer has a width of 10-12 μm and covers the first passivation layer and the pressure welding area by 5-6 μm.
[0011] The insulating material is a low-temperature processing material with a processing temperature lower than that of the surface metal.
[0012] In this terminal area, circular holes are etched on the first passivation layer at each of the four corners, with a hole diameter of 80-100μm.
[0013] Furthermore, the boundary of the circular hole is covered with a second passivation layer.
[0014] The present invention discloses a method for fabricating an IGBT device, comprising the following steps:
[0015] (1) A metal layer is set on the surface of the wafer substrate and ohmic contact is made with the substrate by drilling to form the emitter and gate electrode;
[0016] (2) Fill the metal gaps between different electrodes with insulating material, with the height consistent with the metal layer;
[0017] (3) A first passivation layer is covered on top of the metal layer and the insulating material. An opening is made on the first passivation layer to expose the emitter bonding area and the gate bonding area. The bonding area is a rounded rectangle. At the same time, circular holes are etched at the four corners of the terminal area.
[0018] (4) A second passivation layer is laid at the boundary between the first passivation layer and the metal boundary of the pressure welding area, and a second passivation layer is laid at the boundary between the first passivation layer and the boundary of the circular hole.
[0019] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:
[0020] 1. To prevent short circuits caused by excessively close spacing between metal parts, insulating material is used to fill and block the gap between the two metal parts, eliminating steps on the surface metal and improving the adhesion of the passivation layer.
[0021] 2. The passivation layer in the traditional pressure welding area is designed with rounded corners instead of right angles, and a second passivation layer with a thickness less than the first passivation layer is applied to the entire corner. This increases the adhesion between the first passivation layer and the metal, and provides a certain degree of stress buffering, thereby reducing the stress accumulation at the corner of the pressure welding area that could lead to cracking and improving the reliability of the device.
[0022] 3. The first passivation layer circular hole area is set at the four corners of the chip terminal. The edge position is the same as the bonding area, and the second passivation layer is covered. This can prevent residual stress from spreading to the chip and avoid stress concentration caused by multiple chips accumulating and causing the passivation layer to crack. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the IGBT device structure;
[0024] Figure 2 This is a schematic diagram of the structure of a traditional IGBT device;
[0025] Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along line AA;
[0026] Figure 4 This is a partial enlarged view of the IGBT device structure;
[0027] Figure 5 for Figure 1 Enlarged view of the location of the circular hole;
[0028] Figure 6 This is a flowchart of the IGBT device fabrication method. Detailed Implementation
[0029] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0030] See Figure 1 The wafer substrate 1 has a terminal region 2 and an active region 3. The terminal region 2 surrounds the entire active region 3. The active region 3 has an emitter metal 401 and a gate metal 402. The surface of the emitter metal 401 and the gate metal 402 is deposited with a passivation layer to protect the surface of the chip. The emitter metal 401 has four emitter bonding areas 5010 on its surface, and the gate metal 402 has a gate bonding area 5020 on its surface. Both the emitter bonding area 5010 and the gate bonding area 5020 are rounded rectangles. The passivation layer includes a first passivation layer 6 located around the emitter bonding area, and a narrower second passivation layer 7 covering the boundary of the bonding area. The second passivation layer 7 includes an inner boundary 7-1 covering the inner edge of the bonding area and an outer boundary 7-2 covering the outer edge of the bonding area. The material of the second passivation layer is different from that of the first passivation layer. The first passivation layer 6 is made of silicon nitride, and the second passivation layer 7 is made of silicon oxide or silicon-rich silicon nitride. Silicon-rich silicon nitride has a higher silicon content and a denser film than silicon nitride, which has a better adsorption effect on impurity ions in the device.
[0031] See Figure 2, a is a plan view of the traditional IGBT device structure, with the chip bonding area being a rectangular shape with positive sides. b is a cross-sectional view of the structure along line BB of a. It can be seen that after the bonding area is formed on the first passivation layer 6, there is a height difference between the first passivation layer 6 and the emitter bonding area 5010 and the gate bonding area 5020. When the passivation layer is subjected to stress, cracks are prone to appear at the metal steps, affecting the reliability of the device.
[0032] See Figure 3 Because silicon nitride films have high stress, thicker silicon nitride films are very prone to cracking, and their step coverage is weak. When the steps are large, it is difficult to form a complete, seamless, continuous film. The area where the emitter metal and gate metal are disconnected is filled with an insulating material 8 that is flush with the metal surface. The insulating material 8 is a low-temperature process material with a processing temperature lower than that of the surface metal, such as aerogel or polymer foam. After etching open the emitter bonding area 5010, a boundary 6-1 is generated. A second passivation layer 7 is deposited above the boundary 6-1, covering half of the first passivation layer 6 and half of the emitter metal 401. The width of the second passivation layer 7 is about 10 μm and the thickness is 0.1 μm. The thickness of the second passivation layer is half that of the first passivation layer.
[0033] See Figure 4 A circular hole 9 with a diameter of 80 μm is etched on the first passivation layer 6 at each of the four corners of the terminal area 2. The boundary of the circular hole 9 is covered by the second passivation layer 7.
[0034] See Figure 5 ,for Figure 1 The enlarged image in the upper right corner shows that the total width of the second passivation layer is 10μm, covering the first passivation layer and the surface metal layer by 5μm each. The coverage width of the second passivation layer is consistent with that of the active region, and the distance between the passivation layer boundary and the chip boundary is consistent.
[0035] like Figure 6 As shown, the specific fabrication steps of an IGBT device are as follows:
[0036] (1) A metal layer is set on the surface of the wafer substrate and ohmic contact is made with the substrate by drilling to form the emitter and gate electrode;
[0037] (2) Fill the metal gaps between different electrodes with insulating material, with the height consistent with the metal layer;
[0038] (3) A first passivation layer is covered on top of the metal layer and the insulating material. An opening is made on the first passivation layer to expose the emitter bonding area and the gate bonding area. The bonding area is a rounded rectangle. At the same time, circular holes are etched at the four corners of the terminal area.
[0039] (4) A second passivation layer is laid at the boundary between the first passivation layer and the metal boundary of the pressure welding area, and a second passivation layer is laid at the boundary between the first passivation layer and the boundary of the circular hole.
Claims
1. An IGBT device, comprising a wafer substrate (1), wherein a terminal region (2) and an active region (3) are provided on the wafer substrate (1), an emitter metal (401) and a gate metal (402) are provided on the active region (3), and a passivation layer (6) protecting the chip surface is deposited on the surfaces of the emitter metal (401) and the gate metal (402), characterized in that, The disconnected region between the emitter metal (401) and the gate metal (402) is filled with an insulating material (8) flush with the metal surface. The passivation layer includes a first passivation layer (6) located around the bonding area and a second passivation layer (7) covering the boundary of the bonding area.
2. The IGBT device according to claim 1, characterized in that, The second passivation layer (7) includes an inner boundary (7-1) covering the edge of the pressure bond area and an outer boundary (7-2) covering the edge of the first passivation layer.
3. The IGBT device according to claim 1, characterized in that, The first passivation layer (6) is made of silicon nitride, and the second passivation layer (7) is made of silicon oxide or silicon-rich silicon nitride.
4. The IGBT device according to claim 1, characterized in that, The weld areas etched on the first passivation layer (6) are all rounded rectangles.
5. The IGBT device according to claim 1, characterized in that, The thickness of the first passivation layer (6) is 0.1 to 0.5 μm, and the thickness of the second passivation layer (7) is 0.05 to 0.2 μm.
6. The IGBT device according to claim 1, characterized in that, The width of the second passivation layer (7) is 10-12 μm, covering the first passivation layer (6) and the pressure welding area by 5-6 μm each.
7. The IGBT device according to claim 1, characterized in that, The insulating material (8) is a low-temperature process material with a processing temperature lower than that of the surface metal.
8. The IGBT device according to claim 1, characterized in that, Circular holes (9) are etched on the first passivation layer (6) at the four corners of the terminal area (2), with a hole diameter of 80-100μm.
9. The IGBT device according to claim 8, characterized in that, The boundary of the circular hole (9) is covered with a second passivation layer (7).
10. A method for fabricating an IGBT device, characterized in that, Includes the following steps: (1) A metal layer is set on the surface of the wafer substrate and ohmic contact is made with the substrate by drilling to form the emitter and gate electrode; (2) Fill the metal gaps between different electrodes with insulating material, with the height consistent with the metal layer; (3) A first passivation layer is covered on top of the metal layer and the insulating material. An opening is made on the first passivation layer to expose the emitter bonding area and the gate bonding area. The bonding area is a rounded rectangle. At the same time, circular holes are etched at the four corners of the terminal area. (4) A second passivation layer is laid at the boundary between the first passivation layer and the metal boundary of the pressure welding area, and a second passivation layer is laid at the boundary between the first passivation layer and the boundary of the circular hole.