SONOS memory device and forming method thereof

Abstract

The invention discloses an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory device and a forming method thereof. The SONOS memory device comprises a substrate; the substrate comprises a first substrate located in the middle area and second substrates located at the two ends; the ONO dielectric layer and the grid electrode are located on the first substrate; the source electrode and the drain electrode are located in the second substrate; the source electrode and the drain electrode are located on the two sides of the ONO dielectric layer respectively; the ballistic emission layer is positioned in the source electrode; the ballistic emission layer is of a P-type doped structure, and the width of the ballistic emission layer is smaller than that of the source electrode. According to the invention, under the condition that the working voltage is not changed, the operation difficulty of multiple programming erasure of the memory device can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a SONOS memory device and a method for forming the same. Background Technology

[0002] Current non-volatile memories, after multiple program-erase cycles, exhibit an electron-hole mismatch in space, with holes accumulating at the drain and electrons accumulating near the source, making subsequent program-erase operations difficult. This phenomenon is typically mitigated by increasing the operating voltage. However, increasing the operating voltage increases the device's power consumption. Summary of the Invention

[0003] The technical problem solved by the present invention is to provide a SONOS memory device and a method for forming the same, which can reduce the difficulty of performing multiple programming and erasing operations on the memory device without changing the operating voltage.

[0004] To solve the above-mentioned technical problems, the technical solution of this application is as follows: According to a first aspect of the embodiments of this application, a SONOS storage device is provided, comprising: Substrate; the substrate includes a first substrate located in the central region and second substrates located at both ends; The ONO dielectric layer and the gate are located on the first substrate; The source and drain are located in the second substrate; the source and drain are respectively located on both sides of the ONO dielectric layer; A ballistic emission layer is located in the source electrode; the ballistic emission layer has a P-type doped structure, and the width of the ballistic emission layer is smaller than the width of the source electrode.

[0005] In one exemplary embodiment, the ratio of the width of the ballistic launch layer to the width of the source electrode is 1:(2-10), and the ballistic launch layer is used to generate a field strength exceeding 10. 5 An electric field of V / cm.

[0006] In one exemplary embodiment, the width of the ballistic launch layer is 10-50 nm.

[0007] In one exemplary embodiment, the thickness of the ballistic launch layer is greater than the thickness of the source electrode and less than the thickness of the substrate.

[0008] In an exemplary embodiment, the ratio of the thickness of the ballistic launch layer to the thickness of the source electrode is 2:1.

[0009] In one exemplary embodiment, the P-type dopant ions include at least one of boron, aluminum, indium, and gallium, and the concentration of P-type dopant ions in the ballistic launch layer is 10. 18 -1020 per cubic centimeter.

[0010] In one exemplary embodiment, the ONO dielectric layer is located on the first substrate, the gate is located on the ONO dielectric layer, and the ONO dielectric layer includes a tunneling oxide layer, a charge storage layer, and a barrier oxide layer stacked sequentially; the tunneling oxide layer is located on the second substrate, and the barrier oxide layer is located on the charge storage layer.

[0011] In one exemplary embodiment, the material of the charge storage layer is a nitride or a oxynitride, and the thickness of the charge storage layer is (15±5) nm.

[0012] In one exemplary embodiment, the thickness ratio of the tunneling oxide layer to the barrier oxide layer is 1:(1-5).

[0013] According to a second aspect of the embodiments of this application, a method for forming a SONOS storage device is provided, the method comprising: A substrate is provided; the substrate includes a first substrate located in a central region and second substrates located at both ends; An ONO dielectric layer and a gate are sequentially formed on the first substrate; The source and drain are formed in the second substrate by an N-type doped ion implantation process; the source and drain are located on opposite sides of the ONO dielectric layer, respectively. A ballistic emission layer is formed in the source electrode by a P-type doped ion implantation process; the ballistic emission layer is a P-type doped structure, and the width of the ballistic emission layer is smaller than the width of the source electrode. According to a third aspect of the embodiments of this application, an electronic device is provided, the device including the above-described SONOS memory device.

[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The SONOS memory device of the present invention includes: a substrate; the substrate comprising a first substrate located in the central region and second substrates located at both ends; an ONO dielectric layer and a gate on the first substrate; a source and a drain located in the second substrate; the source and the drain being located on opposite sides of the ONO dielectric layer; a ballistic emitter layer located in the source; the ballistic emitter layer having a P-type doped structure, and the width of the ballistic emitter layer being smaller than the width of the source. The present invention forms a P-type doped ballistic emitter layer in the source of the memory device. After the memory device performs multiple program-erase cycles, a large number of holes accumulate at the drain, while a strong electric field is formed at the ballistic emitter layer of the source, accelerating passing electrons. This causes high-speed electrons to accumulate at the drain, where they are neutralized by the holes, achieving charge balance in the memory device. Therefore, without changing the operating voltage, the difficulty of performing multiple program-erase cycles in the memory device is reduced, improving the reliability of the memory device. Attached Figure Description

[0015] To more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating a method for forming a SONOS storage device according to an embodiment of the present invention; Figures 2 to 6 This is a cross-sectional structural schematic diagram of the formation process of a SONOS storage device provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a SONOS storage device in the prior art; Figure 8 This is a schematic diagram of the structure of a SONOS storage device provided in an embodiment of the present invention; Figure 9 This is an electron distribution diagram of the charge storage layer after programming in existing SONOS memory devices; Figure 10 This is an electron distribution diagram of the charge storage layer after programming a SONOS memory device, provided in an embodiment of the present invention. Figure 11 This is a diagram showing the electric field distribution at the channel of a SONOS memory device in the prior art; Figure 12 This is an electric field distribution diagram at the channel of a SONOS memory device provided in an embodiment of the present invention; The corresponding reference numerals in the figure are as follows: First substrate 11, second substrate 12, ONO dielectric layer 2, tunneling oxide layer 21, charge storage layer 22, barrier oxide layer 23, gate 3, source 4, drain 5, ballistic emission layer 6. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] As used herein, "an embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that spatial relative terms, such as "below," "under," "lower part," "above," "upper part," "front," "back," "above," and the like, are used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). These are used only for the convenience of describing this application and for simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as limiting this application. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein can be interpreted similarly.

[0019] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0021] Current SONOS (Silicon-Oxide-Nitride-Oxide-Semiconductor) memory devices experience an electron-hole mismatch after multiple program-erase cycles. Holes accumulate at the drain end, while electrons accumulate near the source end, making subsequent program-erase operations difficult. This phenomenon is usually improved by increasing the operating voltage.

[0022] To reduce the power consumption pressure caused by the increase in operating voltage, this application provides a SONOS memory device and its formation method, which can optimize the device structure to improve the charge distribution in the memory cell, thereby solving the above-mentioned problems in the prior art.

[0023] like Figure 1 As shown, this embodiment provides a method for forming a SONOS storage device, including: S1: Provide a substrate; the substrate includes a first substrate located in the central region and second substrates located at both ends.

[0024] S2: An ONO dielectric layer and a gate are sequentially formed on the first substrate.

[0025] S3: A source and a drain are formed in the second substrate by an N-type doped ion implantation process; the source and the drain are located on opposite sides of the ONO dielectric layer.

[0026] S4: A ballistic emission layer is formed in the source electrode by a P-type doped ion implantation process; the ballistic emission layer is a P-type doped structure and the width of the ballistic emission layer is smaller than the width of the source electrode.

[0027] Figures 2-6 This diagram illustrates a cross-sectional structure showing the formation process of a SONOS memory device according to an embodiment of the present invention; as shown. Figure 2 As shown, Figure 2The substrate may include a first substrate 11 in the middle region and second substrates 12 at both ends. The second substrate 12 includes two parts, which are symmetrically arranged and located on both sides of the first substrate 11. The width of the first substrate 11 and the width of each second substrate 12 can be set according to the actual situation. For example, the width of the first substrate 11 and the width of each second substrate 12 are the same. Optionally, the substrate is a P-type substrate, which can be a P-type silicon substrate.

[0028] like Figure 3 As shown, a tunneling oxide layer 21, a charge storage layer 22, and a barrier oxide layer 23 are sequentially formed on a first substrate 11 to constitute an ONO (oxide-nitride-oxide) dielectric layer 2. Exemplarily, a thermal oxidation process can be used to form the tunneling oxide layer 21 on the first substrate 11. If the tunneling oxide layer 21 is too thin, leakage will occur; if it is too thick, tunneling will be hindered. The thickness of the tunneling oxide layer 21 can be set to 1.5-4 nm. Then, a low-pressure chemical vapor deposition or atomic layer deposition process is used to form the charge storage layer 22 on the tunneling oxide layer 21. This charge storage layer 22 is used to trap electrons or holes to achieve non-volatile storage, requiring a high trap density (greater than or equal to 10¹ cm⁻³) and uniformity. For example, the charge storage layer 22 has a thickness of 5-10 nm; the material of the charge storage layer 22 is a nitride or an oxide oxynitride, and the thickness of the charge storage layer 22 is (15±5) nm; then, nitride is deposited on the charge storage layer 22, for example, silicon nitride can be deposited and then oxidized to form oxide oxynitride, to obtain a barrier oxide layer 23; the function of the barrier oxide layer 23 is to prevent charge from escaping to the gate. The thickness ratio of the tunneling oxide layer 21 to the barrier oxide layer 23 is 1:(1-5); for example, the thickness of the tunneling oxide layer 21 is 1.5–4 nm, and the thickness of the barrier oxide layer 23 is 4–9 nm.

[0029] like Figure 4 As shown, polysilicon is deposited on the ONO dielectric layer 2 to form the gate 3. Specifically, polysilicon can be deposited on the ONO dielectric layer 2 first, then the gate pattern can be defined by photolithography, and then the gate 3 can be formed by dry etching process.

[0030] like Figure 5 As shown, source and drain regions are defined by photolithography on the second substrates 22 on both sides near the gate 3. Then, source 4 and drain 5 are formed in the second substrates 22 on both sides by N-type doped ion implantation process. Source 4 and drain 5 are symmetrically arranged and can be set to the same size. Source 4 and drain 5 are located on both sides of the ONO dielectric layer 2. The positions of source 4 and drain 5 can be adjusted according to the actual situation.

[0031] like Figure 6 As shown, a ballistic emission layer 6 is formed in the source 4 using a P-type doped ion implantation process; the P-type dopant ions include at least one of boron, aluminum, indium, and gallium, and the concentration of P-type dopant ions in the ballistic emission layer 6 is 10. 18 -10 20 Per cubic centimeter. The ballistic launch layer 6 is a P-type doped structure, and the width of the ballistic launch layer 6 is smaller than the width of the source electrode 4; the ratio of the width of the ballistic launch layer 6 to the width of the source electrode 6 is 1:(2-10), and the ballistic launch layer 6 is used to form a field strength exceeding 10. 5 An electric field of V / cm. The thickness of the ballistic emission layer 6 is greater than the thickness of the source electrode 4 and less than the thickness of the substrate. For example, the width of the source electrode 4 is 110±50nm, and the width of the ballistic emission layer 6 is 10-50nm. The ratio of the thickness of the ballistic emission layer 6 to the thickness of the source electrode 4 is 2:1.

[0032] In this embodiment, a P-type doped ballistic emitter layer is formed in the source of the memory device. After the memory device performs multiple program-erase cycles, a large number of holes are accumulated at the drain. At the same time, a strong electric field is formed at the ballistic emitter layer of the source, which accelerates the passing electrons, causing high-speed electrons to accumulate at the drain. The high-speed electrons are then neutralized by the holes in the drain, achieving charge balance in the memory device. This reduces the difficulty of performing multiple program-erase cycles without changing the operating voltage, and improves the reliability of the memory device.

[0033] like Figure 6 As shown in the figure, an embodiment of the present invention provides a structural schematic diagram of a SONOS storage device, including: Substrate; the substrate includes a first substrate 11 located in the central region and a second substrate 12 located at both ends; The ONO dielectric layer 2 and the gate 3 are located on the first substrate 11; The source electrode 4 and the drain electrode 5 are located in the second substrate 12; the source electrode 4 and the drain electrode 5 are respectively located on both sides of the ONO dielectric layer 2; The ballistic emission layer 6 is located in the source electrode 4; the ballistic emission layer 6 is a P-type doped structure, and the width of the ballistic emission layer 6 is smaller than the width of the source electrode 4.

[0034] The substrate can be any suitable substrate material, such as silicon, silicon-on-insulator, germanium, silicon carbide, silicon germanide, etc., or a substrate material on which a semiconductor epitaxial layer such as silicon carbide is epitaxially grown. In this embodiment of the invention, the substrate can be a P-type silicon substrate. The substrate can include a first substrate 11 in the central region and second substrates 12 at both ends, wherein the second substrate 12 includes two parts, the two parts of the second substrate 12 are symmetrically arranged, and are respectively located on both sides of the first substrate 11; the width of the first substrate 11 and the width of each second substrate 12 can be set according to the actual situation. For example, the width of the first substrate 11 and the width of each second substrate 12 are the same.

[0035] In an exemplary embodiment, the ONO dielectric layer 2 is located on the first substrate 11, the gate 3 is located on the ONO dielectric layer 2, and the ONO dielectric layer 2 includes a tunneling oxide layer 21, a charge storage layer 22 and a barrier oxide layer 23 stacked sequentially; the tunneling oxide layer 21 is located on the second substrate 12, and the barrier oxide layer 23 is located on the charge storage layer 22.

[0036] The charge storage layer 22 is made of nitride or oxynitride, and its thickness is (15±5) nm. The thickness ratio of the tunneling oxide layer 21 to the barrier oxide layer 23 is 1:(1-5).

[0037] The p-type doped ions of the ballistic launch layer 6 include at least one of boron, aluminum, indium, and gallium, and the concentration of the p-type doped ions in the ballistic launch layer 6 is 10. 18 -10 20 per cubic centimeter.

[0038] The ratio of the width of the ballistic launch layer 6 to the width of the source electrode 4 is 1:(2-10), and the ballistic launch layer 6 is used to form a field strength exceeding 10. 5 An electric field of V / cm. Optionally, the width of the ballistic emission layer 6 is 10-50 nm. The thickness of the ballistic emission layer 6 is greater than the thickness of the source electrode 4 and less than the thickness of the substrate. The ratio of the thickness of the ballistic emission layer 6 to the thickness of the source electrode 4 is 2:1.

[0039] Continue as Figure 6 As shown, the ballistic launch layer 6 divides the source 4 into a first source close to the gate 3 and a second source far away from the gate 3. For example, the width of the first source is smaller than the width of the second source, that is, the closer the ballistic launch layer 6 is to the gate 3, the greater the field strength it generates.

[0040] In one exemplary embodiment, simulation experiments of programming and erasing operations are performed using both existing SONOS memory devices and the SONOS memory device of this embodiment. Figure 7 This is a schematic diagram of the structure of a SONOS storage device in the prior art. Figure 8 This is a schematic diagram of the SONOS storage device in this embodiment. Figure 9 Electron distribution map of charge storage layer after programming existing SONOS memory devices. Figure 10 The electron distribution diagram of the charge storage layer after programming the SONOS memory device in this embodiment is as follows: Figure 7-8 As shown, the horizontal axis represents the lateral dimensions of the device, in μm (micrometers); the vertical axis represents the net doping concentration, in cm³, meaning the number of impurity atoms per cubic centimeter; compared to existing technologies, the SONOS memory device in this embodiment introduces a ballistic emission layer 6; as... Figure 9-10 As shown, the colors represent electron distribution; the closer the color is to red, the higher the concentration, and the closer it is to blue, the lower the concentration. Compared to existing technologies, in this embodiment of the SONOS memory device, the electron distribution is closer to the drain end (right side). When the device size approaches the mean free path of the charge carriers, the ballistic transport effect can still significantly improve the device performance. This transport method is particularly important in high-speed electronic devices, as it can significantly improve the device's operating speed. The ballistic launch layer in this memory mainly increases the transport velocity of hot carriers, allowing them to gain a greater initial velocity and accelerate to near the drain end before being captured by the charge storage layer. Simulation experiments show that in this embodiment, the electrons captured by the charge storage layer are more concentrated at the drain end, perfectly neutralizing the holes during subsequent erasure and improving the device's reliability.

[0041] like Figure 11-12 As shown, Figure 11 This is a diagram showing the electric field distribution at the channel of a prior art SONOS memory device. Figure 12 This is an electric field distribution diagram at the channel of the SONOS memory device in this embodiment, where the channel is the structure directly below the charge storage layer. The simulation shows that the electric field at the channel is increased by about an order of magnitude after the ballistic launch layer structure is added. Therefore, the acceleration of hot carriers in the early stage is relatively obvious, making it easier for them to be accelerated to the drain end and captured by the charge storage layer.

[0042] This embodiment also provides a method for operating a SONOS storage device, including: When a write operation is performed on the SONOS memory device and "0" is written, a first positive voltage is applied to the gate, no voltage is applied to the source and drain, and a second positive voltage is applied to the source, and electrons tunnel from the channel into the charge storage layer. When a write operation is performed on the SONOS memory device and a "1" is written, a first negative voltage is applied to the gate; No voltage is applied to the source, and a third positive voltage is applied to the drain. The source is suspended, and the holes generated by collision ionization tunnel from the channel into the charge storage layer. When performing a read operation on a SONOS memory device, a first read voltage is applied to the gate, a fourth positive voltage is applied to the drain, and the current in the channel is read.

[0043] For example, the first positive voltage is 4 to 12V, the second positive voltage is 2 to 6V, the third positive voltage is 2 to -8V, the fourth positive voltage is 0.2 to 3V, the first negative voltage is -4V to -10V, and the first read voltage is 1 to 3V; Specifically, writing a "0" does not change the stored charge state, and the device is in the off state. Writing a "1" changes the stored charge state, holes accumulate on the channel surface, and the device is in the on state.

[0044] After a memory device performs multiple program-erase cycles, a large number of holes accumulate at the drain, while a strong electric field is formed at the ballistic emission layer of the source, accelerating the passing electrons. This causes high-speed electrons to accumulate at the drain, where they are neutralized by the holes, achieving charge balance in the memory device. This reduces the difficulty of performing multiple program-erase cycles without changing the operating voltage, thus improving the reliability of the memory device.

[0045] The present invention also provides an electronic device, the device including the SONOS storage device provided in the embodiments of the present invention.

[0046] The electronic device in this embodiment can be any electronic product or device with photoelectric sensing function, such as a mobile phone, tablet computer, laptop computer, navigator, camera, camcorder, robot vacuum cleaner, virtual reality device, augmented reality device, etc., or any intermediate product including the aforementioned SONOS storage device.

[0047] The SONOS memory device of this specification includes: a substrate; the substrate includes a first substrate located in the central region and second substrates located at both ends; an ONO dielectric layer and a gate on the first substrate; a source and a drain in the second substrate; the source and the drain are respectively located on both sides of the ONO dielectric layer; a ballistic emitter layer in the source; the ballistic emitter layer is a P-type doped structure, and the width of the ballistic emitter layer is smaller than the width of the source. This invention forms a P-type doped ballistic emitter layer in the source of the memory device. After the memory device performs multiple program-erase cycles, a large number of holes accumulate at the drain, and a strong electric field is formed at the ballistic emitter layer of the source, accelerating passing electrons. This causes high-speed electrons to accumulate at the drain, where they are neutralized by the holes, achieving charge balance in the memory device. Therefore, without changing the operating voltage, the difficulty of performing multiple program-erase cycles in the memory device is reduced, improving the reliability of the memory device.

[0048] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0049] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A SONOS storage device, characterized in that, include: Substrate; the substrate includes a first substrate located in the central region and second substrates located at both ends; The ONO dielectric layer and the gate are located on the first substrate; The source and drain are located in the second substrate; the source and drain are respectively located on both sides of the ONO dielectric layer; A ballistic emission layer is located in the source electrode; the ballistic emission layer has a P-type doped structure, and the width of the ballistic emission layer is smaller than the width of the source electrode.

2. The storage device according to claim 1, characterized in that, The ratio of the width of the ballistic launch layer to the width of the source electrode is 1:(2-10), and the ballistic launch layer is used to generate a field strength exceeding 10. 5 An electric field of V / cm.

3. The storage device according to claim 1, characterized in that, The width of the ballistic launch layer is 10-50 nm.

4. The storage device according to claim 1, characterized in that, The thickness of the ballistic launch layer is greater than the thickness of the source electrode and less than the thickness of the substrate.

5. The storage device according to claim 4, characterized in that, The ratio of the thickness of the ballistic launch layer to the thickness of the source electrode is 2:

1.

6. The storage device according to claim 1, characterized in that, The P-type doped ions include at least one of boron, aluminum, indium, and gallium, and the concentration of P-type doped ions in the ballistic launch layer is 10. 18 -10 20 per cubic centimeter.

7. The storage device according to any one of claims 1-6, characterized in that, The ONO dielectric layer is located on the first substrate, and the gate is located on the ONO dielectric layer. The ONO dielectric layer includes a tunneling oxide layer, a charge storage layer, and a barrier oxide layer stacked sequentially. The tunneling oxide layer is located on the second substrate, and the barrier oxide layer is located on the charge storage layer.

8. The storage device according to claim 7, characterized in that, The charge storage layer is made of nitride or oxynitride and has a thickness of (15±5) nm.

9. The storage device according to claim 7, characterized in that, The thickness ratio of the tunneling oxide layer to the barrier oxide layer is 1:(1-5).

10. A method for forming a SONOS storage device, characterized in that, The method includes: A substrate is provided; the substrate includes a first substrate located in a central region and second substrates located at both ends; An ONO dielectric layer and a gate are sequentially formed on the first substrate; The source and drain are formed in the second substrate by an N-type doped ion implantation process; the source and drain are located on opposite sides of the ONO dielectric layer, respectively. A ballistic emission layer is formed in the source electrode using a P-type doped ion implantation process; the ballistic emission layer is a P-type doped structure, and the width of the ballistic emission layer is smaller than the width of the source electrode.

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