Manufacturing process of super junction device

Abstract

The invention discloses a manufacturing process of a super junction device, which comprises the steps that paired wafers are provided, each wafer comprises a substrate and an epitaxial layer formed on the substrate, a deep groove structure is formed in each epitaxial layer, and the paired wafers comprise a first wafer and a second wafer; performing a front bonding process on the first wafer and the second wafer to enable the deep groove structures in the first wafer to be aligned with the deep groove structures in the second wafer in a one-to-one correspondence manner; performing a back thinning process on the first wafer to remove a substrate and a part of an epitaxial layer of the first wafer until the deep groove structure in the first wafer is exposed; and performing a subsequent process on the surface, exposed with the deep groove structure, of the epitaxial layer to obtain the super junction device. According to the scheme, the process limit of the cylinder depth can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing process of a super-junction device. BACKGROUND

[0002] The core advantage of the super-junction device is that, by means of the alternating arrangement of P-type pillars and N-type pillars, high withstand voltage is achieved while the on-resistance is greatly reduced, thereby breaking through the compromise limit of the withstand voltage-on-resistance of traditional power devices and becoming the core technical direction in the field of high-voltage power semiconductors. Among them, the deep pillar structure is the key to determining the withstand voltage capability of the super-junction device, mainly because the pillar depth directly determines the expansion range of the depletion region under reverse bias, and the greater the depth, the higher the reverse voltage that can be withstood.

[0003] Due to the limitation of process capability, the current process for preparing deep-pillar high-voltage super-junction products is difficult and complex, which results in a large limitation of the pillar depth. SUMMARY

[0004] The present application provides a manufacturing process of a super-junction device, which can improve the process limit of the pillar depth.

[0005] The present application provides a manufacturing process of a super-junction device, which includes: providing a pair of wafers, the wafers including a substrate and an epitaxial layer formed on the substrate, and a deep trench structure formed in the epitaxial layer, wherein the pair of wafers includes a first wafer and a second wafer; performing a front bonding process on the first wafer and the second wafer, so that the deep trench structures in the first wafer and the second wafer are correspondingly aligned; performing a back thinning process on the first wafer to remove the substrate and part of the epitaxial layer of the first wafer until the deep trench structure in the first wafer is exposed; performing subsequent processes on the surface of the epitaxial layer where the deep trench structure is exposed to obtain a super-junction device.

[0006] In some embodiments, the deep trench structure is formed in the epitaxial layer by a deep trench backfilling process.

[0007] In some embodiments, after the front bonding process, the deep trench structures in the first wafer and the second wafer that are aligned with each other jointly constitute a pillar structure.

[0008] In some embodiments, the step of performing a front bonding process on the first wafer and the second wafer includes: performing surface pretreatment on the epitaxial layer surface of the first wafer and the second wafer; putting the first wafer and the second wafer which have been subjected to surface pretreatment into a bonder; performing Si-Si bonding on the front surface of the first wafer and the front surface of the second wafer by the bonder; performing high-temperature thermal annealing treatment on the first wafer and the second wafer after Si-Si bonding.

[0009] In some embodiments, the surface pretreatment on the epitaxial layer surface of the first wafer and the second wafer comprises: surface thinning treatment on the epitaxial layer surface of the first wafer and the second wafer; chemical mechanical polishing treatment on the epitaxial layer surface of the first wafer and the second wafer; surface cleaning treatment on the epitaxial layer surface of the first wafer and the second wafer.

[0010] The technical scheme of the present application has at least the following advantages: 1. By providing a pair of wafers, including a first wafer and a second wafer, and combining the first wafer and the second wafer by a front bonding process as a substrate for forming a super junction device later, wherein the deep trench structures in the first wafer and the second wafer are combined one by one, and then a back thinning process is performed on the first wafer to remove the substrate and part of the epitaxial layer of the first wafer until the deep trench structure in the first wafer is exposed, compared with a column structure formed by one deep trench structure, in the present application, two deep trench structures in the first wafer and the second wafer are combined into a column structure by the bonding process, effectively improving the process limit of the depth of the column structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the specific embodiments of the present application or the technical scheme in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0012] Figure 1 is a flowchart of the manufacturing process of the super junction device provided by an exemplary embodiment of the present application; Figures 2-4 is a device schematic diagram of the manufacturing process of the super junction device provided by an exemplary embodiment of the present application in the execution process.

[0013] Explanation of reference signs: W1, first wafer; W2, second wafer; 2, substrate; 3, epitaxial layer; 41, deep trench structure; 42, column structure. DETAILED DESCRIPTION

[0014] The technical solutions in the present application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0015] In the description of the present application, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0016] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, or it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0017] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0018] The conductivity type of the semiconductor region in the present application includes opposite first conductivity type and second conductivity type, that is, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

[0019] N-type semiconductor and P-type semiconductor are generated according to different impurities doped into the semiconductor. Among them, by doping a certain element in group V of the periodic table, such as arsenic or antimony, etc. into the semiconductor as a donor impurity, an N-type semiconductor can be obtained; by doping an element in group III of the periodic table, such as boron or indium, etc. into the semiconductor as an acceptor impurity, a P-type semiconductor can be obtained.

[0020] The conductivity performance of the N-type semiconductor and the P-type semiconductor is different.

[0021] This application provides a manufacturing process for a superjunction device, referring to... Figure 1 It includes the following steps: S1: Provide a pair of wafers, each wafer including a substrate and an epitaxial layer formed on the substrate, wherein a deep trench structure is formed in the epitaxial layer, and the pair of wafers includes a first wafer and a second wafer.

[0022] For example, refer to Figure 2 and Figure 3 The system provides paired wafers, each wafer including a substrate 2 and an epitaxial layer 3 formed on the substrate 2. The substrate 2 and the epitaxial layer 3 have opposite ion doping types; in this application, an example is provided where the substrate 2 is P-type and the epitaxial layer 3 is N-type. A plurality of spaced deep trench structures 41 are formed in the epitaxial layer 3. The paired wafers include a first wafer W1 and a second wafer W2 with identical structures.

[0023] Furthermore, the deep trench structure 41 is formed in the epitaxial layer 3 through a deep trench backfilling process. For example, several deep trenches can be formed in the epitaxial layer 3 first through photolithography and etching processes. After etching, the photoresist is removed, and then residual impurities generated during etching are removed through processes such as deionized water rinsing and ultrasonic cleaning to ensure the cleanliness of the deep trenches. Subsequently, an isolation oxide layer can be grown on the sidewalls of the deep trenches, and then through multiple filling and back-etching processes, a specified material is filled into the deep trenches to obtain the deep trench structure 41.

[0024] S2: Perform a front-side bonding process on the first wafer and the second wafer to align the deep trench structures in the first wafer and the deep trench structures in the second wafer in a one-to-one correspondence.

[0025] For example, refer to Figure 3 A front-side bonding process is performed on the first wafer W1 and the second wafer W2. Here, the front side of the wafer refers to the surface of the epitaxial layer 3, and the back side refers to the back side of the substrate 2. After the front-side bonding process, the deep trench structures 41 in the first wafer W1 and the deep trench structures 41 in the second wafer W2 are aligned one-to-one.

[0026] Furthermore, step S2 includes the following processing procedures: S21: Perform surface pretreatment on the epitaxial layer surfaces of the first wafer and the second wafer.

[0027] For example, the epitaxial layers 3 of the first wafer W1 and the second wafer W2 are first pretreated to ensure that their surface conditions meet the requirements of the bonding process.

[0028] Furthermore, step S21 may include the following processing: The epitaxial layer surfaces of the first and second wafers are subjected to surface thinning treatment.

[0029] Exemplarily, surface thinning treatment can be performed on the epitaxial layers 3 of the first wafer W1 and the second wafer W2 by mechanical grinding or chemical etching or the like process until the thicknesses of the first wafer W1 and the second wafer W2 meet the process requirements. At the same time, the surface thinning treatment can also reduce wafer warping and ensure the surface adhesion of the first wafer W1 and the second wafer W2 in the subsequent bonding process.

[0030] The surfaces of the epitaxial layers of the first wafer and the second wafer are subjected to chemical mechanical polishing treatment.

[0031] Exemplarily, chemical mechanical polishing treatment can be performed on the surfaces of the epitaxial layers 3 of the first wafer W1 and the second wafer W2 to reduce surface roughness.

[0032] The surfaces of the epitaxial layers of the first wafer and the second wafer are subjected to surface cleaning treatment.

[0033] Exemplarily, physical cleaning (such as deionized water flushing, ultrasonic cleaning) plus chemical cleaning can be used to perform surface cleaning treatment on the surfaces of the epitaxial layers to remove abrasive particles and chemical impurities remaining on the surfaces of the wafers after the chemical mechanical polishing treatment.

[0034] S22: The first wafer and the second wafer subjected to surface pretreatment are placed into a bonding machine.

[0035] Exemplarily, the first wafer W1 and the second wafer W2 subjected to surface pretreatment are placed into a bonding machine, in which the front surface of the first wafer W1 and the front surface of the second wafer W2 are aligned so that the deep trench structures 41 in the first wafer W1 and the deep trench structures 41 in the second wafer W2 are correspondingly aligned one by one.

[0036] S23: Si-Si bonding is performed on the front surface of the first wafer and the front surface of the second wafer by the bonding machine.

[0037] Exemplarily, Si-Si bonding is performed on the front surface of the first wafer W1 and the front surface of the second wafer W2 by the bonding machine. Through the bonding treatment, the "van der Waals force" or "hydrogen bond" between atoms will spontaneously adhere the front surfaces of the first wafer W1 and the second wafer W2 to form weak bonding. Through the bonding treatment, the corresponding deep trench structures 41 in the first wafer W1 and the deep trench structures 41 in the second wafer W2 form the column structures 42 in the subsequent super-junction device.

[0038] S24: High-temperature thermal annealing treatment is performed on the first wafer and the second wafer after Si-Si bonding.

[0039] Exemplarily, by high-temperature thermal annealing treatment on the first wafer W1 and the second wafer W2 after the Si-Si bonding, atomic diffusion occurs on the bonding surface of the first wafer W1 and the second wafer W2, forming stable covalent bonds, so that the weak bonding between the first wafer W1 and the second wafer W2 is converted into strong bonding.

[0040] S3: performing a back-thinning process on the first wafer to remove the substrate and part of the epitaxial layer of the first wafer until the deep trench structure in the first wafer is exposed.

[0041] Exemplarily, referring to Figure 4 The back-thinning process is performed on the first wafer W1, so as to sequentially remove the substrate 2 of the first wafer W1 and part of the epitaxial layer 3 in the first wafer W1. The back-thinning process is stopped until the deep trench structure 41, i.e. the column structure 42, in the first wafer W1 is exposed.

[0042] S4: performing subsequent processes on the surface of the epitaxial layer where the deep trench structure is exposed to obtain a super junction device.

[0043] Exemplarily, the semiconductor device composed of the first wafer W1 and the second wafer W2 bonded as described above can be used as a substrate, and subsequent processes are performed on the surface of the epitaxial layer 3 where the deep trench structure 41, i.e. the column structure 42, is exposed, and finally a super junction device is obtained. The subsequent processes can include P ring process, guard ring process, gate trench formation process, gate polysilicon deposition process, doping ion implantation process, contact hole generation process, injection hole generation process, top metal process, passivation process, etc., which are consistent with the formation process of the super junction device in the prior art, and the embodiments of the present application will not be described again.

[0044] The manufacturing process of the super junction device provided in the embodiments of the present application provides a pair of wafers including a first wafer W1 and a second wafer W2, and combines the first wafer W1 and the second wafer W2 by a front bonding process, as a substrate for subsequent formation of a super junction device, wherein the deep trench structures in the first wafer W1 and the second wafer W2 form a column structure 42. Then, a back-thinning process is performed on the first wafer W1 to remove the substrate 2 and part of the epitaxial layer 3 of the first wafer W1 until the deep trench structure 41 in the first wafer W1 is exposed. Compared with the column structure 42 formed by one deep trench structure 41, in the present application, two deep trench structures 41 in the first wafer W1 and the second wafer W2 are combined into the column structure 42 by the bonding process, which effectively improves the process limit of the depth of the column structure 42.

[0045] Obviously, the above embodiments are merely example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated and it is impossible to enumerate all the embodiments. The changes or variations derived from the above are still within the protection scope of the present application.

Claims

1. A manufacturing process for a superjunction device, characterized in that, include: Provided a pair of wafers, the wafers including a substrate and an epitaxial layer formed on the substrate, the epitaxial layer having a deep trench structure formed therein, wherein the pair of wafers includes a first wafer and a second wafer; A front-side bonding process is performed on the first wafer and the second wafer to align the deep trench structures in the first wafer and the deep trench structures in the second wafer in a one-to-one correspondence. The first wafer is subjected to a back-side thinning process to remove the substrate and part of the epitaxial layer of the first wafer until the deep trench structure in the first wafer is exposed. Subsequent processes are performed on the surface of the epitaxial layer where the deep trench structure is exposed to obtain a superjunction device.

2. The manufacturing process of the superjunction device according to claim 1, characterized in that, The deep trench structure is formed in the epitaxial layer through a deep trench backfilling process.

3. The manufacturing process of the superjunction device according to claim 1, characterized in that, After the front bonding process, the deep trench structures in the first wafer and the deep trench structures in the second wafer, which are aligned with each other, together form a columnar structure.

4. The manufacturing process of the superjunction device according to claim 1, characterized in that, The step of performing a bonding process on the front sides of the first wafer and the second wafer includes: Surface pretreatment is performed on the epitaxial layer surfaces of the first wafer and the second wafer; The first and second wafers, which have undergone surface pretreatment, are placed into the bonding machine. Si-Si bonding is performed on the front side of the first wafer and the front side of the second wafer using a bonding machine. The first and second wafers after Si-Si bonding are subjected to high-temperature thermal annealing.

5. The manufacturing process of the superjunction device according to claim 4, characterized in that, The surface pretreatment of the epitaxial layer surfaces of the first wafer and the second wafer includes: The epitaxial layer surfaces of the first and second wafers are subjected to surface thinning treatment; The epitaxial layer surfaces of the first and second wafers are subjected to chemical mechanical polishing. The epitaxial layer surfaces of the first and second wafers are subjected to surface cleaning treatment.

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