Heat dissipation type flip chip stacked packaging structure

Abstract

The invention discloses a heat dissipation type flip chip stacked packaging structure. The heat dissipation type flip chip stacked packaging structure comprises a first substrate, a first flip chip, a second flip chip, a third flip chip, a fourth flip chip, a second substrate, a first packaging body and a second packaging body, the first flip chip is arranged on the first substrate in a flip manner and is electrically connected with the first substrate, and the second flip chip and the third flip chip are stacked on the first flip chip in a flip manner and are electrically connected with the first substrate; the first flip chip, the second flip chip and the third flip chip are packaged on the first substrate through the first packaging body; the fourth flip chip is arranged on the second substrate in a flip mode and electrically connected with the second substrate, and the fourth flip chip is packaged on the second substrate through the second packaging body and located above the first packaging body. The invention relates to the technical field of chip packaging, and can solve the problem that in the prior art, a TCB interconnection mode of top layer packaging cannot meet the requirements of smaller packaging size, lamination height and heat dissipation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a heat dissipation type flip chip layer packaging structure. BACKGROUND

[0002] In the field of logic circuit and memory integration, package on package (PoP) has become the preferred choice in the industry, mainly applied to the manufacture of advanced mobile communication platforms used in high-end portable devices and smart phones, which brings huge demand for POP technology. POP technology combines processors and memories together, as the performance of products such as mobile phone AP processors continues to improve, the layer packaging structure needs to have stronger digital signal processing capability and new memory structure, and the memory also needs to have larger capacity.

[0003] The requirement for smaller packaging size promotes the continuous reduction of solder ball pitch, and the gap height between the top packaging and the bottom packaging will also become smaller after reflow. At present, the greatest effort in this regard is to use TCB (Thermal Compression Bonding) interconnection for the top packaging. The TCB interconnection of the prior art cannot meet the requirements of smaller packaging size, stacking height and heat dissipation, therefore, it is necessary to provide a heat dissipation type flip chip layer packaging structure, which can solve the problem that the TCB interconnection of the top packaging in the prior art cannot meet the requirements of smaller packaging size, stacking height and heat dissipation. SUMMARY

[0004] The purpose of the present application is to provide a heat dissipation type flip chip layer packaging structure, which can solve the problem that the TCB interconnection of the top packaging in the prior art cannot meet the requirements of smaller packaging size, stacking height and heat dissipation.

[0005] The present application is implemented as follows:

[0006] A heat dissipation type flip chip layer packaging structure, comprising a first substrate, a first flip chip, a second flip chip, a third flip chip, a fourth flip chip, a second substrate, a first package and a second package; the first flip chip is flip-chip mounted on the first substrate and electrically connected to the first substrate, and the second flip chip and the third flip chip are flip-chip stacked on the first flip chip and electrically connected to the first substrate; the first flip chip, the second flip chip and the third flip chip are packaged on the first substrate by the first package; the fourth flip chip is flip-chip mounted on the second substrate and electrically connected to the second substrate, and the fourth flip chip is packaged on the second substrate by the second package and located above the first package.

[0007] The second flip chip and the third flip chip are integrally exposed to the first package away from the surface of the first substrate.

[0008] The exposed surfaces of the second flip chip and the third flip chip are filled with a heat-conducting medium between the exposed surfaces and an external heat sink.

[0009] The surface of the fourth flip chip away from the second substrate is entirely exposed to the second package, and a first gap is left between the surface of the fourth flip chip away from the second substrate and the first package.

[0010] The second flip chip and the third flip chip are located in the same layer, and a second gap is provided between the second flip chip and the third flip chip, which is filled with the first package.

[0011] The second flip chip and the third flip chip are staggered in the height direction with the first flip chip, so that the first flip chip is located below the second gap between the second flip chip and the third flip chip.

[0012] The second flip chip and the third flip chip are staggered in the height direction with the fourth flip chip, so that the fourth flip chip is located above the second gap between the second flip chip and the third flip chip.

[0013] Compared with the prior art, the present application has the following beneficial effects:

[0014] 1. The first flip chip, the second flip chip and the third flip chip are flip-chip connected to the first substrate, and the fourth flip chip is flip-chip connected to the second substrate, so that the first flip chip, the second flip chip and the third flip chip, and the fourth flip chip are staggered in the height direction and form a vertically stacked structure, which has the advantages of shortening the signal path, reducing the parasitic effect of the flip chip, and the advantages of high density and high integration of the layer packaging.

[0015] 2. The surface of the second flip chip and the third flip chip is entirely exposed to the first package, and the surface of the fourth flip chip is entirely exposed to the second package, and the heat of the chip can be quickly and directly conducted to the external heat sink through the heat-conducting medium, which optimizes the heat-conducting path and greatly improves the heat-conducting and heat-dissipating efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structural schematic diagram of the heat dissipation type flip chip layer packaging structure of the present application.

[0017] In the figure, the first substrate 1, the first flip chip 2, the second flip chip 3, the third flip chip 4, the fourth flip chip 5, the second substrate 6, the first package 7 and the second package 8. DETAILED DESCRIPTION

[0018] The application will be further described below in conjunction with the drawings and specific embodiments.

[0019] Please refer to the accompanying Figure 1 The application discloses a heat-dissipation flip-chip laminated packaging structure, which comprises a first substrate 1, a first flip-chip 2, a second flip-chip 3, a third flip-chip 4, a fourth flip-chip 5, a second substrate 6, a first packaging body 7 and a second packaging body 8; the first flip-chip 2 is arranged on the first substrate 1 in a flip-chip mode and is electrically connected to the first substrate 1 through solder balls; the second flip-chip 3 and the third flip-chip 4 are arranged on the first flip-chip 2 in a flip-chip mode and are electrically connected to the first substrate 1 through solder balls; the first flip-chip 2, the second flip-chip 3 and the third flip-chip 4 are packaged on the first substrate 1 through the first packaging body 7; the fourth flip-chip 5 is arranged on the second substrate 6 in a flip-chip mode and is electrically connected to the second substrate 6 through solder balls; and the fourth flip-chip 5 is packaged on the second substrate 6 through the second packaging body 8 and is located above the first packaging body 7.

[0020] The first flip-chip 2, the second flip-chip 3 and the third flip-chip 4 are arranged on the first substrate 1 in a flip-chip mode to form a packaging body stack; and the fourth flip-chip 5 is arranged on the second substrate 6 in a flip-chip mode to form a packaging body, that is, the electronic connection points of the chips are turned downward and are directly connected to the first substrate 1 through solder balls, so that the signal path is shortened, the electrical performance is improved, and the heat dissipation path is optimized compared with the traditional heat conduction mode of the chip to the substrate, and the influence of the chip heating is reduced.

[0021] The first flip-chip 2, the second flip-chip 3, the third flip-chip 4 and the fourth flip-chip 5 are arranged in a vertical stack laminated packaging mode in the height direction, high-density packaging is realized, and more functions can be integrated in a limited space.

[0022] The second flip-chip 3 and the third flip-chip 4 are integrally exposed to the first packaging body 7 away from the surface of the first substrate 1.

[0023] The heat of the second flip-chip 3 and the third flip-chip 4 can be quickly conducted to the packaging material, the external heat sink and other components outside the chip through the surface exposure of the second flip-chip 3 and the third flip-chip 4, so that the purpose of high-efficiency heat dissipation is achieved.

[0024] Preferably, the exposed surface of the second flip-chip 3 and the third flip-chip 4 is flush with the surface of the first packaging body 7, so that the heat dissipation efficiency is ensured and the appearance is considered.

[0025] The exposed surface of the second flip-chip 3 and the third flip-chip 4 is filled with a heat-conducting medium between the external heat sink.

[0026] Preferably, the heat-conducting medium can adopt a material with high thermal conductivity, such as copper, silver, aluminum alloy, heat-conducting silicon grease, etc., so as to ensure the direct and rapid conduction of the heat of the second flip chip 3 and the third flip chip 4 to the external heat sink, shorten the heat-conducting path, and reduce the thermal resistance. Meanwhile, the heat can be dissipated more quickly by combining the existing active heat dissipation mode such as a fan and a heat sink.

[0027] The fourth flip chip 5 is exposed on the surface of the second package 8, and a first gap is left between the surface of the fourth flip chip 5 away from the second substrate 6 and the first package 7.

[0028] The exposure of the surface of the fourth flip chip 5 can enable the heat of the fourth flip chip 5 to be quickly conducted outward from the chip, and the heat dissipation is ensured through the first gap, so as to achieve the purpose of high-efficiency heat dissipation.

[0029] Preferably, the exposed surface of the fourth flip chip 5 is flush with the surface of the second package 8, so as to ensure the heat dissipation efficiency while taking into account the aesthetics.

[0030] The second flip chip 3 and the third flip chip 4 are located in the same layer, and a second gap is arranged between the second flip chip 3 and the third flip chip 4, which is filled with the first package 7.

[0031] The arrangement of the second gap facilitates the arrangement of the first flip chip 2 and the fourth flip chip 5, and also avoids the heat accumulation between the second flip chip 3 and the third flip chip 4.

[0032] The second flip chip 3 and the third flip chip 4 are arranged in a staggered manner in the height direction with the first flip chip 2, so that the first flip chip 2 is located below the second gap between the second flip chip 3 and the third flip chip 4.

[0033] The second flip chip 3 and the third flip chip 4 are arranged in a staggered manner in the height direction with the fourth flip chip 5, so that the fourth flip chip 5 is located above the second gap between the second flip chip 3 and the third flip chip 4.

[0034] The arrangement of the first gap and the second gap ensures the small-size stacked package and high-efficiency heat dissipation, and also enables the first flip chip 2 and the fourth flip chip 5 to be used in cooperation, such as the transmission and reception of optical signals.

[0035] The above merely describes the preferred embodiments of the present application, but is not used to limit the protection scope of the present application, and therefore, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A heat-dissipating flip-chip stacked package structure, characterized in that: It includes a first substrate (1), a first flip chip (2), a second flip chip (3), a third flip chip (4), a fourth flip chip (5), a second substrate (6), a first package (7), and a second package (8); the first flip chip (2) is flipped onto the first substrate (1) and electrically connected to the first substrate (1); the second flip chip (3) and the third flip chip (4) are flipped onto the first flip chip (2) and electrically connected to the first substrate (1); the first flip chip (2), the second flip chip (3), and the third flip chip (4) are packaged on the first substrate (1) through the first package (7); the fourth flip chip (5) is flipped onto the second substrate (6) and electrically connected to the second substrate (6); the fourth flip chip (5) is packaged on the second substrate (6) through the second package (8) and is located above the first package (7).

2. The heat-dissipating flip-chip stacked package structure according to claim 1, characterized in that: The surfaces of the second flip chip (3) and the third flip chip (4) away from the first substrate (1) are entirely exposed on the first package (7).

3. The heat-dissipating flip-chip stacked package structure according to claim 2, characterized in that: The exposed surfaces of the second flip chip (3) and the third flip chip (4) are filled with a thermally conductive medium between them and the external heat sink.

4. The heat-dissipating flip-chip stacked package structure according to claim 1, characterized in that: The surface of the fourth flip chip (5) away from the second substrate (6) is entirely exposed in the second package (8), and a first gap is left between the surface of the fourth flip chip (5) away from the second substrate (6) and the first package (7).

5. The heat-dissipating flip-chip stacked package structure according to any one of claims 1-3, characterized in that: The second flip chip (3) and the third flip chip (4) are located in the same layer, and a second gap is provided between the second flip chip (3) and the third flip chip (4), which is filled by the first package (7).

6. The heat-dissipating flip-chip stacked package structure according to claim 5, characterized in that: The second flip chip (3) and the third flip chip (4) are offset from the first flip chip (2) in the height direction, so that the first flip chip (2) is located below the second gap between the second flip chip (3) and the third flip chip (4).

7. The heat-dissipating flip-chip stacked package structure according to claim 5, characterized in that: The second flip chip (3) and the third flip chip (4) are offset from the fourth flip chip (5) in the height direction, so that the fourth flip chip (5) is located above the second gap between the second flip chip (3) and the third flip chip (4).

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