Method of manufacturing a semiconductor structure

Abstract

The application relates to a preparation method of a semiconductor structure, comprising the following steps: providing a substrate; sequentially forming a pseudo-gate material layer, a hard mask layer on the pseudo-gate material layer and a sacrificial mask layer on the hard mask layer on the substrate; etching the sacrificial mask layer, the hard mask layer and the pseudo-gate material layer in sequence to form a plurality of discrete pseudo-gates, a hard mask pattern on the pseudo-gates and a sacrificial mask pattern on the hard mask pattern on the substrate, wherein the top surface of the sacrificial mask pattern is uneven, and the height of the sacrificial mask pattern on different regions of the substrate is different; removing the sacrificial mask pattern and retaining the pseudo-gates and the hard mask pattern; and forming a side wall on the sidewall surface of the pseudo-gates. The method can prevent the two ends of the top surface of the pseudo-gates from being over-etched.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing processes, as device feature sizes continue to shrink, traditional silicon dioxide / polysilicon gate structures can no longer meet the demands of advanced processes, leading to the development of high-k metal gate (HKMG) technology. HKMG is an important technology in semiconductor manufacturing, using metal materials as the gate material for transistors. Compared to traditional polysilicon gates, metal gates offer higher conductivity, lower resistivity, and better compatibility with high-k dielectric materials (such as HfO2 and HfSiNO).

[0003] Current high-k metal gate fabrication typically employs a gate-last process. This process requires a dummy gate to define the gate structure formation area, followed by sidewall formation, and then a dielectric layer to fill the gaps between the dummy gates. The dummy gates are then removed, and the removed areas are filled with metal to form the metal gate. However, in current gate-last processes, the top two ends of the dummy gate are over-etched, which introduces defects in subsequent processes and affects device performance. Summary of the Invention

[0004] Based on this, this application provides a method for fabricating a semiconductor structure to improve the bonding strength of a wafer.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, comprising:

[0006] Provide substrate;

[0007] A dummy gate material layer, a hard mask layer on the dummy gate material layer, and a sacrificial mask layer on the hard mask layer are sequentially formed on the substrate. The material of the sacrificial mask layer is different from that of the hard mask layer.

[0008] The sacrificial mask layer, hard mask layer and dummy gate material layer are etched sequentially to form multiple discrete dummy gates, hard mask patterns on the dummy gates and sacrificial mask patterns on the hard mask patterns on the substrate. The top surface of the sacrificial mask patterns is uneven and the height of the sacrificial mask patterns in different regions of the substrate is different.

[0009] Remove the sacrificial mask pattern, and retain the pseudo-gated and hard mask patterns;

[0010] Sidewalls are formed on the sidewall surface of the pseudo-gate.

[0011] In some embodiments of this application, a wet etching process is used to remove the sacrificial mask pattern.

[0012] In some embodiments of this application, the process of removing the sacrificial mask pattern includes: forming a protective layer on a substrate that covers the dummy gate, the hard mask pattern, and the sacrificial mask pattern;

[0013] The protective layer is thinned to expose the sacrificial mask pattern, while the remaining protective layer still covers the sidewalls of the pseudo gate and hard mask pattern;

[0014] After thinning the protective layer, the sacrificial mask pattern is removed;

[0015] After removing the sacrificial mask pattern, remove the protective layer.

[0016] In some embodiments of this application, the hard mask layer comprises a single-layer structure formed by one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or a stacked structure formed by two or more of the above materials.

[0017] The material of the sacrificial mask layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride;

[0018] The protective layer is made of photoresist.

[0019] In some embodiments of this application, before sequentially etching the sacrificial mask layer, the hard mask layer, and the dummy gate material layer, the method further includes:

[0020] A spin-coated material layer is formed on the sacrificial mask layer;

[0021] A patterned photoresist layer is formed on the spin-coated material layer.

[0022] In some embodiments of this application, the sequential etching of the sacrificial mask layer, the hard mask layer, and the dummy gate material layer includes: using a patterned photoresist layer, sequentially etching the spin-coated material layer, the sacrificial mask layer, the hard mask layer, and the dummy gate material layer, and during the etching process, the patterned photoresist layer and the spin-coated material layer are removed simultaneously.

[0023] In some embodiments of this application, it also includes:

[0024] The source and drain regions are formed in the substrate on both sides of the sidewall, respectively;

[0025] A dielectric layer covering the pseudo-gate and hard mask pattern is formed on the substrate;

[0026] Planarize the dielectric layer and hard mask pattern until the pseudo gate is exposed;

[0027] Remove the dummy gates to form grooves;

[0028] A metal gate is formed in the groove.

[0029] In some embodiments of this application, different regions of the substrate include a first region and a second region, and multiple discrete dummy gates are formed on the substrate of the first region and the second region, respectively.

[0030] In some embodiments of this application, the size of the pseudo-gate on the first region is larger than the size of the pseudo-gate on the second region, and the height of the sacrificial mask pattern on the pseudo-gate in the first region is greater than the height of the sacrificial mask pattern on the pseudo-gate in the second region.

[0031] In some embodiments of this application, the first region is an NMOS region and the second region is a PMOS region, or the first region is a PMOS region and the second region is an NMOS region.

[0032] The embodiments of this application can produce the following unexpected technical effects:

[0033] The method for fabricating a semiconductor structure according to the embodiments of this application includes: providing a substrate; sequentially forming a dummy gate material layer, a hard mask layer on the dummy gate material layer, and a sacrificial mask layer on the hard mask layer on the substrate; sequentially etching the sacrificial mask layer, the hard mask layer, and the dummy gate material layer to form multiple discrete dummy gates, hard mask patterns on the dummy gates, and sacrificial mask patterns on the hard mask patterns on the substrate, wherein the top surface of the sacrificial mask patterns is uneven, and the height of the sacrificial mask patterns in different regions of the substrate is different; removing the sacrificial mask patterns, retaining the dummy gates and the hard mask patterns; and forming sidewalls on the sidewall surface of the dummy gates. In this application, since a sacrificial mask layer is formed on the hard mask layer, and the sacrificial mask layer, hard mask layer, and dummy gate material layer are etched sequentially to form a dummy gate, a hard mask pattern on the dummy gate, and a sacrificial mask pattern on the hard mask pattern, although the top surface of the formed sacrificial mask pattern may be uneven and the height of the sacrificial mask pattern on different areas of the substrate may be different, the top surface of the formed hard mask pattern can remain flat, and the height of the hard mask pattern on different areas of the substrate can be kept consistent. Therefore, in the process of forming sidewalls on the sidewalls of the dummy gate after removing the sacrificial mask pattern, there will be no problem that the hard mask pattern on a certain area of ​​the substrate will be consumed too quickly due to uneven top surfaces and different heights, resulting in premature exposure and over-etching of the top two ends of the dummy gate. That is, in this application, in the entire process of forming sidewalls on the sidewalls of the dummy gate, the top two ends of all dummy gates on the substrate can still be covered by a hard mask pattern of a certain thickness, so that the top two ends of the dummy gate will not be over-etched, thereby improving the performance of the device.

[0034] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a substrate and a cross-sectional structure after forming multiple films on the substrate is provided in the existing high-k metal gate fabrication process.

[0037] Figure 2 This is a schematic diagram of the cross-sectional structure after etching multiple film layers to form a pseudo-gate in the existing high-K metal gate fabrication process.

[0038] Figure 3 This is a schematic diagram of the cross-sectional structure after the sidewalls are formed on the sidewall surface of the dummy gate in the existing high-K metal gate fabrication process.

[0039] Figure 4 This is a schematic flowchart illustrating the method for fabricating semiconductor structures provided in some embodiments of this application;

[0040] Figure 5 This is a schematic cross-sectional view of the semiconductor structure fabrication method provided in some embodiments of this application, after a dummy gate material layer, a hard mask layer on the dummy gate material layer, and a sacrificial mask layer are sequentially formed on the substrate.

[0041] Figure 6 This is a schematic cross-sectional view of the semiconductor structure fabricated by sequentially etching the sacrificial mask layer, hard mask layer and dummy gate material layer in some embodiments of this application.

[0042] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after the protective layer is formed in the preparation method of the semiconductor structure provided in some embodiments of this application;

[0043] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after the patterned protective layer in the fabrication method of the semiconductor structure provided in some embodiments of this application;

[0044] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after removing the sacrificial mask pattern in a method for fabricating a semiconductor structure provided in some embodiments of this application.

[0045] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the protective layer has been removed in some embodiments of this application.

[0046] Figure 11 This is a schematic cross-sectional view of the semiconductor structure after the sidewall is formed on the sidewall surface of the dummy gate in the method for fabricating the semiconductor structure provided in some embodiments of this application.

[0047] Figure 12 This is a schematic cross-sectional view of the semiconductor structure after trenches are formed in the substrates on both sides of the dummy gate and sidewalls in a method for fabricating a semiconductor structure provided in some embodiments of this application.

[0048] Explanation of reference numerals in the attached figures:

[0049] Substrate 101; Buffer layer 102; Pseudo-gate material layer 103; First hard mask layer 104; Second hard mask layer 105; Sacrificial mask layer 106; First spin-coating material layer 107; Second spin-coating material layer 108; Patterned photoresist layer 109; Pseudo-gate 110; First hard mask pattern 111; Second hard mask pattern 112; Sacrificial mask pattern 113; Protective layer 114; Sidewall 115; Mask layer 116; Trench 117. Detailed Implementation

[0050] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this application, the term “and / or” includes any and all combinations of the associated listed items.

[0055] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0056] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.

[0057] The existing process for fabricating high-k metal gates using gate-last technology generally includes: (Reference) Figure 1 A substrate 101 is provided; a buffer layer 102, a dummy gate material layer 103, a first hard mask layer 104, a second hard mask layer 105, a first spin-coating material layer 107, a second spin-coating material layer 108, and a patterned photoresist layer 109 are sequentially formed on the substrate 101. The dummy gate material layer 103 is made of polysilicon, the first hard mask layer 104 and the second hard mask layer 105 are made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride, the first spin-coating material layer 107 is made of spin-coated carbon material, and the second spin-coating material layer 108 is made of spin-coated silicon glass; Reference Figure 2 Using a patterned photoresist layer 109, a second spin-coating material layer 108, a first spin-coating material layer 107, a second hard mask layer 105, a first hard mask layer 104, and a dummy gate material layer 103 are sequentially etched to form a dummy gate 110, a first hard mask pattern 111 on the dummy gate 110, and a second hard mask pattern 112 on the first hard mask pattern 111. The patterned photoresist layer 109, the second spin-coating material layer 108, and the first spin-coating material layer 107 are simultaneously removed during the etching process. (Reference) Figure 3 A sidewall 115 is formed on the sidewall surface of the dummy gate 110; a dielectric layer (not shown) is formed covering the sidewall 115, the first hard mask pattern 111 and the surface of the substrate 101; the dielectric layer and the first hard mask pattern 111 are planarized until the dummy gate 110 (not shown) is exposed; the dummy gate is removed to form a groove (not shown); a metal gate (not shown) is formed in the groove.

[0058] Research has found that continued reference Figure 2 Since the size of the dummy gate 110 formed on different regions of the substrate 101 will be different (for example, the size of the dummy gate 110 formed on the first region 11 is larger than the size of the dummy gate 110 formed on the second region 12), and due to the etching load effect during the aforementioned etching process, the top surface of the second hard mask pattern 112 formed after etching will be uneven (for example, it will have an arc shape with a high center and a low edge), and the height of the second hard mask pattern 112 on dummy gate 110 of different sizes (or on substrate 101 of different regions) will also be different (for example, the height of the second hard mask pattern 112 on the dummy gate 110 of the second region 12 will be lower than the height of the second hard mask pattern 112 on the dummy gate 110 of the first region 11, that is, the thickness of the second hard mask pattern 112 on the dummy gate 110 of the second region 12 will be less than the thickness of the second hard mask pattern 112 on the dummy gate 110 of the first region 11).

[0059] The uneven top surface and varying height of the second hard mask pattern 112 will cause over-etching at both ends of the top of some dummy gates 110 during the aforementioned process. For details, please refer to [link / reference]. Figure 3 After forming the dummy gate 110, a sidewall 115 is formed on the sidewall surface of the dummy gate 110. The sidewall 115 can be a multilayer sidewall. In one example, the sidewall 115 includes a first silicon oxide sidewall located on the sidewall surface of the dummy gate, a silicon nitride sidewall located on the sidewall surface of the first silicon oxide sidewall, and a second silicon oxide sidewall located on the sidewall surface of the silicon nitride sidewall. The process of forming the sidewall 115 generally includes: using a deposition process to cover the dummy gate 110, the first hard mask pattern 111, the second hard mask pattern 112, and the sidewall material layer on the surface of the substrate 101; etching the sidewall material layer using a maskless etching process to form the sidewall 115 on the sidewall surface of the dummy gate 110. When the sidewall 115 is multilayer, multiple deposition processes and multiple maskless etching processes are required. Since the sidewall material layer is made of the same material as the first hard mask pattern 111 and the second hard mask pattern 112, namely silicon oxide or silicon nitride, the first hard mask pattern 111 and the second hard mask pattern 112 will be etched simultaneously during the etching of the sidewall material layer. When the second hard mask pattern 112 is completely consumed, the first hard mask pattern 111 will also be gradually consumed, and the top surface of the first hard mask pattern 111 will be uneven (exhibiting an arc-shaped morphology with a high center and low edges), and the height of the first hard mask pattern 111 in different regions will also be different (e.g., the second...). The height of the first hard mask pattern 111 on the pseudo gate 110 in region 12 will be lower than the height of the first hard mask pattern 111 on the pseudo gate 110 in the first region 11, that is, the thickness of the first hard mask pattern 111 on the pseudo gate 110 in the second region 12 will be less than the thickness of the first hard mask pattern 111 on the pseudo gate 110 in the first region 11. As the first hard mask pattern 111 is consumed, the edges of the first hard mask pattern 111 on the second region 12 will be consumed first, so that the top two ends of the pseudo gate 110 on the second region 12 will be exposed and over-etched (e.g. Figure 3 (As shown in the dashed box 13), the first hard mask pattern 111 on the first region 11 still has some thickness, and the top two ends of the pseudo gate 110 on the first region 11 will not be over-etched.

[0060] The top two ends of the pseudo-gate 110 in the second region 12 will be over-etched (e.g., Figure 3 (As shown within the dashed box 13), this will introduce defects in subsequent processes, affecting device performance. Specifically:

[0061] On the one hand, in some examples, after forming the sidewall 115, trenches (not shown in the figure) are also formed in the substrate 101 on both sides of the sidewall 115 in some processes. During the formation of the trench, the exposed dummy gate 110 is further over-etched, which further intensifies the over-etching temperature of the dummy gate. After the trench is formed, silicon-germanium material (or silicon carbide material) is filled in the trench by epitaxy to form the silicon-germanium source / drain region (or silicon carbide source / drain region) of the transistor to improve the carrier mobility (the silicon-germanium source / drain region can improve the hole mobility, and the silicon carbide source / drain region can improve the electron mobility). When epitaxially forming silicon-germanium material, since the top two ends of the dummy gate 110 in the second region 12 are exposed by over-etching, this region will also be epitaxially formed with silicon-germanium material. When removing the dummy gate 110 and forming the groove, since the material of the dummy gate 110 (polysilicon) is different from that of the silicon-germanium material (or silicon carbide material), this will result in the presence of silicon-germanium material (or silicon carbide material) residue, affecting the performance of forming a metal gate at the location where the dummy gate 110 is removed.

[0062] On the other hand, during the aforementioned planarization of the dielectric layer and the first hard mask pattern until the dummy gate 110 is exposed, the top two ends of the dummy gate 110 in the second region 12 will be over-etched, causing the over-etched areas to be filled by the dielectric layer material. When the dummy gate 110 is removed to form a groove, the dielectric layer material at the over-etched areas will not be removed. The over-etched areas will cause the groove opening to be reduced, which is not conducive to the formation of the metal gate and affects the performance of the metal gate.

[0063] Therefore, this application provides a method for preparing a semiconductor structure. Figure 4 This is a schematic flowchart illustrating the method for fabricating semiconductor structures provided in some embodiments of this application; Figures 5-12 This is a schematic diagram of the various stages in the semiconductor structure fabrication method provided in some embodiments of this application.

[0064] refer to Figure 4 A method for fabricating a semiconductor structure, comprising the following steps:

[0065] Step S101: Provide a substrate;

[0066] In step S102, a dummy gate material layer, a hard mask layer on the dummy gate material layer, and a sacrificial mask layer on the hard mask layer are sequentially formed on the substrate. The material of the sacrificial mask layer is different from that of the hard mask layer.

[0067] Step S103: The sacrificial mask layer, hard mask layer and dummy gate material layer are etched sequentially to form multiple discrete dummy gates, hard mask patterns on the dummy gates and sacrificial mask patterns on the hard mask patterns on the substrate. The top surface of the sacrificial mask patterns is uneven and the height of the sacrificial mask patterns in different regions of the substrate is different.

[0068] Step S104: Remove the sacrificial mask pattern, and retain the pseudo-gate and hard mask patterns;

[0069] Step S105: A sidewall is formed on the sidewall surface of the pseudo gate.

[0070] In this application, in the aforementioned fabrication method, since a sacrificial mask layer is formed on the hard mask layer, and the sacrificial mask layer, hard mask layer, and dummy gate material layer are etched sequentially to form a dummy gate, a hard mask pattern on the dummy gate, and a sacrificial mask pattern on the hard mask pattern, although the top surface of the formed sacrificial mask pattern may be uneven and the height of the sacrificial mask pattern in different areas of the substrate may be different, the top surface of the formed hard mask pattern can remain flat, and the height of the hard mask pattern in different areas of the substrate can remain consistent. Therefore, in the process of forming sidewalls on the sidewalls of the dummy gate after removing the sacrificial mask pattern, there will be no problem that the hard mask pattern in different areas of the substrate will be consumed too quickly due to uneven top surfaces and different heights, resulting in premature exposure and over-etching of the top two ends of the dummy gate. That is, in this application, in the entire process of forming sidewalls on the sidewalls of the dummy gate, the top two ends of all dummy gates on the substrate can still be covered by a hard mask pattern of a certain thickness, so that the top two ends of the dummy gate will not be over-etched, thereby improving the performance of the device.

[0071] The fabrication method of the aforementioned semiconductor structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0072] First, refer to Figure 4 In conjunction with references Figure 5 In step S101, a substrate 101 is provided; in step S102, a dummy gate material layer 103, a hard mask layer on the dummy gate material layer 103, and a sacrificial mask layer 106 on the hard mask layer are sequentially formed on the substrate 101. The material of the sacrificial mask layer 106 is different from that of the hard mask layer.

[0073] Substrate 101 serves as a platform for subsequent processes. Substrate 101 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, substrate 101 can also be a layered substrate including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator.

[0074] The dummy gate material layer 103 is subsequently used to form the dummy gate. In one example, the material of the dummy gate material layer 103 can be polycrystalline silicon or amorphous silicon.

[0075] In some embodiments, a buffer layer 102 may be formed between the dummy gate material layer 103 and the substrate 101. The material of the buffer layer 102 may be silicon oxide to reduce the stress between the dummy gate material layer 103 and the substrate 101.

[0076] The hard mask layer is subsequently used to form a hard mask pattern, which serves as a mask when the dummy gate material layer 103 is etched to form a dummy gate. The hard mask layer can be a single-layer or multi-layer stacked structure. In some embodiments, the hard mask layer is a two-layer stacked structure, including a first hard mask layer 104 and a second hard mask layer 105 located on the first hard mask layer 104.

[0077] In some embodiments, the materials of the first hard mask layer 104 and the second hard mask layer 105 are different, and the thickness of the first hard mask layer 104 is less than the thickness of the second hard mask layer 105. In some embodiments, the material of the first hard mask layer 104 includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the material of the second hard mask layer 105 includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In a specific example, the material of the first hard mask layer 104 is silicon nitride, and the material of the second hard mask layer 105 is silicon oxide.

[0078] The sacrificial mask layer 106 is subsequently used to form the sacrificial mask pattern 113 (reference). Figure 6 The sacrificial mask pattern 113 serves as the subsequent etching of the dummy gate material layer and the hard mask layer. It acts as a sacrificial mask during the formation of the dummy gate 110 and the hard mask pattern, protecting the top surface of the hard mask pattern (including the first hard mask pattern 111 and the second hard mask pattern 112) from being etched. This ensures that after the dummy gate 110 is formed, the sacrificial mask pattern 113 (see reference) remains intact. Figure 6 The top surface of the substrate 101 will be uneven, and the sacrificial mask pattern 113 on different regions of the substrate 101 (refer to...) Figure 6 The heights of the hard mask patterns (including the first hard mask pattern 111 and the second hard mask pattern 112) are different, but the top surface of the hard mask pattern (including the first hard mask pattern 111 and the second hard mask pattern 112) can remain flat, and the heights of the hard mask patterns (including the first hard mask pattern 111 and the second hard mask pattern 112) in different regions of the substrate can be kept consistent. This allows sidewalls 115 to be formed on the sidewalls of the pseudo gate 110 after the sacrificial mask pattern 113 is removed (see reference). Figure 11 During the process of fabrication, there will be no problem where the hard mask pattern in different areas of the substrate 101 is consumed too quickly due to uneven top surface and different height, resulting in premature exposure and over-etching of the top two ends of the dummy gate 110. That is, in this application, sidewalls 115 are formed on the sidewalls of the dummy gate 110 (see reference). Figure 11Throughout the entire process, the top ends of all dummy gates 110 on the substrate 101 can still be covered by a hard mask pattern (111) of a certain thickness, so that the top ends of the dummy gates 110 (such as...) Figure 11 The dashed box in section 13 will not be over-etched, thus improving the performance of the device.

[0079] The material of the sacrificial mask layer 106 is different from that of the hard mask layer. During subsequent removal of the formed sacrificial mask pattern, the etching rate of the etch solution or etch gas on the sacrificial mask pattern is much greater than that on the hard mask pattern (the etching selectivity ratio is greater than 2:1), thereby reducing the amount of hard mask pattern etched and ensuring its integrity. In some embodiments, when the hard mask layer is multilayered, the material of the sacrificial mask layer 106 is different from the material of the topmost hard mask layer it contacts.

[0080] In some embodiments, the material of the sacrificial mask layer 106 includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the material used to form the sacrificial mask layer 106 includes a chemical vapor deposition process. In one specific embodiment, the material of the sacrificial mask layer 106 is different from the material of the second hard mask layer 105, and the material of the sacrificial mask layer 106 is silicon nitride.

[0081] In some embodiments, the method further includes: forming a spin-coating material layer on the sacrificial mask layer 106; and forming a patterned photoresist layer 109 on the spin-coating material layer.

[0082] The spin-coating material layer provides a flat surface for forming the patterned photoresist layer 109. The spin-coating material layer may include a single-layer or multi-layer stacked structure. In some embodiments, the spin-coating material layer is a double-layer stacked structure, including a first spin-coating material layer 107 and a second spin-coating material layer 108 located on the first spin-coating material layer 107. The materials of the first spin-coating material layer 107 and the second spin-coating material layer 108 are different. In one example, the material of the first spin-coating material layer 107 includes spin-coating carbon material, and the material of the second spin-coating material layer 108 includes spin-coating silicon glass. The process for forming the first spin-coating material layer 107 and the second spin-coating material layer 108 includes a spin-coating process.

[0083] The patterned photoresist layer 109 defines the location where the aforementioned stacked structure needs to be etched. There are multiple discrete patterned photoresist layers 109. There are openings between adjacent patterned photoresist layers 109 that expose the second spin-coated material layer 108. The dimensions (e.g., width) of the multiple patterned photoresist layers 109 can be different, so that the dimensions (e.g., width) of the dummy gates formed on different regions of the subsequent substrate 101 can be different to meet the requirements of different processes.

[0084] In a specific example, different regions of the substrate 101 may include a first region 11 and a second region 12. The first region 11 and the second region 12 may be adjacent or not adjacent. The size of the patterned photoresist layer 109 formed on the first region 11 is different from the size of the patterned photoresist layer 109 formed on the second region. Specifically, the size of the patterned photoresist layer 109 formed on the first region 11 may be larger than the size of the patterned photoresist layer 109 formed on the second region. Therefore, the size of the dummy gate formed on the first region 11 may be larger than the size of the dummy gate formed on the second region.

[0085] In some embodiments, the first region is an NMOS region and the second region is a PMOS region, or the first region is a PMOS region and the second region is an NMOS region. Subsequently, an NMOS transistor is formed in the NMOS region and a PMOS transistor is formed in the PMOS region. Correspondingly, the metal gate formed on the NMOS region serves as the metal gate of the NMOS transistor, and the metal gate formed on the PMOS region serves as the metal gate of the PMOS transistor.

[0086] In some embodiments, the process of forming the patterned photoresist layer 109 includes a spin coating process, an exposure process, and a development process.

[0087] Next, firstly, refer to Figure 4 In conjunction with references Figure 6 In step S103, the sacrificial mask layer 106, the hard mask layer, and the dummy gate material layer 103 are etched sequentially (see reference). Figure 5 Multiple discrete pseudo gates 110, hard mask patterns on the pseudo gates 110, and sacrificial mask patterns 113 on the hard mask patterns are formed on the substrate 101. The top surface of the sacrificial mask patterns 113 is uneven, and the height of the sacrificial mask patterns 113 on different regions of the substrate 101 is different.

[0088] The number of layers in the hard mask pattern corresponds to the number of hard mask layers, and the hard mask pattern can be a single-layer or multi-layer stacked structure. In some embodiments, the hard mask pattern is a two-layer stacked structure, including a first hard mask pattern 111 and a second hard mask pattern 112 located on the first hard mask pattern 111.

[0089] In some embodiments, sequentially etching the sacrificial mask layer 106, the hard mask layer, and the dummy gate material layer 103 includes: sequentially etching the spin-coated material layer, the sacrificial mask layer 106, the hard mask layer, and the dummy gate material layer 103 using a patterned photoresist layer 109, and during the etching process, the patterned photoresist layer 109 (refer to...) Figure 5 ) and spin-coated material layers (such as Figure 5As shown, the first spin-coated material layer 107 and the second spin-coated material layer 108 are removed simultaneously, while the material layer below the spin-coated material layer is retained to form the corresponding pattern (sacrifice mask pattern 113, hard mask pattern and pseudo gate 110).

[0090] During the etching process, the sizes of the dummy gates 110 formed on different regions of the substrate 101 will vary (for example, the size of the dummy gate 110 formed on the first region 11 is larger than the size of the dummy gate 110 formed on the second region 12). Furthermore, due to the etching load effect, the top surface of the sacrificial mask pattern 113 formed after etching will be uneven (e.g., exhibiting an arc-shaped morphology with a high center and low edges). The heights of the sacrificial mask patterns 113 on dummy gates 110 of different sizes (or on substrates 101 in different regions) will also differ (e.g., the height of the sacrificial mask pattern 113 on the dummy gate 110 in the second region 12 will be lower than the height of the sacrificial mask pattern 113 on the dummy gate 110 in the first region 11, meaning the thickness of the sacrificial mask pattern 113 on the dummy gate 110 in the second region 12 will be less than the thickness of the sacrificial mask pattern 113 on the dummy gate 110 in the first region 11). Meanwhile, the hard mask pattern (such as...) Figure 5 As shown, the top surface of the first hard mask pattern 111 and the second hard mask pattern 112 can remain flat, and the height of the hard mask pattern in different regions of the substrate can remain consistent (the height is the vertical distance between the top surface of the hard mask layer and the surface of the substrate 101, specifically the vertical distance between the top surface of the second hard mask pattern 112 and the surface of the substrate 101).

[0091] In some embodiments, the sequential etching of the sacrificial mask layer 106, the hard mask layer, and the dummy gate material layer 103 can employ an anisotropic dry etching process, including anisotropic plasma etching.

[0092] Next, refer to Figure 4 In conjunction with references Figures 7-10 Then proceed to step S104, remove the sacrificial mask pattern 113, and retain the pseudo gate 110 and the hard mask pattern.

[0093] In some embodiments, the process of removing the sacrificial mask pattern 113 includes: referencing Figure 7 A protective layer 114 is formed on the substrate 101 to cover the dummy gate 110, the hard mask pattern, and the sacrificial mask pattern. The material of the protective layer 114 can be a photoresist material or other suitable materials (such as amorphous carbon). When the material of the protective layer 114 is a photoresist material, the formation process of the protective layer 114 and the subsequent patterning and removal processes are simple, the cost is low, and the damage to the dummy gate 110 and the hard mask pattern is small.

[0094] refer to Figure 8The protective layer 114 is thinned to expose the sacrificial mask pattern 113, while the remaining protective layer 114 still covers the pseudo gate 110 and the sidewalls of the hard mask pattern. In one example, when the material of the protective layer 114 is photoresist, the thinning of the protective layer 114 can be performed using an exposure process and a development process, and no photomask is required during the exposure process. In another example, the protective layer can be thinned using an etching process, and the top surface of the remaining protective layer 114 can be flush with or slightly lower than the top surface of the hard mask pattern (second hard mask pattern 112).

[0095] refer to Figure 9 After thinning the protective layer 114, the sacrificial mask pattern 113 is removed. The sacrificial mask pattern 113 can be removed by a wet etching process.

[0096] refer to Figure 10 After removing the sacrificial mask pattern 113, the protective layer 114 is removed. In one example, when the material of the protective layer 114 is photoresist, the protective layer 114 can be removed using an ashing process. In another example, the protective layer 114 can be removed using a wet etching process. When removing the sacrificial mask pattern 113 using the aforementioned process, since the dummy gate 110, the hard mask pattern (including the first hard mask pattern 111 and the second hard mask pattern 112), and the substrate 101 are all protected by the protective layer 114, no etching damage will occur.

[0097] refer to Figure 11 In step S105, a sidewall 115 is formed on the sidewall surface of the pseudo gate 110.

[0098] Sidewall 115 can be a multilayer sidewall. In one example, sidewall 115 is an ONO structure. Sidewall 115 includes a first silicon oxide sidewall located on the sidewall surface of the dummy gate 110, a silicon nitride sidewall located on the sidewall surface of the first silicon oxide sidewall, and a second silicon oxide sidewall located on the sidewall surface of the silicon nitride sidewall. The process of forming sidewall 115 generally includes: using a deposition process to cover the dummy gate 110, the first hard mask pattern 111, the second hard mask pattern 112, and the sidewall material layer on the surface of the substrate 101; etching the sidewall material layer using a maskless etching process to form sidewall 115 on the sidewall surface of the dummy gate 110. When sidewall 115 is multilayer, multiple deposition processes and multiple maskless etching processes are required.

[0099] Since the sidewall material layer is made of the same material as the first hard mask pattern 111 and the second hard mask pattern 112, which are both silicon oxide or silicon nitride, the first hard mask pattern 111 and the second hard mask pattern 112 are also etched simultaneously during the etching of the sidewall material layer. When the second hard mask pattern 112 is completely consumed, the first hard mask pattern 111 will also be gradually consumed. In this application, before the sidewall 115 is formed, the sacrificial mask pattern 113 due to uneven top surface and different heights is removed, leaving the hard mask pattern (such as...) Figure 10 As shown, the top surface of the first hard mask pattern 111 and the second hard mask pattern 112 can remain flat, and the height of the hard mask patterns in different regions of the substrate 101 can remain consistent. Therefore, when a sidewall 115 is formed on the sidewall of the dummy gate 110, there will be no problem where the hard mask patterns in different regions of the substrate 101 are consumed too quickly, resulting in premature exposure and over-etching of the top two ends of the dummy gate 110 due to uneven top surfaces and different heights. That is, in this application, a sidewall 115 is formed on the sidewall of the dummy gate 110 (see reference). Figure 11 During the entire process, after the second hard mask pattern 112 is consumed, the first hard mask pattern 111 will also be gradually consumed. However, the top and two ends of all dummy gates 110 on the substrate 101 can still be covered by the first hard mask pattern 111 of a certain thickness, so that the top and two ends of the dummy gates 110 (such as...) Figure 11 The dashed box in section 13 will not be over-etched, thus improving the performance of the device.

[0100] In some embodiments, the method further includes forming a source region and a drain region (not shown in the figure) in the substrate 101 on both sides of the sidewall 115.

[0101] A dielectric layer (not shown) covering the dummy gate 110 and the hard mask pattern is formed on the substrate 101.

[0102] Planarize the dielectric layer and hard mask pattern until the pseudo gate 110 (not shown in the figure) is exposed.

[0103] Remove the pseudo-gate 110 to form a groove (not shown in the figure);

[0104] A metal gate (not shown in the figure) is formed in the groove.

[0105] In some embodiments, the source region and the drain region are embedded source regions and embedded drain regions, and the process of forming the embedded source region and the embedded drain region includes: referencing Figure 12In this application, trenches 117 are formed in the substrate 101 on both sides of the dummy gate 110 and sidewall 115 in a certain region. In one example, the dummy gate 110 and sidewall 115 on the first region 11 are covered by a mask layer 116, and the substrate 101 on both sides of the dummy gate 110 and sidewall 115 on the second region 12 is etched to form trenches 117. Silicon-germanium material (or silicon carbide material) is filled into the trenches 117 using an epitaxial process to form embedded source and embedded drain regions (not shown in the figure). During the formation of the trenches 117, since the top surface of the dummy gate 110 on the second region is still covered by the first hard mask pattern 111, the two ends of the top surface of the dummy gate 110 on the second region are not exposed or over-etched. When the trenches 117 are filled with silicon-germanium material (or silicon carbide material) using an epitaxial process, the two ends of the top surface of the dummy gate 110 on the second region (e.g., Figure 12 In the dashed box 13, no silicon-germanium material (or silicon carbide material) will be epitaxially formed. When removing the dummy gate 110 and forming the groove, there will be no residue of silicon-germanium material (or silicon carbide material), which further improves the performance of the device.

[0106] In some embodiments, the metal gate includes a high-k gate dielectric layer located on the sidewalls and bottom surface of the trench, and a metal gate electrode located on the high-k gate dielectric layer and filling the trench. The high-k gate dielectric layer is made of one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO. The metal gate electrode is made of one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0107] In the description of this application, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this application, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0109] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A dummy gate material layer, a hard mask layer on the dummy gate material layer, and a sacrificial mask layer on the hard mask layer are sequentially formed on the substrate. The material of the sacrificial mask layer is different from that of the hard mask layer. The sacrificial mask layer, the hard mask layer, and the dummy gate material layer are etched sequentially to form multiple discrete dummy gates, hard mask patterns on the dummy gates, and sacrificial mask patterns on the hard mask patterns on the substrate. The top surface of the sacrificial mask patterns is uneven, and the height of the sacrificial mask patterns in different regions of the substrate is different. Remove the sacrificial mask pattern, retain the pseudo gate and the hard mask pattern, wherein the top surface of the hard mask pattern remains flat and the height of the hard mask pattern in different regions of the substrate remains consistent; A sidewall is formed on the sidewall surface of the pseudo-gate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sacrificial mask pattern is removed using a wet etching process.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of removing the sacrificial mask pattern includes: forming a protective layer on the substrate that covers the dummy gate, the hard mask pattern, and the sacrificial mask pattern; The protective layer is thinned to expose the sacrificial mask pattern, while the remaining protective layer still covers the pseudo gate and the sidewalls of the hard mask pattern; After thinning the protective layer, the sacrificial mask pattern is removed; After removing the sacrificial mask pattern, remove the protective layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The hard mask layer comprises a single-layer structure formed by one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonide, and silicon carbonitride, or a stacked structure formed by two or more of the above materials. The material of the sacrificial mask layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride; The protective layer is made of photoresist.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before sequentially etching the sacrificial mask layer, the hard mask layer, and the dummy gate material layer, the process further includes: A spin-coated material layer is formed on the sacrificial mask layer; A patterned photoresist layer is formed on the spin-coated material layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The sequential etching of the sacrificial mask layer, the hard mask layer, and the dummy gate material layer includes: using the patterned photoresist layer, sequentially etching the spin-coated material layer, the sacrificial mask layer, the hard mask layer, and the dummy gate material layer, and during the etching process, the patterned photoresist layer and the spin-coated material layer are removed simultaneously.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: Source and drain regions are formed in the substrates on both sides of the sidewall, respectively; A dielectric layer covering the dummy gate and the hard mask pattern is formed on the substrate; Flatten the dielectric layer and hard mask pattern until the pseudo gate is exposed; Remove the dummy gate to form a groove; A metal gate is formed in the groove.

8. The method for preparing a semiconductor structure according to claim 1 or 7, characterized in that, The substrate includes a first region and a second region, and a plurality of discrete pseudogates are formed on the substrate in the first region and the second region, respectively.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The size of the pseudo-gate on the first region is larger than the size of the pseudo-gate on the second region, and the height of the sacrificial mask pattern on the pseudo-gate in the first region is greater than the height of the sacrificial mask pattern on the pseudo-gate in the second region.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The first region is an NMOS region and the second region is a PMOS region, or the first region is a PMOS region and the second region is an NMOS region.

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