HDI circuit board impedance performance intelligent testing system and method

Abstract

The application belongs to the technical field of performance test, and specifically discloses an intelligent test system and method for impedance performance of HDI circuit board. The system starts the interlayer collection module immediately after completing the lamination of each circuit layer, collects in-situ impedance data by using the POFV test structure for electrical fine alignment, a diagnosis and prediction module analyzes and processes the data, generates an impedance deviation parameter set, calculates an impedance performance compliance coefficient fused with layer influence factors, and outputs a trend result through time series analysis, an impedance state determination module determines abnormalities based on preset rules according to the compliance coefficient and the trend result, and starts an adjustment trigger marking module when an abnormality is determined, and finally a test report output module generates a test report containing the impedance performance score of the whole board and the impedance performance distribution. The application realizes layer-by-layer, real-time and closed-loop intelligent test and regulation of impedance performance, and effectively improves product quality and production efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of performance testing, and in particular, relates to an HDI circuit board impedance performance intelligent testing system and method. BACKGROUND

[0002] The HDI circuit board is usually a multi-layer stacked structure, and higher circuit density and component integration are mainly achieved through micro blind hole, buried hole and other technologies. The impedance performance test is a core link to guarantee the signal transmission quality, equipment stability and product reliability of the HDI circuit board, and its importance is self-evident.

[0003] The prior art 1 is a PCB high impedance performance detection method and system disclosed in a Chinese patent application with the application number 2023103234109, which collects data from multiple physical test points, obtains expected parameters of a design prototype through a simulation model, identifies and quantifies the difference between physical test and simulation data through a maximum deviation feature extraction technology, actively compensates for performance disturbance and measurement noise caused by such deviation, and finally realizes more reliable comprehensive evaluation of the impedance performance of the PCB.

[0004] The prior art 2 is a PCB high impedance performance detection method and system disclosed in a Chinese patent application with the application number 2024116346075, which solves the influence of temperature fluctuation on resistance measurement value through real-time compensation of the resistance temperature coefficient, and observes the actual response of the high impedance area in dynamic work by applying a load and analyzing real-time signal waveforms, combines static resistance distribution with dynamic circuit behavior, and thus realizes more real evaluation of the performance of the PCB under actual use conditions.

[0005] The prior art 1 focuses on deviation compensation of test data and simulation model, but does not involve layer-by-layer testing and timing analysis. The prior art 2 focuses on temperature compensation and dynamic load response, but does not solve the influence of multi-factors such as layer-to-layer alignment accuracy and medium thickness, and the current detection is carried out when the PCB is a complete finished product or a semi-finished product, which is post-detection, resulting in delayed problem discovery and inability to locate the specific source of impedance deviation. SUMMARY

[0006] In view of this, in order to solve the above problems, an HDI circuit board impedance performance intelligent testing system and method are provided.

[0007] The purpose of the application can be achieved by the following technical scheme: the application provides an HDI circuit board impedance performance intelligent testing system, which comprises an interlayer data acquisition module, after completing the lamination of any independent circuit layer and its medium layer, marking the circuit layer as the current test layer, starting the preset POFV test structure of the test layer for alignment and then collecting the impedance data thereof.

[0008] The diagnostic prediction module processes the impedance data, generates an impedance deviation parameter set, calculates an impedance performance compliance coefficient based on the impedance deviation parameter set, and outputs an impedance deviation trend analysis result through deviation time series analysis.

[0009] The impedance state determination module determines impedance performance abnormalities through a preset determination rule based on the impedance performance compliance coefficient and the impedance deviation trend analysis result.

[0010] The adjustment trigger marking module triggers a process adjustment prompt instruction for the next production layer and performs an adjustment marking when an abnormality is determined.

[0011] The test report output module collects and calculates impedance performance compliance coefficients of subsequent test layers, and generates a final test report in combination with the adjustment marking.

[0012] The application further provides an HDI circuit board impedance performance intelligent testing method, which comprises the following steps: after the compression of any independent circuit layer and its medium layer is completed, marking the circuit layer as a current test layer, and collecting impedance data of the test layer after alignment of a preset POFV test structure of the test layer.

[0013] The impedance data are processed to generate an impedance deviation parameter set, an impedance performance compliance coefficient is calculated based on the impedance deviation parameter set, and an impedance deviation trend analysis result is output through deviation time series analysis.

[0014] Impedance performance abnormalities are determined through a preset determination rule based on the impedance performance compliance coefficient and the impedance deviation trend analysis result.

[0015] A process adjustment prompt instruction for the next production layer is triggered and an adjustment marking is performed when an abnormality is determined.

[0016] Impedance performance compliance coefficients of subsequent test layers are collected and calculated, and a final test report is generated in combination with the adjustment marking.

[0017] Compared with the prior art, the application has the following beneficial effects: (1) the application performs in-situ impedance testing immediately after compression, moves the detection node from the front end of the finished product terminal to each production layer, and thus can capture and record the layer-by-layer changes of impedance parameters in the lamination process in real time, which facilitates accurate positioning of the specific source of impedance deviation in a production layer and guarantees the timeliness of problem detection.

[0018] (2) The present application realizes comprehensive evaluation of multiple dimensions of impedance performance by calculating various impedance deviation parameters such as interlayer relative change rate, spatial distribution unevenness, phase frequency characteristics, overcomes the limitation of the prior art which only focuses on a single factor, and can more truly and completely reflect the actual working state of the HDI circuit board under complex electrical load, thereby significantly improving the accuracy and reliability of the evaluation.

[0019] (3) The present application can identify the long-term change direction and volatility evolution law of the parameters by trend mining of the impedance data in the continuous production cycle through deviation time series analysis. Thus, not only can the current state be judged, but also the future performance degradation trend can be predicted, and early warning of potential process risks can be realized, thereby realizing forward-looking prediction of future risks.

[0020] (4) The present application realizes rapid, accurate and consistent evaluation of the impedance performance of the circuit board by fusing the impedance deviation parameters of multiple dimensions into a single quantitative impedance performance compliance coefficient, and introducing layer-by-layer influence factor correction for critical states, thereby not only significantly improving the detection efficiency and judgment accuracy, but also providing a core decision basis for subsequent trend prediction and process adaptive adjustment.

[0021] (5) The present application triggers the process adjustment prompt instruction of the next production layer when it is determined that the impedance performance is abnormal, which forms a precise and adaptive intelligent closed-loop production, effectively prevents batch quality problems from the source, and realizes self-optimization of the manufacturing process. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0023] Figure 1 It is a schematic diagram of the system module connection of the present application.

[0024] Figure 2 It is a schematic diagram of the overall implementation process of the method of the present application.

[0025] Figure 3 It is a schematic diagram of the impedance deviation parameter set generation process of the present application.

[0026] Figure 4 It is a schematic diagram of the impedance performance compliance coefficient calculation process of the present application.

[0027] Figure 5 It is a schematic diagram of the deviation time series analysis process of the present application.

[0028] Figure 6 The preset determination rule determination flowchart of the application is shown in the figure. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the application will be apparently and completely described in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all the other embodiments obtained by a person of ordinary skill in the art without creative work belong to the protection scope of the application.

[0030] Please refer to Figure 1 The application provides an intelligent HDI circuit board impedance performance testing system, which comprises an interlayer data acquisition module, a diagnosis prediction module, an impedance state determination module, an adjustment trigger marking module and a test report output module.

[0031] In the above, the diagnosis prediction module is connected with the interlayer data acquisition module and the impedance state determination module, and the adjustment trigger marking module is connected with the impedance state determination module and the test report output module.

[0032] In one embodiment, the HDI circuit board has blind hole design between each layer, and the blind hole stack is used for conduction at the impedance test position, so that the impedance test structure is used for testing after the impedance of the previous layer is completed, and the impedance test structure is a POFV test structure based on the blind hole stack, which collects the impedance data between layers after the electrical probe contacts the conductive surface.

[0033] The interlayer data acquisition module marks the circuit layer as the current test layer after the independent circuit layer and the dielectric layer are laminated, and collects the impedance data of the test layer after alignment of the preset POFV test structure of the test layer.

[0034] The accuracy of impedance testing fundamentally depends on the accurate electrical contact between the probe array and the conductive surface of the test structure. An ideal alignment state should ensure that the detection signal can be stably transmitted through the contact interface without introducing additional and uncontrollable contact impedance due to slight position deviation. Meanwhile, the accurate positioning of the test structure is affected by multiple factors such as the transparency of the dielectric layer, the surface reflection and the mechanical positioning error.

[0035] In practice, it is difficult to ensure perfect electrical contact between the probe and the test point only by optical or mechanical preliminary positioning. Deviation in micro-scale positioning is not significant in vision, but it can significantly change the signal, especially the transmission path and coupling state of high-frequency signal, thus causing obvious changes in sensitive parameters such as phase angle of the monitoring signal, and finally leading to distortion of the impedance measurement result.

[0036] Based on this, the alignment execution process of the embodiment of the present application operates as follows: an optical image of the current test layer surface is collected, and the actual position coordinates of the POFV test structure are identified and extracted by an image recognition algorithm. Then, the identified position coordinates are matched with the preset theoretical coordinates, and the positioning platform is driven to move according to this, to complete the preliminary positioning of the probe array.

[0037] Among them, the actual position coordinates of the POFV test structure are identified and extracted by an image recognition algorithm, which is a common technical means in the prior art and will not be described in detail.

[0038] After completing the preliminary positioning, a probe signal is applied to the test structure by the probe array, and the phase angle change of the probe signal is monitored with high precision at the same time. When the monitored phase angle change is stably within a preset small change range, it is determined that the probe array and the conductive surface of the test structure have reached the state of accurate electrical alignment.

[0039] Among them, the frequency of the probe signal is suitable for exciting the impedance response of the POFV test structure, and the voltage amplitude is insufficient to cause electrical damage to the test structure. Exemplarily, the frequency range of the probe signal can be 10MHz to 1GHz, and the voltage amplitude range can be 10mV to 500mV.

[0040] If the monitored phase angle change is not within the above-mentioned preset change range, the preset compensation scheme is automatically matched according to the specific direction and size of the phase deviation, and the positioning platform is immediately controlled to perform accurate fine positioning adjustment. This process is repeated until the phase angle change is stably within the preset change range, thereby forming a real-time electrical closed-loop alignment control.

[0041] Understandably, the preset change range can be empirically valued according to the phase fluctuation amplitude tolerance range corresponding to the process and material of the HDI board. And the alignment deviation usually exists in horizontal and vertical directions, so based on the statistical results of a large number of experimental data in the HDI board test process, the preset compensation schemes of horizontal and vertical compensation types are established, thereby facilitating subsequent rapid adjustment of the conductive surface alignment.

[0042] As a preferred embodiment, the construction process of the preset compensation scheme of the two compensation types is as follows: firstly, a series of known position deviations are set on a standard HDI test board using a high-precision displacement platform, the corresponding phase deviation values are measured, the horizontal displacement compensation proportion coefficient and the vertical displacement compensation proportion coefficient in different deviation intervals are calculated by linear regression of least squares, wherein the horizontal compensation is performed when the deviation is negative, the vertical compensation is performed when the deviation is positive, and the compensation strategy under different deviation intervals is obtained according to the experience of HDI circuit board test positioning, and the compensation proportion coefficient and the compensation strategy are integrated to obtain the preset compensation scheme of the two compensation types under different deviation intervals.

[0043] In the implementation of horizontal compensation, the corresponding compensation strategy is automatically selected according to the real-time monitored phase deviation value. When the phase deviation is detected to be negative, the offset direction is determined by comparing the phase distribution of the four symmetrical detection points, and the corresponding proportion coefficient and compensation mode are automatically selected according to the range of the deviation value, so as to realize the complete compensation process from rapid positioning to fine adjustment.

[0044] In the implementation of vertical compensation, the pressure adjustment scheme is automatically selected according to the real-time monitored phase deviation value. By different ways such as smooth pressurization or step pressurization, stable and reliable electrical contact between the probe and the test structure is ensured.

[0045] Further, in actual testing, if the probe and the test point are not accurately positioned or in poor contact, additional impedance will be introduced, resulting in measurement distortion. In addition, if a connection is established and tested for each test point separately, the efficiency is low, and it is difficult to meet the needs of modern HDI board high-density and large-batch testing.

[0046] Based on this, the specific collection process of the impedance data of the embodiment of the application is performed according to the following steps: the probe array of the impedance test equipment is controlled to be positioned with the conductive surface of the preset POFV test structure on the current test layer.

[0047] After the positioning is completed, the positioning platform is driven to press the probe array on the conductive surface of the test structure with constant pressure, so as to establish stable electrical connection, and a connectivity self-checking verification is performed immediately after the connection is established, to ensure the reliability of the connection.

[0048] For the electrical connection that passes the verification, a series of preset frequency and amplitude sweep test excitation signals are applied to different test points or test point groups in sequence or in parallel by the same set of probe arrays by using time division multiplexing or frequency division multiplexing technology. The frequency range of the sweep signal is specially designed to cover the main frequency spectrum components of the working signal of the circuit board.

[0049] Synchronously receiving and recording a response signal from the test structure, the response signal containing complete voltage and phase information. Subsequently, the response signal is converted into a digital waveform sequence, thereby obtaining raw impedance waveform data containing a plurality of test points, i.e. as the impedance data. And for each test point, a complete data record containing a time stamp, a frequency point, an impedance amplitude and a phase angle is generated for subsequent analysis.

[0050] The diagnostic prediction module processes the impedance data to generate a set of impedance deviation parameters, calculates an impedance performance compliance coefficient based on the set of impedance deviation parameters, and outputs an impedance deviation trend analysis result through a deviation time series analysis.

[0051] Since the impedance performance of an HDI circuit board is a comprehensive index affected by interlayer materials, intra-layer process consistency and signal frequency response characteristics. In order to accurately diagnose and predict the impedance performance offline, it is necessary to extract feature parameters that can quantify the deviation from the ideal state from multiple dimensions, so as to comprehensively and deeply evaluate the quality state.

[0052] If only relying on a single dimension of impedance amplitude or a few simple statistics, such as average value and extreme value, it is difficult to capture the complex performance degradation caused by process fluctuations. It is impossible to effectively distinguish the gradual change of interlayer performance caused by lamination process, the spatial dispersion caused by uneven pattern etching, and the phase nonlinear distortion caused by dielectric material frequency variation characteristics. This lack of evaluation dimension leads to insensitive early warning and inaccurate positioning of potential quality risks.

[0053] Based on this, please refer to Figure 3 The embodiment of the present application generates the set of impedance deviation parameters according to the following steps: A1, filtering the impedance data to obtain an effective impedance data set.

[0054] Among them, the filtering processing of data is a common data processing means, which will not be described in detail.

[0055] A2, extracting impedance feature parameters of each test point from the obtained effective impedance data set, the feature parameters including impedance amplitude sequence and phase angle distribution.

[0056] A3, obtaining the average impedance amplitude of the same test point of the current test layer and the previous test layer, and calculating the relative change rate to obtain the interlayer impedance amplitude relative change rate.

[0057] A4, calculating the standard deviation of the impedance amplitude corresponding to each test point in the current test layer as the impedance spatial distribution uniformity.

[0058] A5, based on the phase angle measurement values at different frequency points, a gradient of change of the phase angle with frequency is obtained by linear fitting, and a residual sum of squares of each measurement value and the gradient of change is calculated as a phase linearity index.

[0059] A6, based on the interlayer impedance amplitude relative change rate, impedance spatial distribution non-uniformity, gradient of change of the phase angle with frequency, and phase linearity index, an impedance deviation parameter set is generated.

[0060] Further, the impedance performance of the HDI circuit board is the core index of its electrical reliability, and a quantitative coefficient is needed to quickly and objectively judge whether it meets the standard. And it needs to comprehensively reflect the deviation of impedance in multiple dimensions such as interlayer, intralayer and frequency domain, and has a clear pass / fail limit to support automatic quality judgment and process adjustment decision.

[0061] The common evaluation method at present usually simply weights each dimension parameter, ignoring the fact that different circuit layers have significant differences in sensitivity and tolerance of impedance deviation due to differences in wiring density, signal type and position in the laminated structure. For example, for high-speed signal layers, slight phase nonlinearity may be more critical than slight changes in impedance amplitude. If a uniform judgment threshold is used for all layers, it may lead to overly lenient misjudgment of critical layers or overly harsh judgment of non-critical layers, thereby affecting the evaluation accuracy and possibly causing unnecessary process adjustment.

[0062] Based on this, referring to Figure 4 The embodiment of the present application calculates the impedance performance compliance coefficient by the following steps: B1, normalizing all parameters in the impedance deviation parameter set to obtain each normalized parameter index. The specific normalization method can use min-max normalization.

[0063] B2, the weighted sum of each normalized parameter index is taken as the initial impedance performance compliance coefficient.

[0064] In one specific embodiment, the weights of each normalized parameter index are set based on the severity of their impact on impedance performance, and the sum of the values is 1.

[0065] Preferably, the interlayer relative change rate of impedance amplitude directly reflects the stability of the lamination process, and is given the highest weight, which can be exemplarily taken as 0.3. The impedance spatial distribution non-uniformity is used to focus on monitoring the consistency of pattern etching, and the weight is second, which can be exemplarily taken as 0.25. Because the phase characteristics have a decisive influence on the integrity of high-speed signals, the gradient of change of the phase angle with frequency and the phase linearity index are respectively assigned weights of 0.25 and 0.2. And the data can be adaptively adjusted and changed through process iteration data.

[0066] The linear weighting calculation is a common calculation means, and no formula is shown.

[0067] B3, if the initial impedance performance compliance coefficient is located in a preset critical qualified interval or below the lower limit of the interval, setting a layer influence factor based on the current test layer position.

[0068] It should be noted that, since the HDI circuit board adopts a multi-layer stacking structure, different circuit layers have different roles in the overall circuit function, and the importance of impedance control also has significant differences. For example, the network layer carrying high-speed signals, clocks or radio frequency signals has much lower tolerance to impedance deviation than the network layer used for low-speed control or power distribution. Therefore, when evaluating the impedance performance, a factor that quantifies the difference in importance between layers is introduced to achieve differentiated and accurate evaluation.

[0069] Based on this, the embodiment of the present application sets the layer influence factor by the following steps: S301, calculating a signal strength influence factor: importing the design file of the current HDI circuit board, extracting the geometric profile and grade identification of each network in the current test layer, and calculating the actual layout area of each network in the current test layer. Then, based on the grade identification, the proportion of the total actual layout area of each grade network to the total layout area of the current test layer is calculated to obtain the network proportion of each grade network. Finally, based on the preset influence weight of each grade network, the network proportions of each grade network are linearly weighted and summed, and the calculation result is taken as the signal strength influence factor. The larger the factor, the more critical signals the layer carries, and the more stringent the impedance performance requirements.

[0070] It should be noted that the design file is in Gerber or ODB++ format, and the network geometric profile and grade identification data are extracted through a standard analysis library such as Python's gerber-tools. The grade is preset according to the signal type, and the timing-sensitive network such as clock signal, high-speed differential pair is usually marked as a first-level network, usually assigned a weight of 0.5, the important signal network such as medium-speed data bus and specific impedance control network is usually marked as a second-level network, usually assigned a weight of 0.3, and the power network and ordinary low-speed signal network are usually marked as a third-level network, usually assigned a weight of 0.2.

[0071] It should be noted that the actual layout area calculation can be performed by using the projection area calculation method for the multi-layer overlapping layout area.

[0072] As a preferred embodiment, the actual layout area calculation is performed by using the projection area calculation method, and the specific execution process includes: establishing a two-dimensional rectangular coordinate system with the surface of the current test layer as the reference plane.

[0073] From the geometric profile of each network in the design file, the Boolean union operation is performed on the vertically overlapping wiring patterns by using the polygon clipping algorithm in the computational geometry library to eliminate the repeated calculation area.

[0074] Understandably, if the geometric profile presents a non-linear pattern such as a circular arc or a curve, it usually needs to be segmented and discretized, converted into a polygon approximation, and then participate in the actual wiring area calculation. The polygon clipping algorithm and the Boolean union operation are both existing image processing means, and will not be described again.

[0075] The graph data after Boolean processing is projected onto the reference plane, and the effective area of the projection area is calculated using the scan line algorithm, and the effective area is taken as the actual wiring area. The scan line algorithm is a common area acquisition means, and will not be described again.

[0076] S302, calculate the position influence factor: obtain the medium thickness measurement value between the current test layer and the adjacent layer, and obtain the actual distance between the current test layer and the nearest power layer or ground layer. The medium thickness and the reference layer distance are integrated to calculate the position influence factor by a pre-designed calculation rule.

[0077] Among them, as a preferred embodiment, the specific execution process of calculating the position influence factor by a pre-designed calculation rule includes: extracting the total layer height of the HDI circuit board from the design file, and taking the ratio of the actual distance to the total layer height as the distance influence factor.

[0078] The planned setting medium thickness value between the current test layer and its adjacent layer of the HDI circuit board is extracted from the design file, the medium thickness measurement value and the planned setting medium thickness value are compared, and the ratio is input into the attenuation function to output the medium thickness influence factor, wherein the attenuation function calculation formula is: , wherein, is the medium thickness influence factor, is the ratio of the medium thickness measurement value to the planned setting medium thickness value, indicates that the medium is too thick, indicates that the medium is too thin, is a natural constant. The attenuation function is used to quantify the nonlinear influence of thickness deviation on impedance sensitivity.

[0079] The distance influence factor and the medium thickness influence factor are calculated by the geometric mean method, and the final position influence factor is output.

[0080] It should be noted that the farther the signal layer is from the power supply or ground, the weaker the electromagnetic coupling between them, the larger the return path inductance, resulting in increased difficulty in impedance control and greater sensitivity to deviation. The thinner the dielectric layer, the greater the capacitance between the signal line and the reference layer, the lower the characteristic impedance, and the more sensitive to thickness fluctuations during the manufacturing process. Small thickness changes will cause greater impedance deviation. Based on this, the position influence factor is calculated based on the measured dielectric thickness and the actual distance.

[0081] It should also be noted that the dielectric thickness effect and the distance effect are not independent, but physically determine the characteristic impedance of the transmission line. In order to have the ability to capture the short board effect of the two physical parameters that jointly affect the impedance, the geometric mean method is preferably used to synthesize the position influence factor to ensure that the dielectric is too thin or too far from the reference layer. The combined effect of the synthesis result is fully reflected, thereby more truly reflecting the combined effect of the structural factors on the difficulty of impedance control, so that the final position influence factor can more reliably identify the high sensitivity layer.

[0082] S303, synthesizing the final factor: multiplying the signal strength influence factor obtained in the above steps and the position influence factor, and outputting the product as the final layer-specific influence factor. This factor will be used as a key parameter to modify the impedance performance compliance coefficient of the test layer in the set critical qualified interval, thereby ensuring that the evaluation result matches the actual electrical performance requirements of the circuit board.

[0083] In a specific embodiment, the impedance performance requirements of different levels of HDI circuit board are significantly different, and this difference mainly comes from the characteristic difference of each layer carrying signals and the physical characteristic difference brought by the laminated structure. By synthesizing the signal strength influence factor and the position influence factor, the comprehensive influence of electrical performance requirements and physical structure characteristics on impedance control can be considered at the same time.

[0084] And the operation relationship of the product ensures that only when both the signal strength and the structural characteristics are good, the layer-specific influence factor will remain low. Any significant risk in either aspect will be fully reflected in the final result, thereby achieving precise differentiated evaluation of different levels. Further, it can accurately reflect the relative importance of different levels in the whole board, providing differentiated evaluation criteria for subsequent impedance performance evaluation. At the same time, through this operation, the key level that needs to be monitored can be automatically identified, which can effectively improve the impedance control accuracy of high requirement levels and avoid excessive control of non-key levels, thereby improving the overall balance of product quality and production efficiency.

[0085] B4, modifying the initial impedance performance compliance coefficient through the layer-specific influence factor, and taking the modified result as the final impedance performance compliance coefficient.

[0086] The step of correcting the initial impedance performance compliance coefficient by the layer-specific influence factor can be performed by multiplying the initial impedance performance compliance coefficient by the sum of 1 and the layer-specific influence factor.

[0087] B5, if the initial impedance performance compliance coefficient is higher than the upper limit of the preset critical qualified interval, taking the initial impedance performance compliance coefficient as the final impedance performance compliance coefficient.

[0088] Through the above steps, the test layer in the critical state can be evaluated individually, the critical layer is subjected to stricter discrimination standards, and a final quantitative compliance coefficient that can truly reflect the electrical performance quality is output.

[0089] It should be noted that when the initial impedance performance compliance coefficient is higher than the upper limit of the critical interval, it is directly output, which takes into account that the high-quality layer has stable process performance and sufficient quality margin. At this time, if the layer-specific correction is continued to be introduced, the evaluation standard may be too strict, causing unnecessary process adjustment, which in turn affects production efficiency and cost control. The design prioritizes the rapid passing of high-quality products, concentrates quality management resources on critical and unqualified situations that really need intervention, and optimizes the efficiency of quality control.

[0090] Further, considering that the production of an HDI circuit board is a continuous process, the evolution of its impedance performance contains process states. The static data of a single test layer can only reflect the instantaneous quality, but cannot reveal the potential systemic risks caused by equipment wear, material batch changes or process parameter drift.

[0091] And if it is limited to the qualified or unqualified determination of a single board or a single batch, it lacks deep mining of cross-production cycle and continuous multi-layer data. On the one hand, it cannot identify slow-growing implicit trends, which are often discovered when problems accumulate to cause batch defects. On the other hand, it cannot distinguish between random normal fluctuations of parameters and systemic abnormal fluctuations indicating process out-of-control, thus causing false positives or false negatives.

[0092] Based on this, referring to FIG. 1, the embodiment of the present application performs deviation time series analysis by the following steps to realize early warning and forward-looking control of quality degradation, and the steps specifically include: Figure 5 C1, storing impedance deviation parameter sets of each cumulative test layer in chronological order to generate an impedance deviation parameter time sequence.

[0093] C2, extracting impedance deviation parameter sets in a continuous time interval through a preset sliding window, calculating the moving average and standard deviation of each impedance deviation parameter in each window, and generating a moving average time sequence and a standard deviation time sequence of each impedance deviation parameter.

[0094] Among them, the preset sliding window contains at least 3 complete production cycle data, which can be set to cover 5-10 continuous production cycle data by default, and for the new product introduction stage, a shorter initial window needs to be set, such as 3-5 cycles.

[0095] C3, the moving average time series of each impedance deviation parameter is calculated by the exponential weighted moving average algorithm, the long-term trend component of each impedance deviation parameter is output, and the gradient value of the standard deviation corresponding to each impedance deviation parameter is calculated by linear regression.

[0096] Among them, the exponential weighted moving average algorithm and linear regression calculation are common existing calculation algorithms, and the formula is not shown.

[0097] C4, for each impedance deviation parameter, divide the gradient value by the average of the long-term trend component to obtain the volatility coefficient index, and calculate the change rate of the trend component between adjacent windows as the growth trend index.

[0098] C5, the growth trend index and the volatility coefficient index of each impedance deviation parameter are taken as the impedance deviation trend analysis result.

[0099] The embodiment of the application can simultaneously capture the systematic drift and random divergence of the impedance deviation by calculating the growth trend index and the volatility coefficient index, thereby realizing more comprehensive monitoring of the process state.

[0100] The impedance state determination module determines the impedance performance abnormality based on the impedance performance compliance coefficient and the impedance deviation trend analysis result through a preset determination rule.

[0101] Since the production of the HDI circuit board is a dynamic process, the qualified determination of the impedance performance not only needs to be based on the instantaneous state of the current test layer, but also needs to be forward-looking, and can identify the trend abnormal state which is temporarily qualified but is in a continuous deterioration trend. That is, the judgment rule should be able to distinguish between random fluctuations and early signals of systematic deterioration, so as to realize early warning and prevent trouble in advance.

[0102] For the case where the measured value is in a critical state, simple qualified or unqualified determination is too arbitrary. If it is determined to be qualified, the brewing process risk may be ignored. If it is determined to be unqualified, the production may be interrupted due to excessive reaction to instantaneous fluctuations, affecting efficiency.

[0103] Based on this, please refer to Figure 6 The embodiment of the application determines the impedance performance abnormality through the following multi-layer preset determination rule: D1, compare the impedance performance compliance coefficient of the current test layer with the preset qualified compliance coefficient. If the impedance performance compliance coefficient is greater than or equal to the qualified compliance coefficient, it is directly determined that the impedance performance of the current test layer does not exist.

[0104] D2, if the impedance performance compliance coefficient is less than the qualified compliance coefficient, but its value is within a preset critical qualified interval, the system starts trend analysis to determine whether to trigger any of the following conditions: Condition 1: the growth trend index of any impedance deviation parameter in a sequence formed by consecutive number of production cycles has consistent change direction and monotonically increasing change rate.

[0105] Condition 2: the fluctuation coefficient index of any impedance deviation parameter in a sequence formed by consecutive number of production cycles has first-order difference always positive and second-order difference greater than zero.

[0106] In one specific embodiment, the specific number of consecutive production cycles is a fixed integer not less than two.

[0107] D3, if any of conditions 1 or 2 is triggered, it is determined that the current test layer impedance performance is abnormal. If none of them is triggered, it is determined that there is no abnormality.

[0108] D4, if the impedance performance compliance coefficient is lower than the lower limit value of the critical qualified interval, it is directly determined that the current test layer impedance performance is abnormal.

[0109] In one specific embodiment, the qualified compliance coefficient and the aforementioned preset critical qualified interval can be manually input by HDI circuit board production related calculation personnel as a value between 0 and 1, to better fit the impedance performance determination requirements of the actual HDI circuit board application scenario.

[0110] This determination rule establishes a three-level determination mode of qualified, critical observation and abnormal by introducing critical interval and dynamic trend analysis, significantly improves the prediction ability and scientificity of the determination of potential quality risk, and also realizes the transformation from post-determination to pre-warning.

[0111] The adjustment trigger marker module triggers the process adjustment prompt instruction of the next production layer when it is determined to be abnormal, and performs an adjustment marker.

[0112] The test report output module collects and calculates the impedance performance compliance coefficients of subsequent test layers, and generates a final test report in combination with the adjustment marker.

[0113] Since the overall quality of the HDI circuit board depends on the collective performance of all circuit layers, a comprehensive test report needs to be generated after all layers are tested. This report not only visually presents the impedance performance level of the entire board, but also traces the distribution of performance problems, providing accurate data support and decision basis for process improvement.

[0114] Traditional test reports usually only provide simple conclusions of pass or fail, or list a large amount of raw data, lacking deep data integration and intuitive quality portraits. This makes it difficult for production personnel to quickly assess the overall quality level of the product, unable to effectively identify whether it is an occasional single-layer problem or a systemic process out of control, and also difficult to quantitatively evaluate the actual effect of the process adjustment measures already implemented.

[0115] Based on this, the embodiment of the present application generates a final test report by the following steps: E1, combining the impedance performance compliance coefficients of all test layers to form an impedance performance distribution map of the whole board.

[0116] E2, based on the impedance performance compliance coefficient size of each test layer and its conclusion in the judgment link, it is accurately marked as one of the following four categories: qualified layer: the impedance performance compliance coefficient is greater than or equal to the qualified compliance coefficient.

[0117] Critical layer: the impedance performance compliance coefficient is in the critical qualified interval, and is not judged as abnormal.

[0118] Abnormal layer: the impedance performance is judged as abnormal.

[0119] Serious abnormal layer: on the basis of the abnormal layer, the layer with adjustment mark is added. This mark means that the system has triggered process adjustment due to its abnormality, indicating that there is a confirmed process problem that needs to be focused on here.

[0120] E3, the number of each type of state layer is counted, and their respective proportions in the total number of test layers are calculated. At the same time, the proportion of the number of serious abnormal layers to the total number of abnormal layers is calculated, which reflects the severity of abnormal problems.

[0121] E4, based on the proportion, an overall board impedance performance score is calculated through a pre-set scoring algorithm, which can comprehensively reflect the overall quality of the board.

[0122] Since the overall board impedance performance score needs to intuitively reflect the comprehensive impedance quality state of the entire HDI circuit board after all layers are tested. If only the average value of the compliance coefficients of all test layers is simply calculated, the impact of local serious problems on the overall reliability of the board will be severely diluted. For example, an HDI circuit board with a few abnormal layers may have its overall performance averaged to an apparently acceptable score by a large number of normal layers, which masks its high risk of failure. Therefore, the score needs to scientifically integrate the statistical proportion of each layer state, and has enough differentiated treatment for abnormalities, especially serious abnormalities.

[0123] Based on this, the embodiment of the present application calculates the whole-board impedance performance score by the following three conditions of the differentiated preset scoring rules: the first condition: if the proportion of abnormal layers in the test layer and the proportion of serious abnormal layers in the abnormal layers exceed a preset first proportion threshold, the whole-board impedance performance score is output as a default minimum score, for example, 0.

[0124] The second condition: if the proportion of abnormal layers is greater than or equal to a preset second proportion threshold but does not exceed the preset first proportion threshold, the complement of the proportion of test layers is taken as a reference score, and the complement of the proportion of the number of serious abnormal layers to the number of abnormal layers is multiplied by the reference score to output the final whole-board impedance performance score.

[0125] The third condition: if the proportion of abnormal layers is lower than the preset second proportion threshold, the weighted sum of the proportion of qualified layers, the proportion of critical layers and the proportion of abnormal layers is taken as the final whole-board impedance performance score.

[0126] In one specific embodiment, the first proportion threshold and the second proportion threshold are set based on the statistical process control principle and engineering experience: the first proportion threshold is recommended to be set to 50%, which is used as a critical point of the out-of-control production quality of the HDI circuit board. When the proportion of abnormal layers exceeds this threshold, it indicates that the process has systematic deviation. The second proportion threshold is recommended to be set to one-third, which is used as an early warning line for the deterioration of process stability based on the one-third principle in quality management.

[0127] In another specific embodiment, the weighted calculation of each proportion is linear weighted calculation, the formula is not shown, and when the proportion of abnormal layers is low, the weight settings of the proportion of qualified layers, the proportion of critical layers and the proportion of abnormal layers are based on the scoring orientation of mainly encouraging and secondarily warning, that is, the qualified layers are given the highest weight of 0.6 to fully affirm their core contribution to the whole-board quality, the critical layers are given a medium weight of 0.3 to acknowledge their basic standard state and reflect the quality gap between them and the completely qualified layers through the weight difference, and the abnormal layers are given a small weight of 0.1 to make them have a moderate negative impact on the total score and avoid the distortion of the score caused by the small number of abnormal layers.

[0128] E5, the whole-board impedance performance score and the impedance performance distribution are packaged and output as a final test report.

[0129] Please refer to Figure 2 As shown in the figure, the present application provides an intelligent test method for the impedance performance of an HDI circuit board, which comprises: after the compression of any independent circuit layer and its medium layer, marking the circuit layer as the current test layer, and starting the preset POFV test structure of the test layer to collect the impedance data after alignment.

[0130] The impedance data is processed to generate a set of impedance deviation parameters, an impedance performance compliance coefficient is calculated based on the set of impedance deviation parameters, and an impedance deviation trend analysis result is output through a deviation time series analysis.

[0131] Based on the impedance performance compliance coefficient and the impedance deviation trend analysis result, an impedance performance abnormality determination is made through a preset determination rule.

[0132] When an abnormality is determined, a process adjustment prompt instruction for the next production layer is triggered, and an adjustment mark is made.

[0133] Impedance performance compliance coefficients of subsequent test layers are collected and calculated, and a final test report is generated in combination with the adjustment mark.

[0134] The above is merely an example and description of the present application, and those skilled in the art can make various modifications or supplements to the described specific embodiments or replace them with similar ways, as long as they do not deviate from the concept of the present application or exceed the scope defined by the present application, which shall fall within the protection scope of the present application.

Claims

1. An intelligent testing system for the impedance performance of HDI circuit boards, characterized in that, The system includes: The interlayer data acquisition module, after completing the lamination of any independent line layer and its dielectric layer, marks the line layer as the current test layer, starts the preset POFV test structure of the test layer for alignment, and then acquires its impedance data. The diagnostic prediction module processes the impedance data to generate an impedance deviation parameter set, calculates the impedance performance compliance coefficient based on the impedance deviation parameter set, and outputs the impedance deviation trend analysis results through deviation time series analysis, which includes: Store the impedance deviation parameter set of each cumulative test layer in chronological order of production time to generate a timing sequence of impedance deviation parameters. The impedance deviation parameter set of continuous time intervals is extracted by a preset sliding window, the moving average and standard deviation of each impedance deviation parameter in each window are calculated, and the moving average time series and standard deviation time series of each impedance deviation parameter are generated. The moving average time series of each impedance deviation parameter is calculated using the exponentially weighted moving average algorithm, and the long-term trend component of each impedance deviation parameter is output. The gradient value of the standard deviation corresponding to each impedance deviation parameter is calculated by linear regression. For each impedance deviation parameter, its gradient value is divided by the mean of the long-term trend component to obtain the fluctuation coefficient index, and the rate of change of the trend component between adjacent windows is calculated as the growth trend index. The growth trend index and fluctuation coefficient index of each impedance deviation parameter are used as the results of impedance deviation trend analysis. The impedance status determination module determines impedance performance anomalies based on the impedance performance compliance coefficient and the impedance deviation trend analysis results, using preset determination rules. Adjust the trigger flag module. When an anomaly is detected, trigger the process adjustment prompt instruction for the next production layer and perform an adjustment flag. The test report output module collects and calculates the impedance performance compliance coefficient of each subsequent test layer, and generates the final test report in conjunction with the adjustment marks.

2. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 1, characterized in that: The alignment process includes: Acquire optical images of the current test layer surface, identify and extract the position coordinates of the POFV test structure; The location coordinates are matched with preset theoretical coordinates to drive the positioning platform to perform preliminary positioning; After initial positioning is completed, a probe signal is applied to the test structure through a probe array, and the phase angle change of the probe signal is monitored simultaneously. When the detected phase angle change is within the preset range, it is determined that the probe array and the conductive surface of the test structure have reached an electrical alignment state. If the phase angle change is not within the preset range, a preset compensation scheme is matched according to the direction and magnitude of the phase deviation, and the positioning platform is controlled to perform alignment adjustment until the phase angle change is within the preset range.

3. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 1, characterized in that: The process of generating the impedance deviation parameter set includes: The impedance data is filtered to obtain an effective impedance dataset; The impedance characteristic parameters of each test point are extracted from the obtained effective impedance dataset. The impedance characteristic parameters include the impedance amplitude sequence and the phase angle distribution. Obtain the average impedance amplitude of the current test layer and the previous test layer at the same test point, and calculate their relative change rate to obtain the relative change rate of interlayer impedance amplitude; Calculate the standard deviation of the impedance amplitude corresponding to each test point in the current test layer, which is used as the impedance spatial distribution non-uniformity. Based on the phase angle measurements at different frequency points, the gradient of phase angle change with frequency is obtained through linear fitting, and the sum of squared residuals between each measurement value and the gradient is calculated as an index of phase linearity. Based on the relative rate of change of interlayer impedance amplitude, impedance spatial non-uniformity, phase angle gradient with frequency, and phase linearity index, an impedance deviation parameter set is generated.

4. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 1, characterized in that: The calculated impedance performance compliance factor includes: All parameters in the impedance deviation parameter set are normalized to obtain the normalized parameter index. The weighted sum of the normalized parameters is used as the initial impedance performance compliance coefficient. If the initial impedance performance compliance coefficient is located in the preset critical qualified range or is lower than the lower limit of the range, then the layer influence factor is set based on the current test layer position; The initial impedance performance compliance coefficient is corrected by the stratification influence factor, and the correction result is used as the final impedance performance compliance coefficient. If the initial impedance performance compliance coefficient is higher than the upper limit of the preset critical qualified range, the initial impedance performance compliance coefficient shall be used as the final impedance performance compliance coefficient.

5. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 4, characterized in that: The setting of the stratification influence factor includes: Import the design file of the current HDI circuit board, extract the geometric outline and level identifier of each network in the current test layer, and calculate the actual wiring area of ​​each network in the current test layer. Based on the grade identifier, the ratio of the total actual cabling area of ​​each grade network to the total cabling area of ​​the current test layer is calculated to obtain the network proportion of each grade network, and the linear weighted sum of the network proportions of each grade network is used as the signal strength influence factor. Obtain the dielectric thickness measurement between the current test layer and the adjacent layer, as well as the actual distance between the current test layer and the nearest power layer or ground layer; The location influence factor is calculated by combining the measured values ​​of the medium thickness and the actual distance. The product of the signal strength influence factor and the location influence factor is output as the final stratification influence factor.

6. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 1, characterized in that: The preset judgment rule includes the following: Compare the current impedance performance compliance coefficient of the test layer with the preset compliance coefficient; If the impedance performance compliance coefficient is greater than or equal to the qualified compliance coefficient, then it is determined that the impedance performance of the current test layer is not abnormal. If the impedance performance compliance coefficient is less than the qualified compliance coefficient but is within the preset critical qualified range, then determine whether any of the following conditions are triggered: Condition 1: The growth trend index of any impedance deviation parameter forms a sequence over several consecutive production cycles, and the direction of change is consistent and the rate of change is monotonically increasing. Condition 2: The first-order difference of the fluctuation coefficient index of any impedance deviation parameter in a series formed over several consecutive production cycles is always positive and the second-order difference is greater than zero. If condition 1 or condition 2 is triggered, it is determined that the impedance performance of the current test layer is abnormal; if neither condition is triggered, it is determined that the impedance performance of the current test layer is not abnormal. If the impedance performance compliance coefficient is lower than the lower limit of the critical qualified range, it is determined that the impedance performance of the current test layer is abnormal.

7. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 6, characterized in that: The process of generating the final test report includes: By combining the impedance performance compliance coefficients of all test layers, the impedance performance distribution is obtained; Based on the magnitude of the impedance performance compliance coefficient and the impedance performance abnormality judgment conditions, the test layer is marked as one of the qualified layer, critical layer or abnormal layer, and the abnormal layer with adjustment mark is marked as a serious abnormal layer. Calculate the number of qualified layers, critical layers, and abnormal layers, and their respective proportions to the total number of tested layers; also calculate the proportion of severely abnormal layers to the total number of abnormal layers. The overall board impedance performance score is calculated based on all statistical proportions. The overall impedance performance score and impedance performance distribution are packaged and output as the final test report.

8. The intelligent testing system for impedance performance of HDI circuit boards as described in claim 7, characterized in that: The calculation of the overall board impedance performance score includes: If the proportion of abnormal layers in the test layer and the proportion of severely abnormal layers in the abnormal layers exceed the preset first proportion threshold, the output board impedance performance score will be the default lowest score. If the proportion of abnormal layers is greater than or equal to the preset second proportion threshold but does not exceed the preset first proportion threshold, the complement of the test layer proportion is taken as the benchmark score, and the complement of the ratio of the number of severely abnormal layers to the number of abnormal layers is multiplied by the benchmark score to output the final overall board impedance performance score. If the proportion of abnormal layers is lower than the preset second proportion threshold, the weighted sum of the proportion of qualified layers, the proportion of critical layers, and the proportion of abnormal layers will be used as the final overall board impedance performance score.

9. A smart testing method for the impedance performance of HDI circuit boards, characterized in that: The method includes: After completing the lamination of any independent line layer and its dielectric layer, mark the line layer as the current test layer, start the preset POFV test structure of the test layer for alignment, and then collect its impedance data. The impedance data is processed to generate an impedance deviation parameter set. The impedance performance compliance coefficient is calculated based on the impedance deviation parameter set, and the impedance deviation trend analysis results are output through deviation time series analysis. The deviation time series analysis includes: storing the impedance deviation parameter set of each cumulative test layer in production time order to generate an impedance deviation parameter time series; extracting the impedance deviation parameter set of continuous time intervals through a preset sliding window, calculating the moving average and standard deviation of each impedance deviation parameter within each window, and generating a time series of moving averages and standard deviations for each impedance deviation parameter; calculating the time series of moving averages for each impedance deviation parameter using an exponentially weighted moving average algorithm, outputting the long-term trend component of each impedance deviation parameter, and calculating the gradient value of the corresponding standard deviation for each impedance deviation parameter through linear regression; for each impedance deviation parameter, dividing its gradient value by the mean of the long-term trend component to obtain a fluctuation coefficient index, and calculating the rate of change of the trend component between adjacent windows as a growth trend index; and using the growth trend index and fluctuation coefficient index of each impedance deviation parameter as the impedance deviation trend analysis result. Based on the impedance performance compliance coefficient and the impedance deviation trend analysis results, an impedance performance anomaly is determined by a preset judgment rule. When an anomaly is determined, a process adjustment prompt instruction is triggered for the next production layer, and an adjustment mark is made. The impedance performance compliance coefficients of each subsequent test layer are collected and calculated, and the final test report is generated in conjunction with the adjustment marks.

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