A wireline controller system and method

Abstract

The application belongs to the technical field of pay-off control, and specifically discloses a pay-off control system and a control method. The system comprises a master control module, wherein the master control module is electrically connected with a pressure sensor, an inclination sensor, a hydraulic control module and a lock control module. The master control module generates a control instruction based on pressure and inclination data collected by the pressure sensor and the inclination sensor in real time. The hydraulic control module is used for controlling the actions of a main hydraulic cylinder and an auxiliary hydraulic cylinder in the pay-off based on the control instruction generated by the master control module, so as to adjust the arm opening range and the overall inclination of the pay-off. The lock control module is used for controlling the opening and closing of the protection lock of each guide groove pulley in the pay-off based on the control instruction generated by the master control module. The application can improve the control precision, stability and safety of the pay-off.

Description

Technical Field

[0001] This application belongs to the field of wire feeder control technology, specifically relating to a wire feeder control system and control method. Background Technology

[0002] Currently, existing wire-laying control systems have significant shortcomings in complex construction environments. For example, their sensor signals are easily interfered with in complex construction environments, leading to inaccurate measurements. The clock, power supply, and storage architecture of the core control unit have poor reliability, making it difficult to ensure stable operation and fault tracing. At the same time, the hydraulic drive module has a slow dynamic response and lacks a hardware-level fast protection mechanism. Furthermore, the status feedback of the safety lock control system is uncertain due to mechanical vibration and electrical noise, which to some extent restricts the accuracy, efficiency, and safety of wire-laying operations. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the purpose of this application is to provide a wire feeder control system and control method, which aims to improve the control accuracy, stability and safety of the wire feeder.

[0004] To achieve the above objectives, this application provides the following technical solution:

[0005] A wire-feeding device control system includes: a main control module electrically connected to a pressure sensor, an inclination sensor, a hydraulic control module, and a locking control module; wherein the main control module generates control commands based on pressure and inclination data collected in real time by the pressure sensor and the inclination sensor; the hydraulic control module controls the movement of the main hydraulic cylinder and the auxiliary hydraulic cylinder in the wire-feeding device based on the control commands generated by the main control module, so as to adjust the arm extension amplitude and overall inclination angle of the wire-feeding device; and the locking control module controls the opening and closing of the protective locks of each guide pulley in the wire-feeding device based on the control commands generated by the main control module.

[0006] Optionally, the control module includes: a main control chip, which is electrically connected to a clock unit, an analog signal processing unit, a storage unit, and a reset unit; wherein, the clock unit is used to provide a stable and accurate clock signal to the main control chip to ensure the time base for its internal logic and instruction execution; the analog signal processing unit is used to receive and condition the analog signals collected from the pressure sensor and tilt sensor, and convert them into digital signals for the main control chip to analyze and process; the storage unit is used to store the processed data of the main control chip; and the reset unit is used to generate a reset signal to reset the main control chip.

[0007] Optionally, the analog signal processing unit includes: an input interface circuit, an amplification circuit, and a filtering circuit; wherein, the input interface circuit is used to receive pressure sensing signals and tilt sensing signals and perform preprocessing; the amplification circuit is used to amplify the preprocessed pressure sensing signals and tilt sensing signals; and the filtering circuit is used to filter the amplified pressure sensing signals and tilt sensing signals.

[0008] Optionally, the input interface circuit includes: an input connector, a PTC resettable fuse, a first resistor, and a first dual-channel analog switch; wherein, the ground pin GND of the input connector is connected to the first ground terminal, and the signal pin, while connecting to the pressure sensor and the tilt sensor, is connected in series with the PTC resettable fuse and the first resistor, and then connected to the first normally closed terminal of the first dual-channel analog switch to form a first node; the input interface circuit also includes a TVS diode, a first capacitor, a second resistor, and a first reference voltage source, wherein the first end of the TVS diode is connected to the first node, and the second end is connected to the second ground terminal; the first end of the first capacitor is connected to the first node, and the second end is connected to the third ground terminal; the power input pin of the first reference voltage source is connected to a +5V power supply, the ground pin is connected to the fourth ground terminal, and the output pin is connected to the second normally closed terminal of the first dual-channel analog switch through the second resistor; the common output terminal of the first dual-channel analog switch is connected to the input terminal of the amplifier circuit.

[0009] Optionally, the amplification circuit includes: a programmable amplifier, a digital potentiometer, a voltage buffer, a digital-to-analog converter, a second reference voltage source, a second capacitor, and a third capacitor; wherein, the non-inverting input terminal of the programmable amplifier serves as the input terminal of the amplification circuit, used to receive analog signals from the pressure sensor and tilt sensor input via the input interface circuit, and the inverting input terminal of the programmable amplifier is grounded through a calibration network; the first gain setting pin and the second gain setting pin of the programmable amplifier are both connected to the output terminal of the digital potentiometer; the reference pin of the programmable amplifier is connected to the output terminal of the digital-to-analog converter through the voltage buffer, the positive power supply pin of the programmable amplifier is connected to a +12V isolated power supply, the negative power supply pin is connected to a -12V isolated power supply, and the output pin is connected to the input terminal of the filter circuit.

[0010] Optionally, the filtering circuit includes: an operational amplifier, a fourth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an ADC; wherein, the non-inverting input of the operational amplifier serves as the input of the filtering circuit, and is connected to the output of the programmable amplifier in sequence through the third resistor and a pre-amplifier RC passive filter network. The pre-amplifier RC passive filter network includes the fourth capacitor and the fourth resistor, wherein the first end of the fourth resistor is connected to the connection point between the third resistor and the non-inverting input of the operational amplifier, and the second end is connected to the ninth ground terminal through the fourth capacitor; the inverting input of the operational amplifier is connected to its output terminal through the fifth resistor, and the output terminal of the operational amplifier is connected to the non-inverting input of the voltage follower, and the inverting input of the voltage follower is connected to its output terminal; the output of the voltage follower is divided into three paths, wherein the first path is connected to the analog input pin of the ADC; the second path is connected to the normally open terminal of the second dual-channel analog switch through the sixth resistor, forming an output signal readback path; and the third path is connected to the auxiliary ADC channel of the main control chip for cross-validation.

[0011] Optionally, the hydraulic control module includes: an electro-hydraulic proportional valve drive circuit, a first power management circuit, and a fault protection circuit; wherein, the electro-hydraulic proportional valve drive circuit is used to receive control commands from the main control module and output precise and controllable power current to regulate the hydraulic flow and pressure of the main hydraulic cylinder and auxiliary hydraulic cylinder in the wire feeder; the fault protection circuit is used to monitor key parameters in real time to prevent damage to the electro-hydraulic proportional valve drive circuit; the first power management circuit is used to convert external input power to provide stable voltage for the electro-hydraulic proportional valve drive circuit and the fault protection circuit.

[0012] Optionally, the electro-hydraulic proportional valve drive circuit includes: an electro-hydraulic proportional valve drive chip, a first power MOSFET, a second power MOSFET, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a seventh capacitor, an eighth capacitor, a first optocoupler, and a second optocoupler; wherein, the power input pin of the electro-hydraulic proportional valve drive chip is connected to a 24V power supply, and is also connected to the twelfth ground terminal through the seventh and eighth capacitors connected in parallel; the sleep mode control pin of the electro-hydraulic proportional valve drive chip is connected to a 3.3V power supply through the thirteenth resistor; the first output pin of the electro-hydraulic proportional valve drive chip is connected to the gate of the first power MOSFET through the fifteenth resistor, and the first power MOSFET... The drain of the electro-hydraulic proportional valve driver chip is connected to a 24V power supply, and the source is connected to the positive terminal of the electro-hydraulic proportional valve coil. The second output pin of the electro-hydraulic proportional valve driver chip is connected to the gate of the second power MOSFET via the fourteenth resistor. The drain of the second power MOSFET is connected to a 24V power supply, and the source is connected to the negative terminal of the electro-hydraulic proportional valve coil. The second digital logic input pin of the electro-hydraulic proportional valve driver chip is connected to the collector of the first optocoupler. The emitter of the first optocoupler is connected to the fifteenth ground terminal. The anode of the first optocoupler is connected to the first PWM pin of the main control chip via the seventeenth resistor, and the cathode of the first optocoupler is connected to the sixteenth ground terminal. The first digital logic input pin of the actuator chip is connected to the collector of the second optocoupler, the emitter of the second optocoupler is connected to the seventeenth ground terminal, the anode of the second optocoupler is connected to the second PWM pin of the main control chip through the eighteenth resistor, and the cathode of the second optocoupler is connected to the eighteenth ground terminal; the fault status indication pin of the electro-hydraulic proportional valve drive chip is connected to a 3.3V power supply through the nineteenth resistor, and is also connected to the fifth GPIO pin of the main control chip; the fault protection circuit includes: a current detection amplifier, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a first comparator, a second comparator, and a... The system consists of three comparators, a fourth comparator, an OR gate logic chip, an SR latch, and a fourth power MOSFET. The first terminal of the twenty-second resistor is connected to a 24V power supply, and the second terminal is connected to the power input pin of the electro-hydraulic proportional valve driver chip. A current-sense amplifier is connected across the twenty-second resistor, and its output is simultaneously connected to the non-inverting input of the first comparator and the inverting input of the second comparator. The inverting input of the first comparator is connected to the first upper threshold voltage generated by the reference power supply. The non-inverting input of the second comparator is connected to the first lower threshold voltage generated by the reference power supply. The first terminal of the twenty-third resistor is connected to 3V.A 3V power supply is connected in series with the 24th resistor and then to the 25th ground terminal. The connection point between the 23rd and 24th resistors outputs a temperature voltage signal, which is simultaneously connected to the non-inverting input of the 3rd comparator and the inverting input of the 4th comparator. The inverting input of the 3rd comparator is connected to the 2nd upper threshold voltage; the non-inverting input of the 4th comparator is connected to the 2nd lower threshold voltage. The outputs of the 1st, 2nd, 3rd, and 4th comparators are connected to the four input pins of an OR gate logic chip. The output pin of the OR gate logic chip is connected to the set pin of the SR latch. The output of the SR latch is connected to the gate of the 4th power MOSFET through the 25th resistor. The drain of the 4th power MOSFET is connected to the power input pin of the electro-hydraulic proportional valve driver chip, and the source of the 4th power MOSFET is connected to a 24V power supply.

[0013] Optionally, the lock control module includes a second power management circuit, which includes a DC-DC step-down chip and an LDO voltage regulator chip. The DC-DC step-down chip and the LDO voltage regulator chip are electrically connected to a first CAN FD transceiver, a second CAN FD transceiver, a microcontroller, a lock drive circuit, and a status feedback circuit, respectively. The DC-DC step-down chip converts the input 24V power supply to 5V, which is then regulated to 3.3V by the LDO voltage regulator chip.

[0014] This application also provides a wire feeder control method, the method comprising: real-time acquisition of pressure data and tilt angle data of the wire feeder; generating control commands based on the pressure data and tilt angle data; controlling the hydraulic actuator of the wire feeder according to the control commands to adjust the arm amplitude and overall tilt angle of the wire feeder; and controlling the opening and closing of the guide pulley protection lock of the wire feeder according to the control commands.

[0015] Compared with the prior art, the beneficial effects of this application are as follows:

[0016] This application constructs a high-precision sensor signal conditioning, redundant and reliable main control timing and storage architecture, an electro-hydraulic proportional valve drive with hardware-level fast protection, and an intelligent locking control system based on CAN FD communication and anti-interference status feedback. It can achieve precise, stable, and adaptive control of the boom amplitude and overall tilt angle of the wire feeder under complex working conditions. At the same time, it can improve the response speed, operational reliability, and fault self-protection capability of the control system, and overcome the bottlenecks of traditional control systems in terms of accuracy, reliability, and safety. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of the main control module provided in one embodiment of this application;

[0018] Figure 2This is a schematic diagram of the circuit structure of the input interface circuit provided in another embodiment of this application;

[0019] Figure 3 This is a schematic diagram of the circuit structure of an amplifier circuit provided in another embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the circuit structure of a filter circuit provided in another embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the circuit structure of a reset unit provided in another embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the circuit structure of an electro-hydraulic proportional valve drive circuit provided in another embodiment of this application;

[0023] Figure 7 This is a schematic diagram of the circuit structure of the first power management circuit provided in another embodiment of this application;

[0024] Figure 8 This is a schematic diagram of the circuit structure of a fault protection circuit provided in another embodiment of this application;

[0025] Figure 9 This is a schematic diagram showing the connection between a first CAN FD transceiver and a second CAN FD transceiver provided in another embodiment of this application;

[0026] Figure 10 This is a schematic diagram of the circuit structure of a lock driving circuit provided in another embodiment of this application;

[0027] Figure 11 This is a schematic diagram of the circuit structure of a state feedback circuit provided in another embodiment of this application. Detailed Implementation

[0028] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings. To facilitate understanding of the embodiments of this application, further explanations and descriptions will be provided below using specific embodiments as examples, and the accompanying drawings do not constitute a limitation on the embodiments of this application.

[0029] Figure 1This is a schematic diagram of the overall structure of a wire-feeding device control system according to an embodiment of this application. The main structure of the wire-feeding device consists of a retractable support frame, including a main hydraulic cylinder and its driven symmetrical double arms. The vertical extension and retraction of the cylinders allow for adjustment of the opening of the wire-feeding nozzle. A guide pulley assembly (usually divided into left, middle, and right sections) is installed at the top of the arms. Each pulley is equipped with an independent protective lock device to lock the pulley in the non-working state for safety. Furthermore, the wire-feeding device is connected to a base via an auxiliary hydraulic cylinder. The auxiliary hydraulic cylinder adjusts the overall tilt angle of the wire-feeding device. The base integrates a pressure sensor and an omnidirectional deflection angle sensor to monitor the load-bearing capacity and attitude in real time. The main hydraulic cylinder, auxiliary hydraulic cylinder, and base are all controlled by the control system. The wire-feeding device control system is used to control the wire-feeding operation of the wire-feeding device, such as... Figure 1 As shown, the control system includes: a main control module, which is electrically connected to a pressure sensor, an inclination sensor, a hydraulic control module, and a locking control module. The main control module generates control commands based on the pressure and inclination data collected in real time by the pressure sensor and the inclination sensor. The hydraulic control module controls the movement of the main hydraulic cylinder and the auxiliary hydraulic cylinder in the wire feeder based on the control commands generated by the main control module, so as to adjust the arm extension amplitude and overall inclination angle of the wire feeder. The locking control module controls the opening and closing of the protective locks of each guide pulley in the wire feeder based on the control commands.

[0030] In another exemplary embodiment, the main control module includes: a main control chip U1 (e.g., an STM32H743VIT6), the main control chip U1 being electrically connected to a clock unit, an analog signal processing unit, a storage unit, and a reset unit. The clock unit provides a stable and accurate clock signal to the main control chip U1, ensuring the time base for its internal logic and instruction execution. The analog signal processing unit receives and conditions analog signals collected from pressure and tilt sensors, converting them into digital signals for analysis and processing by the main control chip U1. The storage unit stores the processed data of the main control chip U1. The reset unit generates a reset signal to reset the main control chip U1.

[0031] In this embodiment, the main control module, as the core of the wire feeder control system, can control the clock unit, reset unit, storage unit, and analog signal processing unit. The main control module precisely adjusts the pressure and tilt signals from the sensors through the analog signal processing unit, provides a stable timing reference through the clock unit, realizes fast startup, real-time data caching and long-term operation recording through the storage unit, and ensures reliable system initialization and abnormal recovery through the reset unit. Thus, it can ensure that the wire feeder has a comprehensive capability of high-precision control, fast response and reliable operation under complex working conditions.

[0032] In another exemplary embodiment, the analog signal processing unit includes an input interface circuit, an amplification circuit, and a filtering circuit, wherein the input interface circuit is used to receive and preprocess pressure sensing signals and tilt sensing signals; the amplification circuit is used to amplify the preprocessed pressure sensing signals and tilt sensing signals; and the filtering circuit is used to filter the amplified pressure sensing signals and tilt sensing signals.

[0033] In another exemplary embodiment, such as Figure 2 As shown, the input interface circuit includes an input connector J1, a PTC resettable fuse R_PROTECT, a first resistor R1, and a first dual-channel analog switch U2. The power supply pin Vcc of the input connector J1 is connected to a +5V power supply, and the ground pin GND is connected to the first ground terminal GND1. The signal pin Signal, while connecting the pressure sensor and the tilt sensor, is connected in series with the PTC resettable fuse R_PROTECT and the first resistor R1, and then connected to the first normally closed terminal NC1 of the first dual-channel analog switch U2 (such as ADG5433) to form the first node N1. The input interface circuit also includes a TVS diode TVS1, a first... The circuit consists of a capacitor C1, a second resistor R2, and a first reference voltage source U3 (e.g., a REF5025). The first terminal of the TVS transistor TVS1 is connected to the first node N1, and the second terminal is connected to the second ground terminal GND2. The first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal is connected to the third ground terminal GND3. The power input pin VIN of the first reference voltage source U3 is connected to a +5V power supply, the ground pin GND is connected to the fourth ground terminal GND4, and the output pin VOUT is connected to the second normally closed terminal NC2 of the first dual-channel analog switch U2 via the second resistor R2. The common output terminal COM1 of the first dual-channel analog switch U2 is connected to the input terminal of the amplifier circuit.

[0034] In this embodiment, the input interface circuit serves as the primary channel for sensor signals to enter the control system. It connects to analog pressure and tilt signals acquired from pressure and tilt sensors via input connector J1. These signals then pass through a current-limiting and overcurrent protection link composed of a PTC resettable fuse R_PROTECT and a first resistor R1 to prevent large current surges from impacting subsequent circuits due to sensor-side anomalies or field interference. When the analog signal passes through the first node N1, transient voltage suppression and surge voltage clamping are provided by the TVS diode TVS1. Simultaneously, the first capacitor C1 filters the analog signal for high-frequency noise to improve signal stability. Furthermore, the first reference voltage source U3 outputs a high-precision reference voltage, which is introduced to the second normally closed terminal NC2 of the first dual-channel analog switch U2 via the second resistor R2, providing an optional reference calibration signal for the control system. The first dual-channel analog switch U2 is responsible for switching and selecting among the multiple input analog signals, ultimately sending the selected analog signal to the subsequent amplifier circuit via the common output terminal COM1.

[0035] In summary, the input interface circuit, through the coordinated design of multi-level protection and signal conditioning mechanisms, can not only achieve reliable access and electrical isolation of sensor signals, but also enhance the anti-interference capability and long-term operational stability of the control system in complex electromagnetic environments, thereby laying the foundation for subsequent high-precision data acquisition and control decision-making.

[0036] In another exemplary embodiment, such as Figure 3 As shown, the amplifier circuit includes a programmable amplifier U4, a digital potentiometer U5, a voltage buffer U6, a digital-to-analog converter U7, a second reference voltage source U8, a second capacitor C2, and a third capacitor C3. The non-inverting input of the programmable amplifier U4 (e.g., using an AD8251) serves as the input of the amplifier circuit, receiving analog signals from the pressure sensor and tilt sensor via the input interface circuit. The inverting input of the programmable amplifier U4 is grounded through a calibration network. The first gain setting pin RG1 and the second gain setting pin RG2 of the programmable amplifier U4 are both connected to the output (wiper pin) of the digital potentiometer U5 (e.g., using an AD5272). The reference pin REF of the programmable amplifier U4 is connected to the output of the digital-to-analog converter U7 via the voltage buffer U6. The positive power supply pin V+ of the programmable amplifier U4 is connected to a +12V isolated power supply, and the negative power supply pin V- is connected to a -12V isolated power supply. The output pin of the programmable amplifier U4 is connected to the input of the filter circuit.

[0037] In this embodiment, the power supply pin VDD of the digital potentiometer U5 is connected to a 3.3V power supply, and the ground pin GND is connected to the fifth ground terminal GND5; the I of the digital potentiometer U5... 2 C interface (including SDA, SCL) via I2 The C bus connects to the corresponding pins of the main control chip U1 (e.g., the first GPIO pin GPIO1 and the second GPIO pin GPIO2).

[0038] The non-inverting input of voltage buffer U6 (e.g., AD8629) is connected to the output pin VOUT of digital-to-analog converter U7, the inverting input is shorted to its output, the output is connected to the reference pin REF of programmable amplifier U4, and the positive power supply pin V+ and the negative power supply pin V- are connected to the +5V and -5V power supplies, respectively.

[0039] The power supply pin VDD of the digital-to-analog converter U7 (e.g., AD5689R) is connected to the +5V power supply, and the ground pin GND is connected to the sixth ground terminal GND6. The SPI interface (e.g., SDIN, SCLK, SYNC) is connected to the corresponding pins of the main control chip U1 (e.g., SPI1_MOSI, SPI1_SCK, SPI1_CS) via the SPI bus. The reference voltage pin REFIN of the digital-to-analog converter U7 is connected to the output terminal VOUT of the second reference voltage source U8 (e.g., ADR4540). The power supply pin VIN of the second reference voltage source U8 is connected to the +5V power supply. The second capacitor C2 and the third capacitor C3 are connected in parallel. The first terminals of the second capacitor C2 and the third capacitor C3 are connected to the power supply pin VIN of the second reference voltage source U8, and the second terminals of the second capacitor C2 and the third capacitor C3 are connected to the ground pin GND of the reference voltage source U8.

[0040] In this embodiment, the calibration network includes an analog switch U_SW (e.g., ADG5412), a first precision resistor R_CAL1, and a second precision resistor R_CAL2. The ground terminal GND of the analog switch U_SW is connected to the eighth ground terminal GND8. The first common terminal COM1 of the analog switch U_SW is connected to the first terminal of the first precision resistor R_CAL1. The second common terminal COM2 of the analog switch U_SW is connected to the first terminal of the second precision resistor R_CAL2. The first control pin IN1 and the second control pin IN2 of the analog switch U_SW are respectively connected to the third GPIO pin GPIO3 and the fourth GPIO pin GPIO4 of the main control chip U1. The second terminals of the first precision resistor R_CAL1 and the second precision resistor R_CAL2 are connected to form a second node N2. The second node N2 is connected to the seventh ground terminal GND7 while being connected to the inverting input terminal of the programmable amplifier U4.

[0041] The working principle of the amplifier circuit is explained as follows:

[0042] The sensor analog signal, preprocessed by the input interface circuit, is first connected to the non-inverting input of the programmable amplifier U4. The inverting input of the programmable amplifier U4 is then grounded through a calibration network consisting of an analog switch U_SW and two precision resistors, R_CAL1 and R_CAL2. This calibration network is controlled by the GPIO of the main control chip U1 and can dynamically switch different calibration resistors for online zero-point or gain calibration. Simultaneously, the digital potentiometer U5 connects to the input via I... 2 The C-bus receives instructions from the master control chip U1, precisely adjusts the resistance value output by its Wiper pin, and applies it to the first gain setting pin RG1 and the second gain setting pin RG2 of the programmable amplifier U4. This allows for real-time and precise setting of the voltage gain of the programmable amplifier U4, enabling adaptive amplification of input signals of different amplitudes. To further optimize the accuracy and flexibility of signal conditioning, the digital-to-analog converter U7 (such as AD5689R) obtains digital instructions from the master control chip U1 via the SPI bus and outputs a high-precision reference voltage. This reference voltage undergoes impedance transformation and drive capability enhancement through a unity-gain buffer composed of voltage buffer U6 before being fed into the reference pin REF of the programmable amplifier U4. This allows for precise setting of the DC bias level of the programmable amplifier U4 output, ensuring that the amplified signal waveform is ideally positioned within the input range of the subsequent ADC. Throughout the signal path, the programmable amplifier U4 is powered by a ±12V isolated power supply to ensure sufficient output dynamic range. The second reference voltage source U8, which powers its reference circuit, works in conjunction with the second capacitor C2 and the third capacitor C3, acting as coupling capacitors, to provide an extremely stable and low-noise reference voltage for the digital-to-analog converter U7. Finally, after precise and controllable amplification, bias adjustment, and real-time calibration, the fully conditioned analog signal is output from the programmable amplifier U4 and enters the subsequent filtering circuit for further noise suppression, thus laying a solid signal foundation for the system to achieve high-precision pressure and tilt angle measurements.

[0043] In the amplifier circuit, the digital potentiometer U5 and the digital-to-analog converter U7 work together and are uniformly scheduled by the main control chip U1 to achieve independent, precise, and dynamic digital setting of the gain and output bias voltage of the programmable amplifier U4. This not only allows the system to adaptively match sensor signals of different ranges, preventing saturation or signal-to-noise ratio degradation, but also actively "shifts" the signal to the optimal position of the ADC sampling range, maximizing the utilization of the ADC's dynamic range—something that traditional circuits relying on jumper caps or potentiometers for manual adjustment cannot achieve. Furthermore, this amplifier circuit innovatively introduces a calibration network composed of an analog switch U_SW and precision resistors, incorporating it as part of the feedback loop of the programmable amplifier U4. During operation, the system can automatically complete periodic or triggered zero-point and gain calibration by switching different precision resistors via the main control chip U1, compensating in real time for errors introduced by temperature drift and device aging. This enables calibration functions that traditional circuits require shutdown and external equipment to perform in complex industrial environments, significantly improving long-term measurement accuracy and maintenance efficiency.

[0044] In another exemplary embodiment, such as Figure 4 As shown, the filter circuit includes operational amplifier U9, fourth capacitor C4, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, and ADC U11. The non-inverting input of operational amplifier U9 serves as the input of the filter circuit, connected sequentially to the output of programmable amplifier U4 through the third resistor R3 and a pre-amplified RC passive filter network. The pre-amplified RC passive filter network includes the fourth capacitor C4 and the fourth resistor R4. The first end of the fourth resistor R4 is connected to the junction of the third resistor R3 and the non-inverting input of operational amplifier U9, and the second end is connected to the ninth ground terminal GND9 through the fourth capacitor C4. The inverting input of operational amplifier U9 is connected to its output through the fifth resistor R5. The output terminal is connected to the non-inverting input terminal of voltage follower U10 (e.g., using OPA2188), and the inverting input terminal of voltage follower U10 is connected to its output terminal. The output terminal of voltage follower U10 is divided into three paths. The first path is connected to the analog input pin AINP of ADCU11. The second path is connected to the normally open terminal NO1 of the second dual-channel analog switch U12 (e.g., using ADG5433) through the sixth resistor R6, forming an output signal readback path. The third path is connected to the auxiliary ADC channel (ADC_AUX) of the main control chip U1 for cross-validation.

[0045] In this embodiment, the innovation of the filtering circuit lies in its composite architecture of "passive-active cascaded filtering + voltage follower isolation + three redundant outputs," which can simultaneously achieve three major functions—high-frequency noise suppression, impedance transformation, signal readback, and cross-verification—in a single circuit. The specific working principle of the filtering circuit includes: the signal output from the preamplifier circuit first passes through a pre-amplifier RC passive filter network composed of the third resistor R3 and the fourth capacitor C4, and the fourth resistor R4, to initially attenuate the high-frequency noise. Then, it is sent to the non-inverting amplifier structure composed of operational amplifier U9 and the fifth resistor R5 (which also forms a second-order active low-pass filter) for signal amplification and further filtering. The filtered signal is then sent to a buffer stage composed of voltage follower U10, which utilizes its high input impedance and low output impedance to achieve ideal isolation between the pre-amplifier circuit and the subsequent multi-channel load, preventing the ADC sampling action and switching from disturbing the filtering characteristics. Finally, the output of voltage follower U10 is divided into three paths, with the main path directly sent to the ADC. U11 performs high-precision analog-to-digital conversion. The readback path is connected to the second dual-channel analog switch U12 via the sixth resistor R6 to realize self-testing and feedback of the signal output value. The auxiliary path is connected to the auxiliary ADC channel of the main control chip for cross-verification with the main ADC data.

[0046] This filtering circuit not only filters out high-frequency interference and improves the signal-to-noise ratio, but also achieves system self-diagnosis and fault tolerance mechanisms through a unique redundant output design. The circuit ensures the accuracy and stability of signal acquisition in complex electromagnetic environments through active-passive composite filtering, and constructs a closed-loop monitoring link of "acquisition-readback-verification" using a three-output structure. This enables the system to detect ADC faults or channel anomalies in real time, thereby greatly improving the reliability and data trustworthiness of the cable reel control system in safety-critical scenarios.

[0047] In another exemplary embodiment, the clock unit includes a temperature-compensated crystal oscillator Y1, a MEMS oscillator Y2, a clock switching switch U_CLK_SW, a programmable phase-locked loop chip U13, a digital temperature sensor U14, and a GPS module U15; wherein, the temperature-compensated crystal oscillator Y1 serves as the master clock source, its power supply pin Y1_VCC is connected to a 3.3V power supply, its ground pin GNDA_OSC is grounded, and its output pin CLK_TCXO_122M is connected to the first input terminal SW_IN1 of the clock switching switch U_CLK_SW; the MEMS oscillator Y2 serves as the backup clock source, its power supply pin Y2_VDD is connected to a 3.3V power supply, its ground pin GNDD_OSC is grounded, and its output pin CLK_MEMS_125M is connected to the second input terminal SW_IN2 of the clock switching switch U_CLK_SW; the output terminal of the clock switching switch U_CLK_SW is connected to the clock input pin OSC_IN of the main control chip U1; the digital temperature sensor U14 is connected via I... 2 The C bus connects to the main control chip U1's I / O. 2 The serial clock (SCL) pin and serial data (SDA) pin are connected; the I pin of the programmable phase-locked loop chip U13 is connected. 2 C_SCL and I 2 The C_SDA pins are connected to the corresponding I pins of the main control chip U1. 2 C1_SCL and I 2C1_SDA, the multi-channel clock output pins (e.g., OUT0, OUT1) of the programmable phase-locked loop (PLL) chip U13 are connected to the corresponding external clock input pins (e.g., PI0, PA1) of the main control chip U1. The interrupt output pins (e.g., IRQ, LOCK) of the programmable PLL chip U13 are connected to the interrupt input pins (e.g., PE6, PR7) of the main control chip U1. The GPS module U15 is connected to the general-purpose I / O pins of the FPGA through its serial port output pin (UART_TX) to transmit raw NMEA / UBX data, and simultaneously connects its high-precision timing pulse signal (PPS) to another dedicated pin of the FPGA for synchronization and conditioning. The FPGA acts as an intelligent data interface and coprocessor, responsible for... The system parses the raw GPS information and packages it into structured data. Then, it sends the processed data to the corresponding SPI pins (such as PI0-PI3) of the main control chip U1 via a set of SPI buses (including MOSI, MISO, SCK, and CS signals). An independent GPIO pin (such as PE6) is used as an interrupt output connected to the external interrupt input of the main control chip U1 to notify that the data is ready. In addition, the shaped PPS signal output by the FPGA is also connected to the timer input capture pin (such as PH10) of the main control chip U1 to provide a unified and accurate clock reference for the entire system. This realizes a complete link from the acquisition and preprocessing of raw GPS information to efficient and reliable transmission and synchronization with the main control chip.

[0048] In this embodiment, the clock unit seamlessly switches between a temperature-compensated crystal oscillator Y1 as the main clock source and a MEMS oscillator Y2 as the backup clock source via a clock switching switch U_CLK_SW, ensuring continuous system operation even when the main clock fails. Additionally, the digital temperature sensor U14 monitors the ambient temperature in real time, and the main control chip U1 dynamically compensates for the temperature of the temperature-compensated crystal oscillator Y1 accordingly, effectively suppressing frequency drift. Simultaneously, the GPS module U15 provides raw time and location data, which is parsed and packaged into structured information by the FPGA and efficiently transmitted to the main control chip U1 via the SPI bus. Its high-precision PPS timing pulses are shaped by the FPGA and then input to the timer input capture pin of the main control chip U1, achieving nanosecond-level time synchronization. The programmable phase-locked loop chip U13 can generate multiple customized clocks according to the main control instructions to meet the timing requirements of various modules in the system.

[0049] The clock unit employs dual clock redundancy, which not only improves the reliability and accuracy of the clock system, but also enables the wire feeder to maintain precise control and stable operation under complex electromagnetic environments and temperature fluctuations.

[0050] In another exemplary embodiment, such as Figure 5As shown, the reset unit includes: a reset chip U16 (e.g., a TPS3828), a manual reset switch SW1, a fifth capacitor C5, a sixth capacitor C6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and an LED. The first terminal of the manual reset switch SW1 is connected to the manual reset input pin MR of the reset chip U16 to form a third node N3, and the second terminal is connected to the tenth ground terminal GND10. The first terminal of the seventh resistor R7 is connected to a 3.3V power supply, and the second terminal is connected to the third node N3. The fifth capacitor C5 is connected in parallel between the third node N3 and the tenth ground terminal GND10. The eighth resistor R8 and the ninth resistor R9 are connected in series to form a resistor divider network, wherein the first terminals of the eighth resistor R8 and the ninth resistor R9 are both connected to the reset chip. The power monitoring threshold setting pin SENSE of U16 is connected to the 5V power supply via the second end of the eighth resistor R8, and the second end of the ninth resistor R9 is connected to the eleventh ground terminal GND11. The first end of the tenth resistor R10 is connected to the fifth GPIO pin GPIO5 of the main control chip U1, and the second end is connected to the watchdog input pin WDI of the reset chip U16. The first end of the eleventh resistor R11 is connected to the 3.3V power supply, and the second end is connected to the reset signal output pin RESET of the reset chip U16. The anode of the LED is connected to the 3.3V power supply through the twelfth resistor R12, and the cathode is connected to the sixth input / output pin GPIO6 of the main control chip U1. The ground pin GND of the reset chip U16 is connected to the twelfth ground terminal GND12, and the sixth capacitor C6 is connected in parallel between the reset signal output pin RESET and the ground pin GND of the reset chip U16.

[0051] In this embodiment, the reset unit is connected to the power monitoring threshold setting pin SENSE of the reset chip U16 through a resistor divider network composed of the eighth resistor R8 and the ninth resistor R9, thereby innovatively realizing voltage monitoring of the 5V power domain. This design breaks the limitation of traditional reset circuits that only monitor the 3.3V core power supply, enabling the system to detect front-end power abnormalities earlier and implement safe reset in advance. Meanwhile, the reset unit efficiently integrates three independent reset triggering mechanisms into the reset chip U16: manual reset request (via the anti-bounce circuit composed of SW1, R7, and C5), undervoltage detection of the chip's internal power supply, and the watchdog feed signal (WDI) periodically triggered by the main control chip U1 through the tenth resistor R10. This forms a closed loop of coordinated protection—any fault (whether it is user manual intervention, power drop, or program crash) will reliably trigger the reset signal output. In addition, the reset status is not only cleared directly to the main control chip via the RESET pin, but also innovatively introduces a status indication circuit composed of an LED and the twelfth resistor R12. This circuit is controlled by the sixth GPIO pin GPIO6 of the main control chip U1, so that when the system starts up after reset, the cause of the fault can be reported through the specific flashing pattern of the LED. This provides an intuitive visual basis for on-site debugging and fault diagnosis. Combined with the appropriate delay shaping of the reset output signal by the sixth capacitor C6, the system's reliable initialization and abnormal self-recovery capability in complex industrial electromagnetic environments are ensured.

[0052] In another exemplary embodiment, the storage unit includes: boot memory U_BOOT, main running memory U_RAM, and data archive memory U_LOG, wherein the boot memory U_BOOT is connected to the main control chip U1 via a Quad-SPI bus; the main running memory U_RAM is connected to the main control chip U1 via an FMC bus; and the data archive memory U_LOG is composed of FRAM and NAND Flash, wherein the FRAM is connected to the main control chip U1 via an SPI interface, and the NAND Flash is connected to the main control chip U1 via an FMC interface.

[0053] In this embodiment, for the wire feeder, this application coordinates the design of three different types of memory with corresponding buses to achieve technical effects that are difficult to achieve with traditional dual-memory structures. Specifically, the wire feeder may encounter sudden power outages, hydraulic vibrations, and other conditions during operation, requiring the control system to have instantaneous recovery and continuous stable operation capabilities. In this application, U_BOOT can achieve millisecond-level fast startup through Quad-SPI memory mapping, ensuring that the wire feeder can immediately rebuild its control state after an unexpected power outage, avoiding cable loosening or tension loss due to restart delays. U_RAM provides high-speed data buffering via the FMC bus, specifically designed to handle the real-time calculation needs of multi-axis linkage of the main and auxiliary hydraulic cylinders. This enables the main control chip U1 to smoothly process massive amounts of data from tilt and pressure sensors, thereby achieving precise closed-loop control of the boom extension amplitude and overall tilt angle at the cable release port. In addition, U_LOG adopts a heterogeneous combination of FRAM and NAND Flash. FRAM can continuously record key state sequences such as hydraulic valve position and abnormal jitter with unlimited erase and write characteristics, while NAND Flash can non-volatilely store cable arrangement parameters and mechanical wear data formed over long-term operation. The two form a "secure storage chain" through hardware anti-miswrite and power filtering mechanisms, providing a complete and interference-resistant data traceability capability that traditional data recording schemes cannot achieve for analyzing the mechanical life of the cable release device and reproducing operational faults. This application presents a deeply customized storage solution based on the three core requirements of "rapid recovery, real-time control, and fault tracing" in the control scenario of cable laying machines. Through the synergistic enhancement of the timing response, bandwidth allocation, and reliability of each level of memory, it can produce technical effects that are difficult to predict with conventional storage combinations (such as dual storage structures) - that is, it can simultaneously ensure the instantaneity of equipment response, the accuracy of control behavior, and the immutability of operation and maintenance data in complex construction site environments.

[0054] It should be noted that the traditional "startup + operation" dual-storage structure in wire feeder control has the following drawbacks: Due to the lack of a dedicated non-volatile archive memory, the controller has to store key operating parameters (such as high-frequency dynamic data such as instantaneous hydraulic valve pressure, abnormal jitter records, and emergency stop trajectories) together with the program code in the startup memory, or temporarily store them in the volatile operation memory. This not only accelerates the aging of the startup memory and increases the risk of data corruption due to frequent writing, but also loses the key state sequence before the fault recorded in the operation memory during a sudden power outage. This makes it impossible for the system to accurately trace the hydraulic state and mechanical posture of the wire feeder at the moment of loss of control, making it difficult to reproduce the causes of faults such as "sudden tension drop" and "abnormal boom jitter". As a result, the wire feeder is in a passive maintenance state of "faults can occur, but the causes are difficult to trace" for a long time, which seriously restricts the reliability and maintainability of the wire feeder under complex working conditions.

[0055] In another exemplary embodiment, the hydraulic control module includes: an electro-hydraulic proportional valve drive circuit, a first power management circuit, and a fault protection circuit. The electro-hydraulic proportional valve drive circuit receives control commands from the main control module and outputs a precisely controllable power current to regulate the hydraulic flow and pressure of the main and auxiliary hydraulic cylinders in the wire feeder. The fault protection circuit monitors key parameters (e.g., current, temperature) in real time to prevent damage to the electro-hydraulic proportional valve drive circuit. The first power management circuit converts external input power to provide a stable voltage for the electro-hydraulic proportional valve drive circuit and the fault protection circuit.

[0056] In another exemplary embodiment, such as Figure 6As shown, the electro-hydraulic proportional valve drive circuit includes an electro-hydraulic proportional valve drive chip U17 (e.g., a DRV8871), a first power MOSFET Q1, and a second power MOSFET. Q2, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, eighteenth resistor R18, nineteenth resistor R19, seventh capacitor C7, eighth capacitor C8, first optocoupler OPT1 (e.g., TLP281-4), and second optocoupler OPT2; wherein, the power input pin VM of the electro-hydraulic proportional valve driver chip U17 is connected to a 24V power supply, and is connected to the twelfth ground terminal GND12 through the seventh capacitor C7 and the eighth capacitor C8 connected in parallel, and the ground pin GND is connected to the thirteenth ground terminal GND13; the sleep mode control pin nSLEEP of the electro-hydraulic proportional valve driver chip U17 is connected to a 3.3V power supply through the thirteenth resistor R13; the first output pin OUT1 of the electro-hydraulic proportional valve driver chip U17 is connected to the gate of the first power MOSFET Q1 through the fifteenth resistor R15, and the first power MOSFET... The drain of Q1 is connected to a 24V power supply, and the source is connected to the positive terminal of the electro-hydraulic proportional valve coil COIL. The second output pin OUT2 of the electro-hydraulic proportional valve driver chip U17 is connected to the gate of the second power MOSFET Q2 through the fourteenth resistor R14. The drain of the second power MOSFET Q2 is connected to a 24V power supply, and the source is connected to the negative terminal of the electro-hydraulic proportional valve coil COIL. The analog current sensing output pin IPROP1 of the electro-hydraulic proportional valve driver chip U17 is connected to the fourteenth ground terminal GND14 through the sixteenth resistor R16, and is also connected to the ADC pin of the main control chip U1. The second digital logic input pin IN2 of the electro-hydraulic proportional valve driver chip U17 is connected to the collector of the first optocoupler OPT1. The emitter of the first optocoupler OPT1 is connected to the fifteenth ground terminal GND15. The anode of the first optocoupler OPT1 is connected to the first PWM pin PWM1 of the main control chip U1 through the seventeenth resistor R17. The cathode is connected to the sixteenth ground terminal GND16; the first digital logic input pin IN1 of the electro-hydraulic proportional valve driver chip U17 is connected to the collector of the second optocoupler OPT2, the emitter of the second optocoupler OPT2 is connected to the seventeenth ground terminal GND17, the anode of the second optocoupler OPT2 is connected to the second PWM pin PWM2 of the main control chip U1 through the eighteenth resistor R18, and the cathode of the second optocoupler OPT2 is connected to the eighteenth ground terminal GND18; the fault status indication pin nFAULT of the electro-hydraulic proportional valve driver chip U17 is connected to the 3.3V power supply through the nineteenth resistor R19, and is also connected to the fifth GPIO pin GPIO5 of the main control chip U1.

[0057] In this embodiment, the innovation of the electro-hydraulic proportional valve drive circuit lies in its use of a composite power architecture of "integrated driver chip + external MOSFET" and a fully isolated signal design. The circuit outputs a precise gate drive signal through the electro-hydraulic proportional valve drive chip U17, which controls a high-current H-bridge composed of external power MOSFETs (Q1, Q2) via gate resistors (e.g., the fourteenth resistor R14 and the fifteenth resistor R15) to achieve high-power, low-loss drive of the electro-hydraulic proportional valve coil COIL. Simultaneously, the circuit utilizes first and second optocouplers (OPT1, OPT2) to electrically isolate the two PWM signals from the main control chip U1, suppressing power ground noise interference with logic control. This circuit also achieves high-precision, lossless coil current sampling and feedback to the main control chip U1 through the IPROPI pin and the sixteenth resistor R16, forming a current closed-loop control. The nFAULT pin, in conjunction with the pull-up resistor (nineteenth resistor R19), reports overcurrent, overheating, and other fault states to the main control chip U1 in real time. The nSLEEP pin is pulled up through the thirteenth resistor R13 to ensure that the electro-hydraulic proportional valve drive chip U17 is enabled by default. In addition, the seventh capacitor C7 and the eighth capacitor C8 connected in parallel to the power supply perform high-frequency decoupling and energy storage. This circuit simultaneously achieves power expansion, signal isolation, real-time sampling, and multiple protections in a single structure, thereby improving the dynamic response, accuracy, and operational reliability of the payer hydraulic control in harsh industrial environments.

[0058] In another exemplary embodiment, such as Figure 7 As shown, the first power management circuit includes a non-isolated buck controller U18 (e.g., using LM73606), a third power MOSFET Q3 (N-channel), an isolated DC-DC module U19 (e.g., IBF2412S), a digital power supply U20 (e.g., using TPS54332), a digital regulator LDO, and an operational amplifier U21; wherein, the power input pin VIN of the non-isolated buck controller U18 is connected to a 24V power supply, the enable control pin EN is connected to the power input pin VIN through the twentieth resistor R20, the bootstrap capacitor connection pin BOOT is connected to the power switch node pin SW through the ninth capacitor C9, the power switch node pin SW is connected to the first end of the first power inductor L1, the second end of the first power inductor L1 serves as a 12V pre-regulated output, the ground pin GND is connected to the nineteenth ground terminal GND19, and the second end of the first power inductor L1 is connected in parallel to the tenth capacitor C10 and the eleventh capacitor C11 to the twenty-first ground terminal GND21;

[0059] The positive DC power input pin +Vin of the isolated DC-DC module U19 is connected to the second terminal of the first power inductor L1, and the negative DC power input pin -Vin is connected to the twentieth ground terminal GND20. The positive DC power output pin +Vout outputs a +12V isolated power supply and is connected to the positive electrode pin of the operational amplifier U21. The negative DC power output pin -Vout outputs a -12V isolated power supply and is connected to the negative electrode pin of the operational amplifier U21. The non-inverting input terminal of the operational amplifier U21 is connected to the second terminal of the first power inductor L1, and the inverting input terminal is connected to its output terminal. The output terminal is connected to the ADC pin of the main control chip U1.

[0060] The power input pin VIN of the digital power supply U20 is connected to the positive DC power output pin +Vout of the isolated DC-DC module. The enable pin EN is connected to the power input pin VIN. The bootstrap capacitor connection pin BOOT is connected to the power switch node pin SW through the twelfth capacitor C12. The power switch node pin SW is connected to the first end of the second power inductor L2. The ground pin GND is connected to the twenty-second ground terminal GND22. The second end of the second power inductor L2 is connected in parallel to the thirteenth capacitor C13 and the fourteenth capacitor C14 to the twenty-third ground terminal GND23.

[0061] The power input pin VIN of the digital voltage regulator LDO is connected to the second terminal of the second power inductor L2, the ground pin GND is connected to the twenty-fourth ground terminal GND24, and the VOUT pin outputs a 3.3V voltage.

[0062] The gate of the third power MOSFET Q3 is connected to the enable pin GPIO_EN of the main control chip U1 through the twenty-first resistor R21. The source is connected to the first terminal of the first power inductor L1, and the drain is connected to the 12V power supply. The first freewheeling diode D1 is connected in reverse parallel between the source and the drain.

[0063] In this embodiment, in the first power management circuit, the non-isolated buck controller U18 first reduces the 24V input to a 12V pre-regulated output and supplies power to the isolated DC-DC module U19. The isolated DC-DC module U19 converts the 12V non-isolated power supply into a ±12V isolated dual power supply, which is dedicated to analog circuits such as the operational amplifier U21. Its output is buffered by a voltage follower formed by the operational amplifier U21 and then sent to the ADC pin of the main control chip for monitoring. At the same time, the +12V isolated output of the isolated DC-DC module U19 also supplies power to the digital power supply U20. After further stepping down, it is combined with the subsequent LDO to generate a pure 3.3V digital power supply.

[0064] The first power management circuit innovatively introduces a third power MOSFET Q3 controlled by the GPIO_EN pin of the main control chip, which can realize software-controllable on / off management in the 12V pre-regulation path. The inductor-capacitor filter network of each conversion stage output effectively suppresses ripple, thereby enabling high-low voltage conversion, strong-weak current isolation, digital and analog power supply separation and intelligent power consumption control to be realized synchronously in the entire power chain. This provides a stable power supply guarantee for the electro-hydraulic proportional valve drive circuit and fault protection circuit.

[0065] In addition, the first freewheeling diode D1 is connected in reverse parallel between the source and drain of the third power MOSFET Q3. It provides a freewheeling path for the inductive current flowing through the first power inductor L1 when the third power MOSFET Q3 is turned off, preventing dangerous high-voltage spikes from occurring between the drain and source of the third power MOSFET Q3 due to sudden changes in inductor current, thus protecting the third power MOSFET Q3 from breakdown. This configuration, by utilizing the unidirectional conduction characteristic of the diode, ensures the safe release of the energy stored in the first power inductor L1. It not only improves the reliability of the 12V pre-regulated path switching control but also simplifies the circuit structure, achieving efficient energy dissipation and voltage clamping effects at low cost.

[0066] In another exemplary embodiment, such as Figure 8 As shown, the fault protection circuit includes a current-sensing amplifier U22 (e.g., INA240), a 22nd resistor R22, a 23rd resistor R23, a 24th resistor R24, a 25th resistor R25, a first comparator U23, a second comparator U24, a third comparator U25, a fourth comparator U26, an OR gate logic chip U27 (e.g., SN74HC32PWR), an SR latch U28, and a fourth power MOSFET Q4. The first terminal of the 22nd resistor R22 is connected to a 24V power supply, and the second terminal is connected to the power input pin VM of the electro-hydraulic proportional valve driver chip U17. The current-sensing amplifier U22 is connected across the 22nd resistor R22. The output terminal OUT of the current-sensing amplifier U22 is simultaneously connected to the non-inverting input of the first comparator U23 and the inverting input of the second comparator U24. The inverting input of the first comparator U23 is connected to the first upper limit threshold voltage V generated by the reference power supply. high1 (e.g., 2.25V); the non-inverting input of the second comparator U24 is connected to the first lower threshold voltage V generated by the reference power supply. low1(e.g., 0.05V); the first terminal of the twenty-third resistor R23 is connected to a 3.3V power supply, and the second terminal is connected in series with the twenty-fourth resistor R24 ​​and then connected to the twenty-fifth ground terminal GND25. The connection point of the twenty-third resistor R23 and the twenty-fourth resistor R24 ​​(i.e., the voltage divider point) outputs a temperature voltage signal, which is simultaneously connected to the non-inverting input of the third comparator U25 and the inverting input of the fourth comparator U26; the inverting input of the third comparator U25 is connected to the second upper limit threshold voltage V. high2 (e.g., 2.25V); the non-inverting input of the fourth comparator U26 is connected to the second lower threshold voltage V. low2 (e.g., 0.05V); the outputs of the first comparator U23, the second comparator U24, the third comparator U25, and the fourth comparator U26 are respectively connected to the four input pins (IN1, IN2, IN3, IN4) of the OR gate logic chip U27; the output pin OUT of the OR gate logic chip U27 is connected to the set pin S of the SR latch U28, the output pin Q of the SR latch U28 is connected to the gate of the fourth power MOSFET Q4 through the 25th resistor R25, the drain of the fourth power MOSFET Q4 is connected to the power input pin VM of the electro-hydraulic proportional valve driver chip U17, and the source of the fourth power MOSFET Q4 is connected to a 24V power supply.

[0067] In this embodiment, the fault protection circuit constructs a closed-loop protection mechanism of "current-temperature dual-parameter collaborative monitoring and hardware rapid protection". Specifically, the circuit obtains the system current in real time through the current detection amplifier U22 connected across the 22nd resistor R22, and uses a window comparison circuit composed of two pairs of comparators (U23, U24, U25, U26) to distinguish the upper and lower limits of the current signal and the temperature voltage signal converted by the thermistor network (including the 23rd resistor R23 and the 24th resistor R24). If either signal exceeds the limit, the corresponding comparator is triggered to flip. All comparator outputs are integrated through the OR gate logic chip U27 to form the "any fault triggers the whole system" judgment logic, and are sent to the set terminal of the SR latch U28 for state locking. The latch output directly drives the fourth power MOSFET connected in series in the power main circuit. Q4 implements rapid power-off, thereby enabling nanosecond-level response and fault isolation for various anomalies such as overcurrent, undercurrent, overtemperature, and undertemperature in a purely hardware manner without the need for intervention from the main control chip U1. This greatly improves the real-time protection reliability and survivability of the electro-hydraulic proportional valve drive module under complex operating conditions.

[0068] In another exemplary embodiment, the lock control module includes a second power management circuit, which includes a DC-DC step-down chip U35 (e.g., LM2596S-5.0) and an LDO regulator chip U36 (e.g., AMS1117-3.3). The DC-DC step-down chip U35 and the LDO regulator chip U36 are electrically connected to a first CAN FD transceiver U29, a second CAN FD transceiver U30, a microcontroller U31 (e.g., STM32G071CBT6), a lock drive circuit, and a status feedback circuit, respectively. The DC-DC step-down chip U35 is used to convert the input 24V power supply to 5V, and then the LDO regulator chip U36 regulates it to 3.3V.

[0069] In this embodiment, the power supply pin VCC of the first CAN FD transceiver U29 receives the 3.3V voltage output by the LDO voltage regulator chip U36, and as... Figure 9 As shown, the transmit data pin TXD1 of the second CAN FD transceiver U29 is connected to the CAN transmit pin CAN_TX of the microcontroller U31 to receive data to be transmitted from the microcontroller U31. The receive data pin RXD1 of the first CAN FD transceiver U29 is connected to the CAN receive pin CAN_RX of the microcontroller U31 to transmit data received from the bus to the microcontroller U31. The power supply pin VCC of the second CAN FD transceiver U30 also receives the 3.3V voltage output from the LDO regulator chip U36. The longitudinal differential signal pins CANH2 and CANL2 of the second CAN FD transceiver U30 are respectively connected to the CAN bus differential signal pins CANH1 and CANL1 of the first CAN FD transceiver U29. The transmit data pin TXD2 and receive data pin RXD2 of the second CAN FD transceiver U30 are respectively connected to the FDCAN_TX and FDCAN_RX pins of the main control chip U1.

[0070] The two CAN FD transceivers together construct a closed internal communication network based on the CAN FD protocol, used to achieve reliable data exchange between the main control chip U1 and the microcontroller U31. Its working principle is described as follows: When the microcontroller U31 needs to send data to the main control chip U1, its CAN_TX pin sends the data to the TXD1 pin of the first CAN FD transceiver U29. The first CAN FD transceiver U29 then converts the digital signal into a differential electrical signal and drives it onto the physical bus composed of CANH1 and CANL1. Simultaneously, the second CAN FD transceiver U30 listens to this differential signal on the bus through its CANH2 and CANL2 pins, converts it back to a digital signal, and transmits it to the FDCAN_RX pin of the main control chip U1 through the RXD2 pin, thus completing one communication cycle from the microcontroller U31 to the main control chip U1. The reverse communication process is similar: the main control chip U1 sends data through the second CAN FD transceiver U30, and the first CAN FD transceiver U29 receives and transmits it to the microcontroller U31. Throughout the process, the two transceivers act as a bridge at the physical layer, responsible for completing the bidirectional and reliable conversion and transmission between logic signals and differential bus signals. They also utilize the inherent anti-interference characteristics of the CAN bus to ensure stable transmission of control commands in complex industrial environments.

[0071] In another exemplary embodiment, such as Figure 10 As shown, the lock driving circuit includes an H-bridge driver chip U32 (e.g., a DRV8842PWPR), an optocoupler U33 (e.g., a TLP281-4), a 26th resistor R26, and a second freewheeling diode D2. The anode of the optocoupler U33 is connected to the first GPIO pin GPIO1 of the microcontroller U31 via the 26th resistor R26, the cathode is connected to the 27th ground terminal GND27, the collector is connected to the input pin IN1 of the H-bridge driver chip U32, and the emitter is connected to the drive-side ground of the H-bridge driver chip U32. Pin GND1, the first output terminal OUT1 and the second output terminal OUT2 of the H-bridge driver chip U32 are respectively connected to the positive and negative terminals of the protective lock actuator LA (e.g., electromagnetic lock), and the second freewheeling diode D2 is connected in reverse parallel between the first output terminal OUT1 and the second output terminal OUT2 of the H-bridge driver chip U32; the power supply pin VCC of the H-bridge driver chip U32 is connected to the 5V voltage output by the DC-DC step-down chip, the power input pin VM is connected to the 24V power supply, and the output side ground pin GND2 is connected to the twenty-eighth ground terminal GND28.

[0072] In this embodiment, the lock driving circuit outputs a control signal through the first GPIO pin GPIO1 of the microcontroller U31. After current limiting by the twenty-sixth resistor R26, it drives the optocoupler U33 to conduct, thereby electrically isolating the trigger signal on the logic side to the input pin IN1 of the H-bridge driver chip U32. The H-bridge driver chip U32 controls the conduction sequence of the power switches of its internal H-bridge according to the input signal, so that a controllable 24V driving voltage is generated between its first output terminal OUT1 and second output terminal OUT2, thereby driving the protective lock actuator LA (electromagnetic lock) to operate, thus realizing the opening or closing of the lock. At the same time, the second freewheeling diode D2 is connected in reverse parallel between the first output terminal OUT1 and the second output terminal OUT2, providing a freewheeling circuit for the induced current generated by the LA coil at the moment of turn-off, effectively suppressing the high voltage spike caused by the reverse electromotive force and protecting the H-bridge power transistor from breakdown.

[0073] It should be noted that the innovation of this circuit lies in the triple collaborative design of optocoupler isolation, H-bridge drive, and freewheeling protection. Among them, the optocoupler U33 realizes the electrical isolation between the microcontroller's low-voltage logic and the electromagnetic lock's high-voltage drive, which can enhance the system's anti-interference capability and safety. The H-bridge driver chip U32 integrates a full-bridge architecture, replacing the complex drive circuit built with traditional discrete components with a single-chip solution, realizing simplified control and higher efficiency of bidirectional electromagnetic lock drive. The second freewheeling diode D2 serves as a key protection component, solving the inherent energy dissipation problem of inductive loads with a simple and reliable topology.

[0074] In summary, this circuit ensures the reliable and rapid operation of the electromagnetic lock while significantly improving the integration, safety, and robustness of the drive circuit. It effectively suppresses electrical noise and voltage surges caused by load switching, thus ensuring the long-term stable operation of the lock control module in complex industrial environments.

[0075] In another exemplary embodiment, such as Figure 11As shown, the state feedback circuit includes a dual-channel microswitch SW2, a Schmitt trigger U34 (e.g., SN74LVC1G17), a 27th resistor R27, a 28th resistor R28, a 15th capacitor C15, and a 16th capacitor C16. Specifically, the first terminal of switch A in the dual-channel microswitch SW2 is connected to the first terminal of the 27th resistor R27, and the second terminal of the 27th resistor R27 is connected to a 3.3V power supply. The second terminal of switch A is connected to the 31st ground terminal GND31. The first terminal of the 15th capacitor C15 is connected to the junction of the 27th resistor R27 and switch A, and the second terminal of the 15th capacitor C15 is connected to the 30th ground terminal GND30. The first terminal of switch B in the dual-channel microswitch SW2 is connected to the first terminal of the 28th resistor R28. The second terminal of R28 is connected to the 3.3V power supply; the second terminal of switch B is connected to the thirty-second ground terminal GND32; the first terminal of the sixteenth capacitor C16 is connected to the connection point of the twenty-eighth resistor R28 and switch B, and the second terminal of the sixteenth capacitor C16 is connected to the twenty-ninth ground terminal GND29; the first input pin 1A of the Schmitt trigger U34 is connected to the connection point of the twenty-seventh resistor R27 and switch A, the second input pin 2A is connected to the connection point of the twenty-eighth resistor R28 and switch B, the ground pin GND is connected to the thirty-third ground terminal GND33, the power supply pin VCC is connected to the 3.3V voltage, the first output pin 1Y is connected to the second GPIO pin GPIO2 of the microcontroller U31, and the second output pin 2Y is connected to the third GPIO pin GPIO3 of the microcontroller U31.

[0076] In this embodiment, the state feedback circuit uses a dual-channel microswitch SW2 to detect the mechanical position (such as "locked" and "unlocked") of the protective lock actuator in real time: when switch A or B is closed due to actuator action, the input level of its corresponding branch (composed of R27 / C15 or R28 / C16) is pulled low to ground potential; when the switch is opened, the pull-up resistor (R27 / R28) restores the branch level to high level. These level signals are respectively input to pins 1A and 2A of Schmitt trigger U34. After its internal hysteresis comparison function, the level glitches caused by mechanical jitter or noise interference are shaped, and finally, clean and stable digital signals are generated on output pins 1Y and 2Y, and transmitted to the second GPIO pin GPIO2 and the third GPIO pin GPIO3 of microcontroller U31 for accurate identification of the real-time status of the lock.

[0077] It should be noted that the innovation of this circuit lies in the adoption of a composite architecture of "dual-channel redundant detection combined with Schmitt trigger shaping". The design of the dual-channel micro switch SW2 not only realizes independent detection of different positions of the protection lock, but also builds a redundant channel for status feedback, enhancing the reliability of the system. The RC filter network (R27 / C15 and R28 / C16) introduced in each detection branch is combined with the Schmitt trigger U34 to form a dual anti-interference mechanism of "hardware filtering + hysteresis shaping", which can effectively suppress signal oscillation caused by mechanical contact jitter and environmental electromagnetic noise.

[0078] In summary, this circuit enables the control system to acquire highly reliable and jitter-free lock status signals, greatly improving the accuracy of status detection and anti-interference capabilities. It allows the microcontroller to implement effective closed-loop control based on accurate feedback information, thereby ensuring the determinism of lock operation and the safety of system operation in complex industrial environments.

[0079] In another exemplary embodiment, this application also provides a wire feeder control method, the method comprising the following steps:

[0080] S100: Real-time acquisition of pressure and tilt data of the wire feeder;

[0081] In this step, pressure sensors and tilt sensors installed on key parts such as the base of the wire feeder continuously collect the load force (pressure data) borne by the wire feeder and its current tilt angle (tilt data), providing the control system with real-time and accurate on-site working condition information.

[0082] S200: Generate control commands based on the pressure data and tilt angle data;

[0083] In this step, the main control module receives pressure and tilt data from the pressure and tilt sensors, and compares, analyzes, and processes this data with preset safety thresholds, target attitude, and other parameters. Subsequently, based on the processing results, it calculates the required adjustment amount and generates corresponding digital control commands to drive the subsequent actuator actions.

[0084] S300: Control the hydraulic actuator of the wire feeder according to the control command to adjust the arm amplitude and overall tilt angle of the wire feeder;

[0085] In this step, the hydraulic control module receives instructions from the main control module and precisely controls the actions of the main hydraulic cylinder and the auxiliary hydraulic cylinder by driving components such as the electro-hydraulic proportional valve. The main hydraulic cylinder is responsible for adjusting the opening amplitude of the wire feeding arm, and the auxiliary hydraulic cylinder is responsible for adjusting the tilt angle of the entire wire feeding device, thereby achieving precise and stable control of the wire feeding posture.

[0086] S400: Controls the opening and closing of the guide pulley protection lock of the wire feeder according to the control command.

[0087] In this step, the locking module also controls the opening and closing of the protective locks (usually electromagnetic locks) on each guide pulley according to the instructions issued by the main control module. The pulleys are locked when not in operation or when cables need to be secured to ensure safety; they are unlocked promptly during cable laying to ensure smooth cable passage.

[0088] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wire feeder control system, characterized in that, The system includes: The main control module is electrically connected to a pressure sensor, a tilt sensor, a hydraulic control module, and a lock control module. The main control module generates control commands based on the pressure and tilt data collected in real time by the pressure sensor and tilt sensor. The hydraulic control module is used to control the movement of the main hydraulic cylinder and the auxiliary hydraulic cylinder in the wire feeder based on the control commands generated by the main control module, so as to adjust the arm extension amplitude and overall tilt angle of the wire feeder. The locking module is used to control the opening and closing of the protective locks of each guide pulley in the wire feeder based on the control commands generated by the main control module; The hydraulic control module includes: The circuit includes an electro-hydraulic proportional valve drive circuit, a first power management circuit, and a fault protection circuit; among which... The electro-hydraulic proportional valve drive circuit is used to receive control commands from the main control module and output precise and controllable power current to regulate the hydraulic flow and pressure of the main hydraulic cylinder and auxiliary hydraulic cylinder in the control wire feeder. The fault protection circuit is used to monitor key parameters in real time to prevent damage to the electro-hydraulic proportional valve drive circuit; The first power management circuit is used to convert the external input power to provide a stable voltage for the electro-hydraulic proportional valve drive circuit and the fault protection circuit; The electro-hydraulic proportional valve drive circuit includes: The system includes an electro-hydraulic proportional valve driver chip, a first power MOSFET, a second power MOSFET, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a seventh capacitor, an eighth capacitor, a first optocoupler, and a second optocoupler; among which, The power input pin of the electro-hydraulic proportional valve driver chip is connected to a 24V power supply, and is connected to the twelfth ground terminal through the seventh and eighth capacitors connected in parallel. The sleep mode control pin of the electro-hydraulic proportional valve driver chip is connected to a 3.3V power supply via a thirteenth resistor. The first output pin of the electro-hydraulic proportional valve drive chip is connected to the gate of the first power MOSFET through the fifteenth resistor. The drain of the first power MOSFET is connected to a 24V power supply, and the source is connected to the positive terminal of the electro-hydraulic proportional valve coil. The second output pin of the electro-hydraulic proportional valve drive chip is connected to the gate of the second power MOSFET through the fourteenth resistor. The drain of the second power MOSFET is connected to the 24V power supply, and the source is connected to the negative terminal of the electro-hydraulic proportional valve coil. The second digital logic input pin of the electro-hydraulic proportional valve drive chip is connected to the collector of the first optocoupler, the emitter of the first optocoupler is connected to the fifteenth ground terminal, the anode of the first optocoupler is connected to the first PWM pin of the main control chip through the seventeenth resistor, and the cathode of the first optocoupler is connected to the sixteenth ground terminal. The first digital logic input pin of the electro-hydraulic proportional valve driver chip is connected to the collector of the second optocoupler, the emitter of the second optocoupler is connected to the seventeenth ground terminal, the anode of the second optocoupler is connected to the second PWM pin of the main control chip through the eighteenth resistor, and the cathode of the second optocoupler is connected to the eighteenth ground terminal. The fault status indicator pin of the electro-hydraulic proportional valve drive chip is connected to a 3.3V power supply through the nineteenth resistor, and is also connected to the fifth GPIO pin of the main control chip. The fault protection circuit includes: The system includes a current-sensing amplifier, resistors 22, 23, 24, and 25, a first comparator, a second comparator, a third comparator, a fourth comparator, an OR gate logic chip, an SR latch, and a fourth power MOSFET; among which, The first end of the 22nd resistor is connected to a 24V power supply, and the second end is connected to the power input pin of the electro-hydraulic proportional valve drive chip. The current-sense amplifier is connected across the 22nd resistor, and its output is connected to both the non-inverting input of the first comparator and the inverting input of the second comparator. The inverting input of the first comparator is connected to the first upper threshold voltage generated by the reference power supply; The non-inverting input of the second comparator is connected to the first lower threshold voltage generated by the reference power supply. The first end of the 23rd resistor is connected to a 3.3V power supply, and the second end is connected in series with the 24th resistor and then connected to the 25th ground terminal. The connection point of the 23rd and 24th resistors outputs a temperature voltage signal, which is simultaneously connected to the non-inverting input of the third comparator and the inverting input of the fourth comparator. The inverting input of the third comparator is connected to the second upper threshold voltage. The non-inverting input of the fourth comparator is connected to the second lower threshold voltage. The outputs of the first comparator, the second comparator, the third comparator, and the fourth comparator are respectively connected to the four input pins of the OR gate logic chip; The output pin of the OR gate logic chip is connected to the set terminal of the SR latch. The output terminal of the SR latch is connected to the gate of the fourth power MOSFET through the 25th resistor. The drain of the fourth power MOSFET is connected to the power input pin of the electro-hydraulic proportional valve drive chip. The source of the fourth power MOSFET is connected to the 24V power supply.

2. The wire feeder control system according to claim 1, characterized in that, The main control module includes: The main control chip is electrically connected to a clock unit, an analog signal processing unit, a memory unit, and a reset unit; among them, The clock unit is used to provide a stable and accurate clock signal to the main control chip, ensuring the time base for its internal logic and instruction execution; The analog signal processing unit is used to receive and condition the analog signals collected from the pressure sensor and tilt sensor, and convert them into digital signals for the main control chip to analyze and process. The storage unit is used to store the processing data of the main control chip; The reset unit is used to generate a reset signal to reset the main control chip.

3. The wire feeder control system according to claim 2, characterized in that, The analog signal processing unit includes: Input interface circuit, amplifier circuit, and filter circuit; among which, The input interface circuit is used to receive pressure sensing signals and tilt sensing signals and perform preprocessing. The amplifier circuit is used to amplify the pre-processed pressure sensing signal and tilt sensing signal; The filter circuit is used to filter the amplified pressure sensing signal and tilt sensing signal.

4. The wire feeder control system according to claim 3, characterized in that, The input interface circuit includes: Input connector, PTC resettable fuse, first resistor, first dual-channel analog switch; among which, The ground pin GND of the input connector is connected to the first ground terminal. The signal pin is connected to the pressure sensor and the tilt sensor, and then connected in series with the PTC resettable fuse and the first resistor, and then connected to the first normally closed terminal of the first dual-channel analog switch to form the first node. The input interface circuit also includes a TVS diode, a first capacitor, a second resistor, and a first reference voltage source, wherein the first end of the TVS diode is connected to the first node, and the second end is connected to the second ground terminal; The first terminal of the first capacitor is connected to the first node, and the second terminal is connected to the third ground terminal. The power input pin of the first reference voltage source is connected to the +5V power supply, the ground pin is connected to the fourth ground terminal, and the output pin is connected to the second normally closed terminal of the first dual-channel analog switch through the second resistor. The common output terminal of the first dual-channel analog switch is connected to the input terminal of the amplifier circuit.

5. The wire feeder control system according to claim 4, characterized in that, The amplifier circuit includes: Programmable amplifier, digital potentiometer, voltage buffer, digital-to-analog converter, second reference voltage source, second capacitor, and third capacitor; among which, The non-inverting input of the programmable amplifier serves as the input of the amplification circuit, used to receive analog signals from the pressure sensor and tilt sensor input via the input interface circuit. The inverting input of the programmable amplifier is grounded through a calibration network. The first and second gain setting pins of the programmable amplifier are both connected to the output of the digital potentiometer. The reference pin of the programmable amplifier is connected to the output of the digital-to-analog converter via a voltage buffer. The positive power supply pin of the programmable amplifier is connected to a +12V isolated power supply, the negative power supply pin is connected to a -12V isolated power supply, and the output pin is connected to the input of the filter circuit.

6. The wire feeder control system according to claim 4, characterized in that, The filter circuit includes: an operational amplifier, a fourth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an ADC; wherein, The non-inverting input of the operational amplifier serves as the input of the filter circuit. It is connected to the output of the programmable amplifier in sequence through a third resistor and a pre-amplified RC passive filter network. The pre-amplified RC passive filter network includes a fourth capacitor and a fourth resistor. The first end of the fourth resistor is connected to the connection point between the third resistor and the non-inverting input of the operational amplifier, and the second end is connected to the ninth ground terminal through the fourth capacitor. The inverting input of the operational amplifier is connected to its output through the fifth resistor. The output of the operational amplifier is connected to the non-inverting input of the voltage follower. The inverting input of the voltage follower is connected to its output. The output of the voltage follower is divided into three paths. The first path is connected to the analog input pin of the ADC; the second path is connected to the normally open terminal of the second dual-channel analog switch through the sixth resistor, forming the output signal readback path; and the third path is connected to the auxiliary ADC channel of the main control chip for cross-validation.

7. The wire feeder control system according to claim 1, characterized in that, The lock control module includes: a second power management circuit, which includes a DC-DC step-down chip and an LDO regulator chip; wherein... The DC-DC step-down chip and the LDO regulator chip are electrically connected to the first CAN FD transceiver, the second CAN FD transceiver, the microcontroller, the lock drive circuit, and the status feedback circuit, respectively. The DC-DC step-down chip is used to convert the input 24V power supply to 5V, and then the LDO regulator chip regulates it to 3.3V.

8. A wire feeder control method based on the wire feeder control system as described in any one of claims 1 to 7, characterized in that, The method includes: Real-time acquisition of pressure and tilt data from the wire feeder; Control commands are generated based on the pressure and tilt angle data; The hydraulic actuator of the wire feeder is controlled according to the control command to adjust the arm amplitude and overall tilt angle of the wire feeder; The control command controls the opening and closing of the guide pulley protection lock of the wire feeder.

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