A package flow detection method, system and medium for a memory chip

Abstract

The application provides a packaging process detection method, system and medium of a storage chip. The method comprises the following steps: collecting historical packaging characteristic data corresponding to each process in the packaging process of a target storage chip; extracting a corresponding failure rate, a failure influence degree and a process complexity according to the historical packaging characteristic data corresponding to each process; processing the failure rate, the failure influence degree and the process complexity to obtain a corresponding process risk level; matching a corresponding detection mode according to the process risk level; performing packaging process detection work on the target storage chip based on the detection mode corresponding to each process; monitoring the packaging process detection work in a preset time period; extracting execution effect data and evaluating the execution effect, so as to realize the packaging process detection technology of the storage chip.

Description

Technical Field

[0001] This application relates to the field of memory chip technology, and more specifically, to a method, system, and medium for testing the packaging process of memory chips. Background Technology

[0002] In the packaging process of memory chips, defects may be introduced at each step, affecting the performance and reliability of the memory chips. Traditional packaging process testing methods often adopt a uniform testing approach, without taking into account the risk differences between different steps, resulting in low testing efficiency, high testing costs, and difficulty in accurately identifying and locating potential quality problems. Therefore, how to match appropriate testing methods according to the risk level of each step to improve the targeting and effectiveness of testing has become an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this application is to provide a method, system, and medium for inspecting the packaging process of a memory chip. This method involves collecting historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, extracting the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data for each step, processing the defect rate, fault impact, and process complexity to obtain the corresponding process risk level, matching the corresponding detection method according to the process risk level, performing packaging process inspection on the target memory chip based on the detection method corresponding to each step, monitoring the packaging process inspection within a preset time period, extracting execution effect data, and evaluating the execution effect, thereby realizing the technology for inspecting the packaging process of a memory chip.

[0004] This application also provides a method for detecting the packaging process of a memory chip, including the following steps:

[0005] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip;

[0006] Based on the historical packaging characteristic data corresponding to each process, extract the corresponding defect rate, failure impact, and process complexity;

[0007] Based on the aforementioned defect rate, failure impact, and process complexity, the corresponding process risk level is obtained;

[0008] Match the corresponding detection method according to the risk level of the process;

[0009] The target memory chip is subjected to packaging process testing based on the testing methods corresponding to each process.

[0010] Monitor the encapsulation process detection work within a preset time period, extract execution effect data, and evaluate the execution effect.

[0011] Optionally, in the memory chip packaging process detection method described in this application, the step of collecting historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip includes:

[0012] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, including process characteristic data, test record data and fault log data;

[0013] The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency;

[0014] The detection record data includes the number of defective products in the process, the total input of the process, and the chip scrap rate;

[0015] The fault log data includes the frequency of fault occurrence and the fault missed rate.

[0016] Optionally, in the memory chip packaging process inspection method described in this application, the step of extracting the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data corresponding to each process includes:

[0017] The corresponding defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process.

[0018] Based on the chip scrap rate, failure frequency, and failure missed rate corresponding to each process, failure mode and effects analysis is used to obtain the corresponding failure impact degree.

[0019] The process complexity is obtained by processing the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency corresponding to each process through a preset process complexity evaluation model.

[0020] Optionally, in the memory chip packaging process inspection method described in this application, the step of processing based on the defect rate, fault impact, and process complexity to obtain the corresponding process risk level includes:

[0021] The defect rate, failure impact, and process complexity are processed using a preset risk level quantification model to obtain the corresponding process risk score.

[0022] Obtain a preset risk level threshold set, including a first preset risk level threshold and a second preset risk level threshold, wherein the first preset risk level threshold is less than the second preset risk level threshold;

[0023] The process risk score is compared with the preset risk level threshold set;

[0024] If the process risk score is less than or equal to the first preset risk level threshold, the corresponding process risk level is low risk.

[0025] If the process risk score is greater than the first preset risk level threshold and less than the second preset risk level threshold, then the corresponding process risk level is medium risk.

[0026] If the process risk score is greater than or equal to the second preset risk level threshold, then the corresponding process risk level is high risk.

[0027] Optionally, in the memory chip packaging process inspection method described in this application, the step of matching the corresponding inspection method according to the process risk level includes:

[0028] If the risk level of the process is low, the corresponding inspection method for the process is periodic sampling inspection;

[0029] If the risk level of the process is medium risk, the corresponding inspection method for the process is stratified sampling inspection;

[0030] If the risk level of the process is high, then the inspection method for the corresponding process is full inspection.

[0031] Optionally, in the memory chip packaging process detection method described in this application, the step of monitoring the packaging process detection work within a preset time period, extracting execution effect data, and evaluating the execution effect includes:

[0032] Monitor the packaging process detection work within a preset time period and extract execution effect data, including yield improvement, efficiency optimization and cost reduction.

[0033] The yield improvement, efficiency optimization, and cost reduction are weighted to obtain the performance improvement coefficient.

[0034] The improvement coefficient is compared with the preset improvement threshold.

[0035] The effectiveness of the packaging process detection work is judged based on the comparison results.

[0036] If the effect improvement coefficient is less than the preset effect improvement threshold, the execution effect is not up to standard and corresponding optimization measures need to be taken.

[0037] Secondly, this application provides a packaging process inspection system for memory chips. The system includes a memory and a processor. The memory includes a program for a packaging process inspection method for memory chips. When the program for the packaging process inspection method for memory chips is executed by the processor, it performs the following steps:

[0038] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip;

[0039] Based on the historical packaging characteristic data corresponding to each process, extract the corresponding defect rate, failure impact, and process complexity;

[0040] Based on the aforementioned defect rate, failure impact, and process complexity, the corresponding process risk level is obtained;

[0041] Match the corresponding detection method according to the risk level of the process;

[0042] The target memory chip is subjected to packaging process testing based on the testing methods corresponding to each process.

[0043] Monitor the encapsulation process detection work within a preset time period, extract execution effect data, and evaluate the execution effect.

[0044] Optionally, in the memory chip packaging process detection system described in this application, the step of collecting historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip includes:

[0045] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, including process characteristic data, test record data and fault log data;

[0046] The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency;

[0047] The detection record data includes the number of defective products in the process, the total input of the process, and the chip scrap rate;

[0048] The fault log data includes the frequency of fault occurrence and the fault missed rate.

[0049] Optionally, in the memory chip packaging process inspection system described in this application, the step of extracting the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data corresponding to each process includes:

[0050] The corresponding defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process.

[0051] Based on the chip scrap rate, failure frequency, and failure missed rate corresponding to each process, failure mode and effects analysis is used to obtain the corresponding failure impact degree.

[0052] The process complexity is obtained by processing the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency corresponding to each process through a preset process complexity evaluation model.

[0053] Thirdly, this application also provides a computer-readable storage medium storing a method program for detecting the packaging process of a memory chip. When the method program for detecting the packaging process of a memory chip is executed by a processor, it implements the steps of the method for detecting the packaging process of a memory chip as described in any of the preceding claims.

[0054] As can be seen from the above, the packaging process detection method, system, and medium for memory chips disclosed in this invention collect historical packaging characteristic data corresponding to each process in the packaging process of the target memory chip, extract the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data corresponding to each process, process the defect rate, fault impact, and process complexity to obtain the corresponding process risk level, match the corresponding detection method according to the process risk level, perform packaging process detection on the target memory chip based on the detection method corresponding to each process, monitor the packaging process detection within a preset time period, extract the execution effect data and evaluate the execution effect, thereby realizing the technology of packaging process detection for memory chips.

[0055] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A flowchart of the packaging process detection method for memory chips provided in this application embodiment;

[0058] Figure 2 A flowchart illustrating the extraction of defect rate, fault impact, and process complexity of the memory chip packaging process detection method provided in this application embodiment;

[0059] Figure 3 A flowchart illustrating how the packaging process detection method for memory chips provided in this application obtains the corresponding process risk level;

[0060] Figure 4 This is a flowchart illustrating the matching detection method for the packaging process detection method of the memory chip provided in this application embodiment. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0062] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0063] Please refer to Figure 1 , Figure 1 This is a flowchart of a memory chip packaging process detection method according to some embodiments of this application. This memory chip packaging process detection method is used in terminal devices, such as computers and mobile phones. The memory chip packaging process detection method includes the following steps:

[0064] S11. Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip;

[0065] S12. Extract the corresponding defect rate, fault impact and process complexity based on the historical packaging characteristic data corresponding to each process.

[0066] S13. Process the defect rate, failure impact, and process complexity to obtain the corresponding process risk level;

[0067] S14. Match the corresponding detection method according to the risk level of the process;

[0068] S15. Perform packaging process testing on the target memory chip based on the testing methods corresponding to each process.

[0069] S16. Monitor the encapsulation process detection work within a preset time period, extract execution effect data, and evaluate the execution effect.

[0070] It should be noted that the process involves collecting historical packaging characteristic data for each step in the packaging process of the target memory chip, including process characteristic data, inspection record data, and fault log data. The defect rate is extracted based on the number of defective products and the total input for each step. The fault impact is extracted based on the chip scrap rate, fault occurrence frequency, and fault missed detection rate for each step. Furthermore, the process complexity is extracted based on the number of process parameters, processing time, number of trials, and optimization iteration frequency. Then, the defect rate, fault impact, and process complexity are processed to obtain the corresponding process risk level, including high, medium, and low risk levels. Corresponding detection methods are then matched, and packaging process inspection is performed on the target memory chip based on the detection methods for each step. The execution status is monitored after a period of time, and the execution effect data is extracted and evaluated, thereby realizing the technology for packaging process inspection of memory chips.

[0071] According to an embodiment of the present invention, the collection of historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip includes:

[0072] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, including process characteristic data, test record data and fault log data;

[0073] The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency;

[0074] The detection record data includes the number of defective products in the process, the total input of the process, and the chip scrap rate;

[0075] The fault log data includes the frequency of fault occurrence and the fault missed rate.

[0076] It should be noted that the historical packaging characteristic data for each step in the packaging process of the target memory chip is collected, including process characteristic data, inspection record data, and fault log data. The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency. The number of process parameters includes the set values ​​and actual operating values ​​of various process parameters such as temperature, pressure, time, and current intensity. The processing time data accurately records the time from raw material input to the completion of the process. The number of trials and errors reflects the number of attempts made to achieve the ideal packaging effect during process debugging, new product introduction, and other stages. The optimization iteration frequency reflects the changes in process parameters and... The frequency of operational method improvements; inspection record data includes the number of defective products in each process, the total number of chips input in each process, and the chip scrap rate; among them, the number of defective products in each process is a detailed count of the number of chips that do not meet quality standards in each process; the total number of chips input in each process clearly records the total number of chips entering that process, and combined with the number of defective products, the yield rate of the process can be calculated intuitively; the chip scrap rate is a statistical analysis of chips that cannot be repaired due to quality problems and can only be scrapped; fault log data includes the frequency of fault occurrence and the fault missed rate; the frequency of fault occurrence is a statistical analysis of the number of times equipment failures, process abnormalities, and other problems occur within a certain time period; the fault missed rate measures the proportion of faults that are not detected in time during the inspection process out of the total number of faults.

[0077] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating the extraction of defect rate, fault impact, and process complexity corresponding to the packaging process detection method for memory chips in some embodiments of this application. According to embodiments of the present invention, the extraction of corresponding defect rate, fault impact, and process complexity based on historical packaging characteristic data corresponding to each process includes:

[0078] S21. Statistical processing is performed based on the number of defective products in each process and the total input of each process to obtain the corresponding defect rate;

[0079] S22. Based on the chip scrap rate, failure frequency and failure missed rate corresponding to each process, the corresponding failure impact is obtained by processing through failure mode and effects analysis.

[0080] S23. Based on the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency corresponding to each process, the corresponding process complexity is obtained by processing through a preset process complexity evaluation model.

[0081] It should be noted that the defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process. Specifically, the defect rate of each process is calculated by dividing the number of defective products in each process by the total input, using the formula: Defect Rate = Number of Defective Products in Process / Total Input in Process × 100%. Using three key data points—chip scrap rate, failure frequency, and failure missed detection rate—Failure Mode and Effects Analysis (FMEA) is introduced to systematically assess the potential risks in the packaging process. First, each data point is assigned a different weight according to its severity of impact on production; for example, chip scrap rate has a weight of 40%, failure frequency has a weight of 35%, and failure missed detection rate has a weight of 25%. Then, the failure impact of each process is calculated using the formula: Failure Impact = Chip Scrap Rate × 40% + Failure Frequency × 35% + Failure Missed Detection Rate × 25%. Loudness score: Based on process characteristic data such as the number of process parameters, processing time, number of trials and errors, and optimization iteration frequency, a pre-set process complexity assessment model is used to quantitatively evaluate the technical difficulty of each packaging process. This model uses the Analytic Hierarchy Process (AHP) to divide each parameter into dimensions such as "operational difficulty," "time cost," and "technology maturity," and assigns corresponding weights to each. For example, the number of process parameters has a weight of 30% (more parameters mean more complex operation and control), processing time data has a weight of 25% (longer processing time means higher cost and risk), the number of trials and errors has a weight of 25% (reflecting technology maturity), and the optimization iteration frequency has a weight of 20% (reflecting the need for process improvement). The quantitative score is obtained by using the weighted summation formula: Process complexity = Number of process parameters × 30% + Processing time data × 25% + Number of trials and errors × 25% + Optimization iteration frequency × 20%.

[0082] Please refer to Figure 3 , Figure 3 This is a flowchart illustrating the process risk level determination method for the packaging process of a memory chip in some embodiments of this application. According to embodiments of the present invention, the step of processing based on the defect rate, fault impact, and process complexity to obtain the corresponding process risk level includes:

[0083] S31. Based on the defect rate, failure impact, and process complexity, the corresponding process risk score is obtained by processing them through a preset risk level quantification model.

[0084] S32. Obtain a set of preset risk level thresholds, including a first preset risk level threshold and a second preset risk level threshold, wherein the first preset risk level threshold is less than the second preset risk level threshold.

[0085] S33. Compare the process risk score with the preset risk level threshold set;

[0086] S34. If the process risk score is less than or equal to the first preset risk level threshold, the corresponding process risk level is low risk;

[0087] S35. If the process risk score is greater than the first preset risk level threshold and less than the second preset risk level threshold, the corresponding process risk level is medium risk;

[0088] S36. If the process risk score is greater than or equal to the second preset risk level threshold, the corresponding process risk level is high risk.

[0089] It should be noted that according to the three quantitative indicators of the defect rate, failure impact degree, and process complexity statistically in the early stage, a preset risk level quantitative model is introduced. This model is constructed based on the Analytic Hierarchy Process (AHP) and the Fuzzy Comprehensive Evaluation Method, and is verified by expert experience and historical data to assign different weights to each indicator; for example, assign a 45% weight to the defect rate (directly reflecting the product quality risk), a 30% weight to the failure impact degree (emphasizing the comprehensive impact of the failure on production), and a 25% weight to the process complexity (reflecting the potential risk brought by the technical difficulty). Through the weighted summation formula: process risk score = defect rate × 45% + failure impact degree × 30% + process complexity × 25%, the multi-dimensional risk factors are transformed into a quantitative score of 0 - 100 points. To achieve a scientific classification of risk levels, the enterprise pre-sets a risk level threshold set based on historical production data, industry standards, and quality goals, including the first preset risk level threshold (denoted as A) and the second preset risk level threshold (denoted as B), and A < B. For example, combined with the actual needs of the enterprise and the historical risk data distribution, A is set to 40 points and B is set to 60 points. Among them, the first threshold A is used as the dividing line between low risk and medium risk to identify minor risk processes; the second threshold B distinguishes medium risk and high risk; the risk scores of each process are compared with the preset threshold set in real time, and a three-level risk determination logic is executed: if the risk score of a certain process ≤ A (such as a score of 35 points), it is determined as low risk, when A < process risk score < B (such as a score of 52 points), it is determined as medium risk, and if the process risk score ≥ B (such as a score of 68 points), it is determined as high risk.

[0090] Please refer to Figure 4 , Figure 4 is a flowchart of the matching corresponding detection method for the package process detection method of the storage chip in some embodiments of the present application. According to an embodiment of the present invention, the matching corresponding detection method according to the process risk level includes:

[0091] S41. If the process risk level is low risk, the detection method for the corresponding process is periodic sampling inspection;

[0092] S42. If the risk level of the process is medium risk, the detection method for the corresponding process is stratified sampling inspection.

[0093] S43. If the risk level of the process is high, the detection method for the corresponding process is full inspection.

[0094] It should be noted that when a process risk level is determined to be low, it indicates that the process is operating stably under current technological conditions, with minimal fluctuations in product quality. For this, a periodic sampling strategy can be adopted, which involves setting a fixed sampling cycle and sample size based on historical production data and quality stability assessments. For medium-risk processes, due to potential quality issues or production fluctuation risks, a stratified sampling approach is required for more meticulous quality control. The stratification strategy is based on process characteristics and risk sources, such as classification by production batch, equipment number, or operator, ensuring that the test samples cover different influencing factors. For high-risk processes, given their potentially significant impact on product quality and production efficiency, a full inspection model is adopted, performing 100% inspection on every chip that passes through this process.

[0095] According to an embodiment of the present invention, the monitoring of the packaging process detection work within a preset time period, extracting execution effect data and evaluating the execution effect includes:

[0096] Monitor the packaging process detection work within a preset time period and extract execution effect data, including yield improvement, efficiency optimization and cost reduction.

[0097] The yield improvement, efficiency optimization, and cost reduction are weighted to obtain the performance improvement coefficient.

[0098] The improvement coefficient is compared with the preset improvement threshold.

[0099] The effectiveness of the packaging process detection work is judged based on the comparison results.

[0100] If the effect improvement coefficient is less than the preset effect improvement threshold, the execution effect is not up to standard and corresponding optimization measures need to be taken.

[0101] It should be noted that, to comprehensively measure the effectiveness of the packaging process inspection, it is necessary to systematically collect execution effect data covering three dimensions: quality, efficiency, and cost within a preset time period (such as monthly, quarterly, or project cycle). Specifically, by comparing the final chip yield before and after the implementation of the inspection work, the specific numerical value of the yield improvement is calculated, i.e., the yield improvement degree; using the number of qualified chips packaged per unit time as a benchmark, the change in production efficiency after the inspection process adjustment is analyzed, i.e., the efficiency optimization degree; and the cost savings resulting from reducing rework of defective products, optimizing the use of inspection equipment, and reducing manpower input are comprehensively calculated, i.e., the cost reduction degree. To integrate multi-dimensional data and form a unified evaluation standard, a weighted processing method is used to construct an effect improvement coefficient, based on the factors of quality, efficiency, and cost in production management. The strategic importance of each component is assigned different weights: for example, in this embodiment, the yield improvement is weighted at 40%, the efficiency optimization at 30%, and the cost reduction at 30%. The quantitative value is calculated using the formula: Effect Improvement Coefficient = Yield Improvement × 40% + Efficiency Optimization × 30% + Cost Reduction × 30%. Then, a preset effect improvement threshold (e.g., 15%) is set as the evaluation benchmark, and the calculated effect improvement coefficient is compared with it. The execution effect of the packaging process inspection is judged based on the comparison result. If the effect improvement coefficient is less than the preset effect improvement threshold, the execution effect is not up to standard, and corresponding optimization measures need to be taken. For example, the existing solution can be partially optimized through the PDCA cycle, such as adjusting the sampling ratio or optimizing the inspection process sequence.

[0102] According to an embodiment of the present invention, it further includes:

[0103] Based on the risk level of the process, upper and lower limit warnings are set for the corresponding equipment process parameters;

[0104] If the risk level of the process is low, then the upper and lower limit warnings are set to 95% of the corresponding standard range;

[0105] If the risk level of the process is medium risk, then the upper and lower limit warnings are set to 90% of the corresponding standard range;

[0106] If the risk level of the process is high, then the upper and lower limit warnings are set to 80% of the corresponding standard range.

[0107] It is important to note that establishing a scientific and reasonable early warning mechanism for equipment process parameters is crucial to ensure the safe and stable operation of equipment, guarantee product quality, and prevent potential risks. Therefore, it is necessary to strictly set precise upper and lower limit warnings for the corresponding equipment process parameters based on the risk level of each process. Specifically, when a process is determined to be low-risk through professional assessment and risk analysis, it means that the possibility of abnormal situations occurring in that process under normal production conditions is relatively small, and the production process is relatively stable. In this case, the upper and lower limit warnings are set to 95% of the corresponding standard range. If the assessment determines that the process is of medium risk, it indicates that there are certain potential risk factors in that process, and the possibility of abnormalities occurring during production has increased. In this case, the upper and lower limit warnings are set to 90% of the corresponding standard range. Compared with the setting of the low risk level, the stricter warning range can capture the changing trend of process parameters earlier. Once the parameter deviates from the standard range by 10%, the system will trigger a warning. When the process risk level is rated as high risk, it means that the process faces a large potential risk. Any abnormal fluctuation of process parameters may cause serious production accidents or quality problems. In order to maximize the protection of production safety and product quality, the upper and lower limit warnings are set to 80% of the corresponding standard range.

[0108] Secondly, the present invention also discloses a packaging process detection system for memory chips, including a memory and a processor. The memory includes a packaging process detection method program for memory chips. When the packaging process detection method program for memory chips is executed by the processor, it performs the following steps:

[0109] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip;

[0110] Based on the historical packaging characteristic data corresponding to each process, extract the corresponding defect rate, failure impact, and process complexity;

[0111] Based on the aforementioned defect rate, failure impact, and process complexity, the corresponding process risk level is obtained;

[0112] Match the corresponding detection method according to the risk level of the process;

[0113] The target memory chip is subjected to packaging process testing based on the testing methods corresponding to each process.

[0114] Monitor the encapsulation process detection work within a preset time period, extract execution effect data, and evaluate the execution effect.

[0115] It should be noted that the process involves collecting historical packaging characteristic data for each step in the packaging process of the target memory chip, including process characteristic data, inspection record data, and fault log data. The defect rate is extracted based on the number of defective products and the total input for each step. The fault impact is extracted based on the chip scrap rate, fault occurrence frequency, and fault missed detection rate for each step. Furthermore, the process complexity is extracted based on the number of process parameters, processing time, number of trials, and optimization iteration frequency. Then, the defect rate, fault impact, and process complexity are processed to obtain the corresponding process risk level, including high, medium, and low risk levels. Corresponding detection methods are then matched, and packaging process inspection is performed on the target memory chip based on the detection methods for each step. The execution status is monitored after a period of time, and the execution effect data is extracted and evaluated, thereby realizing the technology for packaging process inspection of memory chips.

[0116] According to an embodiment of the present invention, the collection of historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip includes:

[0117] Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, including process characteristic data, test record data and fault log data;

[0118] The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency;

[0119] The detection record data includes the number of defective products in the process, the total input of the process, and the chip scrap rate;

[0120] The fault log data includes the frequency of fault occurrence and the fault missed rate.

[0121] It should be noted that the historical packaging characteristic data for each step in the packaging process of the target memory chip is collected, including process characteristic data, inspection record data, and fault log data. The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency. The number of process parameters includes the set values ​​and actual operating values ​​of various process parameters such as temperature, pressure, time, and current intensity. The processing time data accurately records the time from raw material input to the completion of the process. The number of trials and errors reflects the number of attempts made to achieve the ideal packaging effect during process debugging, new product introduction, and other stages. The optimization iteration frequency reflects the changes in process parameters and... The frequency of operational method improvements; inspection record data includes the number of defective products in each process, the total number of chips input in each process, and the chip scrap rate; among them, the number of defective products in each process is a detailed count of the number of chips that do not meet quality standards in each process; the total number of chips input in each process clearly records the total number of chips entering that process, and combined with the number of defective products, the yield rate of the process can be calculated intuitively; the chip scrap rate is a statistical analysis of chips that cannot be repaired due to quality problems and can only be scrapped; fault log data includes the frequency of fault occurrence and the fault missed rate; the frequency of fault occurrence is a statistical analysis of the number of times equipment failures, process abnormalities, and other problems occur within a certain time period; the fault missed rate measures the proportion of faults that are not detected in time during the inspection process out of the total number of faults.

[0122] According to an embodiment of the present invention, the step of extracting the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data corresponding to each process includes:

[0123] The corresponding defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process.

[0124] Based on the chip scrap rate, failure frequency, and failure missed rate corresponding to each process, failure mode and effects analysis is used to obtain the corresponding failure impact degree.

[0125] The process complexity is obtained by processing the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency corresponding to each process through a preset process complexity evaluation model.

[0126] It should be noted that the defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process. Specifically, the defect rate of each process is calculated by dividing the number of defective products in each process by the total input, using the formula: Defect Rate = Number of Defective Products in Process / Total Input of Process × 100%. Using three key data points—chip scrap rate, failure frequency, and failure missed rate—Failure Mode and Effects Analysis (FMEA) is introduced to systematically assess the potential risks in the packaging process. First, each data point is assigned a different weight according to its severity of impact on production; for example, chip scrap rate has a weight of 40%, failure frequency has a weight of 35%, and failure missed rate has a weight of 25%. Then, the failure impact score of each process is calculated using the formula: Failure Impact = Chip Scrap Rate × 40% + Failure Frequency × 35% + Failure Missed Rate × 25%. Based on process characteristic data such as the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency, a preset process... The complexity assessment model quantitatively evaluates the technical difficulty of each packaging process. This model employs the Analytic Hierarchy Process (AHP), dividing each parameter into dimensions such as "operational difficulty," "time cost," and "technology maturity," and assigning corresponding weights to each. For example, the number of process parameters has a weight of 30% (more parameters mean more complex operation and control), processing time data has a weight of 25% (longer processing time means higher cost and risk), the number of trials and errors has a weight of 25% (reflecting technology maturity), and the optimization iteration frequency has a weight of 20% (reflecting the need for process improvement). A quantitative score is obtained through the weighted summation formula: Process Complexity = Number of Process Parameters × 30% + Processing Time Data × 25% + Number of Trials and Errors × 25% + Optimization Iteration Frequency × 20%.

[0127] According to an embodiment of the present invention, the step of processing based on the defect rate, failure impact, and process complexity to obtain the corresponding process risk level includes:

[0128] The defect rate, failure impact, and process complexity are processed using a preset risk level quantification model to obtain the corresponding process risk score.

[0129] Obtain a preset risk level threshold set, including a first preset risk level threshold and a second preset risk level threshold, wherein the first preset risk level threshold is less than the second preset risk level threshold;

[0130] The process risk score is compared with the preset risk level threshold set;

[0131] If the process risk score is less than or equal to the first preset risk level threshold, the corresponding process risk level is low risk.

[0132] If the process risk score is greater than the first preset risk level threshold and less than the second preset risk level threshold, the corresponding process risk level is medium risk;

[0133] If the process risk score is greater than or equal to the second preset risk level threshold, the corresponding process risk level is high risk.

[0134] It should be noted that according to three types of quantitative indicators, namely the defect rate, failure impact degree, and process complexity, which are statistically obtained in the early stage, a preset risk level quantitative model is introduced. This model is constructed based on the Analytic Hierarchy Process (AHP) and the Fuzzy Comprehensive Evaluation Method, and is verified through expert experience and historical data to assign different weights to each indicator. For example, a 45% weight is assigned to the defect rate (directly reflecting the product quality risk), a 30% weight is assigned to the failure impact degree (emphasizing the comprehensive impact of failures on production), and a 25% weight is assigned to the process complexity (reflecting the potential risks brought by technical difficulties). Through the weighted summation formula: process risk score = defect rate × 45% + failure impact degree × 30% + process complexity × 25%, multi-dimensional risk factors are transformed into a quantitative score ranging from 0 to 100 points. To achieve a scientific classification of risk levels, an enterprise pre-sets a risk level threshold set according to historical production data, industry standards, and quality objectives, which includes the first preset risk level threshold (denoted as A) and the second preset risk level threshold (denoted as B), and A < B. For example, in combination with the actual needs of the enterprise and the distribution of historical risk data, A is set to 40 points and B is set to 60 points. Among them, the first threshold A serves as the dividing line between low risk and medium risk, used to identify slightly risky processes; the second threshold B differentiates medium risk and high risk; the risk scores of each process are compared with the preset threshold set in real time, and a three-level risk determination logic is executed: if the risk score of a certain process ≤ A (such as a score of 35 points), it is determined as low risk, when A < process risk score < B (such as a score of 52 points), it is determined as medium risk, and if the process risk score ≥ B (such as a score of 68 points), it is determined as high risk.

[0135] According to an embodiment of the present invention, the matching of the corresponding detection method according to the process risk level includes:

[0136] If the process risk level is low risk, the detection method for the corresponding process is periodic sampling inspection;

[0137] If the process risk level is medium risk, the detection method for the corresponding process is stratified sampling inspection;

[0138] If the process risk level is high risk, the detection method for the corresponding process is full inspection.

[0139] It should be noted that when a process risk level is determined to be low, it indicates that the process is operating stably under current technological conditions, with minimal fluctuations in product quality. For this, a periodic sampling strategy can be adopted, which involves setting a fixed sampling cycle and sample size based on historical production data and quality stability assessments. For medium-risk processes, due to potential quality issues or production fluctuation risks, a stratified sampling approach is required for more meticulous quality control. The stratification strategy is based on process characteristics and risk sources, such as classification by production batch, equipment number, or operator, ensuring that the test samples cover different influencing factors. For high-risk processes, given their potentially significant impact on product quality and production efficiency, a full inspection model is adopted, performing 100% inspection on every chip that passes through this process.

[0140] According to an embodiment of the present invention, the monitoring of the packaging process detection work within a preset time period, extracting execution effect data and evaluating the execution effect includes:

[0141] Monitor the packaging process detection work within a preset time period and extract execution effect data, including yield improvement, efficiency optimization and cost reduction.

[0142] The yield improvement, efficiency optimization, and cost reduction are weighted to obtain the performance improvement coefficient.

[0143] The improvement coefficient is compared with the preset improvement threshold.

[0144] The effectiveness of the packaging process detection work is judged based on the comparison results.

[0145] If the effect improvement coefficient is less than the preset effect improvement threshold, the execution effect is not up to standard and corresponding optimization measures need to be taken.

[0146] It should be noted that, to comprehensively measure the effectiveness of the packaging process inspection, it is necessary to systematically collect execution effect data covering three dimensions: quality, efficiency, and cost within a preset time period (such as monthly, quarterly, or project cycle). Specifically, by comparing the final chip yield before and after the implementation of the inspection work, the specific numerical value of the yield improvement is calculated, i.e., the yield improvement degree; using the number of qualified chips packaged per unit time as a benchmark, the change in production efficiency after the inspection process adjustment is analyzed, i.e., the efficiency optimization degree; and the cost savings resulting from reducing rework of defective products, optimizing the use of inspection equipment, and reducing manpower input are comprehensively calculated, i.e., the cost reduction degree. To integrate multi-dimensional data and form a unified evaluation standard, a weighted processing method is used to construct an effect improvement coefficient, based on the factors of quality, efficiency, and cost in production management. The strategic importance of each component is assigned different weights: for example, in this embodiment, the yield improvement is weighted at 40%, the efficiency optimization at 30%, and the cost reduction at 30%. The quantitative value is calculated using the formula: Effect Improvement Coefficient = Yield Improvement × 40% + Efficiency Optimization × 30% + Cost Reduction × 30%. Then, a preset effect improvement threshold (e.g., 15%) is set as the evaluation benchmark, and the calculated effect improvement coefficient is compared with it. The execution effect of the packaging process inspection is judged based on the comparison result. If the effect improvement coefficient is less than the preset effect improvement threshold, the execution effect is not up to standard, and corresponding optimization measures need to be taken. For example, the existing solution can be partially optimized through the PDCA cycle, such as adjusting the sampling ratio or optimizing the inspection process sequence.

[0147] According to an embodiment of the present invention, it further includes:

[0148] Based on the risk level of the process, upper and lower limit warnings are set for the corresponding equipment process parameters;

[0149] If the risk level of the process is low, then the upper and lower limit warnings are set to 95% of the corresponding standard range;

[0150] If the risk level of the process is medium risk, then the upper and lower limit warnings are set to 90% of the corresponding standard range;

[0151] If the risk level of the process is high, then the upper and lower limit warnings are set to 80% of the corresponding standard range.

[0152] It is important to note that establishing a scientific and reasonable early warning mechanism for equipment process parameters is crucial to ensure the safe and stable operation of equipment, guarantee product quality, and prevent potential risks. Therefore, it is necessary to strictly set precise upper and lower limit warnings for the corresponding equipment process parameters based on the risk level of each process. Specifically, when a process is determined to be low-risk through professional assessment and risk analysis, it means that the possibility of abnormal situations occurring in that process under normal production conditions is relatively small, and the production process is relatively stable. In this case, the upper and lower limit warnings are set to 95% of the corresponding standard range. If the assessment determines that the process is of medium risk, it indicates that there are certain potential risk factors in that process, and the possibility of abnormalities occurring during production has increased. In this case, the upper and lower limit warnings are set to 90% of the corresponding standard range. Compared with the setting of the low risk level, the stricter warning range can capture the changing trend of process parameters earlier. Once the parameter deviates from the standard range by 10%, the system will trigger a warning. When the process risk level is rated as high risk, it means that the process faces a large potential risk. Any abnormal fluctuation of process parameters may cause serious production accidents or quality problems. In order to maximize the protection of production safety and product quality, the upper and lower limit warnings are set to 80% of the corresponding standard range.

[0153] A third aspect of the present invention provides a readable storage medium storing a method program for detecting the packaging process of a memory chip. When the method program for detecting the packaging process of a memory chip is executed by a processor, it implements the steps of the method for detecting the packaging process of a memory chip as described in any of the preceding claims.

[0154] The present invention discloses a method, system, and medium for detecting the packaging process of memory chips. This method collects historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip. Based on this data, it extracts the corresponding defect rate, fault impact, and process complexity. The defect rate, fault impact, and process complexity are then processed to obtain the corresponding process risk level. A corresponding detection method is matched to the process risk level. Based on the detection method for each process, the packaging process is detected on the target memory chip. The detection process is monitored within a preset time period, and the execution effect data is extracted and evaluated, thereby realizing the technology for detecting the packaging process of memory chips.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0156] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0157] In addition, in the various embodiments of the present invention, each functional unit can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0158] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0159] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

Claims

1. A method for detecting the packaging process of a memory chip, characterized in that, Includes the following steps: Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip; Based on the historical packaging characteristic data corresponding to each process, extract the corresponding defect rate, failure impact, and process complexity; Based on the aforementioned defect rate, failure impact, and process complexity, the corresponding process risk level is obtained; Match the corresponding detection method according to the risk level of the process; The target memory chip is subjected to packaging process testing based on the testing methods corresponding to each process. Monitor the encapsulation process detection work within a preset time period, extract execution effect data, and evaluate the execution effect; The step of extracting the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data corresponding to each process includes: The corresponding defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process. Based on the chip scrap rate, failure frequency, and failure missed rate corresponding to each process, failure mode and effects analysis is used to obtain the corresponding failure impact degree. Based on the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency for each process, the corresponding process complexity is obtained by processing through a preset process complexity evaluation model. The process of obtaining the corresponding process risk level based on the defect rate, failure impact, and process complexity includes: The defect rate, failure impact, and process complexity are processed using a preset risk level quantification model to obtain the corresponding process risk score. Obtain a preset risk level threshold set, including a first preset risk level threshold and a second preset risk level threshold, wherein the first preset risk level threshold is less than the second preset risk level threshold; The process risk score is compared with the preset risk level threshold set; If the process risk score is less than or equal to the first preset risk level threshold, the corresponding process risk level is low risk. If the process risk score is greater than the first preset risk level threshold and less than the second preset risk level threshold, then the corresponding process risk level is medium risk. If the process risk score is greater than or equal to the second preset risk level threshold, then the corresponding process risk level is high risk.

2. The method for detecting the packaging process of a memory chip according to claim 1, characterized in that, The historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip is collected, including: Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, including process characteristic data, test record data and fault log data; The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency; The detection record data includes the number of defective products in the process, the total input of the process, and the chip scrap rate; The fault log data includes the frequency of fault occurrence and the fault missed rate.

3. The method for detecting the packaging process of a memory chip according to claim 2, characterized in that, The step of matching the corresponding detection method according to the risk level of the process includes: If the risk level of the process is low, the corresponding inspection method for the process is periodic sampling inspection; If the risk level of the process is medium risk, the corresponding inspection method for the process is stratified sampling inspection; If the risk level of the process is high, then the inspection method for the corresponding process is full inspection.

4. The method for detecting the packaging process of a memory chip according to claim 3, characterized in that, The monitoring of the encapsulation process within the preset time period includes extracting execution effect data and evaluating the execution effect, including: Monitor the packaging process detection work within a preset time period and extract execution effect data, including yield improvement, efficiency optimization and cost reduction. The yield improvement, efficiency optimization, and cost reduction are weighted to obtain the performance improvement coefficient. The improvement coefficient is compared with the preset improvement threshold. The effectiveness of the packaging process detection work is judged based on the comparison results. If the effect improvement coefficient is less than the preset effect improvement threshold, the execution effect is not up to standard and corresponding optimization measures need to be taken.

5. A packaging process inspection system for memory chips, characterized in that, The system includes a memory and a processor. The memory contains a program for detecting the packaging process of a memory chip. When the program for detecting the packaging process of a memory chip is executed by the processor, it performs the following steps: Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip; Based on the historical packaging characteristic data corresponding to each process, extract the corresponding defect rate, failure impact, and process complexity; Based on the aforementioned defect rate, failure impact, and process complexity, the corresponding process risk level is obtained; Match the corresponding detection method according to the risk level of the process; The target memory chip is subjected to packaging process testing based on the testing methods corresponding to each process. Monitor the encapsulation process detection work within a preset time period, extract execution effect data, and evaluate the execution effect; The step of extracting the corresponding defect rate, fault impact, and process complexity based on the historical packaging characteristic data corresponding to each process includes: The corresponding defect rate is obtained by statistically processing the number of defective products in each process and the total input of each process. Based on the chip scrap rate, failure frequency, and failure missed rate corresponding to each process, failure mode and effects analysis is used to obtain the corresponding failure impact degree. Based on the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency for each process, the corresponding process complexity is obtained by processing through a preset process complexity evaluation model. The process of obtaining the corresponding process risk level based on the defect rate, failure impact, and process complexity includes: The defect rate, failure impact, and process complexity are processed using a preset risk level quantification model to obtain the corresponding process risk score. Obtain a preset risk level threshold set, including a first preset risk level threshold and a second preset risk level threshold, wherein the first preset risk level threshold is less than the second preset risk level threshold; The process risk score is compared with the preset risk level threshold set; If the process risk score is less than or equal to the first preset risk level threshold, the corresponding process risk level is low risk. If the process risk score is greater than the first preset risk level threshold and less than the second preset risk level threshold, then the corresponding process risk level is medium risk. If the process risk score is greater than or equal to the second preset risk level threshold, then the corresponding process risk level is high risk.

6. The memory chip packaging process inspection system according to claim 5, characterized in that, The historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip is collected, including: Collect historical packaging characteristic data corresponding to each step in the packaging process of the target memory chip, including process characteristic data, test record data and fault log data; The process characteristic data includes the number of process parameters, processing time data, number of trials and errors, and optimization iteration frequency; The detection record data includes the number of defective products in the process, the total input of the process, and the chip scrap rate; The fault log data includes the frequency of fault occurrence and the fault missed rate.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a method program for detecting the packaging process of a memory chip. When the method program for detecting the packaging process of a memory chip is executed by a processor, it implements the steps of the method for detecting the packaging process of a memory chip as described in any one of claims 1 to 4.

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