Calculation core verification method and device in chip design process, equipment and medium
By introducing a three-party verification system into the chip design process, and by comparing the signals of hardware logic circuits, functional reference models, and behavioral reference models, the problem of error consistency in chip verification is solved, and higher quality verification results are achieved.
Patent Information
- Application Number
- CN202511286869.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-09
- Publication Date
- 2025-12-19
AI Technical Summary
Existing chip verification methods suffer from error consistency issues, making it difficult to detect deep-seated design flaws in a timely manner, thus affecting chip quality and reliability.
A three-party verification system is introduced, consisting of hardware logic circuits, functional reference models, and behavioral reference models. Comprehensive verification is performed by comparing hardware circuit signals, functional reference signals, and behavioral reference signals.
This improves the completeness and coverage of verification, enabling more timely and accurate detection of defects in hardware design and increasing the success rate of chip design.
Smart Images
Figure CN121168356A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip verification technical field, and particularly relates to a verification method, device, equipment and medium for a computing core in a chip design process. BACKGROUND
[0002] In the field of chip design, verification of a computing core is a key process to ensure that the chip can finally operate as expected and meet diversified application requirements. Under the prior art, in order to carry out verification of the computing core, a verification architecture related to the computing core is built, and verification personnel can implement verification around the architecture to determine whether the hardware design of the computing core meets expectations.
[0003] However, this method has obvious disadvantages. That is, since the architecture and the hardware design may have consistency deviation in understanding and transformation of related design requirements, even if the hardware design has defects, the existing verification method may still conclude that the design is correct and meets expectations, so that deep-seated problems hidden in the chip are difficult to be detected in time, which seriously threatens the quality and reliability of the chip. SUMMARY
[0004] The present application provides a verification method, device, equipment and medium for a computing core in a chip design process, to solve the problem of inaccurate and unreliable chip verification in the prior art, and to improve and optimize verification quality.
[0005] The present application provides a verification method for a computing core in a chip design process, comprising: determining a hardware logic circuit, a functional reference model and a behavior reference model of the computing core to be verified, wherein the hardware logic circuit, the functional reference model and the behavior reference model are all developed based on a design specification document of the computing core; inputting an excitation signal into the hardware logic circuit, the functional reference model and the behavior reference model respectively to obtain hardware circuit signals, functional reference signals and behavior reference signals output by the hardware logic circuit, the functional reference model and the behavior reference model respectively; verifying the computing core based on the hardware circuit signals, the functional reference signals and the behavior reference signals to obtain a verification result of the computing core.
[0006] According to the verification method for a computing core in a chip design process provided by the present application, the hardware circuit signals, the functional reference signals and the behavior reference signals are compared to obtain a first comparison result. comparing the hardware circuit signal with the behavior reference signal to obtain a second comparison result; determining a verification result of the computing core based on the first comparison result and the second comparison result.
[0007] According to the chip design process computing core verification method provided by the application, the behavior logic of the behavior reference model is related to the timing of the hardware logic of the hardware logic circuit; The comparison of the hardware circuit signal with the behavior reference signal to obtain a second comparison result comprises: The hardware circuit signal and the behavior reference signal are compared in the timing cycle to obtain a second comparison result.
[0008] According to the chip design process computing core verification method provided by the application, when the verification mode of the computing core is module verification, the method comprises: Determine the hardware logic circuit, functional reference model and behavior reference model of each module in the computing core; The excitation signal is input to the hardware logic circuit, functional reference model and behavior reference model of each module respectively, and the hardware circuit signal, functional reference signal and behavior reference signal output by the hardware logic circuit, functional reference model and behavior reference model of each module are obtained respectively; Based on the hardware circuit signal, functional reference signal and behavior reference signal corresponding to each module, the verification of each module of the computing core is carried out, and the verification result of each module is obtained.
[0009] According to the chip design process computing core verification method provided by the application, when the verification mode of the computing core is integrated verification, the method comprises: Determine the integrated circuit, integrated functional reference model and integrated behavior reference model of the computing core; the integrated circuit is obtained by connecting the hardware logic circuits of each module in series, the integrated functional reference model is obtained by connecting the functional reference models of each module in series, and the integrated behavior reference model is obtained by connecting the behavior reference models of each module in series; The excitation signal is input to the integrated circuit, the integrated functional reference model and the integrated behavior reference model respectively, and the integrated hardware circuit signal, the integrated functional reference signal and the integrated behavior reference signal output by the integrated circuit, the integrated functional reference model and the integrated behavior reference model are obtained respectively; Based on the integrated hardware circuit signal, the integrated functional reference signal and the integrated behavior reference signal, the computing core is verified, and the verification result of the computing core is obtained.
[0010] According to the chip design process computing core verification method provided by the application, positioning information is arranged in each behavior reference model constituting the integrated behavior reference model, and the positioning information is used to indicate the position of the corresponding behavior reference model corresponding module; The verification result of the computing core is obtained by verifying the computing core based on the integrated hardware circuit signal, the integrated function reference signal and the integrated behavior reference signal. If the verification result of the computing core is not passed, the problem is located based on the positioning signal output by the integrated behavior reference model; the positioning signal is time sequence synchronous with the integrated behavior reference signal, and corresponds to the content of the positioning information.
[0011] According to the chip design process computing core verification method provided by the application, the verification result of the computing core is determined based on the first comparison result and the second comparison result, including: If the first comparison result and the second comparison result are consistent, it is determined that the verification result of the computing core is passed. Otherwise, it is determined that the verification result of the computing core is not passed.
[0012] The application also provides a chip design process computing core verification device, including: A determination unit is used to determine the hardware logic circuit, function reference model and behavior reference model of the computing core to be verified; the hardware logic circuit, the function reference model and the behavior reference model are all developed based on the design specification document of the computing core. A processing unit is used to input the excitation signal into the hardware logic circuit, the function reference model and the behavior reference model respectively, and obtain the hardware circuit signal, the function reference signal and the behavior reference signal output by the hardware logic circuit, the function reference model and the behavior reference model respectively. A verification unit is used to verify the computing core based on the hardware circuit signal, the function reference signal and the behavior reference signal, and obtain the verification result of the computing core.
[0013] The application also provides an electronic device, including a memory, a processor and a computer program stored in the memory and running on the processor, and the processor implements the chip design process computing core verification method as described above.
[0014] The application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by the processor to implement the chip design process computing core verification method as described above.
[0015] The application provides a verification method, device, equipment and medium for a computing core in a chip design process, wherein an excitation signal is input into a hardware logic circuit, a function reference model and a behavior reference model of the computing core to be verified, hardware circuit signals, function reference signals and behavior reference signals output by the three are obtained, and the computing core is verified according to the hardware circuit signals, function reference signals and behavior reference signals to obtain a verification result; the hardware logic circuit, the function reference model and the behavior reference model are all developed based on a design specification document of the computing core; the function reference model and the behavior reference model are introduced to perform synchronous verification with the hardware logic circuit, a three-party reference verification system is constructed, and the verification is performed according to the three-party reference verification system, so that the defects of the current single reference model verification, such as error consistency and inaccurate and unreliable verification results, are overcome, the completeness and coverage of the verification are greatly improved, defects existing in the hardware design can be more timely and accurately found, and therefore the verification quality and the success rate of the chip design are improved. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 FIG. 1 is a flowchart of a verification method for a computing core in a chip design process provided by the application; Figure 2 FIG. 2 is a structural diagram of a verification device for a computing core in a chip design process provided by the application; Figure 3 FIG. 3 is a structural diagram of an electronic device provided by the application. DETAILED DESCRIPTION
[0018] In order to make the objects, technical solutions and advantages of the application clearer, the technical solutions in the application will be described clearly and completely below with reference to the drawings in the application. Obviously, the described embodiments are some embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.
[0019] In the design process of modern high-performance chips such as GPU (Graphics Processing Unit), CPU (Central Processing Unit), AI (Artificial Intelligence) chip and the like, the logic function of the compute core is becoming more and more complex, and the verification thereof is a key link to ensure the correctness of the chip function. At present, the mainstream verification method for such a complex compute core is usually to compare the hardware logic circuit (implemented by RTL (register-transfer level) code) with a high abstraction level model such as CModel (a functional model implemented by C language or C++ language).
[0020] However, this two-party comparison verification method has a fatal defect, i.e. error consistency problem. Specifically, when the hardware (RTL) design team and the model (C Model) development team have the same understanding deviation on the design specification document or make the same error in the logic implementation, the RTL and the C Model will both output the wrong results. However, since the error outputs of the two are consistent, the comparator in the verification environment will still determine that the verification is passed, so that a deep design defect escapes and brings great risk to the subsequent chip tape-out.
[0021] To this end, the present application provides a verification method for a compute core in a chip design process, which aims to introduce an independent behavior reference model having the same function as the hardware logic circuit and corresponding logic, and together with the hardware logic circuit and the functional reference model, form a three-party verification system, break the error consistency dependency relationship that may occur in two-party comparison, so as to comprehensively check the hardware logic circuit of the compute core from the two dimensions of function and behavior in the chip design process, and further improve the verification quality and optimize the defect capture capability.
[0022] Figure 1 The present application provides a flowchart of the verification method for the compute core in the chip design process, as shown in Figure 1 The method is applied to the compute core of a general-purpose image processor (GPGPU), and can also be applied to the compute core of other processors such as CPU, GPU and the like. The method comprises the following steps: Step 110, determining the hardware logic circuit, the functional reference model and the behavior reference model of the computing core to be verified; the hardware logic circuit, the functional reference model and the behavior reference model are all developed based on the design specification document of the computing core; Step 120, inputting the excitation signal into the hardware logic circuit, the functional reference model and the behavior reference model respectively to obtain the hardware circuit signal, the functional reference signal and the behavior reference signal output by the hardware logic circuit, the functional reference model and the behavior reference model respectively; Step 130, verifying the computing core based on the hardware circuit signal, the functional reference signal and the behavior reference signal to obtain the verification result of the computing core.
[0023] Specifically, before starting the verification process of a computing core, the object of verification, i.e. the computing core to be verified, needs to be determined first. The computing core refers to the core unit in a chip that performs computing tasks, which can be a core unit in CPU, GPU, etc., can also be a tensor computing unit in a neural network processor, or can also be a core unit in a digital signal processor, and the present embodiment does not make specific limitation. Before verification, the specific target to be verified needs to be determined according to the overall design and verification plan of the chip, i.e. the computing core to be verified.
[0024] Then, the design specification document of the computing core needs to be determined. The design specification document here is the reference of the entire development work, which specifies in detail the architecture, instruction set, function definition, interface protocol, timing constraint, performance index, etc. of the computing core. After obtaining the computing specification document, the development team will develop three key parts according to the design specification document, which are hardware logic circuit, functional reference model and behavior reference model.
[0025] Among them, the hardware logic circuit is written using HDL (Hardware Description Language), such as Verilog, VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), System Verilog, etc., which describes the specific logic structure and timing relationship of the computing core at the gate level circuit layer, and is the basis for subsequent physical implementation (such as synthesis, layout and wiring). In the verification process in the present embodiment, the hardware logic circuit is the object to be tested.
[0026] The functional reference model is a model at an abstract level, which aims to accurately simulate the functions defined in the design specification document. The model can be written in a high-level programming language, such as C, C++, Python, etc. The functional reference model often does not focus on or only superficially considers the implementation details of the hardware, such as the pipeline, timing cycle or specific microarchitecture. For example, for an addition instruction, the functional reference model only needs to calculate the correct addition result, without simulating the multiple pipeline stages such as instruction fetching, decoding, execution, and write back that the instruction experiences in hardware. Due to its high abstraction, the development speed is often fast, and the functional correctness of itself can be easily guaranteed, and it is often used as a reference standard for functional verification.
[0027] The behavioral reference model is a model that takes into account both functional and timing behaviors. Compared with the functional reference model, the behavioral reference model is closer to the hardware implementation, which can simulate the cycle-accurate or transaction-level behavior of the computing core. The model can be written in a language that combines hardware description and high-level programming features, such as SystemVerilog, SystemC, etc. For example, for the addition instruction mentioned above, the behavioral reference model will not only calculate the result, but also simulate the entire process of receiving operands from the input port in a specific clock cycle and generating the result from the output port after several cycles.
[0028] Here, it should be noted that in the embodiments of the present application, the development of the hardware logic circuit, the functional reference model and the behavioral reference model strictly follows the design specification document of the computing core; and the external interface of the developed behavioral reference model and the interface of the hardware logic circuit are consistent, so that the consistency of the two in design intent can be ensured, and the comparison of the output results of the two can also be realized.
[0029] Further, after determining the hardware logic circuit, the functional reference model and the behavioral reference model of the computing core, the verification can be performed in the embodiments of the present application. Here, specifically, after the functional reference model and the behavioral reference model are developed, the verification personnel can integrate the functional reference model and the behavioral reference model in the verification environment; then, the verification environment generates an excitation signal and applies it to the three objects to drive them to run and produce outputs. The excitation signal is a series of input data, instruction sequence and control signal for testing the computing core. The excitation signal can be a predefined, directed test case, or a randomized test case, or an execution trace of a real application, which is not limited in the embodiments of the present application.
[0030] Specifically, after the same (logically equivalent) stimulus signals are given to the hardware logic circuit, the functional reference model and the behavioral reference model, the hardware logic circuit, the functional reference model and the behavioral reference model are independently run, respectively process the stimulus signals, and can obtain corresponding output signals, i.e. hardware circuit signals, functional reference signals and behavioral reference signals. Among them, the hardware circuit signal is the signal waveform or data generated on the output port of the hardware logic circuit after simulation, the functional reference signal is the final calculation result or state output generated after the functional reference model is run, and the behavioral reference signal is the output signal sequence generated after the behavioral reference model is run. The three groups of signals together constitute the basis for verification decision.
[0031] After that, comparison and verification can be performed to determine the final verification result. That is, the hardware circuit signal, the functional reference signal and the behavioral reference signal obtained in the last step are analyzed and compared to determine whether the design of the hardware logic circuit of the computing core is correct.
[0032] Specifically, the comparison and verification process based on the three groups of signals can be performed by a comparator in the verification environment. The verification logic can be very flexible, for example, it can check whether the final calculation result embodied by the hardware circuit signal is consistent with the functional reference signal, and at the same time check whether the cycle-by-cycle change of the hardware circuit signal is consistent with the expected behavior of the behavioral reference signal. Through such multi-angle checking, the correctness of the hardware logic circuit can be more comprehensively evaluated. However, it is worth noting that if any inconsistency is found between the three groups of signals in the comparison and verification process, it can be determined that there is a problem with the hardware logic circuit.
[0033] After the above comparison and verification, the verification result of the computing core can be obtained. The verification result can be a pass or fail status indication; or it can be a detailed report, for example, when the verification result is fail, the report can indicate at which time, under which group of stimulus signals, and between which groups of output signals, inconsistency occurs, and provide relevant information to help chip designers or verification personnel quickly locate and fix the problem.
[0034] The application provides a verification method for a computing core in a chip design process. An excitation signal is input into a hardware logic circuit, a function reference model and a behavior reference model of the computing core to be verified, hardware circuit signals, function reference signals and behavior reference signals output by the three are obtained, and the computing core is verified according to the hardware circuit signals, the function reference signals and the behavior reference signals to obtain a verification result. The hardware logic circuit, the function reference model and the behavior reference model are all developed based on a design specification document of the computing core. The function reference model and the behavior reference model are introduced to perform synchronous verification with the hardware logic circuit, a three-party reference verification system is constructed, and the verification is performed according to the three-party reference verification system, so that the error consistency in the single reference model verification in the traditional scheme is overcome, the defects of the verification result being not accurate and reliable are overcome, the completeness and the coverage of the verification are greatly improved, defects existing in the hardware design can be found more timely and accurately, and therefore the verification quality and the success rate of the chip design are improved.
[0035] Based on the above embodiment, step 130 comprises: comparing the hardware circuit signals with the function reference signals to obtain a first comparison result; comparing the hardware circuit signals with the behavior reference signals to obtain a second comparison result; determining the verification result of the computing core based on the first comparison result and the second comparison result.
[0036] Specifically, the process of verifying the computing core according to the hardware circuit signals, the function reference signals and the behavior reference signals to obtain the verification result can specifically comprise: Firstly, the hardware circuit signals can be compared with the function reference signals to verify the functional correctness of the computing core, so as to obtain a first comparison result. Here, the comparison can be performed by a comparator in a verification environment, that is, whether the data result output by the hardware logic circuit after a series of processes is consistent with the function result output by the function reference model is compared, and the comparison process only focuses on the final functional output (whether the results are consistent) and does not focus on the process. The first comparison result is used to indicate the consistency in the function, which can be consistent or inconsistent.
[0037] Meanwhile, the hardware circuit signal can be compared with the behavior reference signal to verify the behavior correctness of the calculation core, so as to obtain a second comparison result. The comparison process can also be performed by the comparator in the verification environment. Unlike the functional comparison, the behavior comparison not only focuses on the consistency of the final result, but also focuses on the consistency of the process. That is, the dynamic change of the hardware circuit signal is compared with the dynamic behavior predicted by the behavior reference model, such as whether the values of the key interface signals of the two are consistent, whether the number of cycles experienced from the beginning to the end is consistent, whether the state machine jumps are consistent, and the like, to obtain the second comparison result. The second comparison result is used to indicate the consistency in behavior, and the result can also be consistent or inconsistent.
[0038] Then, the two comparison results are integrated, that is, the functional verification conclusion and the behavior verification conclusion represented by the first comparison result and the second comparison result are combined to determine the final conclusion, that is, whether the verification of the calculation core passes or fails.
[0039] Based on the above embodiment, the behavior logic of the behavior reference model is related to the timing of the hardware logic of the hardware logic circuit; The hardware circuit signal is compared with the behavior reference signal to obtain a second comparison result, including: The hardware circuit signal is compared with the behavior reference signal in the timing cycle to obtain the second comparison result.
[0040] Specifically, in chip design, a large number of complex logics and potential defects are closely related to timing behavior, such as arbiter logic and hazard logic in the hardware logic circuit. A pure functional model cannot effectively verify the correctness of these logics, that is, it cannot verify the timing logic, and a special Checker needs to be developed for comparison, which greatly increases the workload and development cost.
[0041] In view of this, to improve the accuracy of verification, in the embodiment of the application, timing can be added to the behavior reference model, so that the behavior logic of the behavior reference model is related to the timing of the hardware logic of the hardware logic circuit. Specifically, the behavior reference model in the embodiment of the application is not a pure functional, time-dimensionless model, but a model that can perceive timing. It can simulate or predict the dynamic behavior of the hardware logic circuit under the driving of the clock.
[0042] Based on this, when comparing the hardware circuit signal and the behavior reference signal, the hardware circuit signal and the behavior reference signal can be compared in a logic comparison in a timing cycle. In the comparison process, not only the consistency of the final result is concerned, but also the consistency at each key time point. That is, the comparator in the verification environment samples the hardware circuit signal from the hardware logic circuit and the behavior reference signal from the behavior reference model at the same time, and performs a point-by-point comparison of the two at each clock cycle (or a specified clock active edge). The comparison content is not limited to the final data result, but can also include various instructions, control signals, state signals, etc. working with the data result.
[0043] In the embodiment of the application, through the accurate timing cycle comparison, the timing errors that are easily ignored in the traditional functional comparison can be accurately captured, thereby greatly improving the accuracy of the verification, and the defects existing in the design can be found earlier and more accurately, thereby improving the success rate of chip design.
[0044] Based on the above embodiment, based on the first comparison result and the second comparison result, the verification result of the calculation core is determined, including: If the first comparison result and the second comparison result are consistent, it is determined that the verification result of the calculation core is passed. Otherwise, it is determined that the verification result of the calculation core is not passed.
[0045] Specifically, the process of determining the verification result of the calculation core according to the first comparison result and the second comparison result includes the following two cases: First, when the first comparison result and the second comparison result are consistent, that is, the hardware logic circuit has both functional correctness (the final output data result is consistent with the functional result of the functional reference model) and behavior correctness (the process, timing and interface protocol of generating the data result are consistent with the behavior reference model), it can be determined that the verification result of the calculation core is passed.
[0046] Second, when any one of the first comparison result and the second comparison result is inconsistent, it can be determined that the final verification result is not passed.
[0047] Here, specifically, when the first comparison result is inconsistent and the second comparison result is consistent, that is, the final output data result of the hardware logic circuit is incorrect, but its timing behavior is consistent with the behavior reference model, it can be determined that the verification result of the computing core is not passed. When the first comparison result is consistent and the second comparison result is inconsistent, that is, the functional output of the hardware logic circuit is consistent with the functional reference model, but the timing behavior is inconsistent with the behavior reference model, in this case, the traditional verification method will be determined as passed, but in the embodiment of the application, it will be determined as not passed, because in this case, the hardware logic circuit is correct in function calculation, but the timing is incorrect, there is a design defect, and it cannot be determined as passed. When the first comparison result and the second comparison result are both inconsistent, that is, the hardware logic circuit deviates from the design specification in both the function and the behavior dimensions, at this time, the verification result can be directly determined as not passed.
[0048] In the embodiment of the application, comparison is made from two dimensions of function and behavior, and the correctness of the hardware logic is determined only when both comparison results are consistent, which effectively breaks the possible "error symbiosis" relationship between the hardware logic circuit and the single functional reference model, eliminates the possibility of design defect escape caused by error consistency problems, and maximizes the completeness of the verification and the quality of the final chip design.
[0049] Based on the above embodiment, when the verification mode of the computing core is module verification, the method comprises: determining the hardware logic circuit, the functional reference model and the behavior reference model of each module in the computing core; inputting the excitation signal into the hardware logic circuit, the functional reference model and the behavior reference model of each module respectively to obtain the hardware circuit signal, the functional reference signal and the behavior reference signal output by the hardware logic circuit, the functional reference model and the behavior reference model of each module respectively; verifying each module of the computing core based on the hardware circuit signal, the functional reference signal and the behavior reference signal corresponding to each module to obtain the verification result of each module.
[0050] Specifically, in the complex chip design process, the verification work usually follows the strategy of divide and conquer, that is, each independent module in the computing core is verified first, and then the entire integrated circuit integrated by these modules is verified.
[0051] In detail, when the current verification mode is UT (Unit Test) verification, i.e., the verification mode of the computing core is module verification, the hardware logic circuit, the functional reference model and the behavior reference model of each module in the computing core can be determined first. It should be noted that the hardware logic circuit, the functional reference model and the behavior reference model of each module are also developed based on the design specification document of the computing core, but the micro-architecture and the functional description of each module in the design specification document are specifically referred to.
[0052] It should be noted that a computing core is usually composed of multiple modules, and module verification focuses on these modules. For example, a computing core of a GPU usually includes a fetch module, a decoding module, an arithmetic module, a storage module, etc.
[0053] In this verification mode, the verification object is no longer the entire computing core, but these modules. Therefore, before verification starts, the hardware logic circuit, the functional reference model and the behavior reference model of each module need to be determined. Then, the verification can be performed using the stimulus signal, i.e., for each module, the same stimulus signal can be applied to the hardware logic circuit, the functional reference model and the behavior reference model of the module, and after simulation and running, the hardware circuit signal, the functional reference signal and the behavior reference signal will be output respectively. Repeating this process can obtain the hardware circuit signal, the functional reference signal and the behavior reference signal corresponding to each module.
[0054] After that, independent verification of each module can be performed, i.e., for each module, the verification environment compares its hardware circuit signal with the functional reference signal and the behavior reference signal respectively, and determines the verification result of the module, i.e., pass or fail, based on the two comparison results. This process will be performed for all modules in the computing core, and finally the verification results of each module in the computing core can be obtained.
[0055] It should be noted that only when each module passes the verification, high-quality data basis can be provided for the next stage of integrated verification. If a problem is found in module verification, since the verification range is limited within a single module, the problem positioning is convenient and efficient.
[0056] Based on the above embodiment, when the verification mode of the computing core is integrated verification, the method comprises: determining the integrated circuit, the integrated functional reference model and the integrated behavior reference model of the computing core; the integrated circuit is obtained by connecting the hardware logic circuits of the modules in series, the integrated functional reference model is obtained by connecting the functional reference models of the modules in series, and the integrated behavior reference model is obtained by connecting the behavior reference models of the modules in series; The excitation signal is input to the integrated circuit, the integrated functional reference model and the integrated behavior reference model respectively, to obtain integrated hardware circuit signals, integrated functional reference signals and integrated behavior reference signals output by the integrated circuit, the integrated functional reference model and the integrated behavior reference model respectively. Based on the integrated hardware circuit signals, the integrated functional reference signals and the integrated behavior reference signals, the computing core is verified to obtain a verification result of the computing core.
[0057] Specifically, when the current verification mode is integrated verification, since the target of integrated verification is to verify whether the modules can work together and achieve the expected function and performance of the entire computing core after being combined, it is necessary to first build three key parts of the computing core level, i.e., the integrated circuit, the integrated functional reference model and the integrated behavior reference model.
[0058] The integrated circuit is a complete hardware logic circuit of the computing core, which can be obtained based on the hardware logic circuits of the modules in series. That is, the input and output ports of the modules can be connected to each other according to the topology structure defined in the design specification document, to form a complete integrated circuit.
[0059] The integrated functional reference model is a functional reference model at the computing core level. When the modules are verified, each module has its independent functional reference model. When integrated verification is performed, these independent functional reference models can be connected in series, i.e., in the manner of simulating hardware connection, to connect these functional reference models, thereby building an integrated model capable of simulating the function of the entire computing core, i.e., the integrated functional reference model.
[0060] The integrated behavior reference model is a behavior reference model at the computing core level. Similar to the construction method of the integrated circuit and the integrated functional reference model, the behavior reference models of the modules are connected in series according to the hardware connection relationship, to form an integrated model capable of simulating the timing behavior of the entire computing core, i.e., the integrated behavior reference model.
[0061] Here, through the "bottom-up" integration method, it is ensured that the integrated circuit, the integrated functional reference model and the integrated behavior reference model at the integrated level all originate from the verified and reliable sub-modules, thereby guaranteeing the quality of the starting point of integrated verification.
[0062] Subsequently, the stimulus signal can be input into the integrated circuit, the integrated functional reference model and the integrated behavior reference model respectively. In the integrated verification environment, the level of the stimulus signal is higher and the content is more complex. The stimulus signal is no longer a signal for a specific module interface, but an instruction sequence for the entire computing core. For example, the stimulus signal can be a test program containing multiple instruction types (arithmetic, logic, memory access, jump, etc.). The program is loaded and executed by the integrated circuit, the integrated functional reference model and the integrated behavior reference model. The verification environment needs to ensure that the three receive logically equivalent instructions. After simulation, the three generate integrated hardware circuit signals, integrated functional reference signals and integrated behavior reference signals representing the output of the entire computing core.
[0063] Then, the integrated hardware circuit signal, the integrated functional reference signal and the integrated behavior reference signal can be used to verify the computing core. That is, the comparator in the verification environment focuses on the final result and the process behavior of the computing core and performs double comparison. That is, the integrated hardware circuit signal (final result) is compared with the integrated functional reference signal, and the integrated hardware circuit signal (process behavior) is compared with the integrated behavior reference signal in the timing cycle. According to the comparison results in two dimensions, the verification result of the entire computing core is determined.
[0064] In the embodiment of the present application, by extending the modular three-party verification system to the integrated verification stage, a complete verification process from "part to total" is constructed, multi-granularity and multi-dimensional verification is realized, and the completeness and coverage of the verification process are fully guaranteed.
[0065] Based on the above embodiment, the behavior reference model constituting the integrated behavior reference model is provided with positioning information, and the positioning information is used to indicate the position of the corresponding module of the corresponding behavior reference model. Based on the integrated hardware circuit signal, the integrated functional reference signal and the integrated behavior reference signal, the computing core is verified to obtain the verification result of the computing core. Subsequently, the following steps are further included: If the verification result of the computing core is not passed, the positioning signal output based on the integrated behavior reference model is used for problem positioning. The positioning signal is time-synchronous with the integrated behavior reference signal and corresponds to the content of the positioning information.
[0066] Specifically, in the complex integrated verification environment, when the verification result is not passed, in order to facilitate the designer to quickly find the problem and then repair the problem, in the embodiment of the present application, positioning information can be set in each behavior reference model constituting the integrated behavior reference model, and the positioning information can correspond to the output path or internal critical path of the specific behavior reference model corresponding module. That is, when developing the behavior reference model of each module, in addition to realizing the behavior logic, additional positioning information needs to be embedded in the model. The positioning information can be a static and configurable identifier, which can indicate the module corresponding to each behavior reference model, and it can be defined in the model by parameter transmission and the like.
[0067] In detail, after obtaining the verification result of the calculation core, if the verification result is not passed, i.e. the verification fails, at this time, the positioning signal output by the integrated behavior reference model can be used for problem positioning. The positioning signal has two key characteristics, i.e. time sequence synchronization with the integrated behavior reference signal (the change of the positioning signal is synchronized with the time sequence of the integrated behavior reference signal output by the integrated behavior reference model), and correspondence with the positioning information content (being able to indicate the specific module).
[0068] In the embodiment of the present application, the positioning information is embedded in the behavior reference model, and the problem is positioned by the corresponding positioning signal, which can accurately reflect the start and end points of the problem in the case of verification failure, so as to quickly locate the problem area in the hardware logic circuit, greatly reduce the difficulty of problem positioning, shorten the time period of problem positioning, save the cost, and accelerate the development process of the chip.
[0069] The verification device of the calculation core in the chip design process provided by the present application is described below, and the verification device of the calculation core in the chip design process described below can be correspondingly referred to the verification method of the calculation core in the chip design process described above.
[0070] Figure 2 is a structural schematic diagram of the verification device of the calculation core in the chip design process provided by the present application, as Figure 2 shown, the device comprises: A determination unit 210 is configured to determine the hardware logic circuit, the function reference model and the behavior reference model of the calculation core to be verified, wherein the hardware logic circuit, the function reference model and the behavior reference model are all developed based on the design specification document of the calculation core; A processing unit 220 is configured to input the excitation signal into the hardware logic circuit, the function reference model and the behavior reference model respectively, and obtain the hardware circuit signal, the function reference signal and the behavior reference signal output by the hardware logic circuit, the function reference model and the behavior reference model respectively. The verification unit 230 is configured to verify the computing core based on the hardware circuit signal, the function reference signal and the behavior reference signal, and obtain a verification result of the computing core.
[0071] The verification device for the computing core in the chip design process provided by the application inputs the excitation signal into the hardware logic circuit, the function reference model and the behavior reference model of the computing core to be verified respectively, obtains the hardware circuit signal, the function reference signal and the behavior reference signal output by the three respectively, and verifies the computing core based on the hardware circuit signal, the function reference signal and the behavior reference signal, and obtains a verification result. The hardware logic circuit, the function reference model and the behavior reference model are all developed based on the design specification document of the computing core. The function reference model and the behavior reference model are introduced to perform synchronous verification with the hardware logic circuit, and a three-party reference verification system is constructed. The verification is performed based on the three-party reference verification system, the defects of the traditional scheme that the single reference model verification has error consistency and the verification result is not accurate and reliable are overcome, the completeness and coverage of the verification are greatly improved, the defects existing in the hardware design can be found more timely and accurately, and thus the verification quality and the success rate of the chip design are improved.
[0072] Based on the above embodiment, the verification unit 230 is configured to: compare the hardware circuit signal with the function reference signal to obtain a first comparison result; compare the hardware circuit signal with the behavior reference signal to obtain a second comparison result; determine the verification result of the computing core based on the first comparison result and the second comparison result.
[0073] Based on the above embodiment, the behavior logic of the behavior reference model is related to the timing of the hardware logic of the hardware logic circuit. The verification unit 230 is configured to: perform logical comparison on the hardware circuit signal and the behavior reference signal in a timing cycle to obtain a second comparison result.
[0074] Based on the above embodiment, when the verification mode of the computing core is module verification, the determination unit 210 is configured to: determine the hardware logic circuit, the function reference model and the behavior reference model of each module in the computing core; The processing unit 220 is configured to: input the excitation signal into the hardware logic circuit, the function reference model and the behavior reference model of each module respectively to obtain the hardware circuit signal, the function reference signal and the behavior reference signal output by the hardware logic circuit, the function reference model and the behavior reference model of each module respectively; The verification unit 230 is configured to: The verification unit 230 is configured to:
[0075] Based on the above embodiment, when the verification mode of the computing core is integrated verification, the determination unit 210 is configured to: determine an integrated circuit, an integrated functional reference model and an integrated behavior reference model of the computing core; the integrated circuit is obtained by connecting the hardware logic circuits of the modules in series, the integrated functional reference model is obtained by connecting the functional reference models of the modules in series, and the integrated behavior reference model is obtained by connecting the behavior reference models of the modules in series; The processing unit 220 is configured to: input an excitation signal into the integrated circuit, the integrated functional reference model and the integrated behavior reference model respectively, to obtain an integrated hardware circuit signal, an integrated functional reference signal and an integrated behavior reference signal output by the integrated circuit, the integrated functional reference model and the integrated behavior reference model respectively; The verification unit 230 is configured to: verify the computing core based on the integrated hardware circuit signal, the integrated functional reference signal and the integrated behavior reference signal, to obtain a verification result of the computing core.
[0076] Based on the above embodiment, each behavior reference model constituting the integrated behavior reference model is provided with positioning information, the positioning information being used to indicate the position of the corresponding module of the corresponding behavior reference model; the device further includes a problem positioning unit configured to: If the verification result of the computing core is not passed, the problem positioning unit is configured to perform problem positioning based on a positioning signal output by the integrated behavior reference model; the positioning signal is time-synchronous with the integrated behavior reference signal and corresponds to the content of the positioning information.
[0077] Based on the above embodiment, the verification unit 230 is configured to: If the first comparison result and the second comparison result are consistent, it is determined that the verification result of the computing core is passed; Otherwise, it is determined that the verification result of the computing core is not passed.
[0078] Figure 3 An example of an entity structure diagram of an electronic device is shown in FIG. 1. Figure 3As shown, the electronic device can include a processor 310, a communications interface 320, a memory 330, and a communications bus 340, wherein the processor 310, the communications interface 320, and the memory 330 complete communication with each other through the communications bus 340. The processor 310 can invoke a logical instruction in the memory 330 to execute a verification method of a computing core in a chip design process, the method comprising: determining a hardware logic circuit of a computing core to be verified, a functional reference model, and a behavior reference model; the hardware logic circuit, the functional reference model, and the behavior reference model are all developed based on a design specification document of the computing core; inputting an excitation signal to the hardware logic circuit, the functional reference model, and the behavior reference model respectively to obtain hardware circuit signals, functional reference signals, and behavior reference signals output by the hardware logic circuit, the functional reference model, and the behavior reference model respectively; verifying the computing core based on the hardware circuit signals, the functional reference signals, and the behavior reference signals to obtain a verification result of the computing core.
[0079] In addition, the logical instructions in the memory 330 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.
[0080] In another aspect, the present application also provides a computer program product, which comprises a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the verification method of the computing core in the chip design process provided by the above-mentioned methods, the method comprising: determining a hardware logic circuit, a functional reference model and a behavioral reference model of a computing core to be verified; the hardware logic circuit, the functional reference model and the behavioral reference model are all developed based on a design specification document of the computing core; inputting an excitation signal into the hardware logic circuit, the functional reference model and the behavioral reference model respectively to obtain hardware circuit signals, functional reference signals and behavioral reference signals output by the hardware logic circuit, the functional reference model and the behavioral reference model respectively; verifying the computing core based on the hardware circuit signals, the functional reference signals and the behavioral reference signals to obtain a verification result of the computing core.
[0081] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a verification method of a computing core in a chip design process provided by the above-mentioned methods, the method comprising: determining a hardware logic circuit, a functional reference model and a behavioral reference model of a computing core to be verified; the hardware logic circuit, the functional reference model and the behavioral reference model are all developed based on a design specification document of the computing core; inputting an excitation signal into the hardware logic circuit, the functional reference model and the behavioral reference model respectively to obtain hardware circuit signals, functional reference signals and behavioral reference signals output by the hardware logic circuit, the functional reference model and the behavioral reference model respectively; verifying the computing core based on the hardware circuit signals, the functional reference signals and the behavioral reference signals to obtain a verification result of the computing core.
[0082] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.
[0083] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0084] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for verifying computational cores during chip design, characterized in that, include: Determine the hardware logic circuit, functional reference model, and behavioral reference model of the computing core to be verified; The hardware logic circuit, the functional reference model, and the behavioral reference model are all developed based on the design specification document of the computing core. The excitation signal is input to the hardware logic circuit, the functional reference model and the behavioral reference model respectively to obtain the hardware circuit signal, functional reference signal and behavioral reference signal output by the hardware logic circuit, the functional reference model and the behavioral reference model respectively; The computing core is verified based on the hardware circuit signals, the functional reference signals, and the behavioral reference signals to obtain the verification results of the computing core.
2. The method for verifying computational cores during chip design according to claim 1, characterized in that, The verification of the computing core based on the hardware circuit signals, the functional reference signals, and the behavioral reference signals, to obtain the verification result of the computing core, includes: The hardware circuit signal is compared with the functional reference signal to obtain a first comparison result; The hardware circuit signal is compared with the behavioral reference signal to obtain a second comparison result; Based on the first comparison result and the second comparison result, the verification result of the computing core is determined.
3. The method for verifying computational cores during chip design according to claim 2, characterized in that, The behavioral logic of the behavioral reference model is time-dependent on the hardware logic of the hardware logic circuit. The step of comparing the hardware circuit signal with the behavioral reference signal to obtain a second comparison result includes: The hardware circuit signal and the behavioral reference signal are logically compared in terms of timing period to obtain a second comparison result.
4. The method for verifying computational cores during chip design according to any one of claims 1 to 3, characterized in that, When the verification mode of the computing core is module verification, the method includes: Determine the hardware logic circuit, functional reference model, and behavioral reference model of each module in the computing core; The excitation signal is input to the hardware logic circuit, functional reference model and behavioral reference model of each module respectively, and the hardware circuit signal, functional reference signal and behavioral reference signal output by the hardware logic circuit, functional reference model and behavioral reference model of each module are obtained respectively. Based on the hardware circuit signals, functional reference signals, and behavioral reference signals corresponding to each module, the modules of the computing core are verified to obtain the verification results of each module.
5. The method for verifying computational cores during chip design according to claim 4, characterized in that, When the verification mode of the computing core is integrated verification, the method includes: The integrated circuit, integrated functional reference model, and integrated behavioral reference model of the computing core are determined; the integrated circuit is obtained by connecting the hardware logic circuits of each module in series, the integrated functional reference model is obtained by connecting the functional reference models of each module in series, and the integrated behavioral reference model is obtained by connecting the behavioral reference models of each module in series. The excitation signal is input to the integrated circuit, the integrated functional reference model, and the integrated behavioral reference model respectively to obtain the integrated hardware circuit signal, integrated functional reference signal, and integrated behavioral reference signal output by the integrated circuit, the integrated functional reference model, and the integrated behavioral reference model respectively; The computing core is verified based on the integrated hardware circuit signals, the integrated functional reference signals, and the integrated behavioral reference signals to obtain the verification results of the computing core.
6. The method for verifying computational cores during chip design according to claim 5, characterized in that, Each behavior reference model constituting the integrated behavior reference model is provided with positioning information, which is used to indicate the position of the corresponding module of the corresponding behavior reference model. The process of verifying the computing core based on the integrated hardware circuit signals, the integrated functional reference signals, and the integrated behavioral reference signals to obtain the verification result of the computing core further includes: If the verification result of the computational core is unsuccessful, the problem is located based on the location signal output by the integrated behavior reference model; the location signal is time-synchronized with the integrated behavior reference signal and corresponds to the location information content.
7. The method for verifying computational cores during chip design according to claim 2 or 3, characterized in that, The step of determining the verification result of the computing core based on the first comparison result and the second comparison result includes: If both the first comparison result and the second comparison result are consistent, then the verification result of the computing core is determined to be passed; Otherwise, the verification result of the computational core is determined to be unsuccessful.
8. A verification device for computational cores during chip design, characterized in that, include: The determination unit is used to determine the hardware logic circuit, functional reference model, and behavioral reference model of the computing core to be verified. The hardware logic circuit, the functional reference model, and the behavioral reference model are all developed based on the design specification document of the computing core. The processing unit is used to input the excitation signal to the hardware logic circuit, the functional reference model and the behavioral reference model respectively, and obtain the hardware circuit signal, functional reference signal and behavioral reference signal output by the hardware logic circuit, the functional reference model and the behavioral reference model respectively; The verification unit is used to verify the computing core based on the hardware circuit signals, the functional reference signals, and the behavioral reference signals, and to obtain the verification result of the computing core.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the verification method for the computational core during the chip design process as described in any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method for verifying the computational core during the chip design process as described in any one of claims 1 to 7.