Semiconductor device manufacturing method and semiconductor device
By combining chemical mechanical polishing and wet etching, mask residues in split-gate transistor semiconductor devices are removed, solving the problem of trenches affecting finished product quality and improving finished product quality and manufacturing process stability.
Patent Information
- Application Number
- CN202511320513.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-12-19
AI Technical Summary
In the prior art, the geometric characteristics of the trenches affect the quality of the finished product during the processing of split-gate transistor semiconductor devices, resulting in unhealthy manufacturing processes and a decline in finished product quality.
A combination of chemical mechanical polishing and wet etching is used to first remove the outer oxide layer, then wet etching is used to remove the mask residue of the silicon nitride layer and oxide pad layer, followed by cleaning to ensure the wafer surface is clean.
It effectively eliminates the drifting effect of mask residue, improving the finished product quality of semiconductor devices and the health of the manufacturing process.
Smart Images
Figure CN121171884A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device manufacturing method and a semiconductor device. Background Technology
[0002] A split-gate transistor (SGT) is a transistor design that introduces a split structure in the gate region to improve performance. Its unique structural design gives it significant advantages in high performance, low power consumption, and high reliability, and it is commonly used in components such as non-volatile memories, memory cells, and floating-gate transistors. It has broad application prospects in power semiconductors, memory, consumer electronics, communications, new energy, and automotive electronics. However, similar to split-gate transistors, these semiconductor devices involve etching trenches on the wafer during fabrication. The geometry of these trenches can affect the semiconductor device fabrication process, leading to a decrease in the quality of the finished product.
[0003] In related technologies, the manufacturing methods for this type of semiconductor device still need to be optimized to compensate for the impact of trenches on the fabrication process and improve the quality of the finished product. Summary of the Invention
[0004] This application provides a semiconductor device manufacturing method and a semiconductor device. For an initial wafer with etched trenches, after removing the mask layer on the surface of the initial wafer, the mask residue of the silicon nitride layer is cleaned by wet etching to effectively remove the mask residue on the surface of the wafer to be cleaned, reduce the negative impact of the drift of the mask residue on the semiconductor device manufacturing process, and effectively improve the quality of the finished semiconductor device.
[0005] To achieve the above objectives, the main technical solutions adopted in this application include:
[0006] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising:
[0007] An initial wafer with a mask layer grown is provided; wherein trenches are etched in the initial wafer, and the mask layer comprises an oxide pad layer, a silicon nitride layer and an oxide outer layer sequentially stacked along the thickness direction of the initial wafer;
[0008] The surface of the initial wafer is subjected to chemical mechanical polishing until the silicon nitride layer is exposed to remove the oxide outer layer;
[0009] The surface of the initial wafer after chemical mechanical polishing is wet etched to remove the oxide pad layer and the silicon nitride layer, resulting in a wafer to be cleaned; wherein, the surface of the wafer to be cleaned contains mask residue of the silicon nitride layer;
[0010] The mask residue on the wafer to be cleaned is cleaned to obtain the target wafer;
[0011] The semiconductor device is formed on the target wafer by photolithography and etching.
[0012] The semiconductor device manufacturing method proposed in this application targets an initial wafer with a mask layer including an oxide pad layer, a silicon nitride layer, and an oxide outer layer, and with etched trenches. First, the surface of the initial wafer is chemically mechanically polished until the silicon nitride layer is exposed to remove the oxide outer layer. The exposed silicon nitride layer is then wet-etched to remove the mask residue from the oxide pad layer and the oxide outer layer, resulting in a wafer to be cleaned. Next, the wafer to be cleaned is cleaned to remove the mask residue from the silicon nitride layer on its surface, yielding the target wafer. Compared to related technologies, this application removes the mask residue from the silicon nitride layer on the surface of the wafer after mask layer removal, suppressing the unhealthy process conditions caused by the drift of the silicon nitride layer mask residue, and effectively improving the quality of the finished semiconductor device.
[0013] Optionally, the step of cleaning the mask residue on the wafer to be cleaned to obtain the target wafer includes:
[0014] The surface of the wafer to be cleaned is subjected to acid bath cleaning to remove any residual mask layer on the wafer;
[0015] After the acid bath cleaning reaction is completed, the surface of the wafer to be cleaned is washed with a chemical solution and dried to obtain the target wafer.
[0016] Optionally, the chemical solution used for cleaning the acid tank includes a phosphoric acid solution, wherein the concentration ratio of H3PO4 to H2O in the phosphoric acid solution is 85:1.
[0017] Optionally, the cleaning temperature when using the phosphoric acid solution for cleaning is 160°C.
[0018] Optionally, the cleaning time using the phosphoric acid solution is 40 seconds.
[0019] Optionally, the depth of the trench is greater than 1 micrometer.
[0020] Optionally, the surface of the initial wafer has a warpage with a negative value.
[0021] Optionally, the thickness of the oxide pad layer is to The thickness of the silicon nitride layer is to The thickness of the oxide outer layer is to
[0022] Optionally, the process of forming the semiconductor device on the target wafer by photolithography and etching includes:
[0023] A photoresist is deposited on the surface of the target wafer to form a photomask;
[0024] The etching positioning pattern is transferred to the surface of the photomask by photolithography, and the target wafer is etched according to the etching positioning pattern to form the semiconductor device.
[0025] Secondly, embodiments of this application provide a semiconductor device manufactured by any one of the methods described in the above embodiments. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0027] Figure 1 This is a step diagram of a semiconductor device manufacturing method provided in an embodiment of this application;
[0028] Figure 2a This is a schematic flowchart of a semiconductor device manufacturing method in an embodiment of this application;
[0029] Figure 2b This is a schematic flowchart of a semiconductor device manufacturing method in an embodiment of this application;
[0030] Figure 2c This is a schematic flowchart of a semiconductor device manufacturing method in an embodiment of this application;
[0031] Figure 2d This is a schematic flowchart of a semiconductor device manufacturing method in an embodiment of this application;
[0032] Figure 2e This is a schematic flowchart of a semiconductor device manufacturing method in an embodiment of this application;
[0033] Figure 3 This is a diagram illustrating the steps involved in obtaining the target wafer in an embodiment of this application.
[0034] Figure 4 This is a diagram illustrating the steps involved in forming a semiconductor device in an embodiment of this application;
[0035] Figure 5 This is a schematic flowchart of a semiconductor device manufacturing method in an embodiment of this application.
[0036] Figure reference numerals: 100. Initial wafer, 110. Trench, 120. Mask layer, 121. Oxide pad layer, 122. Silicon nitride layer, 123. Outer oxide layer, 124. Mask residue from the outer oxide layer, 125. Mask residue from the silicon nitride layer, 126. Mask residue from the oxide pad layer, 130. Photolithography mask, 200. Wafer to be cleaned, 300. Target wafer. Detailed Implementation
[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0042] A split-gate transistor (SGT) is a transistor design that introduces a split structure in the gate region to improve performance. Its unique structural design gives it significant advantages in high performance, low power consumption, and high reliability, and it is commonly used in components such as non-volatile memories, memory cells, and floating-gate transistors. It has broad application prospects in power semiconductors, memory, consumer electronics, communications, new energy, and automotive electronics. However, similar to split-gate transistors, these semiconductor devices involve etching trenches on the wafer during fabrication. The geometry of these trenches can affect the fabrication process, leading to a decrease in the quality of the finished semiconductor device. In related technologies, the manufacturing methods for this type of semiconductor device still need optimization to compensate for the impact of trenches on the fabrication process and improve the quality of the finished product.
[0043] To address the aforementioned problems, this application provides a semiconductor device manufacturing method and a semiconductor device. The method includes: providing an initial wafer with a mask layer grown thereon; wherein trenches are etched in the initial wafer, and the mask layer includes an oxide pad layer, a silicon nitride layer, and an oxide outer layer sequentially stacked along the thickness direction of the initial wafer; performing chemical mechanical polishing on the surface of the initial wafer until the silicon nitride layer is exposed to remove the oxide outer layer; performing wet etching on the surface of the chemically mechanically polished initial wafer to remove the oxide pad layer and the silicon nitride layer, obtaining a wafer to be cleaned; wherein mask residue of the silicon nitride layer exists on the surface of the wafer to be cleaned; cleaning the mask residue on the wafer to be cleaned to obtain a target wafer; and forming a semiconductor device on the target wafer by photolithography and etching.
[0044] The semiconductor device manufacturing method provided in this application targets an initial wafer with a mask layer including an oxide pad layer, a silicon nitride layer, and an oxide outer layer, and with etched trenches. First, the surface of the initial wafer is chemically mechanically polished until the silicon nitride layer is exposed to remove the oxide outer layer. Then, the exposed silicon nitride layer is wet-etched to remove the oxide pad layer and the mask residue of the oxide outer layer after removing the silicon nitride layer, resulting in a wafer to be cleaned. On this basis, the wafer to be cleaned is cleaned to remove the mask residue of the silicon nitride layer on the surface of the wafer to be cleaned, resulting in a target wafer.
[0045] Compared with related technologies, this application removes the mask residue of the silicon nitride layer on the surface of the wafer after the mask layer has been removed by cleaning it. This suppresses the unhealthy process caused by the drift of the mask residue of the silicon nitride layer, and effectively improves the finished product quality of semiconductor devices.
[0046] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0047] Reference Figure 1 As shown, the method includes:
[0048] S100. An initial wafer on which a mask layer has been grown is provided; wherein, trenches are etched in the initial wafer, and the mask layer includes an oxide pad layer, a silicon nitride layer and an oxide outer layer stacked sequentially along the thickness direction of the initial wafer.
[0049] S200. The surface of the initial wafer is chemically and mechanically polished until the silicon nitride layer is exposed to remove the oxide outer layer.
[0050] S300. The surface of the initial wafer after chemical mechanical polishing is wet etched to remove the oxide pad layer and silicon nitride layer, resulting in a wafer to be cleaned; wherein, the surface of the wafer to be cleaned contains a mask residue of the silicon nitride layer.
[0051] S400. Clean the mask residue on the wafer to be cleaned to obtain the target wafer.
[0052] S500. Semiconductor devices are formed on a target wafer through photolithography and etching.
[0053] Specifically, refer to Figure 2a As shown, this embodiment is applied to an initial wafer 100 with etched trenches 110. The initial wafer 100 can have one or more trenches 110, and the depth of each trench 110 is greater than its width, so that the trenches 110 can provide isolation for different functional regions in the semiconductor device in the depth direction. A mask layer 120 for providing protection is also grown on the surface of the initial wafer 100. The mask layer 120 includes an oxide pad layer 121, a silicon nitride layer 122 and an oxide outer layer 123 stacked sequentially on the surface of the initial wafer 100. The oxide pad layer 121 is on the side of the mask layer 120 closer to the initial wafer 100, the silicon nitride layer 122 is between the oxide pad layer 121 and the oxide outer layer 123, and the oxide outer layer 123 is on the side of the mask layer 120 away from the initial wafer 100. The oxide outer layer 123 is also used to fill the trenches 110 to improve the flatness of the trench openings. Understandably, the initial wafer 100 can be used to fabricate semiconductor devices containing multiple functional regions that require isolation between different functional regions, such as split-gate transistors. It should be noted that for trenches 110 whose depth is greater than their width, due to limitations in the trench 110 etching process, the opening of each trench 110 is not completely flat, resulting in a non-planar surface on the initial wafer 100. This affects the polishing effect of the mask layer 120, leading to mask residue 124 of an oxide outer layer on the surface of the silicon nitride layer 122 after chemical mechanical polishing, thus affecting the final quality of the semiconductor device.
[0054] Reference Figure 2bAs shown, the surface of the initial wafer 100 is subjected to chemical mechanical polishing (CMP) to gradually remove the oxide outer layer 123, and polishing is stopped when the silicon nitride layer 122 is exposed. It is understood that, compared with conventional physical polishing, CMP can polish the non-planar surface of the initial wafer 100 at a consistent polishing speed, improving the stability of the polishing process and ensuring a high degree of surface flatness after polishing. It should be noted that because trenches 110 are etched in the initial wafer 100, the trench structure causes the surface of the initial wafer 100 to exhibit a non-planar characteristic, resulting in non-planar areas on some parts of the initial wafer 100 surface. In this case, the oxide pad layer 121 and silicon nitride layer 122 grown on the surface of the initial wafer 100 also correspondingly exhibit non-planar areas, leading to the fact that the oxide outer layer 123 corresponding to these non-planar areas is not removed after polishing, resulting in oxide outer layer mask residue 124 on some parts of the silicon nitride layer 122 surface.
[0055] Reference Figure 2c As shown, after grinding is completed and the silicon nitride layer 122 is exposed, the silicon nitride layer 122 is removed by wet etching, exposing the oxide pad layer 121 so that the subsequent oxide pad layer 121 removal process can be performed. It is understood that during the removal of the silicon nitride layer 122, the wet etching solution has a high selectivity for silicon nitride, resulting in a high etching rate for the silicon nitride layer 122 and a lower etching rate for the oxide pad layer 121. Only the silicon nitride layer 122 is removed during the etching process. It should be noted that during the removal of the silicon nitride layer 122, due to the presence of mask residue 124 on the outer oxide layer, part of the silicon nitride layer 122 is covered by the mask residue 124 and cannot be wet etched, resulting in a portion of the oxide pad layer 121 having a silicon nitride layer mask residue 125 on its surface after wet etching.
[0056] Reference Figure 2d As shown, after removing the silicon nitride layer 122, wet etching is performed on the surface of the initial wafer 100 to remove the oxide pad layer 121, thereby completely removing the mask layer 120 on the surface of the initial wafer 100, resulting in the wafer 200 to be cleaned. It should be noted that if a mask residue 125 of the silicon nitride layer exists on a portion of the surface of the oxide pad layer 121, after removing the oxide pad layer 121 and the mask residue 124 of the outer oxide layer, the mask residue 125 of the silicon nitride layer separates from the surface of the wafer 200 to be cleaned. The mask residue 125 will be lifted up during the semiconductor device manufacturing process and float on the surface of the wafer 200 to be cleaned, thus affecting the health of the manufacturing process, causing defects on the surface of the wafer 200 to be cleaned, and affecting the quality of the finished semiconductor device.
[0057] In some embodiments, the solution used for wet etching to remove the oxide pad 121 is a hydrogen fluoride solvent, wherein the hydrogen fluoride solvent is a 100:1 ratio of HF and H2O. It is understood that hydrogen fluoride has a high selectivity for oxides and can react rapidly with oxides, resulting in a high etching rate for the oxide pad 121 and the mask residue 124 of the oxide outer layer, while having a lower etching rate for the silicon nitride layer 122. This effectively removes the oxide pad 121 and the mask residue 124 of the oxide outer layer without affecting the silicon nitride layer 122.
[0058] Furthermore, after wet etching using hydrogen fluoride solvent, the initial wafer 100 is further cleaned using a standard cleaning solvent to effectively remove contaminants and residues from its surface, ensuring the cleanliness of the initial wafer 100 surface to obtain the wafer 200 to be cleaned. The standard cleaning solvent includes NH4OH, H2O2, and H2O. NH4OH helps dissolve and remove organic contaminants or residues from the surface of the initial wafer 100, while H2O2 oxidizes and decomposes contaminants or residues on the surface of the initial wafer 100, thereby effectively cleaning the surface of the initial wafer 100.
[0059] Reference Figure 2e As shown, for the wafer 200 to be cleaned, its surface is cleaned to specifically remove the floating mask residue 125 on the surface of the wafer 200, resulting in the target wafer 300. It is understood that during the cleaning process, the mask residue 125 of the silicon nitride layer reacts with the cleaning solution, dissolving and rinsing it away. This effectively removes the mask residue 125 from the silicon nitride layer, reducing the negative impact of the floating mask residue 125 on the semiconductor manufacturing process and improving the quality of the finished semiconductor device.
[0060] Furthermore, based on the target wafer 300, multiple functional regions of the semiconductor device are formed in the target wafer 300 through further photolithography and etching, thereby forming the desired semiconductor device. It is understood that by cleaning the wafer 200 to be cleaned, the obstruction and contact of contaminants or residues on the surface of the target wafer 300 are avoided, reducing the negative impact on the semiconductor device manufacturing process, ensuring the health of the semiconductor manufacturing process, and thus improving the quality of the finished semiconductor device.
[0061] The semiconductor device manufacturing method provided in this embodiment targets an initial wafer with a mask layer including an oxide pad layer, a silicon nitride layer, and an oxide outer layer, and with etched trenches. First, the surface of the initial wafer is chemically mechanically polished until the silicon nitride layer is exposed to remove the oxide outer layer. Then, the exposed silicon nitride layer is wet-etched to remove the oxide pad layer and the mask residue of the oxide outer layer after removing the silicon nitride layer, resulting in a wafer to be cleaned. On this basis, the wafer to be cleaned is cleaned to remove the mask residue of the silicon nitride layer on the surface of the wafer to be cleaned, resulting in the target wafer.
[0062] Compared with related technologies, this application removes the mask residue of the silicon nitride layer on the surface of the wafer after the mask layer has been removed by cleaning it. This suppresses the unhealthy process caused by the drift of the mask residue of the silicon nitride layer, and effectively improves the finished product quality of semiconductor devices.
[0063] Reference Figure 3 As shown, in one embodiment of this application, cleaning mask residue on a wafer to be cleaned to obtain a target wafer includes:
[0064] S410. Perform acid bath cleaning on the surface of the wafer to be cleaned to remove any remaining mask layer on the wafer.
[0065] S420. After the acid bath cleaning reaction is completed, the surface of the wafer to be cleaned is washed with a chemical solution and dried to obtain the target wafer.
[0066] Specifically, after removing the mask layer 120 and obtaining the wafer 200 to be cleaned, the wafer 200 to be cleaned is placed in an acid bath, the temperature inside the acid bath is set to a preset temperature, and a chemical solution heated to the preset temperature is injected into the acid bath to clean the surface of the wafer 200 to be cleaned at the preset temperature, thereby removing the mask residue 125 present on the wafer 200 to be cleaned.
[0067] Furthermore, after the reaction process in the acid bath is completed, the surface of the wafer 200 to be cleaned is rinsed with plasma water to remove any residual chemical solutions and reaction products, ensuring the cleanliness of the wafer 200 surface. After rinsing, the surface of the wafer 200 to be cleaned is dried to prevent any residual plasma water from affecting the wafer 200, thereby obtaining the target wafer 300.
[0068] As one embodiment of this application, the chemical solution used for acid tank cleaning includes a phosphoric acid solution, wherein the concentration ratio of H3PO4 to H2O in the phosphoric acid solution is 85:1.
[0069] As one embodiment of this application, the cleaning temperature when using phosphoric acid solution for cleaning is 160°C.
[0070] In one embodiment of this application, the cleaning time using phosphoric acid solution is 40 seconds.
[0071] Specifically, phosphoric acid exhibits a high selectivity for silicon nitrides, enabling it to react rapidly with the silicon nitride layer 122 to effectively remove mask residue 125 of the silicon nitride layer on the surface of the wafer 200 to be cleaned. During acid bath cleaning, the temperature of the phosphoric acid solution is controlled at 160°C, which enhances the reaction rate of the acid bath cleaning process. Furthermore, the concentration ratio of H3PO4 to H2O in the phosphoric acid solution is 85:1, and the cleaning time is set to 40 seconds, ensuring the selectivity and controllability of the acid bath cleaning and effectively reducing damage to the surface of the wafer 200 to be cleaned by the phosphoric acid solution.
[0072] As one embodiment of this application, the depth of the trench is greater than 1 micrometer.
[0073] Specifically, trenches 110 with a depth greater than 1 micrometer are etched in the initial wafer 100. The trenches 110 provide isolation between different functional regions in the semiconductor device, improving the stability and performance of the semiconductor device. In addition, by extending the trenches 110 in the thickness direction of the initial wafer 100, the area of the initial wafer 100 required to manufacture the semiconductor device is reduced, thus promoting the miniaturization of the semiconductor device.
[0074] As one embodiment of this application, the surface of the initial wafer has a warpage with a negative value.
[0075] Specifically, one or more trenches 110 can be etched in the initial wafer 100, each trench 110 having a depth greater than its width. However, due to limitations in the trench 110 etching process, the opening of each trench 110 is not perfectly flat, resulting in a negative warpage on the surface of the initial wafer 100, causing it to exhibit a non-planar characteristic. Understandably, with a negative warpage, the surface of the initial wafer 100 exhibits a lower center and higher periphery; that is, the location where the trenches 110 are etched on the surface of the initial wafer 100 is lower than the surrounding area. In this case, after polishing, oxide outer layer mask residue 124 is prone to appear at the edges of the initial wafer 100, affecting the health of subsequent semiconductor manufacturing processes.
[0076] As one embodiment of this application, the thickness of the oxide pad layer is: to The thickness of the silicon nitride layer is to The thickness of the oxide outer layer is to
[0077] Specifically, in mask layer 120, oxide pad layer 121 is in direct contact with the surface of initial wafer 100, providing a buffer between initial wafer 100 and silicon nitride layer 122, reducing stress differences between the surface of silicon nitride layer 122 and initial wafer 100, and lowering the probability of mask layer 120 detachment. It is understood that a thickness less than... The oxide pad 121 is too thin to relieve stress and cannot effectively buffer the load, while a thickness greater than 121 is insufficient. The oxide pad 121 is too thick, which increases material cost and process time cost and causes unnecessary losses in the fabrication of semiconductor devices.
[0078] Furthermore, since the silicon nitride layer 122 is made of a different material than the oxide pad layer 121 and the outer oxide layer 123, it needs to be removed using different methods. Therefore, it can serve as a protective layer in the semiconductor processing flow, reducing the impact of steps such as trench 110 etching on the surrounding initial wafer 100 surface. It is understood that when the trench 110 is deep, the thickness is less than... The silicon nitride layer 122 cannot provide effective protection during the etching of trench 110, while the thickness is greater than Excessive stress in the silicon nitride layer 122 can cause warping of the initial wafer 100, affecting the final quality of the semiconductor device. Furthermore, an excessively thick silicon nitride layer 122 will result in additional material and processing time costs.
[0079] Furthermore, the oxide outer layer 123 is located on the side of the mask layer 120 away from the initial wafer 100, providing top-layer protection for both the mask layer 120 and the initial wafer 100, while also serving as a transfer layer for the trench 110 etching positioning pattern. It is understood that the thickness is less than... The oxide outer layer 123 cannot provide effective protection for the mask layer 120 and the initial wafer 100, while the thickness is greater than The excessively thick oxide outer layer 123 increases the stress in the mask layer 120, affecting the finished quality of the semiconductor device. In addition, an excessively thick oxide outer layer 123 will also cause additional increases in material costs and process time costs.
[0080] Reference Figure 4 As shown, in one embodiment of this application, a semiconductor device is formed on a target wafer by photolithography and etching, including:
[0081] S510. Photoresist is deposited on the surface of the target wafer to form a photomask.
[0082] S520. The etching positioning pattern is transferred to the surface of the photomask by photolithography, and the target wafer is etched according to the etching positioning pattern to form a semiconductor device.
[0083] Reference Figure 5 As shown, after obtaining the target wafer 300, photoresist is deposited on the surface of the target wafer 300 to form a photomask 130 for transferring the etching positioning pattern. The etching positioning pattern is transferred to the surface of the photomask 130 via photolithography, thereby performing trench etching on the target wafer 300 according to the etching positioning pattern for further processing. It can be understood that after multiple processing steps according to actual needs, multiple required functional regions can be formed in the target wafer 300, forming the corresponding semiconductor device.
[0084] This application also provides a semiconductor device manufactured by any one of the methods described in the above embodiments.
[0085] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0086] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0087] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
[0088] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: An initial wafer with a mask layer grown is provided; wherein trenches are etched in the initial wafer, and the mask layer comprises an oxide pad layer, a silicon nitride layer and an oxide outer layer sequentially stacked along the thickness direction of the initial wafer; The surface of the initial wafer is subjected to chemical mechanical polishing until the silicon nitride layer is exposed to remove the oxide outer layer; The surface of the initial wafer after chemical mechanical polishing is wet etched to remove the oxide pad layer and the silicon nitride layer, resulting in a wafer to be cleaned; wherein, the surface of the wafer to be cleaned contains mask residue of the silicon nitride layer; The mask residue on the wafer to be cleaned is cleaned to obtain the target wafer; The semiconductor device is formed on the target wafer by photolithography and etching.
2. The method according to claim 1, characterized in that, The step of cleaning the mask residue on the wafer to be cleaned to obtain the target wafer includes: The surface of the wafer to be cleaned is subjected to acid bath cleaning to remove any residual mask layer on the wafer; After the acid bath cleaning reaction is completed, the surface of the wafer to be cleaned is washed with a chemical solution and dried to obtain the target wafer.
3. The method according to claim 2, characterized in that, The chemical solution used for cleaning acid tanks includes a phosphoric acid solution, wherein the concentration ratio of H3PO4 to H2O in the phosphoric acid solution is 85:
1.
4. The method according to claim 3, characterized in that, The cleaning temperature when using the phosphoric acid solution for cleaning is 160°C.
5. The method according to claim 3, characterized in that, The cleaning time using the phosphoric acid solution is 40 seconds.
6. The method according to claim 1, characterized in that, The depth of the trench is greater than 1 micrometer.
7. The method according to claim 1, characterized in that, The surface of the initial wafer has a warpage with a negative value.
8. The method according to claim 1, characterized in that, The thickness of the oxide pad layer is to The thickness of the silicon nitride layer is to The thickness of the oxide outer layer is to 9. The method according to claim 1, characterized in that, The process of forming the semiconductor device on the target wafer through photolithography and etching includes: A photoresist is deposited on the surface of the target wafer to form a photomask; The etching positioning pattern is transferred to the surface of the photomask by photolithography, and the target wafer is etched according to the etching positioning pattern to form the semiconductor device.
10. A semiconductor device, characterized in that, Manufactured by the method of any one of claims 1 to 9.