MOS (Metal Oxide Semiconductor) chip heat dissipation packaging structure and packaging process thereof

Abstract

The invention discloses a metal oxide semiconductor (MOS) chip heat dissipation packaging structure and a packaging process thereof, the structure comprises a bare chip which is packaged in a packaging body, electrodes are arranged on the A surface and the opposite B surface of the bare chip, the electrode on the A surface of the bare chip is exposed out of the packaging body through a pin A, and a wiring layer is electroplated on the electrode on the B surface of the bare chip; one end of the side metal layer is electrically connected with the wiring layer, the other opposite end of the side metal layer is electrically connected with a pin B, and the pin A and the pin B are flush and exposed out of the same surface of the packaging body; the insulating layer is arranged on the surface, away from the bare chip B-surface electrode, of the wiring layer, insulates the electrical property of the bare chip B-surface electrode and conducts heat of the bare chip B-surface electrode, and the orthographic projection of the insulating layer on the bare chip B-surface completely covers the bare chip B-surface; the heat dissipation layer is arranged on the surface, away from the wiring layer, of the insulating layer; the bare chip is an MOS chip, a drain electrode is arranged on the A surface of the bare chip, and a source electrode and a gate electrode are arranged on the B surface of the bare chip. According to the packaging structure, double-surface efficient heat dissipation is achieved, electric transmission of a heat dissipation layer is avoided, and safe use of a product is guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and particularly relates to a heat dissipation packaging structure for a MOS chip and its packaging process. Background Technology

[0002] MOS chips (metal-oxide-semiconductor chips) are semiconductor devices based on MOSFETs (metal-oxide-semiconductor field-effect transistors) as their core structure. They have the advantages of high integration, low power consumption, and fast switching speed, and are widely used in analog circuits, digital circuits, and power electronics. When packaging MOS chips, heat dissipation performance needs to be considered, because temperature is a core factor affecting the performance, reliability, and lifespan of MOS chips. The heat dissipation effect of the packaging structure directly affects the performance of MOS chips.

[0003] During the packaging process of MOS chips, electrical leads need to be brought out at the chip electrodes. The front of the MOS chip has the source and gate, and the back has the drain. The electrodes occupy a large area of ​​the chip surface. While bringing out the electrical leads of the chip, they also need to perform the function of heat dissipation. In the existing MOS chip packaging structure, after the chip is encapsulated, laser drilling is required to expose the electrodes before wiring and heat dissipation. This can easily damage the electrodes. Moreover, after the electrical leads are brought out by traditional wiring, the heat dissipation area is small and thermal resistance accumulates in the package. Summary of the Invention

[0004] To address the problems in the prior art, the present invention provides a heat dissipation packaging structure for a MOS chip and its packaging process.

[0005] To achieve the above objectives, the present invention proposes a heat dissipation packaging structure for a MOS chip, comprising: The bare die is encapsulated in a package. Electrodes are provided on both side A and the opposite side B of the bare die. The electrode on side A of the bare die is exposed outside the package through lead A, and the electrode on side B of the bare die is plated with a wiring layer. The side metal layer is electrically connected to the wiring layer at one end and to pin B at the other end. Pins A and B are flush with each other and exposed on the same surface of the package. An insulating layer is disposed on the surface of the wiring layer away from the electrode on the B side of the die. It insulates the electrical properties of the electrode on the B side of the die and conducts heat from the electrode on the B side of the die. The orthogonal projection of the insulating layer onto the B side of the die completely covers the B side of the die. The heat dissipation layer is located on the surface of the insulation layer away from the wiring layer.

[0006] Furthermore, the die is a MOS chip, with a drain electrode on side A and a source and gate electrode on side B. The wiring layer electrically rewires and leads out the source and gate electrodes on side B of the die.

[0007] Furthermore, the side metal layer is a pillar, which is electrically connected to the wiring layer of the electrode on the B side of the bare die, and electrically pulls the electrode on the B side of the bare die to the surface of the package where the A side of the bare die is located through the pin B.

[0008] Furthermore, the side metal layer serves as a sidewall, which covers the side of the bare die after being encapsulated with a material spaced apart from the side of the die.

[0009] Furthermore, the heat dissipation layer completely covers one, three, or five surfaces of the package.

[0010] A MOS chip heat dissipation packaging process includes the following steps: Die mounting steps: A substrate is provided, the surface of which is covered with metal foil. The die A side is mounted with the metal foil facing the substrate. The first encapsulation is performed. After the die is completely encapsulated, the electrode on the die B side is exposed, forming an encapsulation layer 1. Etching and electroplating: Vertical etching of the encapsulation layer one forms a groove, exposing the metal foil surface at the bottom of the groove. Metal is electroplated on the inner wall of the groove, and a wiring layer is electroplated on the B side of the bare die. The wiring layer is connected to the metal electroplated on the inner wall of the groove. A second encapsulation is continued on the basis of the first encapsulation. After the wiring layer is completely encapsulated and the inside of the groove is filled, the top surface of the wiring layer is exposed, forming the second encapsulation layer. Cover with insulating layer: Cover the surface of the wiring layer away from the B-side electrode of the bare die with an insulating layer to insulate the electrical properties of the B-side electrode of the bare die and conduct heat to the B-side electrode of the bare die. The orthogonal projection of the insulating layer on the B-side of the bare die completely covers the B-side of the bare die. Heat dissipation layer: A heat dissipation layer is covered on the surface of the insulation layer away from the wiring layer. On the basis of the second encapsulation layer, the surface of the heat dissipation layer is further encapsulated and exposed to form the third encapsulation layer. Forming pins A and B: Peel off the substrate, flip the whole thing over, etch the surface of the metal foil to form pins A and B, separate the metal inside the etched groove into the side metal layer, expose the electrode on the A side of the bare die through pin A outside the package body, the side metal layer is electrically connected to pin B, continue to encapsulate pins A and B, and form encapsulation layer four on the surface of pins A and B, encapsulation layers one, two, three and four constitute the package body, and finally cut into product units.

[0011] Furthermore, in the die mounting step, the die is a MOS chip, with a drain electrode on side A and a source and gate electrode on side B. The wiring layer formed in the etching and electroplating step electrically rewires and leads out the source and gate electrodes on side B of the die.

[0012] Furthermore, in the step of forming pins A and B, the side metal layer is a pillar, which is electrically connected to the wiring layer of the electrode on the B side of the bare die, and electrically pulls the electrode on the B side of the bare die to the surface of the package where the A side of the bare die is located through pin B.

[0013] Furthermore, in the step of forming pin A and pin B, the side metal layer is a sidewall, which is covered by encapsulant after being spaced apart from the side of the bare die.

[0014] Furthermore, in the step of covering the heat dissipation layer, the heat dissipation layer completely covers one, three, or five surfaces of the package.

[0015] Beneficial effects of this invention: 1. The wiring layer and side metal layer pull the electrode on the B side of the bare die to the corresponding package surface on the A side of the bare die, and each pin is flush with the same surface of the package, which facilitates subsequent mounting in the working area. 2. Heat from the electrode on side A of the bare die is dissipated directly through pin A, while heat from the electrode on side B is dissipated through the insulating layer and the heat dissipation layer. The heat dissipation area is large, the package structure provides double-sided heat dissipation, and the heat dissipation layer and wiring layer are electrically isolated by the insulating layer to avoid electrical transmission of heat through the heat dissipation layer and ensure safe use of the product. 3. The outermost heat dissipation layer of the package forms a shield while dissipating heat, blocking electromagnetic interference and electromagnetic radiation. Attached Figure Description

[0016] Figures 1-3 This is a cross-sectional view of the die mounting steps in a MOS chip heat dissipation packaging process according to the present invention; Figures 4-6 This is a cross-sectional view of the etching and electroplating steps in a MOS chip heat dissipation packaging process according to the present invention. Figure 7 This is a cross-sectional view of the insulating layer covering step in a MOS chip heat dissipation packaging process according to the present invention; Figure 8 This is a cross-sectional view of the heat dissipation layer covering step in a MOS chip heat dissipation packaging process according to the present invention; Figures 9-11 This is a cross-sectional view of the pin formation steps in a MOS chip heat dissipation packaging process according to the present invention; Figures 12-14 This is a cross-sectional view of a MOS chip heat dissipation packaging structure according to the present invention.

[0017] In the diagram: 1. Metal foil; 2. Bare die; 3. Encapsulation layer one; 4. Groove; 5. Wiring layer; 6. Encapsulation layer two; 7. Insulating layer; 8. Heat dissipation layer; 9. Encapsulation layer three; 10. Pin A; 11. Pin B; 12. Encapsulation layer four; 13. Package body; 14. Side metal layer. Detailed Implementation

[0018] The present invention will now be described in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout.

[0019] The directional terms used in this invention, such as up, down, left, right, front, back, inside, outside, front, back, side, etc., are merely for reference to the accompanying drawings. The embodiments and directional terms used in the following description with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Furthermore, the various specific processes and materials provided in this invention are examples that those skilled in the art will recognize for the application of other processes and / or the use of other materials.

[0020] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a MOS chip heat dissipation packaging structure and its packaging process proposed in this invention. Example 1

[0021] The process specifically includes the following steps: Bare die 2 mounting: Provides a commonly used resin substrate in the art, with a metal foil 1 (e.g.) covering the surface of the substrate. Figure 1 As shown), the thickness of metal foil 1 is customized according to product design requirements. Metal foil 1 can be copper foil. The substrate is placed horizontally with the surface of metal foil 1 facing upwards. The A side of bare sheet 2 is mounted with metal foil 1 facing upwards (the A and B sides of bare sheet 2 are not shown in the attached diagram). Figure 2 (As shown).

[0022] The die 2 can be a MOS chip. The A side of the die 2 is provided with a drain electrode (D), and the B side of the die 2 is the opposite side of the A side. The B side of the die 2 is provided with a source electrode (S) and a gate electrode (G). Depending on the surface bearing capacity of the substrate, one or more uniformly arranged dies 2 can be mounted on its surface. This invention takes mounting four as an example.

[0023] The first encapsulation uses an encapsulating material such as epoxy resin to completely encapsulate the bare die 2. Then, the B-side electrode of the bare die 2 is exposed through grinding or other methods. After the encapsulating material cures, an encapsulation layer 3 is formed. The encapsulation surface is horizontal and flat (e.g., ...). Figure 3 (As shown).

[0024] Etching and electroplating: Vertical etching is performed at the corresponding positions of the encapsulation layer 3 to form grooves 4, the bottom of which exposes the surface of the metal foil 1 (e.g., Figure 4 As shown), the width of the groove 4 and the height of the encapsulation layer 3 satisfy the following condition: 0.3 of the height of the encapsulation layer 3 ≤ the width of the groove 4 ≤ 0.35 of the height of the encapsulation layer 3, so as to ensure a certain width of the groove 4. By controlling the precise mask coverage, electroplating solution composition, current density, etc., the inner wall of the groove 4 is electroplated with metal, while the groove 4 is not filled with metal.

[0025] Metal is electroplated on the inner wall of the groove 4, and the bottom end of the metal on the inner wall of the groove 4 is integrated with the metal foil 1. A wiring layer 5 is electroplated on the B side of the bare die 2, and the wiring layer 5 is integrated with the metal electroplated on the inner wall of the groove 4. The wiring layer 5 transfers the electrical properties of the B-side electrodes of the bare die 2 to the metal foil 1 through the corresponding metal electroplated on the inner wall of the groove 4 (e.g., ...). Figure 5 (As shown).

[0026] Then, using encapsulating material, a second encapsulation is performed on top of the first encapsulation layer 3, completely encapsulating the wiring layer 5 and filling the interior of the groove 4. Afterwards, the top surface of the wiring layer 5 is exposed through grinding or other methods, forming the second encapsulation layer 6 (e.g., ...). Figure 6 (As shown).

[0027] Insulating layer 7: An insulating layer 7 is applied to the surface of the B-side electrode of the wiring layer 2 away from the bare die 2 (e.g., Figure 7 As shown), the insulating layer 7 can be a thin plate made of insulating and thermally conductive material, such as a ceramic thin plate (active metal brazing ceramic substrate), which has strong insulation, stable thermal conductivity and reliable chemical properties. The insulating layer 7 is covered on the surface of the B-side electrode of the wiring layer 5 away from the bare die 2 by thermally conductive insulating adhesive. The insulating layer 7 is thermally conductive but not electrical.

[0028] An insulating layer 7 of the appropriate size can be fabricated before the process flow. Using an active solder containing titanium, zirconium, etc. (such as Ti / Ag-Cu solder), the ceramic substrate (commonly silicon nitride, aluminum nitride, etc.) is metallurgically bonded to the copper layer at a temperature below 800°C. The active metal can chemically react with the ceramic surface to form a stable interface layer, which solves the contradiction of the large difference in thermal expansion coefficients between ceramic and copper, avoids the impact of the difference in expansion coefficients on the wiring layer, and at the same time creates an efficient heat dissipation channel. The insulating layer 7 covers the surface of the wiring layer 5. The heat generated by the bare die 2 is conducted to the wiring layer 5 by the electrodes, and then quickly diffused through the insulating layer 7 and transferred to the heat dissipation structure, avoiding local heat accumulation inside the package 13.

[0029] To ensure the transfer of electrode heat, wiring layer 5 can be electroplated to cover the corresponding electrode surface and fan out the electrode electrical properties. Insulating layer 7 can insulate the electrical properties of the B-side electrode of bare die 2 and conduct the heat of the B-side electrode of bare die 2, so that the electrical properties of the B-side electrode of bare die 2 are conducted by wiring layer 5 and the heat is conducted by insulating layer 7. The orthographic projection of insulating layer 7 on the B-side of bare die 2 completely covers the B-side of bare die 2 to ensure heat transfer.

[0030] Heat dissipation layer 8: Heat dissipation layer 8 is covered on the surface of insulating layer 7 away from wiring layer 5. Heat dissipation layer 8 is also adhered to the surface of insulating layer 7 away from wiring layer 5 by insulating thermally conductive adhesive. Commonly used insulating thermally conductive adhesives in this field include epoxy thermally conductive insulating adhesive or silicone thermally conductive insulating adhesive.

[0031] The heat dissipation layer 8 completely covers the surface of the insulation layer 7. A third encapsulation is then performed on top of the second encapsulation layer 6, completely encapsulating both the heat dissipation layer 8 and the insulation layer 7. The top surface of the encapsulation is then ground until the surface of the heat dissipation layer 8 is exposed. This exposed surface is the surface of the heat dissipation layer 8 furthest from the insulation layer 7. After the encapsulation material cures, a third encapsulation layer 9 is formed (e.g., ...). Figure 8 (As shown).

[0032] The heat dissipation layer 8 can be electroplated onto the surface of the package 13. Other methods of setting the package 13 on the surface are also within the scope of protection of this invention and are not limited thereto.

[0033] Forming pins A10 and B11: Peel off the substrate and flip the entire encapsulation over so that surface A of the bare die 2 faces upwards, exposing the metal foil 1 (e.g., Figure 9 As shown), the surface of the metal foil 1 is etched to form pins A10 and B11. The etching process is also a commonly used process in the field. In the etching and electroplating step, the groove 4 is etched and the inner wall is electroplated with metal. The metal is electroplated together with the metal foil 2. After etching the metal foil 1, etching continues. The metal on the bottom inner wall of the groove 4 is separated, so that the metal on the inner wall of the groove 4 is separated into the side metal layer 14.

[0034] A portion of the metal foil 1 is etched away using an etching process. Parameters such as the etching rate and etching solution composition are controlled to ensure that the corresponding area of ​​the metal foil 1 retains the pins A10 and B11 (e.g., ...). Figure 10 As shown), pin A10 covers the A-side electrode of die 2. The A-side electrode of die 2 is exposed outside the package 13 through pin A10. Pin B11 is next to pin A10. The surfaces of pin A10 and pin B11 are on the same horizontal plane. Pin B11 is electrically connected to the side metal layer 14.

[0035] The bare die 2 electrode is directly attached to the metal foil 1, and the metal foil 1 is etched to form pins A10 and B11. There is no need to use laser etching to expose the encapsulation material and then electroplate the pins. This avoids the adverse effects on the electrodes when laser etching exposes the electrodes, resulting in less damage to the product during the process and more stable and reliable product performance.

[0036] In this embodiment, the etched groove 4 is short in length, that is, the groove 4 is only formed in a local position in the package 13. After being separated into a side metal layer 14, one end of the side metal layer 14 is electrically connected to the wiring layer 5, and the other end is electrically connected to the pin B11. The side metal layer 14 is a pillar. The groove 4, pillars, etc. are set according to the number of electrodes of the bare die 2, and are electrically connected to the wiring layer 5 of the B-side electrode of the bare die 2 respectively. The B-side electrode of the bare die 2 is electrically pulled from the wiring layer 5 to the surface of the package 13 where the A-side of the bare die 2 is located through the pin B11.

[0037] Continue encapsulating leads A10 and B11 using encapsulating material, and grind to expose the surfaces of leads A10 and B11, forming encapsulation layer four 12 (e.g. Figure 11 As shown), encapsulation layer 1 (3), encapsulation layer 2 (6), encapsulation layer 3 (9), and encapsulation layer 4 (12) constitute the package 13. Finally, it is cut into product units. During the product design phase, the cutting path is designed within the groove 4. The width of the cutting path is less than the width of the groove 4, and their central axes are the same. The groove 4 is filled with encapsulation material. During cutting, the cut is made along the cutting path within the groove 4 until multiple identical or different bare dies placed on the substrate have undergone the same or different wiring layouts. The cutting within the cutting path separates the entire package into multiple product units. Finally, the substrate is removed, forming multiple product units (such as...). Figure 12 (As shown).

[0038] Furthermore, the heat dissipation layer 8 is larger than the insulating layer 7. The heat dissipation layer 8 can be formed to cover the surface of the insulating layer 7 through processes such as electroplating. After covering the surface of the insulating layer 7, the side of the heat dissipation layer 8 extends to the edge of the cutting channel. After being cut and separated into product units, the side of the heat dissipation layer 8 is flush with and exposed to the package 13 of the product unit (e.g., Figure 13 As shown), at this time, the heat dissipation layer 8 covers one surface of the package 13. When the side covers of the package 13 are subsequently formed, the heat dissipation layers 8 covering each side of the package 13 are electroplated together to form a complete whole (as shown). Figure 14 As shown in the figure, this reduces the risk of delamination between the surface and the encapsulating material, resulting in a more stable structure.

[0039] Metal plating can be applied to opposite or all sides of the package 13, so that the heat dissipation layer 8 completely covers three or five surfaces of the package 13. This enhances multi-faceted heat dissipation while blocking electromagnetic interference and electromagnetic radiation, preventing external electromagnetic waves from entering the MOS chip, avoiding threshold voltage drift and switching timing disorder, blocking electromagnetic radiation generated by the MOS chip during operation, and preventing interference with surrounding sensitive devices.

[0040] The B-side electrode of die 2 is transferred to the side metal layer 14 through the corresponding wiring layer 5 and then led to pin B11. The A-side electrode of die 2 is directly led out to pin A10. Pin A10 and pin B11 are flush and exposed on the same surface of package 13. The heat of die 2 is transferred to the insulating layer 7 through wiring layer 5 and then diffused to the outside of package 13 by heat dissipation layer 8. It is also diffused to the outside of package 13 through pin A10. The MOS chip has double-sided heat dissipation to avoid heat accumulation.

[0041] Finally, a protective layer, such as a tin layer, is plated on the exposed pins A and B11 of package 13 and the heat dissipation layer 8 flush with the surface of the package body 13. This can prevent corrosion and oxidation and extend the service life.

[0042] The above process sequence is adjustable and is not limited to the above process sequence. Other processes that only change the process sequence to obtain the heat dissipation packaging structure of the MOS chip of the present invention are also within the protection scope of the present invention. Example 2

[0043] In this embodiment, the etched groove 4 is long, meaning that the groove 4 is formed by half-cutting and separating the product unit within the dicing channel in the package 13. Metal is electroplated on the inner wall of the groove 4. Simultaneously with the pin etching, the side metal layer 14 is etched and separated. One end of the side metal layer 14 is electrically connected to the wiring layer 5, and the other end is electrically connected to the pin B11. The side metal layer 14 serves as a sidewall, covering the side of the bare die 2 after being encapsulated with a spacer. Depending on the product requirements, sidewalls can be formed on multiple sides of the bare die 2. The sidewalls can cover two or all four opposite sides of the bare die 2, forming a conductive medium for the B-side electrode of the bare die 2 to be led out to the surface of the package 13 where the A-side of the bare die 2 is located. Moreover, it can shield the bare die 2 and external signal interference. Matching the three or five surfaces of the package 13 covered by the heat dissipation layer 8, it forms a double-layer shielding structure with better shielding effect.

[0044] The heat dissipation layer 8 covers three or five surfaces of the package 13, which means one top or bottom surface, two or four sides. Furthermore, when the sidewalls formed by the side metal layer 14 cover two opposite sides of the bare die 2, the heat dissipation layer 8 can cover the other two corresponding sides of the bare die 2, forming a complete shielding structure.

[0045] The packaging process of this invention exposes pins A10 and B11 flush with the package body 13, forming the basic structure of the MOS chip. The wiring layer 5 and the side metal layer 14 pull the B-side electrode of the bare die 2 to the surface of the package body 13 corresponding to the A-side of the bare die 2, so that the electrode pins of the MOS chip package structure are located on the same surface of the package body 13, which facilitates subsequent mounting in the working area. The heat of the A-side electrode of the bare die 2 is directly dissipated through pin A10, and the heat of the B-side electrode is dissipated through the insulating layer 7 and the heat dissipation layer 8. The heat dissipation area is large, and the package structure provides double-sided heat dissipation, which is highly efficient. Moreover, the heat dissipation layer 8 completely covers one, three, or five surfaces of the package body 13. When covering multiple sides, it forms a shield while dissipating heat, blocking electromagnetic interference and electromagnetic radiation. The heat dissipation layer 8 and the wiring layer 5 are electrically isolated through the insulating layer 7 to avoid electrical transmission of heat dissipation layer 8 and ensure safe use of the product.

[0046] All encapsulation processes involved in this invention utilize molding compounds, such as epoxy resin, cyanate ester, and polyimide. These materials are low-cost, have good curing properties, and are commonly used encapsulation methods in the field. Encapsulation processes play a crucial role in semiconductor manufacturing, primarily in protecting chips, connecting the entire structure, supporting the structure, ensuring reliability, and promoting technological advancement. The encapsulation method in this invention is commonly used in the field, such as compression molding, but other suitable encapsulation methods are also acceptable.

[0047] Moreover, all the post-encapsulation grinding processes involved in the process steps of this invention use grinding machines commonly used in this technical field to perform surface treatment on the packaging cover, and perform horizontal mechanical grinding on the packaging cover. Finally, the ground surface is horizontal and flat, and the outer surface of the entire packaging structure is flat and smooth.

[0048] In all process steps of this invention involving electroplating, a photoresist film is first adhered, followed by photolithography techniques such as exposure and development to form a protective electroplating layer on the surface of the area to be plated. Areas not requiring electroplating are protected with the photoresist film, exposing the areas to be plated. Then, a seed layer is formed on the exposed area to be plated using appropriate methods such as sputtering or copper deposition. The seed layer is made of copper or other metal and serves to ensure the adhesion between the subsequent metal plating and the surface to be plated, while also providing a surface for conductive ion adhesion, thus ensuring the electroplating effect. The entire electroplating process and the materials used are common knowledge in the field; in all electroplating processes of this invention, the plated metal is copper.

[0049] Based on the above-mentioned MOS chip heat dissipation packaging process, a MOS chip heat dissipation packaging structure (such as...) is obtained. Figures 12-14 As shown), the structure includes the following parts: The die 2 is encapsulated within the package 13. Electrodes are provided on both the A-side and the opposite B-side of the die 2. The A-side electrode of the die 2 is exposed outside the package 13 through pin A10. The B-side electrode of the die 2 is plated with a wiring layer 5. The die 2 is a MOS chip. The A-side of the die 2 has a drain electrode, and the B-side of the die 2 has a source electrode and a gate electrode. The source electrode occupies a large space on the B-side of the die 2, and the gate electrode occupies a small remaining space on the B-side of the die 2. The wiring layer 5 electrically rewires and leads out the source and gate electrodes on the B-side of the die 2.

[0050] One end of the side metal layer 14 is electrically connected to the wiring layer 5, and the other end is electrically connected to the pin B11. Pins A10 and B11 are flush with each other and exposed on the same surface of the package 13.

[0051] The side metal layer 14 is formed by etching the encapsulant to form the groove 4, and then electroplating and etching it to separate the inner wall of the groove 4.

[0052] Based on the above two embodiments, the side metal layer 14 can be a pillar, which is electrically connected to the wiring layer 5 of the B-side electrode of the bare die 2, and electrically pulls the B-side electrode of the bare die 2 to the surface of the package body 13 where the A-side of the bare die 2 is located through the pin B11; the side metal layer 14 can be a sidewall, which covers the side of the bare die 2 after being encapsulated with a spacer between it and the side of the bare die 2.

[0053] The insulating layer 7 is disposed on the surface of the B-side electrode of the wiring layer 5 away from the bare die 2. It insulates the electrical properties of the B-side electrode of the bare die 2 and conducts the heat of the B-side electrode of the bare die 2. The orthogonal projection of the insulating layer 7 onto the B-side of the bare die 2 completely covers the B-side of the bare die 2. The insulating layer 7 is a thin plate made of insulating and thermally conductive material, such as active metal brazing ceramic substrate, which has strong insulation, stable thermal conductivity and reliable chemical properties.

[0054] The heat dissipation layer 8 is disposed on the surface of the insulating layer 7 away from the wiring layer 5, and the heat dissipation layer 8 completely covers one, three or five surfaces of the package 13.

[0055] The package 13 is encapsulated in four layers and finally cut into product units. Each product unit encapsulates a MOS chip and a corresponding fan-out structure.

[0056] In this invention, the heat from the A-side electrode of the bare die 2 is directly dissipated through pin A10, and the heat from the B-side electrode is dissipated through the insulating layer 7 and the heat dissipation layer 8. The heat dissipation area is large, and the package structure provides double-sided heat dissipation for efficient heat dissipation. Moreover, the heat dissipation layer 8 completely covers one, three, or five surfaces of the package body 13. When covering multiple sides, it forms a shield while dissipating heat, blocking electromagnetic interference and electromagnetic radiation. The heat dissipation layer 8 and the wiring layer 5 are electrically isolated through the insulating layer 7 to prevent electrical transmission of heat through the heat dissipation layer 8 and ensure safe use of the product.

[0057] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention are within the protection scope of this invention.

Claims

1. A heat dissipation packaging structure for a MOS chip, characterized in that, include: The bare die is encapsulated in a package. Electrodes are provided on both side A and the opposite side B of the bare die. The electrode on side A of the bare die is exposed outside the package through lead A, and the electrode on side B of the bare die is plated with a wiring layer. The side metal layer is electrically connected to the wiring layer at one end and to pin B at the other end. Pins A and B are flush with each other and exposed on the same surface of the package. An insulating layer is disposed on the surface of the wiring layer away from the electrode on the B side of the die. It insulates the electrical properties of the electrode on the B side of the die and conducts heat from the electrode on the B side of the die. The orthogonal projection of the insulating layer onto the B side of the die completely covers the B side of the die. The heat dissipation layer is located on the surface of the insulation layer away from the wiring layer.

2. The MOS chip heat dissipation packaging structure according to claim 1, characterized in that, The die is a MOS chip. The A side of the die has a drain electrode, and the B side of the die has a source electrode and a gate electrode. The wiring layer electrically rewires and leads out the source electrode and the gate electrode on the B side of the die.

3. The MOS chip heat dissipation packaging structure according to claim 2, characterized in that, The side metal layer is a pillar, which is electrically connected to the wiring layer of the electrode on the B side of the bare die, and electrically pulls the electrode on the B side of the bare die to the surface of the package where the A side of the bare die is located through the pin B.

4. The MOS chip heat dissipation packaging structure according to claim 2, characterized in that, The side metal layer serves as a sidewall, which is covered by encapsulant after being spaced apart from the side of the bare die.

5. The MOS chip heat dissipation packaging structure according to claim 1, characterized in that, The heat dissipation layer completely covers one, three, or five surfaces of the package.

6. A heat dissipation packaging process for a MOS chip, characterized in that, Includes the following steps: Die mounting: A substrate is provided, the surface of which is covered with metal foil. The die A side is mounted with the metal foil facing the substrate. The first encapsulation is performed. After the die is completely encapsulated, the electrode on the die B side is exposed, forming an encapsulation layer. Etching and electroplating: Vertical etching of the encapsulation layer one forms a groove, exposing the metal foil surface at the bottom of the groove. Metal is electroplated on the inner wall of the groove, and a wiring layer is electroplated on the B side of the bare die. The wiring layer is connected to the metal electroplated on the inner wall of the groove. A second encapsulation is continued on the basis of the first encapsulation. After the wiring layer is completely encapsulated and the inside of the groove is filled, the top surface of the wiring layer is exposed, forming the second encapsulation layer. Cover with insulating layer: Cover the surface of the wiring layer away from the B-side electrode of the bare die with an insulating layer to insulate the electrical properties of the B-side electrode of the bare die and conduct heat to the B-side electrode of the bare die. The orthogonal projection of the insulating layer on the B-side of the bare die completely covers the B-side of the bare die. Heat dissipation layer: A heat dissipation layer is covered on the surface of the insulation layer away from the wiring layer. On the basis of the second encapsulation layer, the surface of the heat dissipation layer is further encapsulated and exposed to form the third encapsulation layer. Pin formation: Etching metal foil to form pins A and B, etching the inner wall of the groove to separate the metal into a side metal layer, the electrode on the surface of the bare die A is exposed outside the package body through pin A, the side metal layer is electrically connected to pin B, continue to encapsulate pins A and B, and then expose the surface of the pins to form encapsulation layer four. Encapsulation layers one, two, three and four constitute the package body, and finally cut into product units.

7. The MOS chip heat dissipation packaging process according to claim 6, characterized in that, In the die mounting step, the die is a MOS chip. The A side of the die has a drain electrode, and the B side of the die has a source electrode and a gate electrode. The wiring layer formed in the etching and electroplating step electrically rewires and leads out the source electrode and gate electrode on the B side of the die.

8. The MOS chip heat dissipation packaging process according to claim 7, characterized in that, In the step of forming pins A and B, the side metal layer is a pillar, which is electrically connected to the wiring layer of the electrode on the B side of the bare die, and the electrode on the B side of the bare die is electrically pulled to the surface of the package where the A side of the bare die is located through pin B.

9. The MOS chip heat dissipation packaging process according to claim 7, characterized in that, In the steps of forming pin A and pin B, the side metal layer is a sidewall, which is covered by encapsulant after being spaced apart from the side of the bare die.

10. The MOS chip heat dissipation packaging process according to claim 6, characterized in that, In the step of covering the heat dissipation layer, the heat dissipation layer completely covers one, three, or five surfaces of the package.

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