Analog-to-digital converter with offset calibration function, storage and calculation integrated device and electronic equipment

Abstract

The invention relates to an analog-to-digital converter with an offset calibration function, a storage and calculation integrated device and electronic equipment, and the analog-to-digital converter comprises a comparator, a latch and a calibration module. The calibration module comprises a coarse calibration circuit for performing coarse calibration on the offset voltage of the comparator, a fine calibration circuit for performing fine calibration on the offset voltage of the comparator, and a calibration control logic circuit for controlling the coarse calibration circuit and the fine calibration circuit to work; the calibration control logic circuit outputs a coarse calibration control signal to control the coarse calibration circuit to perform coarse calibration on the offset voltage of the comparator; the calibration control logic circuit is further used for outputting a fine calibration control signal used for controlling the fine calibration circuit to work after coarse calibration so as to inject charges into the input end of the comparator and further offset the offset voltage of the comparator, and the calibration range of the fine calibration circuit is larger than one calibration step length of the coarse calibration circuit. The analog-to-digital converter provided by the invention has an offset calibration function, and is small in area, low in power consumption, small in error and not easy to interfere.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to an analog-to-digital converter with a mismatch calibration function, a computing and storage integrated device, and an electronic device. BACKGROUND

[0002] An analog-to-digital converter (ADC) implements conversion of an analog signal to a digital signal. The ADC converts the analog signal to the digital signal by sampling the analog signal and quantizing and encoding the sampled analog signal.

[0003] However, in the process of analog-to-digital conversion, the ADC is affected by noise interference, mismatch, and the like, so that the output digital signal produces an error code. Calibrating the mismatch voltage of the ADC can greatly reduce the error rate of the ADC output signal. Among them, the comparator in the ADC is the main source of the mismatch voltage. For an ideal comparator, when the input voltage difference (Vip - Vin) is 0, the output should switch instantaneously. However, in practice, due to the slight mismatch (such as threshold voltage, size difference) of the transistor in the manufacturing process, the comparator will not flip even if the input difference is 0. The input voltage difference required to make the comparator output flip is the mismatch voltage. The comparator usually has an inherent mismatch voltage, and the mismatch voltage in the comparator containing a latch greatly affects the performance of the comparator. For example, the comparator containing a CMOS latch has a large mismatch voltage, and the mismatch voltage can reach the order of tens of millivolts. For example, in some application scenarios, the comparator is used in a two-step ADC to form a coarse quantization full-parallel ADC, which can cause quantization errors between the coarse quantization full-parallel ADC and the subsequent ADC due to the existence of the mismatch voltage. In a dynamic comparator, the mismatch voltage mainly comes from the mismatch of the transistor in the internal latch stage. This mismatch is random and fixed, and directly reduces the accuracy of the comparator. For high-precision analog-to-digital converters (ADCs), the mismatch of the comparator must be calibrated to a very small level (e.g., less than LSB / 2). Since the comparator is the quantizer of the ADC to implement the quantization function, the comparator is an important component of the ADC. As can be seen from the above, the mismatch of the comparator has an important influence on the overall performance of the ADC.

[0004] Therefore, how to design an analog-to-digital converter with low mismatch voltage is particularly important. However, when calibrating the mismatch voltage, the current ADC usually has problems such as large area, large power consumption, signal path susceptible to interference, large quantization error, and the like, thereby affecting the performance of the ADC and reducing the application range and application objects of the ADC. SUMMARY

[0005] In view of this, in order to solve the above-mentioned problems, the application provides an analog-to-digital converter with a calibration function.

[0006] The analog-to-digital converter comprises a comparator for comparing an input voltage with a reference voltage, a latch for latching a comparison result of the comparator, and a calibration module for calibrating a misadjustment voltage of the comparator; the calibration module comprises a coarse calibration circuit for coarsely calibrating the misadjustment voltage of the comparator, a fine calibration circuit for finely calibrating the misadjustment voltage of the comparator, and a calibration control logic circuit for controlling the coarse calibration circuit and the fine calibration circuit to work; the calibration control logic circuit is configured to output a coarse calibration control signal to control the coarse calibration circuit to coarsely calibrate the misadjustment voltage of the comparator; and the calibration control logic circuit is further configured to output a fine calibration control signal for controlling the fine calibration circuit to finely calibrate after coarse calibration, so as to inject charges into an input end of the comparator, thereby offsetting the misadjustment voltage of the comparator, and the calibration range of the fine calibration circuit is greater than one calibration step of the coarse calibration circuit.

[0007] In a preferred embodiment of the application, the coarse calibration circuit calibrates the misadjustment voltage of the comparator by adjusting the load capacitance of a node inside the comparator.

[0008] In a preferred embodiment of the application, the comparator comprises an internal latch, and the coarse calibration circuit adjusts the load capacitance of two output ends of the internal latch to offset the misadjustment voltage of the comparator.

[0009] In a preferred embodiment of the application, the coarse calibration circuit comprises a first branch electrically connected to a first output end of the internal latch and a second branch electrically connected to a second output end of the internal latch; the first branch comprises a plurality of first switched-capacitor branches connected in parallel, each first switched-capacitor branch comprising a first switch and a first capacitor, one end of the first switch being electrically connected to the first output end of the internal latch, the other end of the first switch being grounded through the first capacitor, and the control end of the first switch being connected to the calibration control logic circuit to receive the coarse calibration control signal; and the second branch comprises a plurality of second switched-capacitor branches connected in parallel, each second switched-capacitor branch comprising a second switch and a second capacitor, one end of the second switch being electrically connected to the second output end of the internal latch, the other end of the second switch being grounded through the second capacitor, and the control end of the second switch being connected to the calibration control logic circuit to receive the coarse calibration control signal.

[0010] In a preferred embodiment of the present application, the calibration control logic circuit is configured to control the fine calibration circuit to inject a preset calibration voltage to the input of the comparator and find a compensation voltage capable of compensating for the offset voltage of the comparator through an iterative algorithm, and the calibration control logic circuit is further configured to apply the compensation voltage to the comparator when the comparator is working.

[0011] In a preferred embodiment of the present application, the fine calibration circuit comprises a plurality of third branches electrically connected to the first input of the comparator and a plurality of fourth branches electrically connected to the second input of the comparator; each of the third branches comprises a third capacitor and a third switch, one end of the third capacitor is electrically connected to the first input of the comparator, the other end of the third capacitor is electrically connected to one end of the third switch, and the control end of the third switch is connected to the calibration control logic circuit, so that the other end of the third switch is switched between the power supply VDD and the ground, thereby injecting electric charge; each of the fourth branches comprises a fourth capacitor and a fourth switch, one end of the fourth capacitor is electrically connected to the second input of the comparator, the other end of the fourth capacitor is electrically connected to one end of the fourth switch, and the control end of the fourth switch is connected to the calibration control logic circuit, so that the other end of the fourth switch is switched between the power supply VDD and the ground, thereby injecting electric charge.

[0012] In a preferred embodiment of the present application, the comparator comprises switch tubes M0, M1a, M1b, M2a, M2b, M3, M4, M5, and M6; the power supply VDD is connected to the ground through the switch tubes M3, M1b, M1a, and M0 in sequence, and the power supply VDD is connected to the ground through the switch tubes M6, M2b, M2a, and M0 in sequence, the control ends of the switch tubes M1a and M1b are connected together to form the first input of the comparator, the connection of the switch tubes M1a and M1b is connected to the power supply VDD through the switch tube M4 and is electrically connected to the coarse calibration circuit, the control ends of the switch tubes M2a and M2b are connected together to form the second input of the comparator, the connection of the switch tubes M2a and M2b is connected to the power supply VDD through the switch tube M5 and is electrically connected to the coarse calibration circuit; the control ends of the switch tubes M0, M3, M4, M5, and M6 are connected to the first clock signal CLK.

[0013] In the preferred embodiment of the present application, the latch comprises: switch tubes M7, M8, M9, M10, M11, M12, M13, M14; the power supply VDD is connected to the control end of the switch tube M10 and the control end of the switch tube M12 in sequence through the switch tube M9 and the switch tube M7, and the control end of the switch tube M7 is connected to the second output end Vmn of the comparator; the power supply VDD is connected to the control end of the switch tube M9 and the control end of the switch tube M11 in sequence through the switch tube M10 and the switch tube M8, and the control end of the switch tube M8 is connected to the first output end Vmp of the comparator, the control end of the switch tube M10 is connected to the ground through the switch tube M13, the control end of the switch tube M10 is also connected to the ground through the switch tube M11, the control end of the switch tube M9 is connected to the ground through the switch tube M12, and the control end of the switch tube M9 is also connected to the ground through the switch tube M14; the control end of the switch tube M13 and the control end of the switch tube M14 are both connected to the second clock signal nCLK.

[0014] The present application also provides a storage-computing integrated device comprising an in-memory computing module and an analog-to-digital converter for converting an analog multiply-accumulate result output by the in-memory computing module into a digital signal, wherein the analog-to-digital converter is any of the analog-to-digital converters described above.

[0015] In the preferred embodiment of the present application, the in-memory computing module comprises: a first in-memory computing circuit based on a digital signal, a second in-memory computing circuit based on an analog signal, and an accumulator, wherein the first in-memory computing circuit performs multiply-accumulate calculation on input feature data and high weight bits of weights based on a digital addition tree to obtain a digital first multiply-accumulate result; the second in-memory computing circuit performs multiply-accumulate calculation on the input feature data and low weight bits of the weights based on a capacitor to obtain an analog multiply-accumulate result, the analog-to-digital converter is used to perform analog-to-digital conversion on the analog multiply-accumulate result output by the second in-memory computing circuit to obtain a digital second multiply-accumulate result, and the accumulator is used to accumulate the first multiply-accumulate result and the second multiply-accumulate result.

[0016] The present application also provides an electronic device comprising any of the analog-to-digital converters described above.

[0017] The analog-to-digital converter provided by the application can perform two-stage calibration of coarse calibration and fine calibration through the calibration module containing a coarse calibration module, a fine calibration module and a calibration control logic circuit. The calibration control logic circuit outputs a coarse calibration control signal to control the coarse calibration circuit to perform coarse calibration on the offset voltage of the comparator. The calibration control logic circuit also outputs a fine calibration control signal after coarse calibration to control the fine calibration circuit to perform fine calibration and inject charges into the input end of the comparator to offset the offset voltage of the comparator. The calibration range of the fine calibration circuit is greater than one calibration step of the coarse calibration circuit. Therefore, the analog-to-digital converter provided by the application can perform coarse calibration on the offset voltage of the comparator in a large range and fine calibration on the offset voltage of the comparator. The coarse calibration circuit performs coarse calibration on the offset voltage in a large voltage range through the coarse calibration control signal, so that the offset voltage in a large range can be calibrated and reduced or offset quickly, and the ADC can be applied to a situation with a large offset voltage. Moreover, after coarse calibration, the fine calibration circuit performs fine calibration based on charge injection, so that the fine calibration circuit can perform high-precision calibration in a small voltage range, thereby reducing the quantization error of the analog-to-digital converter and improving the conversion precision of the analog-to-digital converter. In particular, the calibration range of the fine calibration circuit is greater than one calibration step of the coarse calibration circuit, so that the analog-to-digital converter can perform coarse and fine calibration on the offset voltage in different ranges and modes. Moreover, since the application performs coarse calibration before fine calibration, the offset voltage is calibrated to a small voltage range, so the analog-to-digital converter can use fewer electronic components and smaller calibration steps to accurately calibrate the offset voltage, that is, the analog-to-digital converter can use a smaller circuit area and reduce the power consumption of the circuit, especially the chip circuit. Coarse calibration can reduce the small electronic components that may be needed in the fine calibration circuit, for example, coarse calibration can reduce the small capacitance that may be needed in the fine calibration circuit, thereby reducing the interference of the small capacitance on the input signal path. Therefore, the analog-to-digital converter provided by the application can have the advantages of coarse calibration and fine calibration through two-stage calibration, and the combination of fine calibration based on charge injection can make the analog-to-digital converter have a small area, low cost, low power consumption, signal path not easily disturbed, small quantization error and other functions while calibrating the offset voltage. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0019] Figure 1 is a circuit structure schematic diagram of an analog-to-digital converter provided by an embodiment of the present application; Figure 2 is a circuit structure schematic diagram of an analog-to-digital converter provided by another embodiment of the present application; Figure 3 is a circuit diagram of an analog-to-digital converter provided by an embodiment of the present application; Figure 4 is a control flow chart of two-stage calibration in an embodiment of the present application; Figure 5 is a structure block diagram of a mixed analog-digital in-memory computing device provided by an embodiment of the present application; Figure 6 is a structure schematic diagram of a mixed analog-digital in-memory computing device provided by an embodiment of the present application; Figure 7 is a comparison diagram of an in-memory computing device based on mixed signals compared with an existing analog computing scheme in error provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present application clearer, the various exemplary embodiments to be described below will be described with reference to the corresponding drawings, which constitute a part of the exemplary embodiments and describe various exemplary embodiments that can be used to implement the present application. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation described in the following exemplary embodiments does not represent all the implementations consistent with the present disclosure. It should be understood that they are only examples of processes, methods and devices, etc. consistent with some aspects of the present disclosure as described in the appended claims, and other embodiments can also be used, or structural and functional modifications can be made to the embodiments listed herein, without departing from the scope and spirit of the present application.

[0021] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse" and the like indicate the orientation or positional relationship based on the drawings shown, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the elements referred to must have a particular orientation, be constructed and operated in a particular orientation. The terms "first", "second" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "a plurality of" means two or more. The terms "connected", "connected" should be broadly understood, for example, it can be fixed connection, detachable connection, integral connection, mechanical connection, electrical connection, communication connection, direct connection, indirect connection through intermediate medium, it can be the internal communication of two elements or the interaction relationship of two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0022] Referring to Figure 1 and Figure 2 As shown in the structural schematic diagram of the analog-to-digital converter with the offset calibration function provided by the embodiment of the present application. Among them, the analog-to-digital converter includes: comparator 30, latch 20, and calibration module 10. The comparator 30 is used to compare the input voltage with the reference voltage, the latch 20 is used to latch the comparison result of the comparator 30, and the calibration module 10 is used to calibrate the offset voltage of the comparator 30. The calibration module 10 includes: a coarse calibration circuit 101 for coarse calibration of the offset voltage of the comparator 30, a fine calibration circuit 102 for fine calibration of the offset voltage of the comparator 30, and a calibration control logic circuit 103 for controlling the work of the coarse calibration circuit 101 and the fine calibration circuit 102. The calibration control logic circuit 103 is used to output a coarse calibration control signal to control the coarse calibration circuit 101 to perform coarse calibration on the offset voltage of the comparator 30; the calibration control logic circuit 103 is also used to output a fine calibration control signal for controlling the fine calibration circuit 102 to perform fine calibration after coarse calibration, to inject charge into the input end of the comparator 30, thereby offsetting the offset voltage of the comparator 30, and the calibration range of the fine calibration circuit 102 is greater than one calibration step of the coarse calibration circuit 101.

[0023] Therefore, the analog-to-digital converter provided by the application can perform coarse calibration on the offset voltage of the comparator 30 in the analog-to-digital converter in a large range and fine calibration on the offset voltage of the comparator 30 in the analog-to-digital converter, so as to achieve the quantization range required by the analog-to-digital converter and improve the conversion precision of the analog-to-digital converter. The calibration range of the coarse calibration circuit 101 is greater than the maximum value of the offset voltage of the comparator 30, so that the coarse calibration circuit 101 can perform calibration in a voltage range greater than the maximum value of the offset voltage, and the offset voltage of the comparator 30 can be offset. The calibration module 10 makes the coarse calibration circuit 101 perform coarse calibration on the offset voltage in a large voltage range through a coarse calibration control signal, so that the offset voltage in a large range can be calibrated and reduced or offset quickly, and the ADC can be applied to a situation with a large offset voltage. Moreover, after coarse calibration, the calibration module 10 also performs fine calibration through the fine calibration circuit 102, so that the fine calibration circuit 102 can perform calibration in a small voltage range, so as to reduce the quantization error of the analog-to-digital converter and improve the conversion precision of the analog-to-digital converter. In particular, the calibration range of the fine calibration circuit 102 in the application is greater than one calibration step of the coarse calibration circuit 101, so that the analog-to-digital converter can perform coarse and fine calibration on the offset voltage in different ranges and modes. Moreover, the fine calibration circuit 102 in the application offsets the offset voltage by injecting charges into the input end of the comparator 30, so that the fine calibration circuit 102 can perform calibration in a small calibration range with high precision, and the quantization error can be better solved and the precision can be optimized. Moreover, since the coarse calibration is performed before fine calibration in the application, the offset voltage is calibrated to a small voltage range, so that the analog-to-digital converter can use fewer electronic components to accurately calibrate the offset voltage in a small calibration step, that is, the analog-to-digital converter can use a smaller area of circuit and reduce the power consumption of the circuit, especially the chip circuit. Moreover, coarse calibration can reduce the small electronic components that may be required in the fine calibration circuit 102, for example, coarse calibration can reduce the small capacitance that may be required in the fine calibration circuit 102, so as to reduce the interference of the small capacitance on the input signal path.

[0024] In conclusion, the analog-to-digital converter provided by the present application has the function of self-offset voltage calibration, and the analog-to-digital converter provided by the present application first calibrates the offset voltage to a smaller voltage range through coarse calibration, and then combines the calibration control logic unit and the fine calibration circuit 102 to offset the offset voltage after coarse calibration (the offsetting can refer to completely removing the offset voltage or offsetting the offset voltage to an acceptable very small range). Therefore, the analog-to-digital converter provided by the present application can have the advantages of coarse calibration and fine calibration through coarse and fine calibration, and the combination of the fine calibration based on charge injection enables the analog-to-digital converter to realize the function of calibrating the offset voltage while also making the area of the ADC smaller, the power consumption less, the signal path less susceptible to interference, and the quantization error small.

[0025] The application range and object of the ADC provided by the present application can be wider, for example, the ADC can be applied to high-precision or high-speed analog-to-digital converters. For example, the ADC provided by the present application can be applied to AI computing chips, wireless communication chips, wired communication chips, digital signal processing chips, mobile phone master control chips, AR / VR master control chips, etc.

[0026] Referring to Figure 2As shown, in an embodiment of the present application, the coarse calibration circuit 101 is a switch capacitor based coarse calibration circuit 101 (i.e. the switch capacitor coarse calibration circuit 101 in the figure), which adjusts the capacitance array connected to the node inside the comparator 30, for example, by controlling the access of the capacitor by switches, to change the load capacitance of the node, so as to calibrate / offset the offset voltage. That is, in this preferred embodiment, the coarse calibration circuit 101 adjusts the load capacitance of the node inside the comparator 30 to calibrate the offset voltage of the comparator 30. It can change the voltage at the node inside the comparator 30 by a large margin, and thus perform coarse calibration in a large range by a large margin. The coarse calibration circuit 101 can perform coarse calibration by adjusting the sensitive node inside the comparator 30. Further preferably, the coarse calibration circuit 101 adjusts the load capacitance of the two output terminals of the internal latch of the comparator 30 under the control of the coarse calibration code (i.e. the coarse calibration control signal mentioned above) output by the calibration control logic circuit 103, to offset the offset voltage of the comparator 30. For example, the calibration control logic circuit 103 adjusts the binary weighted switch capacitor array connected to the output terminal of the internal latch, to adjust the load capacitance of the output terminal of the internal latch, so as to quickly perform coarse calibration and relatively simple circuit implementation and low cost. The switch capacitor coarse calibration circuit 101 can change the load capacitance of the node by controlling the access of the capacitor by switches under the control of the calibration control logic circuit 103, so as to adjust the regeneration time constant of the latch 20. Since mismatch will cause the regeneration speed to be fast or slow, by asymmetrically adjusting the capacitance of the two output terminals of the latch 20, the speed difference can be compensated, and thus the offset voltage is offset. Moreover, this method has simple circuit structure, low cost and low power consumption.

[0027] In Figure 2 the fine calibration circuit 102 is a charge injection based fine calibration circuit 102, which can inject a preset calibration voltage to the input terminal of the comparator 30 under the control of the fine calibration code (i.e. the fine calibration control signal mentioned above) output by the calibration control logic circuit 103, and find the voltage value (i.e. the voltage value of the compensation voltage) that can offset the offset voltage of the comparator 30 by an iterative algorithm (e.g. binary search), and store the voltage value of the compensation voltage. That is, it constantly gives the input signal the corresponding output by algorithm, so as to try to find the value of the offset voltage. When the comparator 30 of the analog-to-digital converter is working, the calibration control logic circuit 103 applies the compensation voltage to the comparator 30, so as to realize fine calibration of the offset voltage. This method can quickly and accurately find the compensation voltage, so as to quickly and accurately fine calibrate the offset voltage, and can also reduce the quantization error of the analog-to-digital converter and improve the accuracy of the analog-to-digital converter.

[0028] Referring toFigure 3 and Figure 4 In the preferred embodiment shown in FIG. 1, the coarse calibration circuit 101 is a switched-capacitor circuit with an internal latch. In this preferred embodiment, the coarse calibration circuit 101 includes a first branch 1011 electrically connected to a first output of the internal latch and a second branch 1012 electrically connected to a second output of the internal latch. The first branch 1011 includes a plurality of first switched-capacitor branches connected in parallel, each of which includes a first switch and a first capacitor. One end of the first switch is electrically connected to the first output Vxn of the internal latch, the other end of the first switch is grounded through the first capacitor, and the control terminal of the first switch is connected to the calibration control logic circuit 103 to receive the coarse calibration control signal CCDN. The second branch 1012 includes a plurality of second switched-capacitor branches connected in parallel, each of which includes a second switch and a second capacitor. One end of the second switch is electrically connected to the second output Vxp of the internal latch, the other end of the second switch is grounded through the second capacitor, and the control terminal of the second switch is connected to the calibration control logic circuit 103 to receive the coarse calibration control signal CCDP. Thus, under the control of the calibration control logic circuit 103, the way in which the capacitors in the coarse calibration circuit 101 are connected to the sensitive nodes of the comparator 30 can be changed, thereby changing the load capacitance of the sensitive nodes inside the comparator 30, and thus fine-tuning the regeneration time constant of the latch 20. Since mismatch causes the regeneration speed to be fast or slow, by asymmetrically adjusting the capacitances on both sides, the speed difference can be compensated, thereby offsetting the mismatch. Therefore, it can calibrate the mismatch voltage in a larger voltage range, and its circuit structure is simple, the cost is low, and the power consumption is low.

[0029] Referring again to Figure 3The fine calibration circuit 102 comprises: a plurality of third branches 1021 electrically connected to the first input end Vinp of the comparator 30, and a plurality of fourth branches 1022 electrically connected to the second input end Vinn of the comparator 30; each of the third branches 1021 comprises a third capacitor C3 and a third switch K3, one end of the third capacitor is electrically connected to the first input end Vinp of the comparator 30, the other end of the third capacitor is electrically connected to one end of the third switch, the control end of the third switch is connected to the fine calibration control signal CFDP output by the calibration control logic circuit 103, so that the other end of the third switch is switched between the power supply VDD and the ground, thereby injecting electric charges; each of the fourth branches 1022 comprises a fourth capacitor C4 and a fourth switch K4, one end of the fourth capacitor C4 is electrically connected to the second input end Vinn of the comparator 30, the other end of the fourth capacitor is electrically connected to one end of the fourth switch, the control end of the fourth switch is connected to the fine calibration control signal CFDN output by the calibration control logic circuit 103, so that the other end of the fourth switch is switched between the power supply VDD and the ground, thereby injecting electric charges. Under the control of the calibration control logic circuit 103, the fine calibration control signal CFDP can make the input end Vinp of the comparator 30 connected to the ground through the third capacitor or connected to the power supply VDD through the third capacitor, so as to realize the injection of electric charges into the first input end of the comparator 30 through the plurality of third branches 1021, and the fine calibration control signal CFDN can make the injection of electric charges into the second input end of the comparator 30 through the plurality of fourth branches 1022. The present application can realize the injection of a known calibration voltage (such as injection through a DAC) into the two input ends of the comparator 30, change the load capacitance of the node by controlling the access of the capacitor through the switch, thereby fine-tuning the regeneration time constant of the latch 20. Since the mismatch will cause the regeneration speed to be fast or slow, by asymmetrically adjusting the capacitance of the two input ends of the comparator 30, the speed difference can be compensated, and the offset voltage can be offset. For example, the voltage value capable of compensating for the inherent offset is found through an iterative algorithm (such as binary search), and the digital code is stored. In normal operation, the DAC continuously applies the compensation voltage, so that the fine calibration circuit 102 can realize the offset / calibration of the offset voltage.

[0030] When injecting charges into the two input terminals of the comparator 30, preferably, the charges are injected into the two input terminals of the comparator 30 by a capacitive DAC (i.e. CDAC). In this way, the charges can be continuously and accurately injected into the comparator 30, and the offset voltage can be continuously and accurately fine calibrated in a small voltage range, so that the quantization error of the analog-to-digital converter is small and the conversion precision is high. However, the additional DAC circuit will increase the area and power consumption of the circuit of the analog-to-digital converter. Especially under high precision requirements, the number of bits of the DAC is high, which will occupy more chip area and increase power consumption. Moreover, only a very small capacitor can achieve a small calibration step, but the physical implementation of a small capacitor is difficult (limited by process limitations and transistor parasitic capacitance), and the mismatch of a very small capacitor itself is large. Moreover, the direct injection of voltage into the comparator 30 in the analog input signal path may introduce nonlinearity, noise or load effects, affecting the speed and linearity of the comparator 30. Therefore, in the analog-to-digital converter provided by the present application, before fine calibration, coarse calibration is first performed by the coarse calibration circuit 101 and the calibration control logic circuit 103 in the calibration module 10, so that the offset voltage is first roughly calibrated to a small voltage range, and then a large-area DAC array is not required for calibration, the power consumption of the entire circuit and the analog-to-digital converter can be reduced, and the interference of a small capacitor to the input signal path is reduced.

[0031] In the analog-to-digital converter provided by the present application, the comparator 30 can adopt various circuit structures, preferably, as shown in Figure 3In an embodiment of the present application, the comparator 30 comprises: switch tubes M0, M1a, M1b, M2a, M2b, M3, M4, M5, M6. The power supply VDD is connected to the ground through the switch tubes M3, M1b, M1a, and M0 in sequence, and the power supply VDD is connected to the ground through the switch tubes M6, M2b, M2a, and M0 in sequence. The control terminals of the switch tubes M1a and M1b are connected together to form the first input terminal Vinp of the comparator 30, and the connection point Vxn of the switch tubes M1a and M1b is connected to the power supply VDD through the switch tube M4 and is electrically connected to the coarse calibration circuit 101. The control terminals of the switch tubes M2a and M2b are connected together to form the second input terminal Vinn of the comparator 30, and the connection point Vxp of the switch tubes M2a and M2b is connected to the power supply VDD through the switch tube M5 and is electrically connected to the coarse calibration circuit 101. The control terminals of the switch tubes M0, M3, M4, M5, and M6 are connected to the first clock signal CLK. Therefore, the switch tubes M3-M6 and the switch tube M0 can be controlled by the first clock signal CLK, and the comparator 30 can compare the input voltage and the reference voltage. The comparator 30 has fewer electronic components, a simple circuit structure, low power consumption, low cost, good stability, and fast processing speed.

[0032] The latch for latching the comparison result of the comparator in the analog-to-digital converter comprises: switch tubes M7, M8, M9, M10, M11, M12, M13, M14; the power supply VDD is connected to the control terminals of the switch tubes M10 and M12 through the switch tubes M9 and M7 in sequence, and the control terminal of the switch tube M7 is connected to the second output terminal Vmn of the comparator. The power supply VDD is connected to the control terminals of the switch tubes M9 and M11 through the switch tubes M10 and M8 in sequence, the control terminal of the switch tube M8 is connected to the first output terminal Vmp of the comparator, the control terminal of the switch tube M10 is connected to the ground through the switch tube M13, the control terminal of the switch tube M10 is also connected to the ground through the switch tube M11, the control terminal of the switch tube M9 is connected to the ground through the switch tube M12, and the control terminal of the switch tube M9 is also connected to the ground through the switch tube M14. The control terminals of the switch tubes M13 and M14 are connected to the second clock signal nCLK. The latch has a simple circuit structure, fewer electronic components, low cost, low power consumption, good stability, and fast processing speed.

[0033] The working principle and working process of the present application are described as follows: Figure 3 and Figure 4 The working principle and working process of the present application are described as follows: First, the calibration module performs a rough calibration of the offset voltage using the calibration control logic circuit and the coarse calibration circuit. The first and second branches of the coarse calibration circuit adjust the internal nodes in the comparator (i.e., Figure 3 Specifically, the capacitors (Vxn and Vxp) are calibrated by controlling the on / off state of the switches in the first and second branches through the coarse calibration codes CCDN and CCDP output by the calibration control logic circuit. This controls whether the first and second capacitors are connected to the circuit, thereby adjusting the capacitance of nodes Vxn and Vxp, and thus coarsely calibrating the offset voltage of the comparator. Then, the third and fourth branches included in the fine calibration circuit inject different charges into the two input terminals of the comparator to introduce an input voltage and further finely cancel the offset voltage of the comparator.

[0034] like Figure 3 As shown, when the voltage Vinp at the first input terminal of the comparator is greater than the voltage Vinn at the second input terminal, the conduction capability of switches M1b and M1a is stronger than that of switches M2b and M2a. Therefore, switches M1b and M1a pull a larger current to ground, making the voltage at node Vmp lower than that at node Vmn. The lower Vmp voltage makes the conduction capability of switch M8 stronger than that of M7. Therefore, a larger current flows from the power supply to node Voutp of the latch, making the voltage at node Voutp larger. Then, the positive feedback of the latch formed by switches M7~M14 pulls the voltage at node Voutp to the power supply voltage VDD and pulls the voltage at node Voutn to ground.

[0035] The coarse calibration code CCDN adjusts the capacitance of node Vxn within the comparator by controlling the size of the connected capacitor array. More capacitors connected to the circuit in the first branch result in a lower voltage at node Vxn; similarly, the coarse calibration code CCDP adjusts the capacitance of node Vxp. Therefore, the calibration module effectively generates an equivalent differential voltage at the comparator's input. The calculation process is as follows: in, These are the capacitance differences generated by the capacitor arrays controlled by two coarse calibration codes, CCDN and CCDP. Cvxn and Cvxp are the total capacitance values ​​at nodes Vxn and Vxp, respectively. VT is the gate-source voltage difference between switching transistors M1b and M1a, and VT is the threshold voltage of the switching transistors (i.e., switching transistors M1a, M1b, M2a, and M2b).

[0036] For fine calibration circuits, it controls the capacitor array to switch between VDD and ground to inject charge through fine calibration codes CFDP / CFDN.

[0037] Figure 3 The CDAC is self-provided by the analog-to-digital converter to provide a reference voltage to the input of the comparator. The capacitance C CDAC of the CDAC is usually 100 times larger than Cvxn, because a larger CDAC capacitance can suppress KT / C noise and a smaller mismatch voltage. Usually 0.2 VDD. Therefore, the same capacitance change, the fine calibration capacitance change introduces an equivalent input voltage change of about 1 / 20 of the coarse calibration circuit. The fine calibration circuit has a calibration range greater than one step of the coarse calibration circuit. The calibration range of the coarse calibration circuit is greater than the maximum value of the comparator offset voltage. Therefore, it can be seen that the analog-to-digital converter provided by the present application can first coarsely calibrate the offset voltage in a larger range through the coarse calibration circuit, and then finely calibrate / offset the offset voltage in a smaller range through the fine calibration circuit. Therefore, the coarse calibration ensures the maximum voltage calibration range of the calibration circuit and does not require a large-area DAC or other auxiliary circuit, thereby reducing the area and power consumption of the ADC and also reducing the interference with the input signal path. Moreover, the fine calibration circuit can ensure the minimum step of the calibration circuit, thereby reducing the quantization error of the analog-to-digital converter and improving the accuracy of the analog-to-digital converter.

[0038] Referring to Figure 4 As shown in the figure, it is a calibration control flowchart in an embodiment of the present application. After the calibration starts, coarse calibration is first performed, and the ADC performs coarse calibration scanning, such as scanning 111, 110, 101, 100, 000, 001, 010, 011, and so on, until the coarse calibration end condition is reached. The end condition of the coarse calibration is, for example, one of the following: 1. When the minimum value is scanned, the output of the comparator is still 1; 2. During the scanning process, the output of the comparator flips; 3. When the maximum value is scanned, the output of the comparator is still 0 (at this time, the fine calibration output is 00000). For example, when the coarse calibration satisfies the above end condition 1, the coarse calibration ends and the fine calibration is entered, and until one of the following calibration end conditions is satisfied, the calibration ends: 1. When the minimum value is input (for example, 11111), the output of the comparator is still 1; 2. When the minimum value is input (for example, 11111), the output of the comparator is still 0, but during the scanning process, the comparator flips. For details, refer to Figure 3 The specific examples are not repeated here.

[0039] In summary, the analog-to-digital converter provided by the application solves the problem of large quantization error by means of the two-stage calibration scheme (i.e., coarse calibration followed by fine calibration), while calibrating the offset voltage. The analog-to-digital converter does not need a large-area circuit, and thus the area and power consumption of the ADC, especially in the form of a chip, can be reduced, the interference to the input signal path can be reduced, the performance of the ADC can be improved, and the application range and application objects of the ADC can be increased.

[0040] It is worth noting that the comparator with an internal latch can be set as a super-speed comparator, so that the analog-to-digital converter can be applied to a field requiring super-speed. However, the comparator with an internal latch in the prior art has a large offset voltage, and thus it is not easy to realize a high-precision analog-to-digital converter. However, the analog-to-digital converter provided by the application realizes coarse calibration combined with fine calibration through the calibration module, so that the analog-to-digital converter can realize high precision with only a small area and low power consumption, and thus the analog-to-digital converter can be applied to a wider range of fields. The ADC provided by the application can be applied to, for example, an AI computing chip, a wireless communication chip, a wired communication chip, a digital signal processing chip, a mobile phone main control chip, an AR / VR main control chip, etc.

[0041] The application also provides a memory-compute integrated device based on a mixed signal, which comprises a compute-in-memory module and an analog-to-digital converter for converting an analog multiply-accumulate result output by the compute-in-memory module into a digital signal. The analog-to-digital converter is any one of the analog-to-digital converters described above.

[0042] The memory-compute integrated device can be in various forms, such as a chip or a module. The memory-compute integrated device is very suitable for a low-power AI computing chip. The low-power AI computing chip is a key engine for promoting artificial intelligence from the cloud to real-world scenarios, and its importance is reflected in three aspects. First, it realizes the "ubiquity" of AI applications. Many key AI scenarios, such as smartphones, autonomous vehicles, security monitoring, and wearable devices, have strict limitations on power consumption and heat dissipation. The low-power AI computing chip enables these devices to perform real-time intelligent processing directly at the terminal, freeing them from the dependence on continuous network connection and cloud data transmission, significantly reducing latency, and protecting data privacy. Second, it directly determines the feasibility and durability of AI applications. In the field of Internet of Things and edge computing, devices often need to rely on batteries for long-term independent work. Extremely high power consumption will quickly deplete the power, causing the application to fail. The low-power AI computing chip ensures that the device can operate continuously and stably for months or even years, greatly expanding the deployment boundaries of AI.

[0043] The memory computing integrated device provided by the application is based on a mixed signal and an ADC with a mismatch calibration function, so that the device has low power consumption, small area, low error rate, and can support operations requiring greater computing power, thereby better assisting the AI computing power chip and the AI function of the AI device.

[0044] The memory computing integrated device provided by the application is not only suitable for AI computing, but also can be applied to a memory computing integrated chip and a brain-like chip, and represents a mainstream big data computing chip architecture in the future.

[0045] In the memory computing integrated chip architecture, there are mainly two existing traditional implementation architectures for computing: a digital computing architecture and an analog computing architecture. The digital computing architecture refers to obtaining the accumulated sum of the matrix vector product by cascading the product of the stored data and the input vector data in the memory computing unit matrix through a multi-level addition tree. The analog computing architecture refers to obtaining the accumulated sum of the digital signal by converting the product of the stored data and the input vector data in the memory computing unit matrix through charge or current accumulation and then through an analog-to-digital converter (ADC). The advantage of the digital computing architecture is high computing reliability, which is not easily affected by process, temperature, and voltage fluctuations, so the computing precision is high and the result is not easily damaged. However, the digital computing architecture has the disadvantage of large power consumption and area compared with the analog computing architecture due to the use of a large number of addition trees. The advantage of the analog computing architecture is low power consumption and high computing energy efficiency due to the use of charge or current accumulation for summation, and the use of vertically stacked metal capacitors for voltage conversion of charge or current can save a significant amount of area compared with the addition tree occupying the bottom device to the high-level metal. However, the analog computing architecture has the disadvantage of being easily affected by process, temperature, and voltage fluctuations to change the size of the computing charge or current, especially the high-weight bit accumulation result, thereby causing a large loss of computing precision.

[0046] Referring to Figure 5 and Figure 6In the preferred embodiment shown, the in-memory computing module in the in-memory computing device provided by the application is a mixed-signal based circuit. The in-memory computing module includes a first in-memory computing circuit (CIM) based on digital signals, a second in-memory computing circuit based on analog signals, and an accumulator. The first in-memory computing circuit performs multiplication and accumulation calculation on input feature data and high weight bits of weights based on a digital addition tree to obtain a first digital multiplication and accumulation result. The second in-memory computing circuit performs multiplication and accumulation calculation on input feature data and low weight bits of weights based on a capacitor to obtain an analog multiplication and accumulation result. An analog-to-digital converter (ADC) is used to convert the analog multiplication and accumulation result output by the second in-memory computing circuit into a digital second multiplication and accumulation result. The accumulator is used to accumulate the first multiplication and accumulation result and the second multiplication and accumulation result. The analog-to-digital converter can be any of the ADCs described above. The in-memory computing device provided by the application is based on mixed signals and the ADC with the offset calibration function described above, so that the offset voltage is completely calibrated or the offset voltage is calibrated at a relatively low level. The corresponding in-memory computing device has the advantages of low power consumption, small area, low bit error rate, and support for operations requiring more computing power, and thus can better assist the AI computing chip and the AI function of the AI device.

[0047] As shown in Figure 5 The first in-memory computing circuit includes an in-memory computing array and an addition tree. The in-memory computing array can perform in-memory multiplication calculation, and then the addition tree can perform addition to realize digital in-memory multiplication and accumulation. The second in-memory computing circuit includes an in-memory computing array and a capacitor array. The in-memory computing array can perform in-memory multiplication calculation, and then the capacitor can perform addition to realize analog in-memory multiplication and accumulation. Thus, the in-memory computing device described above can realize in-memory multiplication and accumulation calculation. When the in-memory computing device provided by the application performs data calculation, the data matrix is divided into two parts according to the weights: a high weight bit matrix and a low weight bit matrix. That is, the weights are divided into two parts according to the bits, the high weight bits on the left are the high weight bits, and the remaining weight bits are the low weight bits. Thus, one part of the in-memory computing device is realized in a digital manner, and the other part is realized in an analog manner. Preferably, the weights are evenly divided into two parts according to the bits. Correspondingly, the first in-memory computing circuit is configured to have a digital structure for processing high weight bits, and the second in-memory computing circuit is configured to have an analog structure for processing low weight bits.

[0048] As shown in Figure 6As shown, taking 8-bit data as an example, the high four bits are classified as high-weight bits, and the low four bits are classified as low-weight bits, but this is only an example, and the architecture of the application also includes and is applicable to other grouping manners. The specific grouping can be determined according to the comprehensive consideration of the product to the chip computing precision, power consumption, and area, and the like. For example, for the application object with high precision requirement of automatic driving, the first in-memory computing circuit of the digital type is arranged more than the second in-memory computing circuit of the analog type. The high-weight bit matrix data is calculated by using the digital computing circuit architecture of the multi-stage cascade addition tree with high computing precision, strong computing stability, and high computing reliability, which can ensure high computing precision and is not easy to be damaged. The low-weight bit calculation with lower influence on the computing precision is calculated by using the analog computing circuit architecture with lower energy consumption and smaller area, which can reduce the chip computing power consumption and the chip area. As shown in Figure 7 As shown, taking 8-bit unsigned data calculation as an example, the in-memory computing device based on the mixed signal provided by the application realizes the improvement of the computing precision and the computing stability, and the computing error is reduced from 50% to within 3% compared with the existing analog computing architecture. The in-memory computing device based on the mixed signal and with the offset voltage calibration function of the ADC provided by the application can greatly reduce the area of the in-memory computing chip, and can greatly reduce the power consumption of the in-memory computing chip. The application can be applied to the fields of high-precision, high-reliability, low-power, and low-area cost computing power demand, artificial intelligence training or reasoning, autonomous driving chips, VR chips, robot built-in chips, wearable smart chips, and deep learning applications of parallel computing, and the like. The application also provides an electronic device comprising any one of the analog-to-digital converters or the in-memory computing device. It can be applied to electronic devices related to computing power centers, computing devices, edge computing, autonomous driving, AR, VR, laser radar, and the like, as well as a series of electronic devices such as smartphones, tablet computers, wearable electronic equipment, smart home electronic products, industrial or medical or battery-powered electronic devices, and the like.

[0049] The above only describes the embodiments of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent flow transformation made by using the content of the specification and the drawings, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the application.

[0050] In addition, for the same or similar structure elements, the same or different reference numerals can be used in the present application. In addition, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise expressly and specifically limited.

[0051] In the present application, the word "for example" is used to indicate "serving as an example, instance, or illustration". Any embodiment described as "for example" in the present application is not necessarily to be construed as more preferred or advantageous over other embodiments. The above description is given for enabling any person skilled in the art to carry out and use the present application. In the above description, various details are set forth for the purpose of explanation.

[0052] It should be understood that one of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes are not described in detail to avoid obscuring the description of the present application with unnecessary detail. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope consistent with the principles and features disclosed.

Claims

1. An analog-to-digital converter with offset calibration function, characterized in that, The analog-to-digital converter includes: a comparator for comparing an input voltage with a reference voltage, a latch for latching the comparison result of the comparator, and a calibration module for calibrating the offset voltage of the comparator. The calibration module includes: a coarse calibration circuit for coarse calibration of the offset voltage of the comparator, a fine calibration circuit for fine calibration of the offset voltage of the comparator, and a calibration control logic circuit for controlling the operation of the coarse calibration circuit and the fine calibration circuit. The calibration control logic circuit is used to output a coarse calibration control signal to control the coarse calibration circuit to coarsely calibrate the offset voltage of the comparator; the calibration control logic circuit is also used to output a fine calibration control signal after coarse calibration to control the fine calibration circuit to perform fine calibration, so as to inject charge into the input terminal of the comparator, thereby canceling the offset voltage of the comparator, and the calibration range of the fine calibration circuit is larger than one calibration step of the coarse calibration circuit.

2. The analog-to-digital converter according to claim 1, characterized in that, The coarse calibration circuit calibrates the offset voltage of the comparator by adjusting the load capacitance of the nodes inside the comparator.

3. The analog-to-digital converter according to claim 2, characterized in that, The comparator includes a built-in internal latch, and the coarse calibration circuit is used to adjust the load capacitance of the two output terminals of the internal latch to calibrate the offset voltage of the comparator.

4. The analog-to-digital converter according to claim 3, characterized in that, The coarse calibration circuit includes: a first branch electrically connected to the first output terminal of the internal latch, and a second branch electrically connected to the second output terminal of the internal latch; The first branch includes several first switched capacitor branches connected in parallel. Each first switched capacitor branch includes a first switch and a first capacitor. One end of the first switch is electrically connected to the first output terminal of the internal latch, and the other end of the first switch is grounded through the first capacitor. The control terminal of the first switch is connected to the calibration control logic circuit to receive the coarse calibration control signal. The second branch includes several second switched capacitor branches connected in parallel. Each second switched capacitor branch includes a second switch and a second capacitor. One end of the second switch is electrically connected to the second output terminal of the internal latch, and the other end of the second switch is grounded through the second capacitor. The control terminal of the second switch is connected to the calibration control logic circuit to receive the coarse calibration control signal.

5. The analog-to-digital converter according to claim 1, characterized in that, The calibration control logic circuit is used to control the fine calibration circuit to inject a preset calibration voltage into the input terminal of the comparator and to find a compensation voltage that can compensate for the offset voltage of the comparator through an iterative algorithm. The calibration control logic circuit is also used to apply the compensation voltage to the comparator when the comparator is working.

6. The analog-to-digital converter according to claim 5, characterized in that, The fine calibration circuit includes: a plurality of third branches electrically connected to the first input terminal of the comparator, and a plurality of fourth branches electrically connected to the second input terminal of the comparator; Each of the third branches includes a third capacitor and a third switch. One end of the third capacitor is electrically connected to the first input terminal of the comparator, and the other end of the third capacitor is electrically connected to one end of the third switch. The control terminal of the third switch is connected to the calibration control logic circuit so that the other end of the third switch switches between power supply VDD and ground, thereby injecting charge. Each of the fourth branches includes a fourth capacitor and a fourth switch. One end of the fourth capacitor is electrically connected to the second input terminal of the comparator, and the other end of the fourth capacitor is electrically connected to one end of the fourth switch. The control terminal of the fourth switch is connected to the calibration control logic circuit so that the other end of the fourth switch switches between power supply VDD and ground, thereby injecting charge.

7. The analog-to-digital converter according to any one of claims 1 to 6, characterized in that, The comparator includes: switching transistors M0, M1a, M1b, M2a, M2b, M3, M4, M5, and M6; The power supply VDD is connected to ground sequentially through the switching transistors M3, M1b, M1a, and M0, and also connected to ground sequentially through the switching transistors M6, M2b, M2a, and M0. The control terminals of the switching transistors M1a and M1b are connected together to form the first input terminal of the comparator. The connection point of the switching transistors M1a and M1b is connected to the power supply VDD through the switching transistor M4, and the connection point of the switching transistors M1a and M1b is electrically connected to the coarse calibration circuit. The control terminals of the switching transistors M2a and M2b are connected together to form the second input terminal of the comparator. The connection point of the switching transistors M2a and M2b is connected to the power supply VDD through the switching transistor M5, and the connection point of the switching transistors M2a and M2b is electrically connected to the coarse calibration circuit. The control terminals of the switching transistors M0, M3, M4, M5, and M6 are all connected to the first clock signal CLK.

8. The analog-to-digital converter according to any one of claims 1 to 6, characterized in that, The latch includes: switching transistors M7, M8, M9, M10, M11, M12, M13, and M14; The power supply VDD is connected to the control terminals of the switching transistors M10 and M12 in sequence through switching transistors M9 and M7. The control terminal of the switching transistor M7 is connected to the second output terminal Vmn of the comparator. The power supply VDD is connected to the control terminals of the switching transistors M9 and M11 in sequence through switching transistors M10 and M8. The control terminal of the switching transistor M8 is connected to the first output terminal Vmp of the comparator. The control terminal of the switching transistor M10 is connected to ground through the switching transistor M13. The control terminal of the switching transistor M10 is also connected to ground through the switching transistor M11. The control terminal of the switching transistor M9 is connected to ground through the switching transistor M12. The control terminal of the switching transistor M9 is also connected to ground through the switching transistor M14. The control terminals of both switching transistors M13 and M14 are connected to the second clock signal nCLK.

9. A storage-and-computing integrated device, characterized in that, include: The in-memory computing module and an analog-to-digital converter for converting the analog multiply-accumulate result output by the in-memory computing module into a digital signal, wherein the analog-to-digital converter is the analog-to-digital converter according to any one of claims 1 to 8.

10. The in-memory computing device according to claim 9, characterized in that, The in-memory calculation module includes: a first in-memory calculation circuit based on digital signals, a second in-memory calculation circuit based on analog signals, and an accumulator. The first in-memory calculation circuit performs multiplication and accumulation calculation on the input feature data and the high-weight bits of the weights based on a digital addition tree to obtain a first multiplication and accumulation result. The second in-memory calculation circuit performs multiplication and accumulation calculation on the input feature data and the low-weight bits of the weights based on a capacitor to obtain an analog multiplication and accumulation result. The analog-to-digital converter is used to perform analog-to-digital conversion on the analog multiplication and accumulation result output by the second in-memory calculation circuit to obtain a second multiplication and accumulation result. The accumulator is used to accumulate the first multiplication and accumulation result and the second multiplication and accumulation result.

11. An electronic device, characterized in that, The analog-to-digital converter includes any one of claims 1 to 8.

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