Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system are provided. The semiconductor device includes: a substrate; a gate electrode on the substrate; a gate insulating film between the substrate and the gate electrode; a trench defined within the substrate, the gate insulating film, and the gate electrode; a liner film within the trench and extending along at least a portion of a side surface of the gate insulating film, where the liner film is spaced apart from a lower surface of the trench; and an insulating layer filling the trench and covering an upper surface of the gate electrode, in which the gate insulating film includes a first portion spaced apart from the substrate film and a second portion adjacent to the substrate film, in which a thickness of the second portion is greater than a thickness of the first portion.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, electronic systems including semiconductor devices, and / or methods for manufacturing semiconductor devices. Background Technology

[0002] As electronic products become lighter, thinner, and simpler, the demand for high integration in semiconductor devices is increasing. As semiconductor devices become more highly integrated, the size of components included within them (e.g., transistors) further decreases, leading to leakage current issues. Therefore, controlling leakage current in semiconductor devices can be advantageous to improve their performance and / or reliability.

[0003] In electronic systems requiring data storage, semiconductor devices capable of storing high-capacity data can be advantageous. Therefore, methods to increase the data storage capacity of semiconductor devices are being investigated. For example, in one method of increasing the data storage capacity of a semiconductor device, a semiconductor device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0004] One technical objective of this disclosure is to provide a semiconductor device with improved reliability and / or performance.

[0005] Another technical objective of this disclosure is to provide an electronic system including a semiconductor device with improved reliability and / or performance.

[0006] The technical objectives of this disclosure are not limited to those mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of this disclosure, a semiconductor device may be provided, the semiconductor device comprising: a substrate; a gate electrode on the substrate; a gate insulating film between the substrate and the gate electrode; a trench defined within the substrate, the gate insulating film, and the gate electrode; a liner within the trench and extending along at least a portion of a side surface of the gate insulating film, wherein the liner is spaced apart from a lower surface of the trench; and an insulating layer filling the trench and covering an upper surface of the gate electrode, wherein the gate insulating film includes a first portion spaced apart from the liner and a second portion adjacent to the liner, wherein the thickness of the second portion is greater than the thickness of the first portion.

[0008] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate including a first region and a second region; a first gate electrode on the first region; a first gate insulating film having a first thickness and situated between the substrate and the first gate electrode; a first trench defined within the substrate, the first gate insulating film, and the first gate electrode; a liner within the first trench and extending along at least a portion of a side surface of the first gate insulating film, wherein the liner is spaced apart from a lower surface of the first trench; a second gate electrode on the second region; a second gate insulating film situated between the substrate and the second gate electrode and having a second thickness less than the first thickness; a second trench defined within the substrate, the second gate insulating film, and the second gate electrode; and an insulating layer filling the first trench and the second trench and covering the upper surface of each of the first gate electrode and the second gate electrode, wherein a first depth of the first trench from the upper surface of the first gate electrode to the bottom surface of the first trench is greater than a second depth of the second trench from the upper surface of the second gate electrode to the bottom surface of the second trench.

[0009] According to one aspect of this disclosure, an electronic system is provided, the electronic system comprising: a main substrate; a semiconductor memory device on the main substrate, including a cell region and a peripheral circuit region; and a controller on the main substrate and electrically connected to the semiconductor memory device, wherein the semiconductor memory device comprises: a first substrate in the cell region; a plurality of word lines on the first substrate, stacked on top of each other and spaced apart from each other; a channel structure extending in a vertical direction intersecting the upper surface of the first substrate to intersect the plurality of word lines; bit lines on the plurality of word lines and connected to the channel structure; a second substrate in the peripheral circuit region; and peripheral circuit elements on the second substrate, wherein the peripheral circuit elements comprise: a gate electrode on the second substrate; a gate electrode between the second substrate and the gate electrode; a trench defined within the second substrate, a gate insulating film, and the gate electrode; and a liner within the trench and extending along at least a portion of a side surface of the gate insulating film, wherein the liner is spaced apart from the lower surface of the trench.

[0010] However, the aspects of this disclosure are not limited to those set forth herein. The foregoing and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0012] Figure 1 It is a layout diagram used to illustrate a semiconductor device according to some example embodiments.

[0013] Figure 2 It is along Figure 1 A schematic cross-sectional view taken from lines AA, BB, and CC.

[0014] Figure 3 yes Figure 2 An enlarged sectional view of region P1 in the diagram.

[0015] Figure 4 It is based on some example embodiments along Figure 1 A schematic cross-sectional view of lines AA, BB, and CC cutting through the image.

[0016] Figure 5 yes Figure 4 An enlarged sectional view of region P2 in the diagram.

[0017] Figure 6 It is based on some other example embodiments along Figure 1 A schematic cross-sectional view of lines AA, BB, and CC.

[0018] Figure 7 yes Figure 6 An enlarged sectional view of region P3 in the diagram.

[0019] Figure 8 It is based on some example embodiments along Figure 1 A schematic cross-sectional view of lines AA, BB, and CC.

[0020] Figures 9 to 17 This is a diagram of an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device, based on some example embodiments.

[0021] Figure 18 These are schematic plan views illustrating a non-volatile memory device, based on some example embodiments of the technical ideas of this disclosure.

[0022] Figure 19 It is used to show Figure 18 A block diagram of a non-volatile memory device.

[0023] Figure 20 This is a schematic cross-sectional view illustrating a non-volatile memory device according to some example embodiments.

[0024] Figure 21 These are schematic block diagrams illustrating electronic systems according to some embodiments.

[0025] Figure 22 These are schematic perspective views illustrating electronic systems based on some example embodiments.

[0026] Figure 23 It shows along Figure 22 Various schematic cross-sectional views taken from line I-I' in the diagram. Detailed Implementation

[0027] Although terms such as first, second, upper (upper part), and lower (lower part) are used herein to describe various elements or components, it is clear that these elements or components are not limited by the terms. Rather, these terms are used only to distinguish one element or component from another. Therefore, it is clear that within the spirit of this disclosure, the first element or first component mentioned below can also be a second element or second component. Furthermore, it is clear that within the spirit of this disclosure, the lower element or lower component mentioned below can also be an upper element or upper component.

[0028] It will be understood that elements and / or properties that can be described as “perpendicular,” “parallel,” “coplanar,” etc. relative to other elements and / or their properties (e.g., structure, surface, orientation, etc.) may be “perpendicular,” “parallel,” “coplanar,” etc., or may be “substantially perpendicular,” “substantially parallel,” “substantially coplanar,” etc., relative to the other elements and / or their properties.

[0029] An element and / or its properties that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other elements and / or their properties (e.g., structure, surface, orientation, etc.) shall be understood as being “perpendicular,” “parallel,” or “coplanar” relative to said other elements and / or their properties, respectively, within manufacturing and / or material tolerances, and / or deviating from the “perpendicular,” “parallel,” or “coplanar” nature of said other elements and / or their properties by an amount and / or angle equal to or less than 10% (e.g., ±10% tolerance).

[0030] Figure 1 It is a layout diagram used to illustrate a semiconductor device according to some example embodiments. Figure 2 It is along Figure 1 A schematic cross-sectional view taken from lines AA, BB, and CC. Figure 3 yes Figure 2 An enlarged sectional view of region P1 in the diagram.

[0031] Reference Figures 1 to 3 A semiconductor device according to some example embodiments may include: a substrate 100, a plurality of circuit elements TR1, TR2 and TR3, gate insulating films 111, 112 and 113, gate electrodes 121, 122 and 123 and an insulating layer 130.

[0032] Substrate 100 may include, for example, a semiconductor substrate (such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate). Optionally, substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0033] The substrate 100 may include a first region I, a second region II, and a third region III, each subject to a different voltage.

[0034] For example, the voltage applied to the third region III may be greater than the voltage applied to the second region II, and may be less than the voltage applied to the first region I.

[0035] The first active region 411 can be formed on the first region I. The second active region 412 can be formed on the second region II. The third active region 413 can be formed on the third region III.

[0036] Multiple circuit elements TR1, TR2 and TR3 may be formed on substrate 100. For example, multiple circuit elements TR1, TR2 and TR3 may be formed on active regions 411, 412 and 413 of substrate 100.

[0037] In the following description, examples are given of each of the plurality of circuit elements TR1, TR2, and TR3 being implemented as a transistor. However, this is merely an example, and the technical ideas of this disclosure are not limited thereto. For example, the plurality of circuit elements TR1, TR2, and TR3 may include various active elements (such as transistors) and various passive elements (such as capacitors, resistors, and inductors).

[0038] In some example embodiments, each of the plurality of circuit elements TR1, TR2 and TR3 may be a high-voltage transistor or a low-voltage transistor.

[0039] The first gate electrode 121 may be formed on a first region I of the substrate 100. The first gate electrode 121 may also be formed on a first active region 411 of the substrate 100. Figure 1 In the diagram, the first gate electrode 121 is shown extending in the second direction X2. However, this is merely an example. The technical concept of this disclosure is not limited thereto. For example, the first gate electrode 121 may extend in a direction different from the second direction X2.

[0040] The first gate electrode 121 may include a conductive material. In some example embodiments, the first gate electrode 121 may include multiple conductive films. The multiple conductive films may include at least one of, for example, polycrystalline silicon and metallic materials.

[0041] The second gate electrode 122 may be formed on the second region II of the substrate 100. The second gate electrode 122 may also be formed on the second active region 412 of the substrate 100. Figure 1In the diagram, the second gate electrode 122 is shown extending in the second direction Z2. However, this is merely an example. The technical concept of this disclosure is not limited thereto. For example, the second gate electrode 122 may extend in a direction different from the second direction Z2.

[0042] The second gate electrode 122 may include a conductive material. In some example embodiments, the second gate electrode 122 may include multiple conductive films. The multiple conductive films may include at least one of, for example, polycrystalline silicon and metallic materials.

[0043] The third gate electrode 123 may be formed on the third region III of the substrate 100. The third gate electrode 123 may also be formed on the third active region 413 of the substrate 100. Figure 1 In the diagram, the third gate electrode 123 is shown extending in the second direction Y2. However, this is merely an example. The technical concept of this disclosure is not limited thereto. For example, the third gate electrode 123 may extend in a direction different from the second direction Y2.

[0044] The third gate electrode 123 may include a conductive material. In some example embodiments, the third gate electrode 123 may include multiple conductive films. The multiple conductive films may include at least one of, for example, polycrystalline silicon and metallic materials.

[0045] The first active region 411 may be formed in the substrate 100 and on each of the two opposite sides of the first circuit element TR1. The first active region 411 may be doped with impurities. For example, when the first circuit element TR1 is an n-type or p-type transistor, the first active region 411 may be doped with p-type or n-type impurities.

[0046] The second active region 412 may be formed in the substrate 100 and on each of the two opposite sides of the second circuit element TR2. The second active region 412 may be doped with impurities. For example, when the second circuit element TR2 is an n-type or p-type transistor, the second active region 412 may be doped with p-type or n-type impurities.

[0047] The third active region 413 may be formed in the substrate 100 and on each of the two opposite sides of the third circuit element TR3. The third active region 413 may be doped with impurities. For example, when the third circuit element TR3 is an n-type or p-type transistor, the third active region 413 may be doped with p-type or n-type impurities.

[0048] A first circuit element TR1 may be disposed in a first region I. The first circuit element TR1 may include a first gate electrode 121 and a first gate insulating film 111. A second circuit element TR2 may be disposed in a second region II. The second circuit element TR2 may include a second gate electrode 122 and a second gate insulating film 112. A third circuit element TR3 may be disposed in a third region III. The third circuit element TR3 may include a third gate electrode 123 and a third gate insulating film 113.

[0049] In some example embodiments, each of the first circuit element TR1 and the third circuit element TR3 may be a high-voltage transistor. For example, a high voltage of about 20V or higher may be applied to each of the first circuit element TR1 and the third circuit element TR3. However, some example embodiments of this disclosure are not limited thereto.

[0050] In some example embodiments, the second circuit element TR2 may be a low-voltage transistor. For example, a low voltage of about 10V or lower may be applied to the second circuit element TR2. However, some example embodiments of this disclosure are not limited thereto.

[0051] The first gate insulating film 111 may be disposed in the first region I of the substrate 100. The first gate electrode 121 may be disposed on the first gate insulating film 111. In other words, the first gate insulating film 111 may be disposed between the first gate electrode 121 and the substrate 100.

[0052] The first gate insulating film 111 may include a first portion 111_1 and a second portion 111_2. The first portion 111_1 may be spaced apart from the substrate 140, which will be described later. The second portion 111_2 may be disposed adjacent to the substrate 140.

[0053] The first portion 111_1 may have a first thickness M1. The thickness H1 of the second portion 111_2 may be greater than the first thickness M1 of the first portion 111_1. The thickness of the second portion 111_2 may increase as the second portion 111_2 extends toward the liner 140. The lowermost surface 111_2b of the second portion 111_2 may be disposed between the lower surface 111_1b of the first portion 111_1 and the lower surface 140b of the liner 140. The uppermost surface 111_2u of the second portion 111_2 may be disposed between the upper surface 111_1u of the first portion 111_1 and the upper surface 140u of the liner 140.

[0054] The uppermost surface 111_2u of the second part 111_2 may be located at a vertical height higher than the vertical level of the upper surface 111_1u of the first part 111_1. The lowermost surface 111_2b of the second part 111_2 may be located at a vertical height lower than the vertical level of the lower surface 111_1b of the first part 111_1. For example, the second part 111_2 may include a beak shape.

[0055] The first gate insulating film 111 may include a first portion 111_1 and a second portion 111_2 having a shape different from that of the first portion 111_1. For example, the second portion 111_2 may have a greater thickness, thereby increasing the physical distance between the first gate electrode 121 and the substrate 100. As the physical distance increases, it becomes easier to block leakage current.

[0056] A first trench t1 may be disposed in a substrate 100, a first gate insulating film 111, and a first gate electrode 121. A liner 140 may extend along at least a portion of the side surface of the first gate insulating film 111. The liner 140 may be spaced apart from the lower surface t1_b of the first trench t1. In other words, the liner 140 may not be disposed on the lower surface t1_b of the first trench t1. The length from the upper surface 121u of the first gate electrode 121 to the lower surface t1_b of the first trench t1 may be defined as a first length (or referred to as a "first depth") S1.

[0057] The lower width W1 and upper width W2 of the first groove t1 may be different from each other. For example, the lower width W1 of the first groove t1 may be smaller than its upper width W2. For example, the first groove t1 may include a shape in which the width decreases as the first groove t1 extends in the direction from top to bottom. However, some exemplary embodiments of this disclosure are not limited thereto.

[0058] The liner 140 can completely cover the sidewalls 111s of the first gate insulating film 111. The liner 140 can completely cover the sidewalls 121s of the first gate electrode 121. The liner 140 can cover a portion of the sidewalls 100s of the substrate 100.

[0059] At least a portion of the first gate insulating film 111 in the first region I may be covered by the liner 140. Therefore, the possibility of damage to the first gate insulating film 111 that may occur during subsequent processes can be prevented or reduced.

[0060] The lower surface 140b of the liner 140 may be disposed between the lowermost surface 111_2b of the second part 111_2 and the lower surface t1_b of the first trench t1. The upper surface 140u of the liner 140 may be coplanar with the upper surface 121u of the first gate electrode 121.

[0061] A step 105 may be formed between the liner 140 and the substrate 100. The step 105 may be formed due to the shape of the liner 140 protruding from the substrate 100 toward the first trench t1. For example, the step 105 may be formed between the lowermost surface 111_2b of the second portion 111_2 and the lower surface t1_b of the first trench t1.

[0062] The substrate 140 may include an oxide film. For example, the substrate 140 may include (but is not limited to) a silicon oxide film. Although the boundary between the substrate 140 and the first gate insulating film 111 is shown as visible, some exemplary embodiments of this disclosure are not limited thereto. For example, the boundary between the substrate 140 and the first gate insulating film 111 may be blurred.

[0063] The insulating layer 130 may include a first insulating layer 131 and a second insulating layer 132. The first insulating layer 131 may be disposed on the upper surface 121u of the first gate electrode 121. The second insulating layer 132 may fill trenches t1, t2, and t3. Although the insulating layer 130 is shown as a single layer, some exemplary embodiments of this disclosure are not limited thereto. For example, the insulating layer 130 may include two or more layers.

[0064] The second gate insulating film 112 may be disposed in the second region II of the substrate 100. The second gate electrode 122 may be disposed on the second gate insulating film 112. In other words, the second gate insulating film 112 may be disposed between the second gate electrode 122 and the substrate 100.

[0065] The second gate insulating film 112 may have a second thickness M2. The second thickness M2 may be less than the first thickness M1. A second trench t2 may be disposed in the substrate 100, the second gate insulating film 112, and the second gate electrode 122. The length from the upper surface 122u of the second gate electrode 122 to the lower surface t2_b of the second trench t2 may be defined as a second length (or referred to as a "second depth") S2. The second length S2 may be less than the first length S1.

[0066] The first insulating layer 131 may be disposed on the upper surface 122u of the second gate electrode 122. The second insulating layer 132 may fill the second trench t2.

[0067] The third gate insulating film 113 may be disposed in the third region III of the substrate 100. The third gate electrode 123 may be disposed on the third gate insulating film 113. In other words, the third gate insulating film 113 may be disposed between the third gate electrode 123 and the substrate 100.

[0068] The third gate insulating film 113 may have a third thickness M3. The third thickness M3 may be greater than the second thickness M2 and less than or equal to the first thickness M1. A third trench t3 may be disposed in the substrate 100, the third gate insulating film 113, and the third gate electrode 123. The length from the upper surface 123u of the third gate electrode 123 to the lower surface t3_b of the third trench t3 may be defined as a third length (or referred to as a "third depth") S3. The third length S3 may be less than the first length S1. In some embodiments, the third length S3 may be equal to, greater than, or less than the second length S2.

[0069] The first insulating layer 131 may be disposed on the upper surface 123u of the third gate electrode 123. The second insulating layer 132 may fill the third trench t3.

[0070] The lower surface 111b of the first portion 111_1 of the first gate insulating film 111 and the lower surface 113b of the third gate insulating film 113 may be coplanar with each other. The lower surface 112b of the second gate insulating film 112 may not be coplanar with the lower surface 111b of the first portion 111_1 of the first gate insulating film 111. In some embodiments, the lower surface of the first gate insulating film 111 (e.g., the lowermost surface 111_2b of the second portion 111_2) may be configured to be closer to the lower surface of the substrate 100 than the lower surface 112b of the second gate insulating film 112. The lower surface 112b of the second gate insulating film 112 may not be coplanar with the lower surface 113b of the third gate insulating film 113.

[0071] Each of the first to third gate insulating films 111, 112 and 113 may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3)) or hafnium oxide (HfO2).

[0072] Each of the first to third gate electrodes 121, 122, and 123 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), and titanium carbide (TiC). Tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. This disclosure is not limited thereto.

[0073] For example, insulating layer 130 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material having a dielectric constant lower than that of silicon oxide. Low-k materials may include, for example, FOX (flowable oxide), TOSZ (Toron silazane), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silica), degelatin, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, and / or combinations thereof. However, some exemplary embodiments of this disclosure are not limited thereto.

[0074] Figure 4 It is based on some example embodiments along Figure 1 A schematic cross-sectional view of lines AA, BB, and CC. Figure 5 yes Figure 4 An enlarged sectional view of region P2 in the diagram. For ease of description, a brief description is provided above. Figures 1 to 3 The description contains repeated content, or the description is omitted.

[0075] Reference Figure 4 and Figure 5 The liner 140 may cover a portion of the sidewall 111s of the first gate insulating film 111. The liner 140 may not cover the sidewall 121s of the first gate electrode 121. The liner 140 may cover a portion of the sidewall 100s of the substrate 100.

[0076] The upper surface 140u of the liner 140 may not be coplanar with the upper surface 121u of the first gate electrode 121. For example, the upper surface 140u of the liner 140 may be disposed between the lowermost surface 111_2b and the uppermost surface 111_2u of the second part 111_2.

[0077] A first step 105 and a second step 106 may be formed between the liner 140 and the substrate 100. The first step 105 may be formed by the shape of the lower surface 140b of the liner 140 protruding from the substrate 100 toward the first trench t1. The second step 106 may be formed by the shape of the upper surface 140u of the liner 140 protruding from the substrate 100 toward the first trench t1.

[0078] For example, a first step 105 may be formed between the lowermost surface 111_2b of the second portion 111_2 and the lower surface t1_b of the first groove t1. A second step 106 may be formed between the lowermost surface 111_2b of the second portion 111_2 and the uppermost surface 111_2u of the second portion 111_2.

[0079] Figure 6 It is based on some other example embodiments along Figure 1 A schematic cross-sectional view of lines AA, BB, and CC. Figure 7 yes Figure 6 An enlarged sectional view of region P3 in the diagram. For ease of description, a brief description is provided above. Figures 1 to 3 The description contains repeated content, or the description is omitted.

[0080] Reference Figure 6 and Figure 7 The liner 140 may cover a portion of the sidewall 111s of the first gate insulating film 111. The liner 140 may completely cover the sidewall 121s of the first gate electrode 121. The liner 140 may not cover the sidewall 100s of the substrate 100.

[0081] The lower surface 140b of the liner 140 may be disposed between the lowermost surface 111_2b and the uppermost surface 111_2u of the second part 111_2. The upper surface 140u of the liner 140 may be coplanar with the upper surface 121u of the first gate electrode 121.

[0082] A step 105 may be formed between the liner 140 and the substrate 100. The step 105 may be formed due to the shape of the liner 140 protruding from the substrate 100 toward the first groove t1. For example, the step 105 may be formed between the lowermost surface 111_2b and the uppermost surface 111_2u of the second portion 111_2.

[0083] Figure 8It is based on some other example embodiments along Figure 1 A schematic cross-sectional view of lines AA, BB, and CC. For ease of description, a brief description is provided above. Figures 1 to 3 The description contains repeated content, or the description is omitted.

[0084] Reference Figure 8 The lower surface 111b of the first portion 111_1 of the first gate electrode 121, the lower surface 112b of the second gate electrode 122, and the lower surface 113b of the third gate electrode 123 may be coplanar with each other.

[0085] Figures 9 to 17 This is a diagram of an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device, based on some example embodiments.

[0086] Reference Figure 9 The base 100 is configured to include a first region I, a second region II, and a third region III.

[0087] In the first region I, a first gate insulating film 111, a first gate electrode 121, a first mask MP1, a first sacrificial film 160, a second sacrificial film 170, and a second mask MP2 can be stacked sequentially. In the second region II, a second gate insulating film 112, a second gate electrode 122, a first mask MP1, a first sacrificial film 160, a second sacrificial film 170, and a second mask MP2 can be stacked sequentially. In the third region III, a third gate insulating film 113, a third gate electrode 123, a first mask MP1, a first sacrificial film 160, a second sacrificial film 170, and a second mask MP2 can be stacked sequentially.

[0088] The second mask MP2 may include a first opening F1 on a first region I, a second opening F2 on a second region II, and a third opening F3 on a third region III. The width C1 of the first opening F1 may be equal to the width C3 of the third opening F3. The width C2 of the second opening F2 may be less than each of the widths C1 of the first opening F1 and C3 of the third opening F3.

[0089] The vertical dimension B1 between the upper surface 121u of the first gate electrode 121 and the bottom of the substrate 100 in the first region I can be equal to the vertical dimension B3 between the upper surface 123u of the third gate electrode 123 and the bottom of the substrate 100 in the third region III. In other words, the upper surface 121u of the first gate electrode 121 and the upper surface 123u of the third gate electrode 123 can be coplanar with each other.

[0090] The vertical dimension B2 between the upper surface 122u of the second gate electrode 122 and the bottom of the substrate 100 in the second region II may be greater than the vertical dimension B1 between the upper surface 121u of the first gate electrode 121 and the bottom of the substrate 100 in the first region I. The vertical dimension B2 between the upper surface 122u of the second gate electrode 122 and the bottom of the substrate 100 in the second region II may be greater than the vertical dimension B3 between the upper surface 123u of the third gate electrode 123 and the bottom of the substrate 100 in the third region III.

[0091] The first mask MP1 may include, for example, polyethylene oxide (PEO). However, some exemplary embodiments of this disclosure are not limited thereto. The first sacrificial film 160 may include at least one of a carbon-containing material and a metal. For example, the first sacrificial film 160 may be made by spin-coating a hard mask (SOH). The second sacrificial film 170 may be used as an anti-reflective film. The second mask MP2 may include, for example, a photoresist.

[0092] Reference Figure 10 A first-first trench t1_1, a first-second trench t2_1, and a first-third trench t3_1 are formed in the first mask MP1 using the second mask MP2. After the trenches are formed in the first mask MP1, the first sacrificial film 160, the second sacrificial film 170, and the second mask MP2 can be removed.

[0093] Reference Figure 11 The photoresist PR can be formed on a portion of the first region I, the second region II, and the third region III. As a result, only a portion of the first mask MP1 in the first region I can be exposed.

[0094] An etching process can be performed on the first region I using the first mask MP1. A second-first trench t1_2 can be formed by performing an etching process only on the first region I.

[0095] The second-first trench t1_2 can be, for example... Figure 10 The first trench t1_1 shown is deep.

[0096] Reference Figure 12 Plasma processing can be performed while the photoresist PR has already formed on regions II and III. For reference, regions II and III can be covered by the photoresist PR without being exposed to plasma.

[0097] Reference Figure 13 It can remove the photoresist formed on the second region II and the third region III. Figure 12 (PR in the text). Therefore, the first-second trench t2_1 and the first-third trench t3_1 can be exposed.

[0098] In such Figure 12 In the plasma process shown, a first portion 111_1 and a second portion 111_2 may be formed in a first gate insulating film 111 on a first region I. The first portion 111_1 may be spaced apart from a second-first trench t1_2. The second portion 111_2 may be exposed to the second-first trench t1_2. The thickness H1 of the second portion 111_2 may be greater than the thickness M1 of the first portion 111_1. The thickness H1 of the second portion 111_2 may increase as the second portion 111_2 extends toward the second-first trench t1_2.

[0099] Reference Figure 14 A liner 140 may be formed on the second-first trench t1_2, the first-second trench t2_1, the first-third trench t3_1, and the first mask MP1. The liner 140 may be formed along the contour of each of the trenches. For example, the liner 140 may include an oxide film.

[0100] Reference Figure 15 A portion of the liner 140 can be removed. A portion of the liner 140 formed in the second-first trench t1_2 is retained, and a portion of the liner 140 disposed on the lower surface t1_2b of the second-first trench t1_2 can be removed. As a portion of the liner 140 is removed and a portion is retained, a step 105 can be formed between the liner 140 and the substrate 100.

[0101] A portion of the liner 140 formed in the first-second trench t2_1 and a portion of the liner 140 formed in the first-third trench t3_1 are shown as being removed. However, some exemplary embodiments of this disclosure are not limited thereto. For example, a portion of the liner 140 formed in the first-second trench t2_1 and a portion of the liner 140 formed in the first-third trench t3_1 may be retained. A portion of the liner 140 formed on the first mask MP1 may be removed.

[0102] Reference Figure 16 An etching process can be performed on a first region I, a second region II, and a third region III. The etching process can be performed to form a first trench t1 in the first region I, a second trench t2 in the second region II, and a third trench t3 in the third region III.

[0103] The length from the upper surface 121u of the first gate electrode 121 to the lower surface t1_b of the first trench t1 can be defined as a first length S1. The length from the upper surface 122u of the second gate electrode 122 to the lower surface t2_b of the second trench t2 can be defined as a second length S2. The length from the upper surface 123u of the third gate electrode 123 to the lower surface t3_b of the third trench t3 can be defined as a third length S3.

[0104] The second length S2 can be less than the first length S1. The third length S3 can be less than the first length S1. The second length S2 can be equal to the third length S3.

[0105] Reference Figure 17 The first mask MP1 can be removed.

[0106] Next, refer to Figure 2 An insulating layer 130 can be formed to fill the first trench t1, the second trench t2 and the third trench t3, and cover the upper surfaces 121u, 122u and 123u of the gate electrodes 121, 122 and 123.

[0107] Figure 18 These are schematic plan views illustrating a non-volatile memory device, based on some example embodiments of the technical ideas of this disclosure. Figure 19 It is used to show Figure 18 A block diagram of a non-volatile memory device.

[0108] Reference Figure 18 and Figure 19 According to some example embodiments, a non-volatile memory device may include a cell region (CELL) and a peripheral circuitry region (PERI). The PERI may include a row decoder region (ROW DCR), a page buffer region (PBR), and a column decoder region (COL DCR).

[0109] The cell region (CELL) may include the cell array region (CAR) and the contact region (CTR).

[0110] A memory cell array 1, comprising multiple memory cells, may be formed in a cell array region CAR. The memory cell array 1 may include multiple memory cells and multiple word lines and multiple bit lines electrically connected to the memory cells. In some example embodiments, the memory cell array 1 may include multiple memory blocks BLK0 to BLKn as data erasure units.

[0111] The contact area CTR can be placed between the cell array area CAR and the peripheral circuit area PERI. For example, the contact area CTR can be placed between the cell array area CAR and the row decoder area ROW DCR.

[0112] The row decoder 2, which selects word lines of memory cell array 1, can be located in the row decoder region ROW DCR. A contact wiring structure electrically connecting memory cell array 1 and row decoder 2 can be formed in the contact region CTR. Row decoder 2 can select one of memory blocks BLK0 to BLKn of memory cell array 1 based on address information, and select one word line from the selected memory block. Row decoder 2 can, in response to control by a control circuit (not shown), provide word line voltage generated from a voltage generation circuit (not shown) to each of the selected and unselected word lines.

[0113] Page buffer 3, used for reading information stored in memory cells, can be formed in the page buffer region PBR. Depending on the operating mode, page buffer 3 can temporarily store data to be stored in the memory cell or detect data stored in the memory cell. Page buffer 3 can operate as a write driver circuit in programming operation mode and as a sense amplifier circuit in read operation mode.

[0114] A column decoder 4 connected to the bit lines of the memory cell array 1 may be formed in the column decoder region COL DCR. The column decoder 4 may provide a data transfer path between the page buffer 3 and an external device (e.g., a memory controller).

[0115] Figure 20 This is a schematic cross-sectional view illustrating a non-volatile memory device according to some example embodiments. For ease of description, a brief description is used as described above. Figures 1 to 8 The description contains repeated content, or the description is omitted.

[0116] Reference Figure 20 According to some example embodiments, a non-volatile memory device may include a peripheral circuitry region (PERI) and a cell region (CELL).

[0117] Each of the peripheral circuit region PERI and the cell region CELL may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0118] The word line bonding area (WLBA) can be defined as an area provided with a plurality of cell contact plugs 340, etc. Lower bonding metals 271b and 272b can be formed on the second metal layer 240 of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI can be electrically connected in a bonding manner to the upper bonding metals 371b and 372b of the cell area CELL. Each of the lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b can be made of aluminum, copper, or tungsten. In the word line bonding area WLBA, the cell contact plugs 340 can be connected to the peripheral circuit area PERI via the upper bonding metals 371b and 372b of the cell area CELL and the lower bonding metals 271b and 272b of the peripheral circuit area PERI.

[0119] The bit line bonding region BLBA can be defined as the region where the channel structure CH and bit line 360c are provided. Bit line 360c can be electrically connected to a fifth circuit element 220b in the bit line bonding region BLBA. For example, bit line 360c can be connected to upper bonding metals 371c and 372c in the peripheral circuit region PERI. Upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c connected to the fifth circuit element 220b.

[0120] A common-source contact plug 380 may be disposed in the external pad bonding region PA. The common-source contact plug 380 may be made of a conductive material (such as a metal, metal compound, or polysilicon) and may be electrically connected to the common-source wire 320. A first metal layer 350a and a second metal layer 360a may be disposed below the common-source contact plug 380 and may be stacked sequentially. For example, the region where the common-source contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding region PA. Additionally, input / output pads 205 and 305 may be disposed in the external pad bonding region PA.

[0121] In each of the outer pad bonding region PA and the bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI, respectively, the metal pattern of the uppermost metal layer may exist as a dummy pattern. Alternatively, in each of the outer pad bonding region PA and the bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI, respectively, the uppermost metal layer may be empty.

[0122] In a non-volatile memory device according to some example embodiments, in the external pad bonding region PA, a lower metal pattern 273a with the same shape as the upper metal pattern 372a of the cell region CELL can be formed in the uppermost metal layer of the peripheral circuit region PERI in a manner corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding region PA, an upper metal pattern with the same shape as the lower metal pattern of the peripheral circuit region PERI can be formed in the upper metal layer of the cell region CELL in a manner corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0123] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 372d with the same shape as the lower metal pattern 272d of the peripheral circuit region PERI can be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 272d formed in the uppermost metal layer of the peripheral circuit region PERI. The contact may not be formed on the upper metal pattern 372d formed in the uppermost metal layer of the cell region CELL.

[0124] The peripheral circuit region PERI may include a first substrate 100, an interlayer insulating film 150, a plurality of circuit elements TR1, TR2, TR3, 220a and 220b formed in the first substrate 100, first metal layers 144, 230a and 230b connected to each of the plurality of circuit elements TR1, TR2, TR3, 220a and 220b, and second metal layers 240a and 240b formed on the first metal layers 144, 230a and 230b.

[0125] First circuit element (see) Figure 1 TR1 in the first circuit element can be electrically connected to word line WL. For example, the first region where the first circuit element TR1 is located (see...) Figure 1 The first region I) can be compared with Figure 18 The row decoder region ROW DCR corresponds to this. The first circuit element TR1 can provide the row decoder in the peripheral circuit region PERI (see...). Figure 19 Line decoder 2 in the middle.

[0126] The third circuit element TR3 can be electrically connected to bit line 360c. For example, a third region (see...) is provided with the third circuit element TR3. Figure 1 The third region (III) in the middle can be compared with Figure 18 The page buffer region PBR corresponds to this. The third circuit element TR3 can provide a page buffer in the peripheral circuit region PERI (see...). Figure 19 Page buffer 3 in the middle.

[0127] The second circuit element TR2 may be disposed in at least one of the first region I and the second region II. The second circuit element TR2 may be disposed in regions other than the first region I and the second region II.

[0128] The groove T can be Figures 1 to 8 One of the first groove t1, the second groove t2, and the third groove t3 shown in the figure.

[0129] In this disclosure, only the first metal layers 144, 230a, and 230b and the second metal layers 240, 240a, and 240b are shown and described. However, some exemplary embodiments of this disclosure are not limited thereto. At least one additional metal layer may be formed on the second metal layers 240, 240a, and 240b. At least some of the one or more metal layers formed on the second metal layers 240, 240a, and 240b may be made of aluminum or the like, having a lower resistance than the copper constituting the second metal layers 240, 240a, and 240b.

[0130] In some example embodiments, the first metal layers 144, 230a and 230b may be made of tungsten, which has relatively high resistance, and the second metal layers 240, 240a and 240b may be made of copper, which has relatively low resistance.

[0131] Interlayer insulating film 150 may be disposed on first substrate 100 to cover multiple circuit elements TR1, TR2 and TR3, 220a and 220b, first metal layer 144, 230a and 230b and second metal layer 240, 240a and 240b.

[0132] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 310 and a common-source line 320. On the second substrate 310, multiple word lines (WL) (e.g., 331 to 338) may be stacked along a vertical direction D3 intersecting the upper surface of the second substrate 310. Serial select lines (e.g., ...) Figure 21 UL1, UL2) and ground selection wire (e.g., Figure 21 LL1 and LL2 can be set at the top and bottom of the word line WL, respectively. Multiple word lines WL can be set between the serial select line and the ground select line.

[0133] The channel structure CH can extend vertically and pass through the word line WL, the serial select line, and the ground select line. The common source line 320 can be formed as a semiconductor pattern that contacts the channel structure CH.

[0134] The word line WL may extend along a direction parallel to the upper surface of the second substrate 310 (e.g., a first direction D1) and may be connected to a plurality of cell contact plugs 340. The word line WL and the cell contact plugs 340 may be connected to each other via pads formed by extending at least some of the word lines WL to different lengths. A first metal layer 350b and a second metal layer 360b may be stacked sequentially and may be disposed below each of the cell contact plugs 340 connected to the word line WL, and may be connected to the bottom of each of the cell contact plugs 340 connected to the word line WL.

[0135] In some example embodiments, a lower insulating film 201 covering the lower surface of the first substrate 100 may be formed below the first substrate 100, and a first input / output pad 205 may be formed on the lower insulating film 201. The first input / output pad 205 may be connected via a first input / output contact plug 203 to at least one of a plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit region PERI, and may be insulated from the first substrate 100 via the lower insulating film 201. Furthermore, a side insulating film may be disposed between the first input / output contact plug 203 and the first substrate 100 to electrically insulate the first input / output contact plug 203 from the first substrate 100.

[0136] In some example embodiments, an upper insulating film 301 covering the upper surface of the second substrate 310 may be formed on top of the second substrate 310, and a second input / output pad 305 may be disposed on the upper insulating film 301. The second input / output pad 305 may be connected via a second input / output contact plug 303 to at least one of a plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit region PERI.

[0137] In some example embodiments, the second substrate 310 and the common source line 320 may not be located in the region where the second input / output contact plug 303 is provided. Additionally, the second input / output pad 305 may not overlap with the word line WL in the vertical direction D3. The second input / output contact plug 303 may be insulated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310 (e.g., the first direction D1) and may extend through the interlayer insulating film 315 in the cell region CELL to connect to the second input / output pad 305.

[0138] In some example embodiments, a first input / output pad 205 and a second input / output pad 305 may optionally be formed. For example, a non-volatile memory device according to some example embodiments may include only the first input / output pad 205 disposed on the first substrate 100, or may include only the second input / output pad 305 disposed on the second substrate 310. Alternatively, a non-volatile memory device according to some example embodiments may include both the first input / output pad 205 and the second input / output pad 305.

[0139] Figure 21 These are schematic block diagrams illustrating electronic systems based on some example embodiments.

[0140] Figure 21 This is a schematic diagram illustrating an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0141] Reference Figure 21 An electronic system 1000 according to some example embodiments of this disclosure may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100, or may be an electronic device including a storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0142] Semiconductor device 1100 may be a non-volatile memory device, for example, as referenced above. Figures 1 to 20 The described NAND flash memory device. Semiconductor device 1100 may include a first structure 110F and a second structure 1100S disposed on the first structure 110F. In some example embodiments, the first structure 110F may be disposed adjacent to the second structure 1100S. The first structure 110F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including bit line BL, common source line CSL, word line WL, first gate upper line UL1 and second gate upper line UL2, first gate lower line LL1 and second gate lower line LL2, and a memory cell string CSTR between bit line BL and common source line CSL.

[0143] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary according to the example embodiment.

[0144] In some example embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word lines WL may be the gate electrodes of memory cell transistors MCT, respectively. Gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0145] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 are electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 110F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 110F to the second structure 1100S.

[0146] In the first structure 110F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connection wiring 1135 extending from the first structure 110F to the second structure 1100S.

[0147] Controller 1200 may include processor 1210, NAND controller 1220, and host interface (I / F) 1230. According to some example embodiments, electronic system 1000 may include multiple semiconductor devices 1100. In this case, controller 1200 may control multiple semiconductor devices 1100.

[0148] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate based on predefined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between electronic system 1000 and external host. Upon receiving control commands from external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0149] Figure 22 These are schematic perspective views illustrating electronic systems based on some example embodiments. Figure 23 It shows along Figure 22 Various schematic cross-sectional views are shown, intercepted by line I-I'. For ease of description, a brief description is provided, similar to the ones used above. Figures 1 to 21 The description contains repeated content, or the description is omitted.

[0150] Reference Figure 22 An electronic system according to some example embodiments may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and at least one DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 via a line pattern 2005 formed on the main substrate 2001.

[0151] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host using one of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), Mobile Physical Layer for Universal Flash Memory (UFS) (M-Phy), etc. In some example embodiments, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0152] The main controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000.

[0153] DRAM 2004 can be used as a buffer memory to reduce the difference in operating speed between the external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in electronic system 2000 can operate as a cache memory and can provide space for temporary data storage during the control operation of semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, in addition to a NAND controller for controlling semiconductor package 2003, main controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0154] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be implemented as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 disposed on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structure 2400.

[0155] The package substrate 2100 may be implemented as a printed circuit board including a package pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may be coupled with... Figure 21 The input / output pad 1101 corresponds to the input / output pad 1101 in the semiconductor chip 2200. Each of the semiconductor chips 2200 may include a memory block 3210 and a channel structure 3220. The memory block 3210 may correspond to the memory block in 20, and the channel structure 3220 may correspond to the input / output pad 1101 in the semiconductor chip 2200. Figure 20 The channel structure CH corresponds to this.

[0156] In some example embodiments, the connection structure 2400 may be implemented as bonding wiring that electrically connects the input / output pads 2210 and the package pads 2130 to each other. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wiring scheme and may be electrically connected to the package pads 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (also known as "through-silicon vias"), TSVs, instead of using a bonding wiring scheme.

[0157] In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate intermediate substrate, different from the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be connected to each other via wires formed in the intermediate substrate.

[0158] Reference Figure 23 In the semiconductor package 2003A, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, a lower pad 2125 placed on or exposed through the lower surface of the package substrate body portion 2120, and internal wiring 2135.

[0159] The lower pad 2125 can be connected to, for example, via conductive connector 2800. Figure 22 Wiring pattern 2005 of the main substrate 2001 of the electronic system 2000.

[0160] Each of the semiconductor chips 2200b may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding manner.

[0161] The first structure 4100 may include a peripheral circuit region comprising peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 extending through the gate stack structure 4210, an isolation structure (not shown), and word lines electrically connected to the memory channel structure 4220 and the gate stack structure 4210, respectively. Figure 21The second bonding structure 4250 (WL in the memory channel structure 4220) may be via a bit line 4240 electrically connected to the memory channel structure 4220 and a word line (WL in the memory channel structure 4220). Figure 21 The gate connection wiring 4235 of the WL is electrically connected to the memory channel structure 4220 and the word line (WL) respectively. Figure 21 (WL in the first structure 4100). The first joining structure 4150 of the first structure 4100 and the second joining structure 4250 of the second structure 4200 can join each other while in contact with each other. The joint of each of the first joining structure 4150 and the second joining structure 4250 can be made of, for example, copper (Cu).

[0162] Each of the semiconductor chips 2200b may also include an input / output pad electrically connected to the peripheral wiring 4110 of the first structure 4100. Figure 22 (2210 in the middle).

[0163] Any elements and / or functional blocks disclosed above may include processing circuitry (such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof) or be implemented in processing circuitry such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof (such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof). For example, processing circuitry may more specifically include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processing circuitry may include electrical components such as transistors, resistors, capacitors, etc. Processing circuitry may include electronic components such as logic gates, including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0164] According to some of the foregoing example embodiments, the contact structure that contacts the contact region of the gate electrode can be formed by a process for forming the contact structure, without the need for a step process for forming the contact region of the gate electrode in a stepped shape. In this case, in a semiconductor device with a multi-level stacked structure, a contact structure with a bend can be formed at the same height as the bend corresponding to the channel structure of each level. That is, in the process of forming the channel hole for the channel structure, the contact hole of the contact structure can be formed simultaneously, so that the depth of the contact hole etched in one step can be significantly reduced. Therefore, the possibility of defects such as short circuits caused by the expansion of the contact hole due to the formation of a relatively deep contact hole can be prevented or reduced.

[0165] Although some exemplary embodiments of this disclosure have been described with reference to the accompanying drawings, this disclosure is not limited to the above exemplary embodiments, but can be implemented in various different forms. It will be understood by those skilled in the art that this disclosure can be practiced in other specific forms without altering the technical spirit or essential features of this disclosure. Therefore, it should be understood that the exemplary embodiments described above are not limiting in any respect, but rather illustrative.

[0166] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without fundamentally departing from the principles of the inventive concept. Therefore, the exemplary embodiments disclosed herein are for general and descriptive purposes only and not for limiting purposes.

Claims

1. A semiconductor device, comprising: Base; The gate electrode is on the substrate; A gate insulating film is located between the substrate and the gate electrode; The trench is defined within the substrate, the gate insulating film, and the gate electrode; A liner, within the trench and extending at least along a portion of the side surface of the gate insulating film, wherein the liner is spaced apart from the lower surface of the trench; and An insulating layer fills the trench and covers the upper surface of the gate electrode, wherein... The gate insulating film includes a first portion spaced apart from the liner and a second portion adjacent to the liner. The thickness of the second part is greater than the thickness of the first part.

2. The semiconductor device according to claim 1, wherein, The lower surface of the liner is between the lowest surface of the second part and the lower surface of the groove.

3. The semiconductor device according to claim 1, wherein, The upper surface of the liner is coplanar with the upper surface of the gate electrode.

4. The semiconductor device according to claim 1, wherein, The liner includes an oxide film.

5. The semiconductor device according to claim 1, wherein, The thickness of the second part increases as the second part extends toward the liner.

6. The semiconductor device according to claim 1, wherein, The lowest surface of the second part is between the lower surface of the first part and the lower surface of the liner.

7. The semiconductor device according to claim 1, wherein, The uppermost surface of the second part is between the upper surface of the first part and the upper surface of the liner.

8. The semiconductor device according to claim 1, further comprising: Steps, between the liner and the substrate.

9. The semiconductor device according to claim 1, wherein, The vertical height of the uppermost surface of the second part is higher than the vertical height of the upper surface of the first part, and The vertical height of the bottom surface of the second part is lower than the vertical height of the bottom surface of the first part.

10. A semiconductor device, comprising: The substrate includes a first region and a second region; The first gate electrode is located in the first region; A first gate insulating film having a first thickness is located between a substrate and a first gate electrode; The first trench is defined within the substrate, the first gate insulating film, and the first gate electrode; A liner is located within the first trench and extends at least a portion of the side surface of the first gate insulating film, wherein the liner is spaced apart from the lower surface of the first trench. The second gate electrode is located in the second region; A second gate insulating film is located between the substrate and the second gate electrode, and has a second thickness less than the first thickness; The second trench is defined within the substrate, the second gate insulating film, and the second gate electrode; and An insulating layer fills the first and second trenches and covers the upper surface of each of the first and second gate electrodes. Wherein, the first depth of the first trench from the upper surface of the first gate electrode to the lower surface of the first trench is greater than the second depth of the second trench from the upper surface of the second gate electrode to the lower surface of the second trench.

11. The semiconductor device according to claim 10, wherein, The lower surface of the first gate insulating film is closer to the lower surface of the substrate than the lower surface of the second gate insulating film.

12. The semiconductor device according to claim 10, wherein, The first gate insulating film includes a first portion spaced apart from the liner and a second portion adjacent to the liner. The thickness of the second part is greater than the thickness of the first part.

13. The semiconductor device according to claim 12, wherein, The vertical height of the uppermost surface of the second part is higher than the vertical height of the upper surface of the first part, and The vertical height of the bottom surface of the second part is lower than the vertical height of the bottom surface of the first part.

14. The semiconductor device according to claim 12, wherein, The lower surface of the liner is positioned between the lowermost surface of the second part and the lower surface of the first groove.

15. The semiconductor device according to claim 10, wherein, The base also includes a third region. The semiconductor device further includes: The third gate electrode is located in the third region of the substrate. A third gate insulating film is located between the substrate and the third gate electrode, and has a third thickness; The third trench is defined within the substrate, the third gate insulating film, and the third gate electrode; and An insulating layer fills the third trench and covers the upper surface of the third gate electrode, and The third thickness is greater than the second thickness but less than the first thickness.

16. The semiconductor device according to claim 15, wherein, The third depth of the third trench from the upper surface of the third gate electrode to the lower surface of the third trench is less than the first depth of the first trench, and the third depth of the third trench is greater than the second depth of the second trench.

17. The semiconductor device according to claim 10, wherein, The upper surface of the liner is coplanar with the upper surface of the first gate electrode.

18. An electronic system comprising: Primary base; A semiconductor memory device, on a main substrate, including cell regions and peripheral circuit regions; as well as The controller is located on the main substrate and is electrically connected to the semiconductor memory device. The semiconductor memory device includes: The first base is located in the cell region. Multiple letter lines, on a first base, are stacked on top of each other and spaced apart from one another; The channel structure extends in a vertical direction intersecting the upper surface of the first substrate so as to intersect the plurality of letter lines; Bit lines, on the plurality of word lines, and connected to the channel structure; The second substrate, in the peripheral circuit region; and Peripheral circuit elements, on the second substrate, The peripheral circuit elements include: a gate electrode on a second substrate; a gate insulating film between the second substrate and the gate electrode; a trench defined within the second substrate, the gate insulating film, and the gate electrode; and a liner within the trench and extending at least along a portion of a side surface of the gate insulating film, wherein the liner is spaced apart from the lower surface of the trench.

19. The electronic system according to claim 18, wherein, Peripheral circuit components electrically connect the word lines and the controller to each other.

20. The electronic system according to claim 18, wherein, The peripheral circuitry components electrically connect the bit lines and the controller to each other.

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