Multi-port memory testing using concurrent operations

Abstract

A memory test circuit in a circuit is configured to perform a test on one or more memories in the circuit, each of the one or more memories having a plurality of logical ports. The memory test circuit includes: a test algorithm control unit configured to implement a test algorithm; a reference address generator configured to generate a reference address based on the test algorithm; one or more concurrent address generators configured to generate one or more concurrent addresses based on the reference address; and an address selection circuit for each of the one or more memories configured to select one of the one or more concurrent addresses or the reference address for each of the plurality of logical ports based on an address selection signal. One logical port is configured to receive an algorithm command and the reference address, while the other logical ports are configured to receive a concurrent command and the concurrent address.

Description

TECHNICAL FIELD

[0001] The technology disclosed herein relates to embedded memory testing. Various implementations of the disclosed technology can be particularly suitable for testing multi-port memories. BACKGROUND

[0002] Multi-port memories have multiple independent access ports. Each access port can be coupled to one processor or a portion of one processor through a bus that includes address, data, and control lines. These independent access ports and associated buses allow multiple processors to simultaneously read from or write to different regions of the memory without interfering with each other. This parallel operation can reduce bottlenecks in memory access, resulting in faster data transfer and processing. Multi-port memories can also be used to implement shared memory systems in network environments. For example, in a packet-switched network, a shared memory system can be used to store data packets for transmission between nodes. Through different access ports, these nodes can simultaneously access the memory without interfering with each other. This can result in high throughput, low latency, and simplified system design.

[0003] Due to the close proximity to technology limits in design, memories are more prone to failure than other circuits, which not only affects manufacturing yield but also adversely affects circuit reliability. Built-in self-test (BIST) techniques are commonly used to identify defects and issues in memories both in manufacturing test and in-system test. Conventional memory test solutions have difficulty testing multi-port memories in an environment similar to actual applications. One challenge is how to test all bitline coupling faults and wordline coupling faults within a reasonable amount of time even if the memory layout is unknown. Another challenge is how to achieve simultaneous access to all ports while avoiding conflicts. Yet another challenge is how to avoid attempting to read or write operations outside the memory address range. Therefore, there is a strong need for a solution that overcomes one or more of these challenges, minimizes the number of additional test circuits, and avoids modifying the memory under test. SUMMARY

[0004] Various aspects of the disclosed technology relate to multi-port memory testing. In one aspect, a memory test circuit in a circuit is provided, configured to perform a test on one or more memories in the circuit, each of the one or more memories having a plurality of logical ports, the plurality of logical ports being partitioned into a plurality of test ports, each of the plurality of test ports being capable of performing both a write operation and a read operation and comprising one or two logical ports, the memory test circuit comprising: a test algorithm control unit configured to implement a test algorithm, the test algorithm comprising a sequence of read operations and write operations, each execution of the test algorithm performing a memory test through one of the plurality of test ports, one logical port in the tested test port being configured to receive an algorithm command corresponding to one read operation or one write operation in the sequence of read operations and write operations, logical ports not receiving the algorithm command being configured to receive concurrent commands generated based on the test algorithm; a reference address generator configured to generate a reference address for the one logical port in the tested test port based on the test algorithm; one or more concurrent address generators configured to generate one or more concurrent addresses for the logical ports receiving the concurrent commands based on the reference address; a test port counter configured to increment and generate a test port count signal after each execution of the test algorithm; and an address selection circuit for each of the one or more memories configured to select one of the one or more concurrent addresses or the reference address for each of the plurality of logical ports based on an address selection signal, the address selection signal being generated based on the test port count signal.

[0005] The memory test circuit can further comprise: a global control signal generator configured to generate the algorithm command and the concurrent commands based on the test algorithm; and a local control signal generator in a memory test interface circuit for each of the one or more memories, the local control signal generator configured to both pass the algorithm command to the one logical port in the tested test port and pass the concurrent commands to the logical ports not receiving the algorithm command, and generate the address selection signal based on the test port count signal.

[0006] The address selection signal can comprise a row address selection signal and a column address selection signal, and be configurable to allow a logical port to receive a row address of one of the one or more concurrent addresses and a column address of the reference address, a column address of one of the one or more concurrent addresses and a row address of the reference address, or both a row address and a column address of one of the one or more concurrent addresses.

[0007] The one or more concurrent addresses can be the same as the global concurrent address. Alternatively, the local concurrent address generator is configured to generate the one or more concurrent addresses based on the global concurrent address, no more than one of the one or more concurrent addresses being the same as the global concurrent address for a writable logical port.

[0008] A row address of the global concurrent address can be derived by adding 1 or subtracting 1 from a row address of the reference address, and a column address of the global concurrent address can be derived by adding 1 or subtracting 1 from a column address of the reference column address. The adding 1 or subtracting 1 can be based on whether the reference address is changing in ascending order or descending order.

[0009] Each of the one or more concurrent addresses can be obtained at least in part by applying a concurrent address mask to one or more bits of the reference address. The concurrent address mask can replace selected bits of the reference address with a unique fixed bit pattern, invert one or a unique combination of selected bits of the reference address, or both.

[0010] Each of the one or more concurrent address generators can be in a memory test interface circuit coupled to each of the one or more memories. Each of the one or more concurrent address generators can include an inverter circuit configured to invert a least significant bit of an intermediate concurrent address, the intermediate concurrent address being the reference address or the reference address minus an offset, and a bit replacement circuit to replace selected bits of the intermediate concurrent address with different fixed bit patterns for different logical ports. The inverting and the replacing can be performed on both row addresses and column addresses, and wherein the address selection signal can include a row address selection signal and a column address selection signal and be configurable to allow a logical port to receive a row address of one of the one or more concurrent addresses and a column address of the reference address, a column address of one of the one or more concurrent addresses and a row address of the reference address, or both a row address and a column address of one of the one or more concurrent addresses.

[0011] Some or all of the one or more concurrent address generators can include address threshold check circuitry configured to output a row address of the intermediate concurrent address that is the same as a row address of the reference address if the row address of the reference address is less than a predetermined threshold, or that is an address obtained by subtracting an offset value from the row address of the reference address if the row address of the reference address is greater than or equal to the predetermined threshold.

[0012] In another aspect, one or more computer-readable media are provided, storing computer-executable instructions for causing a computer to perform a method comprising creating the above-described memory test circuit in a circuit design.

[0013] Certain inventive aspects are set forth in the accompanying independent claims and dependent claims, which are incorporated into this specification by reference. Features of the dependent claims can be combined with those of the independent claims and other dependent claims as appropriate, and not just in the specific combinations explicitly set forth in the claims.

[0014] Certain objects and advantages of various inventive aspects have been described above. Of course, it will be appreciated that not necessarily all such objects or advantages can be achieved in accordance with any particular embodiment of the technology disclosed. Thus, for example, those skilled in the art will recognize that the technology disclosed can be embodied or carried out in a manner that achieves or optimizes one advantage or a limited number of advantages as compared with other possible embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 An example block diagram of a typical memory is illustrated.

[0016] Figure 2 An example block diagram of a memory test circuit that can be implemented in accordance with various embodiments of the technology disclosed is illustrated.

[0017] Figure 3 Four examples of test ports are illustrated.

[0018] Figure 4 An example block diagram of a memory test circuit for testing a multi-port memory that can be implemented in accordance with various embodiments of the technology disclosed is illustrated.

[0019] Figure 5 An example block diagram of a memory test circuit for testing one or more multi-port memories based on using the same concurrent address for non-active logical ports that can be implemented in accordance with various embodiments of the technology disclosed is illustrated.

[0020] Figure 6An example block diagram of a memory test circuit that can be implemented in accordance with various embodiments of the disclosed technology for testing one or more multi-port memories based on using a unique concurrent address for each inactive logical port is illustrated.

[0021] Figure 7 An example block diagram of a memory test interface circuit that can be implemented in accordance with various embodiments of the disclosed technology for testing a multi-port memory based on using different concurrent addresses for inactive logical ports is illustrated.

[0022] Figure 8 An example block diagram of a circuit that can be implemented in accordance with various embodiments of the disclosed technology for generating unique concurrent write data for inactive writeable logical ports is illustrated.

[0023] Figure 9 An example block diagram of a parallel comparison circuit that can be implemented in accordance with various embodiments of the disclosed technology for concurrently reading data is illustrated.

[0024] Figure 10 An example block diagram of a serial comparison circuit that can be implemented in accordance with various embodiments of the disclosed technology for concurrently reading data is illustrated.

[0025] Figure 11 A programmable computer system with which various embodiments of the disclosed technology can be used is illustrated. DETAILED DESCRIPTION

[0026] Various aspects of the disclosed technology relate to multi-port memory testing. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present technology. It will be apparent, however, to one ordinarily skilled in the art that the present technology can be practiced without using these specific details. In other instances, well-known features are not described in detail in order to avoid obscuring the present technology.

[0027] Some of the technology described herein can be implemented by software stored on a computer readable medium, software executed on a computer, or some combination thereof. For example, some of the technology disclosed can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0028] The detailed description of the methods or devices sometimes uses terms like “generating” and “executing” to describe the disclosed method or device functions / structures. Such terms are high-level descriptions. Actual operations or functions / structures that correspond to those terms will depend on the specific implementation and one of ordinary skill will readily identify them.

[0029] As used in this disclosure, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Additionally, the term “comprises” means “includes.” Further, the term “coupled” means electrically connected or electromagnetically connected or linked, and includes direct connection or direct linking, as well as indirect connection or indirect linking through one or more intermediate elements that do not affect the intended operation of the circuit.

[0030] Memory constitutes a large portion of a system-on-a-chip circuit. Embedded memory can provide higher bandwidth and consume lower power compared to standalone memory. Figure 1 An example block diagram of a memory 100 having a read-only logic port and a read-write logic port is illustrated. The memory 100 includes memory cells 110, two column address decoders 125 and 135, two row address decoders 124 and 134, a driver circuit 136, and two sets of sense amplifiers 123 and 133. The column address decoder 125, the row address decoder 124, and the sense amplifier 123 are coupled to corresponding inputs, an address input 121 and a control input 122, of the read-only logic port. The sense amplifier 123 is also coupled to a data output 128 of the read-only logic port. The column address decoder 135, the row address decoder 134, the sense amplifier 133, and the driver circuit 136 are coupled to corresponding inputs, an address input 131, a control input 122, and a data input 137, of the read-write logic port. The sense amplifier 133 is also coupled to a data output 138 of the read-write logic port.

[0031] The memory cells 110 are connected in a two-dimensional array. Each of the memory cells 110 can store one bit of binary information. The memory cells 110 can be grouped into fixed word length memory words, such as 1, 2, 4, 8, 16, 32, 64, or 128 bits. It should be noted that the word length is not limited to powers of two. There are two basic components of a memory cell: a storage node and a selection device. The storage node stores the data bit of the memory cell, and the selection device component facilitates addressing the memory cell in the array for reading / writing.

[0032] The row address decoders 124, 134 and the column address decoders 125, 135 determine the cell address that needs to be accessed from the logical address at the address inputs 121, 131, respectively. Based on the address signals output from the row address decoders 124, 134 and the column address decoders 125, 135, during a read operation, the corresponding row(s) and column(s) are selected and connected to the sense amplifiers 123, 133. Each of the sense amplifiers 123, 133 amplifies and sends out the data bit. For a write operation, the required cells that need to have data bits written are selected by the address signals output from the row address decoder 134 and the column address decoder 135, and the driver circuit 136 is used to write the data bits to the selected memory cells.

[0033] Memory can have a significant impact on yield because they take up a large portion of the area of a system-on-chip design and have small feature sizes. However, memory cells typically do not include logic gates and flip-flops. Thus, the behavior of memory faults is different from the classical stuck-at faults of logic circuits. The large size and high density of memory cell arrays also do not lend themselves to using external test vectors. Therefore, memory built-in self-test (MBIST) based techniques have been widely adopted for both manufacturing test and in-system test. MBIST can implement a finite state machine (FSM) to generate and apply stimuli to the memory. The responses output from the memory can then be analyzed to detect faults. MBIST based techniques can add repair circuitry to the memory test circuitry. The repair circuitry can analyze the test results and redundancy information and allocate spare row and / or column storage cells to faulty rows and / or columns. Repair can reduce yield loss and extend the useful life of manufactured chips.

[0034] Figure 2 An example block diagram of a memory test circuit 200 that can be implemented in accordance with various embodiments of the disclosed technology is illustrated. The memory test circuit 200 is configured to perform tests on one or more memories 205. Each of the one or more memories 205 has a plurality of logical ports. The number of logical ports of one memory of the one or more memories 205 can be the same as or different from the number of logical ports of another memory of the one or more memories 205. In addition to testing one or more multi-port memories 205, the memory test circuit 200 can also be configured to test one or more single-port memories simultaneously.

[0035] A logical port can be a write-only port, a read-only port, or a read-write port. A write-only port can perform a write operation in accordance with a control signal for the write operation, a data bit to be stored in the memory, and an address signal indicating in which memory cell the data bit is to be stored. The write-only port also includes a data input port for receiving the data bit to be stored in the memory cell. A read-only port can perform a read operation in accordance with a control signal for the read operation and an address signal indicating from which memory cell the data bit is to be read. The read-only port also includes a data output port for outputting the data bit read from the memory cell. A read-write port can perform a write operation or a read operation in accordance with a received control signal. The read-write port also includes a data input port for the write operation, a data output port for the read operation, and an address port for both the write operation and the read operation.

[0036] For testing purposes, the logical ports can be divided into test ports by memory test interface circuits coupled to each multi-port memory 205. For testing purposes, the test ports need to have the capability of both reading and writing. Thus, a test port can typically have one or two logical ports. Figure 3 Four examples of test ports 310-340 are illustrated. Test port 310 is formed by read-write logical port 315. Test port 320 is formed by read-write logical port 323 and write-only logical port 327. Test port 330 is formed by read-only logical port 333 and read-write logical port 337. Test port 340 is formed by read-only logical port 343 and write-only logical port 347. In the second example, test port 320 uses only the read capability of read-write logical port 323, while read-write logical port 323 itself is configured as another test port for memory testing. In the third example, test port 330 uses only the write capability of read-write logical port 333, while read-write logical port 333 itself is configured as another test port for memory testing.

[0037] Returning to Figure 2 , the memory test circuit 200 includes a test algorithm control unit 270, a reference address generator 210, one or more concurrent address generators 220, a test port counter 230, and an address selection circuit 240 for each of the one or more memories 205. The test algorithm control unit 270 is configured to implement a test algorithm. The test algorithm includes a series of read operations and write operations. Various test algorithms can be employed. One example memory test algorithm is the March C-algorithm, which includes the following operations: write 0 (to initialize); read 0 in ascending address order (from address 0 to address n-1), write 1; read 1 in ascending address order, write 0; read 0 in descending address order (from address n-1 to address 0), write 1; read 1 in descending address order, write 0; and read 0. Another memory test algorithm, the checkerboard algorithm, includes the following operations: write checkerboard in ascending address order; read checkerboard in ascending address order; write inverse checkerboard in ascending address order; and read inverse checkerboard in ascending address order.

[0038] Each execution of a test algorithm implemented by the test algorithm control unit 270 can perform memory tests on each of the one or more memories 205 through one of the plurality of test ports, referred to as the tested test port. One of the logical ports in the tested test port is configured to receive an algorithmic command corresponding to one read operation or one write operation in a series of read operations and write operations, and the logical ports that do not receive the algorithmic command can be configured to receive concurrent commands generated based on the test algorithm. The logical port that receives the algorithmic command can be referred to as an active logical port, and the logical ports that receive the concurrent commands can be referred to as inactive logical ports. Both the algorithmic command and the concurrent commands can cause read or write operations on the memory through the active logical port and the inactive logical ports, respectively. If the tested test port has two logical ports, each of the two logical ports can be an active logical port for one operation of the test algorithm and an inactive logical port for another operation of the test algorithm.

[0039] The test algorithm control unit 270 can include a finite state machine and is typically placed in the MBIST controller. The reference address generator 210 is configured to generate a reference address for the active logical port in the test port based on the test algorithm. The reference address can be an address for a read operation or an address for a write operation, depending on the current operation of the test algorithm. The reference address generator 210 can also be placed in the MBIST controller.

[0040] The one or more concurrent address generators 220 are configured to generate one or more concurrent addresses for the inactive logical ports based on the reference address. The one or more concurrent address generators 220 can be placed only in the MBIST controller, only in the memory test interface circuit for each of the one or more memories 205, or some of them in the MBIST controller and the rest in the memory test interface circuit for each of the one or more memories 205. For example, the one or more concurrent address generators 220 can include a global concurrent address generator placed in the MBIST controller and a local concurrent address generator for each of the one or more memories 205 placed in the memory test interface circuit for that memory. In this setup, the global concurrent address generator can be configured to generate a global concurrent address based on the reference address; and the local concurrent address generator can be configured to receive the global concurrent address and output the one or more concurrent addresses. The concurrent addresses can be the same for all or some of the inactive logical ports. The concurrent addresses can also be unique for each inactive logical port.

[0041] The test port counter 230 is configured to increment and generate a test port count signal after each execution of a test algorithm. It can be placed in the MBIST controller. The test port count signal can be used to generate an address selection signal, which can be used by the address selection circuit 240.

[0042] The address selection circuit 240 is placed in the memory test interface circuit for each of the one or more memories 205. The address selection circuit 240 is configured to select one of a reference address or one or more concurrent addresses for each of the plurality of logical ports based on an address selection signal. The address selection signal can include a row address selection signal and a column address selection signal, which can be independently configured. This can allow a logical port to receive a row address of a concurrent address and a column address of a reference address, a column address of a concurrent address and a row address of a reference address, or both a row address and a column address of a concurrent address.

[0043] The memory test circuit 200 can further include a global control signal generator 250 and a local control signal generator 260 for each of the one or more memories 205. The global control signal generator 250 can be placed in the MBIST controller, while the local control signal generator 260 can be placed in the memory test interface for the one or more memories 205. The global control signal generator 250 can be configured to generate algorithm commands and concurrent commands based on a test algorithm. The local control signal generator can be configured to pass the algorithm commands to active logical ports in the test port under test and the concurrent commands to inactive logical ports. The local control signal generator can also be configured to generate the address selection signal for the address selection circuit 240 based on the test port count signal.

[0044] The memory test circuit 200 can also include a test data generator, not shown in the figure. The test data generator is typically placed in the MBIST controller and configured to provide data to be written to the one or more memories 205 or data to be read from the one or more memories 205 based on a test algorithm. The data to be read from the one or more memories 205 can be used to compare data output from the one or more memories 205 in a read operation to determine whether the memory under test has a defect.

[0045] Figure 4An example block diagram of a memory test circuit 400 for testing a multi-port memory 430 can be implemented in accordance with various embodiments of the disclosed technology is illustrated. The memory test circuit 400 includes an MBIST controller 410 and memory test interface circuits 420. The MBIST controller 410 includes a test algorithm control unit 412, a global control signal generator 413, a global concurrent address generator 414, a reference address generator 415, and a test port counter 416. The memory test circuit 400 can also include a test data generator configured to provide data to be written to or read from the multi-port memory 430. Each memory test interface circuit 420 includes a local control signal generator 423, a local concurrent address generator 424, and an address selection circuit 425. Each memory test interface circuit 420 is coupled to one of the multi-port memory 430.

[0046] The test algorithm control unit 412 can be configured to implement a test algorithm for testing the multi-port memory 430. The global control signal generator 413 can be configured to generate algorithm commands for active logical ports and concurrent commands for inactive logical ports based on the test algorithm and send them to the local control signal generators 423. An active logical port of each of the multi-port memory 430 is a logical port in the test port being tested that receives an algorithm command corresponding to a memory operation in a series of read operations and write operations defined by the test algorithm. The remaining logical ports of each of the multi-port memory 430 are referred to as inactive logical ports. Through the inactive logical ports, concurrent memory operations are performed based on the concurrent commands. As previously mentioned, when a test port has two logical ports, which are used as active or inactive ports can be switched between memory operations.

[0047] The local control signal generators 423 can be configured to pass the received algorithm commands to the active logical ports and the received concurrent commands to the inactive logical ports of each of the multi-port memory 430. The local control signal generators 423 can also be configured to generate address selection signals for the address selection circuits 425 based on a test port count signal. The test port count signal can be generated by the test port counter 416, which can be configured to increment after each execution of the test algorithm.

[0048] The reference address generator 415 can be configured to generate a reference address for each active logical port of the multi-port memory 430 based on the test algorithm. The global concurrent address generator 414 can be configured to generate a global concurrent address based on the reference addresses. The local concurrent address generator 423 can be configured to receive the global concurrent address and output the one or more concurrent addresses. One or all of the concurrent addresses can be set to be the same as the global concurrent address. The concurrent addresses can be set in such a way that each inactive port receives a unique concurrent address.

[0049] The address selection circuit 425 can be configured to select one of the reference address or the one or more concurrent addresses for each of the multiple logical ports of each of the multi-port memories 430 based on an address selection signal provided by the local control signal generator 423. In this example, the address selection circuit 425 employs multiple 2-to-l multiplexers to perform the selection operation. The two inputs of each 2-to-l multiplexer are coupled to the reference address and one of the one or more concurrent addresses, respectively, and the select input is coupled to the address selection signal from the local control signal generator 423.

[0050] As discussed above with respect to the memory test circuit 200, Figure 2 The address selection signal can include a row address selection signal and a column address selection signal, which can be independently configured, as discussed above with respect to the memory test circuit 200. This would allow a logical port to receive a row address of a concurrent address and a column address of a reference address, a column address of a concurrent address and a row address of a reference address, or both a row address and a column address of a concurrent address. Accordingly, two 2-to-l multiplexers can be employed to select an address for each of the multiple logical ports.

[0051] Figure 5 An example block diagram of a memory test circuit 500 for testing one or more multi-port memories 530 based on using the same concurrent address for inactive logical ports is illustrated, which can be implemented in accordance with various embodiments of the disclosed technology. The memory test circuit 500 includes an MBIST controller 510 and a memory test interface circuit 520 for each of the one or more multi-port memories 530. Although only one multi-port memory 530 is shown in the figure, the memory test circuit 500 can test multiple multi-port memories. In this case, a memory test interface circuit like the memory test interface circuit 520 can be added for each additional multi-port memory.

[0052] The MBIST controller 510 includes a test algorithm control unit 540, a global concurrent address generator 550, and a reference address generator 560. As with the memory test circuit 200, Figure 4Similar to the MBIST controller 410 in FIG. 4, the MBIST controller 510 can also include a global control signal generator, a test port counter, and a test data generator. The test algorithm control unit 540 can be configured to implement a test algorithm. The reference address generator 560 can be configured to generate a reference address based on the test algorithm, the reference address including a reference column address 561 (a column address of the reference address) and a reference row address 562 (a row address of the reference address). The global concurrent address generator 550 includes a column address generator 551 and a row address generator 552. The column address generator 551 can be configured to add “1” to the reference column address 561 to generate a concurrent column address if the reference column address 561 is increasing based on the test algorithm, or subtract “1” from the reference column address 561 if the reference column address 561 is decreasing based on the test algorithm. Similarly, the row address generator 552 can be configured to add “1” to the reference row address 562 to generate a concurrent row address if the reference row address 562 is increasing based on the test algorithm, or subtract “1” from the reference row address 562 if the reference row address 562 is decreasing based on the test algorithm.

[0053] The memory test interface circuit 520 includes a local control signal generator 570, a local concurrent address generator 580, and an address selection circuit 590. The address selection circuit 590 includes 2-to-l multiplexers. Each logical port of the multi-port memory 530 receives address signals from the outputs of two 2-to-l multiplexers, one for the row address and the other for the column address. The local concurrent address generator 580 is configured to broadcast either the concurrent column address or the concurrent row address, both of which are received from the global concurrent address generator 550, to the 2-to-l multiplexers. Each 2-to-l multiplexer also receives either the reference column address 561 or the reference row address 562. The local control signal generator 570 is configured to provide address selection signals to the 2-to-l multiplexers, one for selecting between the concurrent column address and the reference column address 561, and the other for selecting between the concurrent row address and the reference row address 562.

[0054] Figure 6 An example block diagram of a memory test circuit 600 for testing one or more multi-port memories 630 based on using a unique concurrent address for each inactive logical port is illustrated, which can be implemented in accordance with various embodiments of the disclosed technology. The memory test circuit 600 includes a MBIST controller 610 and a memory test interface circuit 620 for each of the one or more multi-port memories 630. Again for simplicity, only one pair of multi-port memories 630 and one memory test interface circuit 620 are shown in the figure.

[0055] The MBIST controller 610 includes a test algorithm control unit 640, a global concurrent address generator 650, and a reference address generator 660. The test algorithm control unit 640 can be configured to implement a test algorithm. The reference address generator 660 can be configured to generate reference addresses based on the test algorithm, including a reference column address 661 and a reference row address 662. The global concurrent address generator 650 includes a column address generator 651 and a row address generator 652. Like the column address generator 551 in Figure 5 The column address generator 651 can be configured to generate global concurrent column addresses by adding / subtracting "1" to / from the reference column address 661. Similarly, the row address generator 652 can be configured to generate global concurrent row addresses by adding / subtracting "1" to / from the reference row address 662.

[0056] The memory test interface circuit 620 includes a local control signal generator 670, a local concurrent address generator 680, and an address selection circuit 690. The address selection circuit 690 includes 2-to-l multiplexers. Each logical port of the multi-port memory 630 receives address signals from the outputs of both of the 2-to-l multiplexers, one for a row address and the other for a column address. Like the local concurrent address generator 580 in Figure 5 Unlike the broadcast function performed by the local concurrent address generator 580 in the memory test interface circuit 580, the local concurrent address generator 680 can be configured to generate different concurrent column and row addresses for different logical ports based on the global concurrent column and row addresses. For the first logical port 631, the concurrent column and row addresses are the same as the global concurrent column and row addresses. For the second logical port 632, the concurrent column and row addresses are derived by inverting the second least significant bit of the global concurrent column and row addresses. For the third logical port 633, the concurrent column and row addresses are derived by inverting the third least significant bit of the global concurrent column and row addresses. For the fourth logical port 634, the concurrent column and row addresses are derived by inverting both the second and third least significant bits of the global concurrent column and row addresses.

[0057] The local control signal generator 670 is configured to provide address selection signals to the 2-to-l multiplexers to select column addresses between the reference column address 661 and the concurrent column addresses provided by the local concurrent address generator 680, and to select row addresses between the reference row address 662 and the concurrent row addresses provided by the local concurrent address generator 680.

[0058] Figure 7An example block diagram of a memory test interface circuit 700 for testing a multi-port memory 730 is illustrated, which can be implemented in accordance with various embodiments of the disclosed technology. The memory test interface circuit 700 includes a local control signal generator 710, a concurrent address generator 720, and an address selection circuit 740. The concurrent address generator 720 can be configured to generate different concurrent addresses for the logical ports 731-736 based on a reference address 750. The reference address 750 can be generated by a reference address generator in an MBIST controller, as Figure 4-6 illustrated in the three examples shown. The address selection circuit 740 can be configured to select addresses between the concurrent addresses and the reference address 750 for the logical ports 731-736. The local control signal generator 710 can be configured to generate address selection signals for the address selection circuit 740.

[0059] The concurrent address generator 720 includes an address threshold check circuit 760, an inverter circuit 722, and a bit replacement circuit 723. The threshold check circuit 760 includes a comparison circuit 761 and a processing circuit 762. The comparison circuit 761 can be configured to compare the reference address 750 with a predetermined threshold. The processing circuit 762 can be configured to generate an intermediate concurrent address from the reference address 750 based on the comparison result from the comparison circuit 761. If the reference address 750 is less than the predetermined threshold, the intermediate concurrent address will be the same as the reference address 750. If the reference address 750 is greater than or equal to the predetermined threshold, the intermediate concurrent address will be an address obtained by subtracting an offset value from the reference address 750.

[0060] The address threshold check circuit 760 can prevent any concurrent address from going out of the range of the multi-port memory 730. The address threshold check circuit 760 can be used only for the concurrent row addresses when the number of rows of the memory 730 is not a power of two. The concurrent column addresses cannot go out of range because the number of columns is usually a power of two.

[0061] Inverter circuit 722 can be configured to invert the least significant bits of the intermediate concurrent address output from address threshold check circuit 760. Bit replacement circuit 723 can be configured to output the concurrent address by replacing selected bits of the intermediate concurrent address with different fixed bit patterns for certain logical ports. As shown, for logical ports 731-734, the two bits immediately following the least significant bits of the intermediate concurrent address, bits [2:1], are replaced with "00", "01", "10", "11", respectively. Bit replacement circuit 723 essentially applies a concurrent address mask to the two bits of the intermediate concurrent address to generate four different concurrent addresses for logical ports 731-734, respectively. Logical ports 735-736 share the same concurrent address as logical port 734. In one example, logical ports 731-733 can be write-only logical ports, while logical ports 734-736 can be read-only logical ports.

[0062] Similar to memory test interface circuit 500 in Figure 5 and memory test interface circuit 600 in Figure 6 , the address selection signals generated by local control signal generator 710 can include row address selection signals and column address selection signals, which can be independently configured so that the logical ports can receive the row address of the concurrent address and the column address of reference address 750, the column address of the concurrent address and the row address of reference address 750, or both the row and column addresses of the concurrent address. For simplicity, Figure 7 Separate circuits in concurrent address generator 720 and address selection circuit 740 for concurrent row and column addresses are not shown.

[0063] Similar to the two examples shown in Figure 5 and Figure 6 , the concurrent address is generated by concurrent address generator 720 in memory test interface circuit 700 based on reference address 750 only. In the example shown in Figure 5 , local concurrent address generator 580 in memory test interface circuit 520 only broadcasts the same concurrent address to the inactive logical ports through address selection circuit 590. It is global concurrent address generator 550 in MBIST controller 510 that generates the concurrent address based on the reference address. In the example shown in Figure 6 , global concurrent address generator 650 in MBIST controller 610 and local concurrent address generator 680 in memory test interface circuit 620 work together to generate the concurrent address for the inactive logical ports. Employing a fixed concurrent address mask and generating the concurrent address locally in the memory test interface circuit, as in the example shown in Figure 7 , can result in smaller silicon area and simplify handling memories with incomplete address spaces.

[0064] Figure 8 An example block diagram of circuitry 800 for generating unique concurrent write data for inactive writeable logical ports (inactive write-only logical ports or inactive read-write logical ports) can be implemented in accordance with various embodiments of the disclosed technology is illustrated. The circuitry 800 for generating unique concurrent write data includes a plurality of XOR gates 830 and control circuitry 860. The plurality of XOR gates 830 are configured to invert some preset bits of write data from a write data input 810 based on control signals from the control circuitry 860 and output the result at a write data output 820. The number of the plurality of XOR gates 830 can be determined based on the number of inactive logical ports. The control circuitry 860 is configured to generate control signals based on conc_write_data_unique (concurrent_write_data_unique) control signal 850, conc_write_enable (concurrent_write_enable) control signal 870, and conc_write_data_invert (concurrent_write_data_invert) control signal 840. When the conc_write_enable (concurrent_write_enable) control signal 870 is “0”, no bit of the input write data is inverted. When the three control signals are “1”, “1”, “0”, only bits [0]-[1], [3]-[4], [6]-[7] are inverted. When the three control signals are “1”, “1”, “1”, only bits [2] and [5] are inverted. When the three control signals are “0”, “1”, “1”, bits [0]-[7] are inverted. The control signals can be coupled to different combinations of XOR gates in the plurality of XOR gates 810 to generate different concurrent write data.

[0065] The memory test circuitry can include a comparator that compares the output of the readable logical ports to expected data values after execution of a concurrent read command and a result register that detects whether there was at least one failed comparison during execution of the test algorithm. Figure 9 An example block diagram of parallel comparison circuitry 900 for concurrent read data that can be implemented in accordance with various embodiments of the disclosed technology is illustrated. The parallel comparison circuitry 900 includes comparator circuitry 920, sticky state bit circuitry 930, and multiplexer 940. The memory 910 has three read output ports Q0, Q1, and Q2, each coupled to a comparator in the comparator circuitry 920, which is in turn coupled to a sticky state bit in the sticky state bit circuitry 930. Thus, comparisons can be performed simultaneously on all three readable logical ports. During execution of a test algorithm, one of the read output ports Q0, Q1, and Q2 is part of a test port (active read output port) while the other two output concurrent read data. The output of the active read output port is also selected by the multiplexer 940 for comparison to expected data. The concurrent read addresses can be the same or different.

[0066] Figure 10 An example block diagram of a serial comparison circuit 1000 for concurrent read data is illustrated that can be implemented in accordance with various embodiments of the disclosed technology. A memory 1010 has three read output ports Q0, Q1, and Q2. The serial comparison circuit 1000 is configured to sequentially compare data output from the three read output ports Q0, Q1, and Q2 after a concurrent read command is executed. The read operation is performed simultaneously on all ports. It is assumed that the data output from the three read output ports Q0, Q1, and Q2 is latched.

[0067] Various examples of the disclosed technology can be implemented by a computing device (e.g., a programmable computer) executing software instructions. Thus, Figure 11 An illustrative example of a computing device 1101 is shown. As shown, the computing device 1101 includes a computing unit 1103 having a processing unit 1105 and a system memory 1107. The processing unit 1105 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 1107 can include read only memory (ROM) 1109 and random access memory (RAM) 1111. As is well understood by those of ordinary skill in the art, both the read only memory (ROM) 1109 and the random access memory (RAM) 1111 can store software instructions for execution by the processing unit 1105.

[0068] The processing unit 1105 and the system memory 1107 are connected, either directly or indirectly, through a bus 1113 or alternative communication structure, to one or more peripheral devices. For instance, the processing unit 1105 or the system memory 1107 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" disk drive 1115, a removable disk drive 1117, an optical disk drive 1119, or a flash memory card 1121. The processing unit 1105 and the system memory 1107 can also be directly or indirectly connected to one or more input devices 1123 and one or more output devices 1125. The input devices 1123 can include, for example, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, and a joystick), a scanner, a camera, and a microphone. The output devices 1125 can include, for example, a monitor display, a printer, and a speaker. For various examples of the computer 1101, one or more of the peripheral devices 1115-1125 can be housed together with the computing unit 1103 in an internal housing. Alternatively, one or more of the peripheral devices 1115-1125 can be external to the housing of the computing unit 1103 and connected to the bus 1113 through, for example, a universal serial bus (USB) connection.

[0069] For some implementations, the computing unit 1103 can be directly or indirectly connected to one or more network interfaces 1127 for communicating with other devices constituting a network. The network interface 1127 converts data and control signals from the computing unit 1103 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). Additionally, the interface 1127 can employ any suitable connection agent (or combination of agents) for connecting to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are well known in the art and thus are not discussed in more detail here.

[0070] It should be appreciated that the computer 1101 is merely illustrative and is not intended to limit the disclosed technology. Various embodiments of the disclosed technology can be implemented using one or more computing devices, including Figure 11 components of the computer 1101 shown in FIG. 11, including Figure 11 a subset of the components shown in FIG. 11, or a combination of components from FIG. 11, including Figure 11 components not shown in FIG. 11. For example, various embodiments of the disclosed technology can be implemented using a multi-processor computer, a plurality of single and / or multi-processor computers arranged for parallel processing, or some combination thereof.

[0071] CONCLUSION

[0072] Having thus described the principles of the disclosed technology in some detail, it is to be appreciated that the disclosed embodiments can be modified or varied without departing from the principles of the technology. It is therefore contemplated that the embodiments shown and described are illustrative only and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the technology is to be determined only by the claims and equivalents thereof. Accordingly, we intend to protect all of what we regard as our disclosed technology by the principles and scope of the following claims.

Claims

1. A memory test circuit in a circuit, configured to perform tests on one or more memories in the circuit, each of the one or more memories having a plurality of logic ports, the plurality of logic ports being divided into a plurality of test ports, each of the plurality of test ports being capable of performing both write and read operations and including one or two logic ports, the memory test circuit comprising: The test algorithm control unit is configured to implement a test algorithm, which includes a series of read and write operations. Each execution of the test algorithm performs a memory test through one of the plurality of test ports. One of the test ports being tested is configured to receive an algorithm command corresponding to one of the read or write operations in the series of read and write operations. The logical port that does not receive the algorithm command is configured to receive concurrent commands generated based on the test algorithm. A reference address generator is configured to generate a reference address for one of the logical ports being tested, based on the test algorithm. One or more concurrent address generators are configured to generate one or more concurrent addresses based on the reference address for the logical port receiving the concurrent command; The test port counter is configured to increment and generate a test port count signal after each execution of the test algorithm; as well as Address selection circuitry for each of the one or more memories is configured to select one of the one or more concurrent addresses or the reference address for each of the plurality of logic ports based on an address selection signal generated based on the test port count signal.

2. The memory test circuit as described in claim 1, further comprising: A global control signal generator is configured to generate the algorithm command and the concurrent command based on the test algorithm; as well as A local control signal generator in the memory test interface circuitry for each of the one or more memories is configured to both pass the algorithm command to one of the test ports under test and pass the concurrent command to the logical port that did not receive the algorithm command, and generate the address selection signal based on the test port counting signal.

3. The memory test circuit as described in claim 1, wherein, The address selection signal includes a row address selection signal and a column address selection signal, and can be configured to allow the logic port to receive the row address of one of the one or more concurrent addresses and the column address of the reference address, the column address of one of the one or more concurrent addresses and the row address of the reference address, or both the row address and the column address of one of the one or more concurrent addresses.

4. The memory test circuit as described in claim 1, wherein, The one or more concurrent address generators include: A global concurrent address generator is configured to generate a global concurrent address based on the reference address; and A local concurrent address generator in the memory test interface circuitry for each of the one or more memories, the local concurrent address generator being configured to receive the global concurrent address and output the one or more concurrent addresses.

5. The memory test circuit as described in claim 4, wherein, The one or more concurrent addresses are the same as the global concurrent address.

6. The memory test circuit as described in claim 4, wherein, The local concurrent address generator is configured to generate one or more concurrent addresses based on the global concurrent address. For writable logical ports, no more than one of the one or more concurrent addresses is the same as the global concurrent address.

7. The memory test circuit as described in claim 4, wherein, The row address of the global concurrent address is obtained by adding or subtracting 1 from the row address of the reference address, and the column address of the global concurrent address is obtained by adding or subtracting 1 from the column address of the reference column address.

8. The memory test circuit as described in claim 7, wherein, The increment or decrement is based on whether the reference address changes in ascending or descending order.

9. The memory test circuit as described in claim 1, wherein, Each of the one or more concurrent addresses is obtained at least in part by applying a concurrent address mask to one or more bits of the reference address.

10. The memory test circuit as described in claim 9, wherein, The concurrent address mask replaces the selected position of the reference address with a unique fixed bit pattern, inverts one or a unique combination of the selected positions of the reference address, or both.

11. The memory test circuit as described in claim 1, wherein, Each of the one or more concurrent address generators is in a memory test interface circuit coupled to each of the one or more memories.

12. The memory test circuit as described in claim 11, wherein, Each of the one or more concurrent address generators includes: An inverter circuit is configured to invert the least significant bit of an intermediate concurrent address, which is the reference address or the reference address minus an offset; and The bit replacement circuit is used to replace the selected bit of the intermediate concurrent address with a different fixed bit mode for different logic ports.

13. The memory test circuit as described in claim 12, wherein, The inversion and the replacement are performed on both the row address and the column address, and the address selection signal includes a row address selection signal and a column address selection signal, and is configurable to allow the logic port to receive the row address of one of the one or more concurrent addresses and the column address of the reference address, the column address of one of the one or more concurrent addresses and the row address of the reference address, or both the row address and the column address of one of the one or more concurrent addresses.

14. The memory test circuit as described in claim 13, wherein, Some or all of the one or more concurrent address generators include address threshold checking circuitry configured to output the row address of the intermediate concurrent address, wherein if the row address of the reference address is less than a predetermined threshold, the row address of the intermediate concurrent address is the same as the row address of the reference address, or if the row address of the reference address is greater than or equal to the predetermined threshold, the row address of the intermediate concurrent address is an address obtained by subtracting an offset value from the row address of the reference address.

15. One or more computer-readable media storing computer-executable instructions, the instructions being configured to cause a computer to perform a method, the method comprising: A memory test circuit is created in a circuit design, configured to perform tests on one or more memories in the circuit design, each of the one or more memories having multiple logic ports, the multiple logic ports being divided into multiple test ports, each of the multiple test ports being capable of performing both write and read operations and including one or two logic ports, the memory test circuit comprising: The test algorithm control unit is configured to implement a test algorithm, which includes a series of read and write operations. Each execution of the test algorithm performs a memory test through one of the plurality of test ports. One of the test ports being tested is configured to receive an algorithm command corresponding to one of the read or write operations in the series of read and write operations. The logical port that does not receive the algorithm command is configured to receive concurrent commands generated based on the test algorithm. A reference address generator is configured to generate a reference address for one of the logical ports being tested, based on the test algorithm. One or more concurrent address generators are configured to generate one or more concurrent addresses based on the reference address for the logical port receiving the concurrent command; A test port counter is configured to increment and generate a test port count signal after each execution of the test algorithm; and Address selection circuitry for each of the one or more memories is configured to select one of the one or more concurrent addresses or the reference address for each of the plurality of logic ports based on an address selection signal generated based on the test port count signal.

16. One or more computer-readable media as claimed in claim 15, wherein, The memory test circuit further includes: A global control signal generator is configured to generate the algorithm command and the concurrent command based on the test algorithm; and A local control signal generator in the memory test interface circuitry for each of the one or more memories is configured to both pass the algorithm command to one of the test ports under test and pass the concurrent command to the logical port that did not receive the algorithm command, and generate the address selection signal based on the test port counting signal.

17. One or more computer-readable media as claimed in claim 15, wherein, The address selection signal includes a row address selection signal and a column address selection signal, and can be configured to allow the logic port to receive the row address of one of the one or more concurrent addresses and the column address of the reference address, the column address of one of the one or more concurrent addresses and the row address of the reference address, or both the row address and the column address of one of the one or more concurrent addresses.

18. One or more computer-readable media as claimed in claim 15, wherein, The one or more concurrent address generators include: A global concurrent address generator is configured to generate a global concurrent address based on the reference address; and A local concurrent address generator in the memory test interface circuitry for each of the one or more memories, the local concurrent address generator being configured to receive the global concurrent address and output the one or more concurrent addresses.

19. One or more computer-readable media as claimed in claim 18, wherein, The one or more concurrent addresses are the same as the global concurrent address.

20. One or more computer-readable media as claimed in claim 18, wherein, The local concurrent address generator is configured to generate one or more concurrent addresses based on the global concurrent address. For writable logical ports, no more than one of the one or more concurrent addresses is the same as the global concurrent address.

21. One or more computer-readable media as claimed in claim 18, wherein, The row address of the global concurrent address is obtained by adding or subtracting 1 from the row address of the reference address, and the column address of the global concurrent address is obtained by adding or subtracting 1 from the column address of the reference column address.

22. One or more computer-readable media as claimed in claim 21, wherein, The increment or decrement is based on whether the reference address changes in ascending or descending order.

23. One or more computer-readable media as claimed in claim 15, wherein, Each of the one or more concurrent addresses is obtained at least in part by applying a concurrent address mask to one or more bits of the reference address.

24. One or more computer-readable media as claimed in claim 23, wherein, The concurrent address mask replaces the selected position of the reference address with a unique fixed bit pattern, inverts one or a unique combination of the selected positions of the reference address, or both.

25. One or more computer-readable media as claimed in claim 15, wherein, Each of the one or more concurrent address generators is in a memory test interface circuit coupled to each of the one or more memories.

26. One or more computer-readable media as claimed in claim 25, wherein, Each of the one or more concurrent address generators includes: An inverter circuit is configured to invert the least significant bit of an intermediate concurrent address, which is the reference address or the reference address minus an offset; and The bit replacement circuit is used to replace the selected bit of the intermediate concurrent address with a different fixed bit mode for different logic ports.

27. One or more computer-readable media as claimed in claim 26, wherein, The inversion and the replacement are performed on both the row address and the column address, and the address selection signal includes a row address selection signal and a column address selection signal, and is configurable to allow the logic port to receive the row address of one of the one or more concurrent addresses and the column address of the reference address, the column address of one of the one or more concurrent addresses and the row address of the reference address, or both the row address and the column address of one of the one or more concurrent addresses.

28. One or more computer-readable media as claimed in claim 27, wherein, Some or all of the one or more concurrent address generators include address threshold checking circuitry configured to output the row address of the intermediate concurrent address, wherein if the row address of the reference address is less than a predetermined threshold, the row address of the intermediate concurrent address is the same as the row address of the reference address, or if the row address of the reference address is greater than or equal to the predetermined threshold, the row address of the intermediate concurrent address is an address obtained by subtracting an offset value from the row address of the reference address.

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