A control board for testing aging of electronic devices and a control method thereof

Abstract

The application provides a control panel for testing aging of electronic equipment and a control method thereof. The control panel is provided with a current collection circuit, a power supply control circuit and a host controller. The current collection circuit comprises a sensing resistor and a current detector. The host controller is provided with an IO port, an ADC interface, a communication interface and a USB interface. The IO port is connected to the power supply control circuit, and the ADC interface is connected to the current detector. The host controller is used for responding to a test instruction of a host computer received from the USB interface, controlling the power supply control circuit to perform multiple power-on operations on the equipment to be tested through the IO port, obtaining current data from the ADC interface and reading the running log of the equipment to be tested from the communication interface in each power-on operation, identifying whether the running log contains key characters representing abnormalities according to a preset character rule, determining a test abnormality when the current data exceeds a preset threshold or the key characters are identified, and uploading the current data at the abnormal moment and the abnormal segment of the running log to the host computer, so that test automation is realized and test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of automatic testing of electronic equipment, and in particular to a control board for testing the aging of electronic equipment and a control method thereof. Background Technology

[0002] In the current field of electronic equipment manufacturing, especially HMI (Human-Machine Interface) devices in intelligent power distribution systems, aging testing is a crucial step in ensuring product reliability and stability. Existing mainstream aging testing methods suffer from two major technical bottlenecks: First, for continuous operation aging, a test rack is typically kept constantly powered, relying on manual periodic inspections and visual observation of the equipment's operating status. This approach is not only costly in terms of manpower but also prone to failure to detect anomalies due to human fatigue or negligence. Second, for aging tests targeting equipment startup characteristics, simple timers are commonly used to control power on and off. While this method can achieve cyclic power-on, it cannot collect and analyze detailed operating logs during the power-on process in real time, resulting in a lack of direct evidence for problem localization and low efficiency in debugging and analysis. Especially in harsh environments such as high and low temperature tests and premature failure tests, these methods struggle to achieve accurate fault reproduction and on-site preservation. Therefore, the industry urgently needs a testing solution that can automate the testing process, simultaneously monitor multi-dimensional parameters, and possess intelligent diagnostic and error on-site preservation capabilities. Summary of the Invention

[0003] The main objective of this application is to propose a control board and control method for testing the aging of electronic devices, which realizes full automation of aging testing, greatly improves testing efficiency, reduces manpower and time costs, and greatly accelerates problem localization through software and hardware collaborative diagnosis and error scene preservation.

[0004] To achieve the above objectives, a first aspect of this application provides a control board for testing the aging of electronic devices, comprising:

[0005] The circuit includes a current acquisition circuit, a power control circuit, and a main controller. The current acquisition circuit includes a sensing resistor and a current detector connected to the device under test. The current detector is connected to the sensing resistor and is used to acquire an analog signal characterizing the operating current of the device under test from the sensing resistor and amplify and output it.

[0006] The main controller is equipped with an IO port, an ADC interface, a communication interface for communicating with the device under test, and a USB interface for communicating with the host computer. The IO port is connected to the controlled end of the power control circuit, and the ADC interface is connected to the output end of the current detector to convert the analog signal into current data.

[0007] The main controller is configured to, in response to receiving test commands from the host computer via the USB interface, control the power control circuit on the IO port to perform a preset number of power-on operations on the device under test. During each power-on operation, it continuously acquires current data from the ADC interface and continuously reads the operation log of the device under test from the communication interface. It also identifies whether the operation log contains key characters indicating an anomaly according to preset character rules. When the current data exceeds a preset threshold or a key character is identified, it determines that the test is abnormal and uploads the current data at the time of the anomaly and the abnormal segment of the operation log to the host computer via the USB interface.

[0008] Furthermore, in some embodiments, the power control circuit includes a switching element and a control unit, with the switching element connected in series between the input and output terminals of the power control circuit.

[0009] The controlled terminal of the control unit is connected to the I / O port as the controlled terminal of the power control circuit, and the output terminal of the control unit is connected to the control electrode of the switching element;

[0010] The control unit is used to drive the switching elements to turn on or off according to the control signals output from the IO port in order to control the power supply circuit to the device under test.

[0011] Furthermore, in some embodiments, the switching element is a PMOS transistor, and the control unit includes an NPN transistor and a first current-limiting resistor; the base of the transistor is connected to the I / O port of the main controller through the first current-limiting resistor, the emitter of the transistor is grounded, and the collector of the transistor is connected to the gate of the PMOS transistor; the source of the PMOS transistor is connected to the input terminal of the power control circuit, and the drain of the PMOS transistor is connected to the output terminal of the power control circuit.

[0012] Furthermore, in some embodiments, the main controller is also configured to:

[0013] According to the test command, a control signal characterized as high level is output on the IO port to control the transistor to be in the self-conducting state so that the PMOS transistor is pulled low to the low level and supplies power to the device under test.

[0014] Alternatively, a control signal characterized as a low level can be output at the IO port according to the test command to control the transistor to be in a self-cutoff state, so that the PMOS transistor is pulled up to a high level and the power supply circuit of the device under test is turned off.

[0015] Furthermore, in some embodiments, the control board further includes: a multi-stage step-down DC-DC power supply circuit, the DC-DC power supply circuit including at least a first-stage step-down module and a second-stage step-down module, the input terminal of the first-stage step-down module being used to connect to an external DC power supply, and the output terminal of the first-stage step-down module being connected to the input terminal of the power control circuit and the input terminal of the second-stage step-down module, respectively.

[0016] The first-stage step-down module converts the input voltage of the DC power supply into a first operating voltage as the main operating voltage of the device under test, and the second-stage step-down module converts the first operating voltage into the operating voltage of the main controller.

[0017] Furthermore, in some embodiments, the second-stage buck module includes a first buck circuit, a second buck circuit, and a third buck circuit, wherein the first buck circuit and the second buck circuit are connected in parallel, and the second buck circuit and the third buck circuit are connected in parallel.

[0018] The output of the first-stage buck module is connected to the input of the first buck circuit, the input of the second buck circuit, and the input of the third buck circuit, respectively.

[0019] The output of the first step-down circuit is connected to the IO port, the output of the second step-down circuit is connected to the core unit of the main controller, and the output of the second step-down circuit is connected to the DDR memory unit of the main controller.

[0020] The first step-down circuit is used to convert the first operating voltage into the operating voltage of the I / O port;

[0021] The second buck circuit is used to convert the first operating voltage into the operating voltage of the core unit;

[0022] The third step-down circuit is used to convert the first operating voltage into the operating voltage of the DDR memory cell.

[0023] Furthermore, in some embodiments, the input terminal of the DC-DC power supply circuit is also provided with a power input protection circuit. The power input protection circuit includes a multi-level protection network arranged in parallel in sequence. The power input protection circuit is used to suppress surges, absorb transient voltages, and regulate and filter the externally input DC power supply.

[0024] Furthermore, in some embodiments, the multi-level protection network includes:

[0025] The gas discharge tube has one end connected to the input terminal of the power supply circuit and the other end used for DC power supply connection. The gas discharge tube is used as the first-level surge protection layer of the DC-DC power supply circuit.

[0026] TVS transient voltage suppressor diode, TVS transient voltage suppressor diode connected in parallel with gas discharge tube, TVS transient voltage suppressor diode is used as secondary transient voltage protection layer in DC-DC power supply circuit;

[0027] A Zener diode, connected in parallel with a gas discharge tube, is used to regulate the voltage of a DC power supply.

[0028] Multiple capacitors, all connected in parallel with the gas discharge tube, form a filter unit to filter the DC power supply.

[0029] Furthermore, in some embodiments, the current acquisition circuit is also provided with a current limiting module. The current limiting module is connected in series in the loop between the device under test and the sensing resistor. The current limiting module includes a current limiter and a second current limiting resistor. The input terminal and the enable terminal of the current limiter serve as the input terminal of the current acquisition circuit to be connected to the device under test. The input terminal of the current limiting module is connected to the sensing resistor. One end of the second current limiting resistor is connected to the current setting terminal of the current limiter, and the other end of the second current limiting resistor is grounded. The current limiter is used to adjust the resistance value of the second current limiting resistor to set the maximum output current value for supplying power to the device under test. That is, the setting condition for the maximum output current value is the adjustable fixed coefficient in the current limiter / the resistance value of the second current limiting resistor.

[0030] To achieve the above objectives, a second aspect of this application proposes a control method for testing the aging of electronic devices, applied to a host computer, comprising:

[0031] Identify the device under test, determine the test items for the device under test, and edit the corresponding test configuration. The test configuration includes test instructions, characters to be detected, and the judgment result of whether the test passes or fails, representing the character's characteristics.

[0032] The test configuration is sent to the main controller of the control board mentioned in the first aspect via the USB interface, so that the main controller responds to the test configuration and controls the power control circuit of the device under test to perform a preset number of power-on operations on the device under test through the IO port. During each power-on operation, current data is continuously acquired from the ADC interface and the operation log of the device under test is continuously read from the communication interface. According to the test configuration, it is identified whether the operation log contains key characters indicating an anomaly. When the current data exceeds the preset threshold or a key character is identified, a test anomaly is determined, and the current data at the time of the anomaly and the abnormal fragment of the operation log are combined into a data packet and uploaded to the host computer through the USB interface.

[0033] In response to receiving a data packet from the master controller, the system saves and displays the current data and abnormal segments of the operation log at the time of the abnormality.

[0034] The embodiments of the first aspect of this application have the following beneficial effects: Through the coordinated control of the main controller and the host computer, the aging test process is fully automated. It can automatically execute cyclic power-on operations according to preset test instructions and simultaneously collect multi-dimensional data, which significantly reduces the manpower required for traditional aging tests. Secondly, the control board adopts a collaborative diagnostic mechanism combining hardware current detection and software log analysis. A high-precision current acquisition circuit detects the device's operating status in real time, while the communication interface acquires and intelligently analyzes the device's internal operating logs. This "hardware and software combined" detection method can promptly detect various problems, from power supply anomalies to system crashes, from hardware faults to software defects, increasing the speed of potential fault exposure several times over. Most importantly, when the main controller detects an anomaly, it can immediately save complete on-site data, including the current waveform and operating log fragments at the moment the anomaly occurs. This precise fault scene preservation mechanism facilitates subsequent problem localization and root cause analysis, enabling debugging personnel to directly reproduce the fault scenario and effectively shorten the problem localization time. Furthermore, the configurability of the main controller to receive different test instructions and its remote control capabilities allow it to adapt to various test scenarios, providing a complete solution for the reliability verification of electronic equipment. Attached Figure Description

[0035] Figure 1 This is an optional schematic diagram of a control board for testing the aging of electronic equipment provided in an embodiment of this application;

[0036] Figure 2 This is an optional schematic diagram of a host computer controlling multiple control boards to test the device under test, provided in an embodiment of this application.

[0037] Figure 3 This is a schematic diagram of an optional current acquisition circuit provided in an embodiment of this application;

[0038] Figure 4 This is a schematic diagram of an optional power control circuit provided in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of an optional first step-down circuit provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of an optional second step-down circuit provided in an embodiment of this application;

[0041] Figure 7 This is a schematic diagram of an optional third step-down circuit provided in an embodiment of this application;

[0042] Figure 8 This is a schematic diagram of an optional power input protection circuit provided in an embodiment of this application;

[0043] Figure 9 This is an optional flowchart of a method for controlling the aging of electronic devices provided in the embodiments of this application;

[0044] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application.

[0045] Figure Description: Control board 10 for testing the aging of electronic equipment, current acquisition circuit 11, power control circuit 12, main controller 13, device under test 20, host computer 30, DC power supply 40, current detector U4, sensing resistor R13, PMOS transistor Q1, transistor Q2, first current limiting resistor R7, gas discharge tube GDT1, TVS transient suppression diode D1, Zener diode Z1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, current limiter U5, second current limiting resistor R5. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0048] It should also be noted that in the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If the terms "first" and "second" are used, they are only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0050] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0051] In the current field of electronic equipment manufacturing, especially for intelligent power distribution and control equipment, aging testing is a crucial step in ensuring product reliability and stability. Existing mainstream aging testing methods suffer from two major technical bottlenecks: First, for continuous operation aging, a test rack is typically kept constantly powered, relying on periodic manual inspections and visual observation of the equipment's operating status. This approach is not only costly in terms of manpower but also prone to failure to detect anomalies promptly due to human fatigue or negligence. Second, for aging tests targeting equipment startup characteristics, simple timers are commonly used to control power on and off. While this method can achieve cyclic power-on, it cannot collect and analyze detailed operating logs during the power-on process in real time, resulting in a lack of direct evidence for problem localization and low efficiency in debugging and analysis. Especially in harsh environments such as high and low temperature tests and premature failure tests, these methods struggle to accurately reproduce faults and preserve on-site information.

[0052] To address these issues, this application proposes a control board and its control method for testing the aging of electronic devices. First, through the coordinated control of the main controller and the host computer, the aging test process is fully automated. It can automatically execute cyclic power-on operations according to preset test instructions and simultaneously collect multi-dimensional data, significantly reducing the manpower required for traditional aging tests. Second, the control board employs a collaborative diagnostic mechanism combining hardware current detection and software log analysis. A high-precision current acquisition circuit monitors the device's operating status in real time, while the communication interface acquires and intelligently analyzes the device's internal operating logs. This "hardware and software combined" detection method can promptly detect everything from power supply anomalies to system crashes, and from hardware faults to software defects. Various issues have accelerated the exposure of potential faults several times over. Most importantly, the main controller can immediately save complete field data when it detects an anomaly, including the current waveform and operation log fragments at the moment the anomaly occurs. This precise fault field preservation mechanism facilitates subsequent problem localization and root cause analysis, enabling commissioning personnel to directly reproduce the fault scenario and effectively shorten the problem localization time. In addition, the configurability of the main controller to receive different test commands and its remote control capabilities enable it to adapt to various test scenarios, providing a complete solution for the reliability verification of electronic equipment, especially HMI human-machine interface devices in intelligent power distribution systems.

[0053] This application provides a control board for testing the aging of electronic equipment, which is specifically described through the following embodiments.

[0054] Firstly, referring to Figures 1 to 3 As shown, Figure 1 This is an optional schematic diagram of a control board for testing the aging of electronic equipment provided in an embodiment of this application. Figure 2 This is an optional schematic diagram illustrating a host computer controlling multiple control boards to test the device under test, provided in an embodiment of this application. Figure 3 This is an optional schematic diagram of the current acquisition circuit provided in the embodiments of this application. The control board 10 includes a current acquisition circuit 11, a power control circuit 12, and a main controller 13. The current acquisition circuit 11 includes a sensing resistor R13 and a current detector connected to the device under test 20. The current detector is connected to the sensing resistor R13 and is used to acquire an analog signal characterizing the operating current of the device under test 20 from the sensing resistor R13 and amplify and output it.

[0055] The main controller 13 is equipped with an I / O port, an ADC interface, a communication interface for communicating with the device under test 20, and a USB interface for communicating with the host computer 30. The I / O port is connected to the controlled terminal of the power control circuit 12, and the ADC interface is connected to the output terminal of the current detector to convert the analog signal into current data. The sensing resistor R13 is connected in series in the power supply circuit of the device under test 20. When the device under test 20 is working, the current flowing through the sensing resistor R13 generates a corresponding voltage difference. The current detector amplifies this weak differential voltage signal and outputs an analog voltage signal to the ADC interface of the main controller 13. The ADC interface samples the analog voltage signal and then converts it into current data.

[0056] In one embodiment, the communication interface includes a UART interface and an RS485 interface, but this application does not specifically limit the scope of the communication interface.

[0057] It should be noted that the device under test is an HMI (Human-Machine Interface) device in an intelligent power distribution system.

[0058] In one possible embodiment, the current detector is an INA180 chip, and the sensing resistor R13 is a high-precision milliohm resistor with a resistance value of 100mΩ.

[0059] The main controller 13 is configured to, in response to receiving test commands from the host computer 30 via the USB interface, control the power control circuit 12 on the device under test 20 to perform a preset number of power-on operations via the IO port. During each power-on operation, it continuously acquires current data from the ADC interface and continuously reads the operation log of the device under test 20 via the communication interface. It also identifies whether the operation log contains key characters indicating an abnormality according to preset character rules. When the current data exceeds a preset threshold or a key character is identified, it determines that the test is abnormal and uploads the current data at the time of the abnormality and the abnormal segment of the operation log to the host computer 30 via the USB interface.

[0060] In one possible embodiment, after receiving test commands from the host computer 30 via a USB interface, the main controller 13 controls the power control circuit 12 to perform automated testing according to a preset test plan (e.g., 1000 cycles of power-on, each power-on lasting 30 seconds, with a power-off interval of 5 seconds). During each power-on, the main controller 13 synchronously performs the following operations: acquiring current data at 1ms intervals via the ADC interface and calculating the effective value in real time, and implementing overcurrent and undercurrent protection by comparing it with preset thresholds (e.g., normal current range of 100mA-500mA); simultaneously receiving the operation log output by the device under test 20 via the UART interface, and using a string matching algorithm to search for preset key characters (e.g., "System Fault", "Boot Success") in real time. When an abnormal current is detected or a fault characteristic character is matched, the main controller 13 immediately saves the current data sequence and log fragments for 2 seconds before and after the fault occurs, and uploads this field data to the host computer 30 via the USB interface, while simultaneously controlling the power control circuit 12 to cut off the power supply to the device under test 20 to protect the device safety.

[0061] It should be noted that, in this embodiment, a complete automated testing closed loop is constructed through the collaborative work of the host computer 30 software and the control board 10. Testers only need to perform a one-time configuration on the host computer 30, and the control board 10 can automatically execute the entire aging test process, including cyclic power-on, command issuance, status monitoring, and result judgment, without the need for manual supervision or frequent intervention. This fundamentally changes the outdated mode of traditional aging tests that relies on manual inspection and operation, freeing testers from repetitive labor and significantly reducing labor costs. At the same time, compared to manual operation, the automated testing process is faster and has a shorter testing cycle, significantly reducing project time costs and achieving a qualitative leap in testing efficiency.

[0062] Furthermore, this embodiment of the application deeply integrates real-time hardware current monitoring with intelligent analysis of software operation logs, forming a collaborative diagnostic mechanism. The control board 10 not only captures any abnormal power fluctuations through the high-precision current acquisition circuit 11, but also analyzes the operation logs of the device under test 20's core in real time, performing automated logical judgments based on preset key characters. This "hardware-software combined" diagnostic approach allows for faster and more efficient exposure of both hardware-level issues like instantaneous short circuits and excessive power consumption, and software-level issues such as driver anomalies, system crashes, and application crashes. Crucially, once the control board 10 detects an anomaly, it immediately triggers a protection mechanism, pausing the test and automatically saving the complete current data sequence and operation log fragments before and after the anomaly. This is akin to capturing an anomaly snapshot of the fault scene, providing developers with irreplaceable first-hand debugging data, greatly accelerating problem localization and root cause analysis, and solving the industry pain point of "fault scene being fleeting" under traditional timer control methods.

[0063] It should also be noted that the control board 10 for testing the aging of electronic devices possesses high flexibility and configurability. The test items, loop parameters, and key character rules of the control board 10 can all be remotely configured and downloaded via the host computer 30, giving the test solution great adaptability and enabling it to quickly respond to the needs of different products and testing scenarios. Furthermore, based on the data-driven testing process, all operational data and logs are recorded, facilitating quality traceability and big data analysis, providing data support for product iteration and improvement. In summary, this application not only achieves automated testing but also intelligent and refined testing, fundamentally improving the reliability, efficiency, and depth of electronic device aging testing.

[0064] Furthermore, the power control circuit 12 includes a switching element and a control unit. The switching element is connected in series between the input terminal and the output terminal of the power control circuit 12. The controlled terminal of the control unit is connected to the IO port as the controlled terminal of the power control circuit 12. The output terminal of the control unit is connected to the control electrode of the switching element. The control unit is used to drive the switching element to turn on or off according to the control signal output from the IO port to control the power supply circuit to the device under test 20.

[0065] In a preferred embodiment of this application, reference is made to Figure 4 As shown, Figure 4This is an optional schematic diagram of the power control circuit provided in this application embodiment. The power control circuit 12 uses discrete components to build a stable and reliable power switch architecture. The switching element is a PMOS transistor Q1 with low on-resistance. The control unit includes an NPN transistor Q2 and a first current-limiting resistor R7. The base of transistor Q2 is connected to the IO port of the main controller 13 through the first current-limiting resistor R7. The emitter of transistor Q2 is grounded, and the collector of transistor Q2 is connected to the gate of PMOS transistor Q1. The source of PMOS transistor Q1 is connected to the input terminal of the power control circuit 12, and the drain of PMOS transistor Q1 is connected to the output terminal of the power control circuit 12 (i.e., connected to the device under test 20 as a controlled power output terminal).

[0066] The power control circuit 12 operates as follows: When the main controller 13 needs to power the device under test 20, the IO port outputs a high-level signal. This signal drives transistor Q2 into saturation conduction through the first current-limiting resistor R7, thereby pulling the gate potential of PMOS transistor Q1 down to approximately ground potential. At this time, a sufficient negative voltage difference is formed between the gate and source of PMOS transistor Q1, allowing it to conduct completely, and the external DC power supply 40 smoothly supplies power to the device under test 20 through PMOS transistor Q1. When power needs to be cut off, the IO port of the main controller 13 outputs a low-level signal, transistor Q2 immediately turns off, and the gate of PMOS transistor Q1 quickly recovers to a high potential through the pull-up resistor, making the voltage difference between the gate and source approach zero, and PMOS transistor Q1 reliably turns off, thereby cutting off the power supply circuit of the device under test 20.

[0067] It should be noted that the embodiments of this application firstly achieve effective control of the high-voltage power supply by the low-voltage logic signal of the microcontroller; secondly, it has fast response characteristics, which can meet the precise requirements of power supply timing in automated testing; in addition, the power switch architecture also provides good electrical isolation to avoid interference of power supply fluctuations on the control signal. Through the power control circuit 12, this application can accurately execute various complex power supply sequence operations, providing a reliable hardware foundation for automated aging testing.

[0068] It is worth noting that during each power-on operation, the main controller 13 is also configured to: output a control signal characterized by a high level on the IO port according to the test command, so as to control the transistor Q2 to be in a self-conducting state, so that the PMOS transistor Q1 is pulled low to supply power to the device under test 20; or, output a control signal characterized by a low level on the IO port according to the test command, so as to control the transistor Q2 to be in a self-cutoff state, so that the PMOS transistor Q1 is pulled high to turn off the power supply circuit of the device under test 20.

[0069] In one specific embodiment of this application, the test control board 10 integrates a highly efficient and reliable multi-stage step-down DC-DC power supply circuit, providing precise and stable power management for the entire test platform. This power supply system adopts a modular design, mainly including a first-stage step-down module and a second-stage step-down module, forming a complete power distribution architecture. Specifically, the first-stage step-down module converts the input voltage of the DC power supply 40 into a first operating voltage as the main operating voltage of the device under test 20, and the second-stage step-down module converts the first operating voltage into the operating voltage of the main controller 13.

[0070] First, the first-stage buck module, serving as the main power conversion unit, connects to an external 24V or 48V industrial standard DC power supply 40 via a DC power supply 40 interface. This module employs a synchronous buck topology, incorporating a high-current power inductor and low-ESR solid-state capacitors, efficiently converting the input high-voltage DC power supply 40 into a first operating voltage of 12V or 5V. This first operating voltage has a dual function: on one hand, it directly serves as the main operating power supply for the device under test 20, precisely controlled by the subsequent power control circuit 12; on the other hand, it serves as an intermediate power supply, providing input power to the second-stage buck module.

[0071] Secondly, the second-stage buck module further refines the first operating voltage, employing a three-way independent output design architecture, referencing... Figure 5 , 6 As shown in Figure 7, Figure 5 This is a schematic diagram of an optional first step-down circuit provided in an embodiment of this application. Figure 6 This is a schematic diagram of an optional second step-down circuit provided in an embodiment of this application. Figure 7This is an optional schematic diagram of the third buck circuit provided in this application embodiment. The second-stage buck module includes a first buck circuit, a second buck circuit, and a third buck circuit. The first buck circuit and the second buck circuit are connected in parallel, as are the second and third buck circuits. The output terminal of the first-stage buck module is connected to the input terminals of the first buck circuit, the second buck circuit, and the third buck circuit, respectively. The output terminal of the first buck circuit is connected to the I / O port, the output terminal of the second buck circuit is connected to the core unit of the main controller 13, and the output terminal of the second buck circuit is connected to the DDR memory unit of the main controller 13. The first buck circuit is specifically designed to power the I / O ports and peripheral interface chips of the main controller 13, accurately converting a 12V or 5V input voltage to a stable 3.3V voltage to ensure the reliability of digital signal transmission. The second buck circuit uses high-precision low-dropout voltage regulation technology to provide a clean 1.2V power supply to the core unit of the main controller 13. This circuit has fast dynamic response characteristics and can meet the instantaneous power consumption requirements of the processor core during high-speed operation. The third step-down circuit is dedicated to the DDR memory cells, providing a 1.8V operating voltage. This output circuit pays special attention to power ripple suppression and can ensure the stability of the memory system through a multi-stage LC filter network.

[0072] The advantage of this hierarchical power supply architecture lies in achieving precise isolation of the power domain, effectively preventing digital noise from interfering with each other through the power path. Each step-down circuit is equipped with comprehensive overcurrent protection, overtemperature protection, and soft-start functions to ensure continuous and stable operation in complex test environments. The entire power supply system works in conjunction with the main controller 13, power control circuit 12, and current acquisition circuit 11 to form a complete test control solution, providing a solid hardware foundation for automated aging testing.

[0073] Furthermore, the input terminal of the DC-DC power supply circuit is also equipped with a power input protection circuit. The power input protection circuit includes a multi-level protection network arranged in parallel. The power input protection circuit is directly connected between the input interface of the external DC power supply 40 and the first-stage step-down module to form a complete power preprocessing system. The power input protection circuit is used to perform surge suppression, transient voltage absorption and voltage regulation filtering on the externally input DC power supply 40.

[0074] In one possible embodiment, refer to Figure 8 As shown, Figure 8This is a schematic diagram of an optional power input protection circuit provided in an embodiment of this application. The multi-stage protection network in the power input protection circuit includes a gas discharge tube (GDT1). One end of the gas discharge tube (GDT1) is connected to the input terminal of the power supply circuit, and the other end of the gas discharge tube (GDT1) is used for DC power supply 40 connection. The gas discharge tube (GDT1) serves as the first-stage surge protection layer of the DC-DC power supply circuit. When a surge voltage with a long duration and high energy appears at the input terminal of the power supply circuit, the gas discharge tube (GDT1) can quickly break down and conduct within microseconds, dissipating the overvoltage energy to the ground wire, effectively preventing high-voltage surges from damaging subsequent circuits. This design is particularly suitable for dealing with high-energy interference caused by lightning strikes, power grid fluctuations, etc.

[0075] In one possible embodiment, the multi-level protection network further includes a TVS transient voltage suppressor diode D1, which is connected in parallel with the gas discharge tube GDT1. The TVS transient voltage suppressor diode D1 serves as a secondary transient voltage protection layer in the DC-DC power supply circuit, effectively suppressing rapid transient voltage spikes that the gas discharge tube GDT1 cannot completely eliminate, such as transient overvoltages caused by inductive load switching or electrostatic discharge. The combined use of the gas discharge tube GDT1 and the TVS diode constitutes a comprehensive transient voltage protection system covering everything from slow high-energy to fast low-energy voltages.

[0076] In one possible embodiment, the multi-level protection network also includes a Zener diode Z1 connected in parallel with the gas discharge tube GDT1. The Zener diode Z1 is used to regulate the DC power supply 40. Its breakdown voltage is carefully selected based on the system's operating voltage range to ensure it remains in a high-resistance state within the normal input voltage range, while promptly conducting when the voltage abnormally rises to maintain the stability of the downstream circuit voltage. This design effectively prevents system malfunctions caused by power supply voltage fluctuations.

[0077] In one possible embodiment, the multi-level protection network also includes multiple capacitors of different capacitance values ​​(capacitor C2, capacitor C3, capacitor C4, capacitor C5), all of which are connected in parallel with the gas discharge tube GDT1. This parallel connection of capacitors forms a filter unit to filter the DC power supply 40. The large-capacity capacitors are responsible for filtering low-frequency ripple and providing instantaneous large currents, while the small-capacity capacitors are specifically used to absorb high-frequency noise. This composite filtering scheme effectively suppresses various frequency interferences introduced from the power input terminal, providing a clean and stable DC power supply 40 for the subsequent DC-DC conversion circuit.

[0078] Furthermore, in some embodiments, reference is made again to... Figure 3As shown, the current acquisition circuit 11 also integrates a configurable current limiting module. The current limiting module is connected in series in the loop between the device under test 20 and the sensing resistor R13, forming a complete current detection and protection system. The current limiting module includes a current limiter U5 and a second current limiting resistor R5. The input terminal and enable terminal of the current limiter U5 serve as the input terminals of the current acquisition circuit 11 to be connected to the device under test 20. The input terminal of the current limiting module is connected to the sensing resistor R13. One end of the second current limiting resistor R5 is connected to the current setting terminal of the current limiter U5, and the other end of the second current limiting resistor R5 is grounded. The current limiter U5 is used to adjust the resistance value of the second current limiting resistor R5 to set the maximum output current value for supplying power to the device under test 20.

[0079] In one possible embodiment, the current limiter U5 is a SY6280AAC chip.

[0080] The second current-limiting resistor R5 is a high-precision, low-temperature-drift metal film resistor. One end of R5 is reliably grounded, and the other end is connected to the current setting pin of the current limiter U5. The resistance value of this resistor is determined according to the formula ILimit(A) = fixed coefficient / R5, that is, the maximum output current value is set by the adjustable fixed coefficient inside the current limiter / the resistance value of the second current-limiting resistor, where the fixed coefficient is determined by the internal circuit characteristics of the current limiter U5. By selecting different values ​​of the second current-limiting resistor R5, the system can flexibly set the current protection threshold from several hundred milliamps to several amperes to meet the testing requirements of different devices under test 20.

[0081] During operation, the current limiter U5 continuously monitors the output current of the device under test (DUT) 20 and compares the actual current value with the threshold set by the second current-limiting resistor R5 through its internal sampling circuit. When the output current of DUT 20 approaches the set value, the current limiter U5 automatically enters constant current mode, stabilizing the output current by adjusting the conduction level of the internal power transistor. In case of a short circuit or severe overload, the current limiter U5 will completely shut off the output within microseconds and remain locked until the fault is cleared. This design enables the test system to not only have current detection capabilities but also provide reliable overcurrent protection. When an abnormality occurs in DUT 20 causing the current to exceed the limit, the current limiting module can achieve rapid hardware-level protection before the software response of the main controller 13, effectively preventing the fault from escalating. It also provides important current characteristic data for subsequent fault analysis, improving the safety and reliability of the entire test system.

[0082] Secondly, referring to Figure 9 As shown, Figure 9 This is an optional flowchart of a control method for testing the aging of electronic equipment provided in the embodiments of this application. It is applied to a host computer and the method may include, but is not limited to, steps S101 to S103.

[0083] Step S101: Identify the device under test, and determine the test items and edit the corresponding test configuration.

[0084] The test configuration includes test instructions, characters to be tested, and the corresponding character representations indicating whether the test passes or fails.

[0085] Step S102: The test configuration is sent to the main controller of the control board of the first aspect via the USB interface, so that the main controller responds to the test configuration and controls the power control circuit of the device under test to perform a preset number of power-on operations on the device under test in the IO port. In each power-on operation, current data is continuously acquired from the ADC interface and the operation log of the device under test is continuously read from the communication interface. The operation log is identified according to the test configuration to see if it contains key characters that indicate an abnormality. When the current data exceeds the preset threshold or key characters are identified, the test is determined to be abnormal and the current data at the time of the abnormality and the abnormal fragment of the operation log are combined into a data packet and uploaded to the host computer via the USB interface.

[0086] Step S103: In response to receiving the data packet sent by the master controller, save and display the current data and abnormal fragments of the operation log at the time of the abnormality.

[0087] In steps S101 to S103 above, firstly, by uniformly configuring test items, test instructions, and key character judgment rules on the host computer and then automating the entire process by sending the configuration to the test control board for execution, the traditional test mode relying on manual operation is completely changed, significantly reducing manpower input, improving test efficiency, and significantly reducing result deviations caused by human error. Secondly, during the test, the cyclic power-on operation of the power control circuit simulates real start-up and shutdown scenarios, while the current acquisition circuit monitors the power status in real time. Combined with the communication interface, the device operation log is parsed in real time and key character matching is performed, forming a collaborative diagnostic mechanism for hardware status and software behavior, which can quickly... This method rapidly and accurately exposes various hidden faults that occur during equipment startup, operation, and load changes. In particular, when the system detects abnormal current or fault characteristics in the logs, it can immediately capture current data fragments and operational log context at the moment of the abnormality and automatically combine them into a complete data packet for uploading. This innovative on-site data storage mechanism provides real and complete first-hand data for subsequent fault tracing and in-depth analysis, greatly shortening the problem location time and improving debugging efficiency. In addition, the standardized process of this method makes it highly reusable and scalable, adaptable to the testing needs of different types of equipment, and provides an efficient and reliable complete solution for the reliability verification of electronic equipment.

[0088] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described control method for testing the aging of an electronic device. This electronic device can be any smart terminal, including mobile phones, tablets, and in-vehicle computers.

[0089] Please see Figure 10 , Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. The electronic device includes:

[0090] The processor 1001 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the aging control method for test electronic equipment provided in the embodiments of this application.

[0091] The memory 1002 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 1002 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1002 and is called and executed by the processor 1001 using the control method for testing the aging of electronic equipment provided in the embodiments of this application.

[0092] Input / output interface 1003 is used to implement information input and output;

[0093] The communication interface 1004 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0094] Bus 1005 transmits information between various components of the device (e.g., processor 1001, memory 1002, input / output interface 1003, and communication interface 1004);

[0095] The processor 1001, memory 1002, input / output interface 1003 and communication interface 1004 are connected to each other within the device via bus 1005.

[0096] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, provides a method for controlling the aging of electronic devices according to this application.

[0097] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0098] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0099] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0100] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0102] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0103] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0104] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0105] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0107] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A control board for testing the aging of electronic equipment, characterized in that, include: The system comprises a current acquisition circuit, a power control circuit, and a main controller. The current acquisition circuit includes a sensing resistor, a current detector, and a current limiting module connected to the device under test (DUT). The current detector is connected to the sensing resistor and is used to acquire an analog signal representing the operating current of the DUT from the sensing resistor and amplify and output it. The current limiting module includes a current limiter and a second current limiting resistor. The input and enable terminals of the current limiter are connected to the DUT, and the input terminal of the current limiting module is connected to the sensing resistor. One end of the second current limiting resistor is connected to the current setting terminal of the current limiter, and the other end of the second current limiting resistor is grounded. The current limiter is used to set the maximum output current value for supplying power to the DUT. The setting condition for the maximum output current value is an adjustable fixed coefficient within the current limiter divided by the resistance value of the second current limiting resistor. The main controller is equipped with an IO port, an ADC interface, a communication interface for communicating with the device under test, and a USB interface for communicating with the host computer. The IO port is connected to the controlled terminal of the power control circuit, and the ADC interface is connected to the output terminal of the current detector to convert the analog signal into current data. The main controller is configured to, in response to receiving a test command from the host computer via the USB interface, control the power control circuit via the IO port to perform a preset number of power-on operations on the device under test. During each power-on operation, it continuously acquires the current data from the ADC interface and continuously reads the operation log of the device under test from the communication interface. It also identifies whether the operation log contains key characters indicating an anomaly according to a preset character rule. When the current data exceeds a preset threshold or the key character is identified, it determines that the test is abnormal and uploads the current data at the time of the anomaly and the abnormal segment of the operation log to the host computer via the USB interface. Furthermore, the power control circuit includes a switching element and a control unit. The switching element is connected in series between the input terminal and the output terminal of the power control circuit. The controlled terminal of the control unit is connected to the I / O port as the controlled terminal of the power control circuit, and the output terminal of the control unit is connected to the control electrode of the switching element. The control unit is used to drive the switching element to turn on or off according to the control signal output from the I / O port to control the power supply circuit to the device under test. The switching element is a PMOS transistor, and the control unit includes an NPN transistor and a first current-limiting resistor. The base of the transistor is connected to the I / O port of the main controller through the first current-limiting resistor, the emitter of the transistor is grounded, and the collector of the transistor is connected to the gate of the PMOS transistor. The source of the PMOS transistor is connected to the input terminal of the power control circuit, and the drain of the PMOS transistor is connected to the output terminal of the power control circuit.

2. The control board according to claim 1, characterized in that, During each power-on operation, the main controller is also configured to: According to the test command, a control signal characterized as high level is output on the IO port to control the transistor to be in a self-conducting state so that the PMOS transistor is pulled low to supply power to the device under test because the gate of the PMOS transistor is pulled low. Alternatively, according to the test instruction, a control signal characterized as a low level is output on the IO port to control the transistor to be in a self-cutoff state, so that the PMOS transistor is pulled up to a high level and the power supply circuit of the device under test is turned off.

3. The control board according to claim 1, characterized in that, Also includes: A multi-stage step-down DC-DC power supply circuit, wherein the DC-DC power supply circuit includes at least a first-stage step-down module and a second-stage step-down module, wherein the input terminal of the first-stage step-down module is used to connect to an external DC power supply, and the output terminal of the first-stage step-down module is connected to the input terminal of the power control circuit and the input terminal of the second-stage step-down module, respectively. The first-stage step-down module is used to convert the input voltage of the DC power supply into a first operating voltage as the main operating voltage of the device under test, and the second-stage step-down module is used to convert the first operating voltage into the operating voltage of the main controller.

4. The control board according to claim 3, characterized in that, The second-stage step-down module includes a first step-down circuit, a second step-down circuit, and a third step-down circuit. The first step-down circuit and the second step-down circuit are connected in parallel, and the second step-down circuit and the third step-down circuit are connected in parallel. The output terminal of the first-stage buck module is connected to the input terminal of the first buck circuit, the input terminal of the second buck circuit, and the input terminal of the third buck circuit, respectively. The output of the first step-down circuit is connected to the IO port, the output of the second step-down circuit is connected to the core unit of the main controller, and the output of the third step-down circuit is connected to the DDR memory unit of the main controller. The first step-down circuit is used to convert the first operating voltage into the operating voltage of the IO port; The second step-down circuit is used to convert the first operating voltage into the operating voltage of the core unit; The third step-down circuit is used to convert the first operating voltage into the operating voltage of the DDR memory cell.

5. The control board according to claim 3 or 4, characterized in that, The input terminal of the DC-DC power supply circuit is also provided with a power input protection circuit, which includes a multi-level protection network arranged in parallel in sequence. The power input protection circuit is used to suppress surges, absorb transient voltages, and regulate and filter the externally input DC power supply.

6. The control board according to claim 5, characterized in that, The multi-level protection network includes: A gas discharge tube, one end of which is connected to the input terminal of the power supply circuit, and the other end of which is used to connect to a DC power supply. The gas discharge tube is used as a primary surge protection layer of the DC-DC power supply circuit. TVS transient voltage suppressor diode, which is connected in parallel with the gas discharge tube, is used as a secondary transient voltage protection layer of the DC-DC power supply circuit; A Zener diode, which is connected in parallel with the gas discharge tube, is used to regulate the voltage of the DC power supply; Multiple capacitors are connected in parallel with the gas discharge tube, and the multiple capacitors connected in parallel form a filter unit to filter the DC power supply.

7. A control method for testing the aging of electronic equipment, characterized in that, Applications in host computers include: Identify the device under test, determine the test items for the device under test, and edit the corresponding test configuration. The test configuration includes test instructions, characters to be detected, and the judgment result corresponding to the characters, indicating whether the test is passed or abnormal. The test configuration is sent to the main controller of the control board for testing the aging of electronic devices as described in any one of claims 1-6 via a USB interface. The main controller responds to the test configuration by controlling the power control circuit on the I / O port to perform a preset number of power-on operations on the device under test. During each power-on operation, current data is continuously acquired from the ADC interface and the operation log of the device under test is continuously read from the communication interface. The test configuration identifies whether the operation log contains key characters indicating an anomaly. When the current data exceeds a preset threshold or the key characters are identified, a test anomaly is determined, and the current data at the time of the anomaly and the abnormal fragment of the operation log are combined into a data packet and uploaded to the host computer via the USB interface. In response to receiving the data packet sent by the main controller, the current data at the abnormal moment and the abnormal segment of the operation log are saved and displayed.

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