FPGA-based reconfigurable intelligent surface focusing transmission device

Abstract

The application relates to an FPGA-based reconfigurable intelligent metasurface focusing transmission device, an FPGA control unit, a reconfigurable intelligent metasurface array, an energy / data sending unit and an energy / data receiving unit. The FPGA control unit serves as an algorithm deployment and control center, undertakes hardware implementation of a phase calculation full-process formula of the reconfigurable intelligent metasurface, simultaneously completes reconfigurable intelligent array control instruction output and energy / data transmission collaborative scheduling; the reconfigurable intelligent metasurface array adjusts phases according to a quantized phase matrix output by the FPGA control unit to focus on the energy / data receiving unit, and realizes energy / data transmission; the energy / data sending unit and the energy / data receiving unit transmit energy / data through the reconfigurable intelligent metasurface array; and the energy / data sending unit and the energy / data receiving unit feed back transmission link parameters to the FPGA control unit.

Description

Technical Field

[0001] This invention relates to the field of reconfigurable intelligent metasurface focusing technology, and more particularly to a reconfigurable intelligent metasurface focusing and transmission device based on FPGA. Background Technology

[0002] The statements in this section are merely background information relating to this disclosure and do not necessarily constitute prior art.

[0003] In fields such as wireless communication, wireless power transfer (WPT), and the Internet of Things, reconfigurable smart metasurfaces, with their ability to dynamically control the phase and amplitude of electromagnetic waves, have become a key technology carrier for realizing "directional focusing of space energy" and "efficient data transmission".

[0004] For example, in indoor wireless power supply / charging scenarios, reconfigurable intelligence is needed to precisely focus energy onto mobile devices to wirelessly power them, avoiding low power supply / charging utilization caused by energy dispersion. In complex industrial communication environments, reconfigurable intelligence is needed to optimize signal propagation paths and reduce the impact of obstructions and electromagnetic interference on data transmission stability. These applications place stringent requirements on the "focusing accuracy," "control response speed," and "energy-data transmission synergy" of reconfigurable intelligent metasurfaces.

[0005] However, current control and transmission processing schemes for reconfigurable smart metasurfaces still face significant technical bottlenecks: reconfigurable smart metasurfaces typically contain tens to hundreds of array elements. To achieve precise focusing and control response speed, the phase adjustment parameters of each element must be calculated in parallel and in real time to ensure accurate focusing. Simultaneously, feedback signals for energy / data transmission (such as interference detection and power regulation) must be processed synchronously. The serial processing mode of CPU / DSP leads to control delays exceeding milliseconds, which not only reduces focusing accuracy (often exceeding 10%) but also causes energy transmission efficiency degradation (below 50%) and increased data transmission error rate (exceeding 10%). -4 This approach fails to meet the demands of real-time applications. Existing hardware acceleration solutions suffer from functional fragmentation: some solutions attempt to use ASICs (Application Specific Integrated Circuits) to accelerate reconfigurable intelligent control, but ASIC design cycles are long and inflexible, making them unsuitable for iterative focusing algorithms in different scenarios (such as parameter adjustment logic under different transmission distances and interference environments); a few FPGA-based solutions are limited to the single function of "reconfigurable unit phase control," failing to integrate FPGA with focusing algorithm optimization and energy-data transmission co-processing—for example, they do not implement real-time interference signal filtering through hardware logic circuits, nor do they design a synchronous scheduling module for energy and data transmission. As a result, although reconfigurable intelligence can achieve focusing, it still faces problems such as high transmission link interference and energy-data transmission conflicts.

[0006] Multi-module integration and reliability shortcomings: In existing reconfigurable intelligent systems, control modules (such as CPU / FPGA), reconfigurable unit arrays, and energy / data transceiver modules are mostly designed separately. The modules are connected through ordinary interfaces (such as UART), which not only causes signal transmission loss (leading to distortion of focusing parameters), but also makes it difficult to cope with unit failures in complex environments (such as industrial electromagnetic interference and multi-obstruction scenarios). Once a single reconfigurable unit fails, the lack of redundant control logic to quickly fill the gap will directly lead to focus area shift and transmission link interruption, making it difficult to guarantee reliability.

[0007] In summary, current technical solutions cannot simultaneously meet the comprehensive requirements of reconfigurable intelligent metasurfaces in terms of "low-latency control," "high-precision focusing," "high-coordinated transmission," and "high environmental adaptability." Therefore, developing an FPGA-based reconfigurable intelligent metasurface focusing and transmission device to achieve precise and efficient transmission of space energy and data has become a key problem that urgently needs to be solved in this field. Summary of the Invention

[0008] To solve the above-mentioned technical problems, or at least partially solve them, the present invention provides a reconfigurable intelligent metasurface focusing and transmission device based on FPGA.

[0009] This invention provides a reconfigurable intelligent metasurface focusing and transmission device based on FPGA, comprising: an FPGA control unit, which serves as the algorithm deployment and control center, undertakes the hardware implementation of the entire phase calculation formula of the reconfigurable intelligent metasurface, and simultaneously completes the output of reconfigurable intelligent array control commands and the coordinated scheduling of energy / data transmission;

[0010] The reconfigurable smart metasurface array adjusts the phase according to the quantization phase matrix output by the FPGA control unit to focus the energy / data receiving unit, thereby realizing the energy / data transmission between the energy / data transmitting unit and the energy / data receiving unit.

[0011] The energy / data transmitting unit and the energy / data receiving unit transmit energy / data through a reconfigurable smart metasurface array; the energy / data transmitting unit and the energy / data receiving unit feed back the transmission link parameters to the FPGA control unit.

[0012] Furthermore, the FPGA control unit adopts a modular parallel pipeline design, divided into multiple hardware computing modules. Each hardware computing module achieves data pipeline transmission through register cascading, avoiding serial computing delays. The hardware computing modules include: a basic parameter preprocessing module containing wavenumber calculation units and distance calculation units; a phase angle and real / imaginary part accumulation and normalization module containing phase angle calculation units and imaginary / real part accumulation and normalization units; a final phase solving module; and a phase correction and quantization module containing phase correction units and quantization and matrix generation units.

[0013] Furthermore, the wavenumber calculation unit: based on the wavelength λ of the input energy / data carrier electromagnetic wave, the FPGA control unit's built-in multiplier and divider IP cores perform fixed-point wavenumber calculations in hardware. ,in, For wave number.

[0014] Furthermore, the distance calculation unit adopts a parallel square root IP core array design, allocating independent distance calculation logic to each reconfigurable unit. The distance calculation module simultaneously receives the input coordinates of the target energy / data transmitting unit, the reconfigurable unit, and the target energy / data receiving unit, calculates the distance from the energy / data transmitting unit to the reconfigurable unit, and calculates the distance from the reconfigurable unit to the target energy / data receiving unit. After the hardware logic performs the square operation of the difference between different coordinate components in parallel, the results are accumulated, and then the parallel square root IP core array is called to output the distance calculation result.

[0015] Furthermore, the phase angle calculation unit calculates the phase angle corresponding to the phase difference between the ij-th reconfigurable unit and all target energy / data receiving units. The phase angle calculation unit adopts a "multiplication-modulus" hardware design. First, a multiplier performs a product operation between the wavenumber and the distance from the ij-th reconfigurable unit to each target energy / data receiving unit to obtain the phase difference between the ij-th reconfigurable unit and each target energy / data receiving unit. Then, a comparator and a subtractor are used to calculate the phase difference. The modulus of the modulus, where the preset To preserve the number of fixed-point values ​​for the set precision decimal places, the phase angles of M target energy / data receiving units are calculated synchronously using M parallel channels.

[0016] Furthermore, the real-imaginary part accumulation and normalization unit uses a CORDIC IP core to calculate the sine and cosine values ​​of the phase angle; the real-imaginary part accumulation and normalization unit adopts a "parallel adder tree and divider" structure design, first synchronizing the accumulation of the sine and cosine of the phase angle between the ij-th reconfigurable unit and all target energy / data receiving units through an adder tree of a set number of levels, to obtain the accumulated imaginary part. With cumulative real part Then, a fixed-point divider is used to perform division by M and normalization, outputting the normalized real and imaginary parts.

[0017] Furthermore, the phase angle calculation unit also supports multiplying the negative wavenumber value with the distance from the ij-th reconfigurable unit to the energy / data transmission unit using a multiplier to obtain the phase difference between the ij-th reconfigurable unit and the energy / data transmission unit.

[0018] Furthermore, the final phase determination module employs a hardware-based quadrant determination state machine and a CORDIC IP core fusion design. The quadrant determination state machine, based on a comparator, determines the sign of the normalized real and normalized imaginary parts to output a 2-bit state signal. Four combinations of these two state signals correspond to four quadrants, thus determining the quadrant. The CORDIC IP core, configured in arctan2 mode on the FPGA control unit, calculates the fundamental arctan value based on the ratio of the input normalized imaginary to normalized real parts. The quadrant determination state machine, through a hardware selector, adjusts the fundamental arctan value by ±... Corrections.

[0019] Furthermore, the phase correction unit receives the reference phase through a register. The reference phase is dynamically configured according to the transmission device, and the phase difference between the ij-th reconfigurable unit and the energy / data transmission unit is... The phase of the ij-th reconfigurable unit phase(i,j); the reference phase After adding the phase phase(i,j) of the ij-th reconfigurable unit, the phase difference is adjusted using a comparator and a subtractor. The mold is taken, and then combined with Perform a subtraction operation to obtain the corrected phase. .

[0020] Furthermore, the quantization and matrix generation unit employs multipliers, rounding, and multiplier hardware logic to first correct the phase. Multiply by 2 / π, then round using a hardware circuit that adds 0.5 and truncates to the nearest integer, finally multiply by π / 2 and take the modulus of 2π to obtain the quantized phase. Quantization phase The quantization phase matrix is ​​output through the operation of "dividing by π / 2, rounding, and taking the modulus of 4". .

[0021] The technical solutions provided in the embodiments of the present invention have the following advantages compared with the prior art:

[0022] This invention achieves synchronous parameter configuration for dozens to hundreds of reconfigurable units by embedding highly parallel reconfigurable unit phase calculation logic within an FPGA. This reduces control latency from milliseconds to microseconds while improving the accuracy of focusing parameter calculation, ensuring that the spatial energy focusing error does not exceed 5%, thus meeting real-time and accuracy requirements. The FPGA hardware handles computationally intensive tasks such as reconfigurable intelligent metasurface focusing control and energy / data preprocessing (e.g., interference filtering, parameter calibration), eliminating reliance on subsequent application platforms (e.g., IoT gateways, wireless power controllers) and saving them over 70% of data processing load. Simultaneously, it outputs precise focusing control commands and a stable energy / data transmission link, facilitating the efficient deployment of reconfigurable intelligent metasurfaces in scenarios such as indoor wireless power supply and communication in complex industrial environments. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0025] Figure 1 An architecture diagram of a reconfigurable intelligent metasurface focusing and transmission device based on FPGA is provided for an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a reconfigurable smart metasurface array and coordinate system provided in an embodiment of the present invention;

[0027] Figure 3 This is an architecture diagram of the FPGA control unit provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0030] Example 1

[0031] This invention aims to address the technical shortcomings of current reconfigurable intelligent metasurface control and transmission solutions, namely "high control latency, low focusing accuracy, functional fragmentation, and poor reliability." It proposes an FPGA-based reconfigurable intelligent metasurface focusing and transmission device. Specifically, by embedding highly parallel reconfigurable unit phase calculation logic within the FPGA, synchronous parameter configuration for dozens to hundreds of reconfigurable units is achieved, reducing control latency from milliseconds to microseconds. Simultaneously, the accuracy of focusing parameter calculation is improved, ensuring that the spatial energy focusing error does not exceed 5%, meeting real-time and accuracy requirements. The FPGA hardware performs computationally intensive tasks such as reconfigurable intelligent metasurface focusing control and energy / data preprocessing (e.g., interference filtering, parameter calibration), eliminating reliance on subsequent application platforms (e.g., IoT gateways, wireless power controllers) and saving them over 70% of data processing load. It also outputs precise focusing control commands and a stable energy / data transmission link, facilitating the efficient deployment of reconfigurable intelligent metasurfaces in scenarios such as indoor wireless power supply and communication in complex industrial environments.

[0032] like Figure 1 As shown, the FPGA-based reconfigurable intelligent metasurface focusing and transmission device of the present invention includes:

[0033] The host computer communicates with the FPGA control unit and provides the FPGA control unit with parameters including coordinate information and reference phase.

[0034] The FPGA control unit serves as the central hub for algorithm deployment and control. It undertakes the hardware implementation of the entire phase calculation formula for the reconfigurable smart metasurface, and simultaneously completes the output of control commands for the reconfigurable smart array and the coordinated scheduling of energy / data transmission.

[0035] A reconfigurable smart metasurface array adjusts the phase of the energy / data receiving unit based on control commands output from an FPGA control unit, thereby enabling energy / data data transmission between the energy / data transmitting and receiving units. Specifically, the reconfigurable smart metasurface array contains I×J reconfigurable units, represented by indices ij. The control commands output by the FPGA control unit include a quantized phase matrix, which the reconfigurable smart metasurface array uses to configure the phase of the reconfigurable units. Figure 2 As shown, for ease of subsequent calculations, this application uses the plane containing the reconfigurable smart metasurface array as the XY plane of the coordinate system, and the axis perpendicular to the reconfigurable smart metasurface array as the Z-axis. Thus, the Z-axis coordinate values ​​of all reconfigurable elements in the reconfigurable smart metasurface array are 0. Figure 2 In the given example, the origin of the coordinate system is located at the center of the reconfigurable smart metasurface array.

[0036] Energy / data transmission units and energy / data receiving units communicate via a reconfigurable smart metasurface array. These units feed back transmission link parameters to the FPGA control unit. The data transmission rate between the energy / data transmission units and the FPGA control unit is no less than 10 Mbps, providing a hardware foundation for control latency not exceeding 1 ms. As an example, the FPGA control unit is interconnected via a high-speed 485 serial port, providing real-time feedback of transmission link parameters (such as received power and bit error rate), forming a closed loop of "computation-control-feedback".

[0037] The energy / data transmitting unit supports adaptive configuration of energy / data carrier electromagnetic waves in the 0.1-10GHz frequency band. The energy / data receiving unit is connected to the control unit; one example control unit uses an ARM development board. The control unit communicates with the FPGA control unit to implement feedback.

[0038] like Figure 3 As shown, the FPGA control unit is designed as follows: The FPGA control unit adopts a modular parallel pipeline design, divided into multiple hardware computing modules. Each hardware computing module achieves data pipeline transmission through register cascading to avoid serial computing delays. The hardware computing modules of the FPGA control unit include: a basic parameter preprocessing module containing wavenumber calculation unit and distance calculation unit; a phase angle and real / imaginary part accumulation and normalization module containing phase angle calculation unit and imaginary / real part accumulation and normalization unit; a final phase solving module; and a phase correction and quantization module containing phase correction unit and quantization and matrix generation unit.

[0039] 1. Basic Parameter Preprocessing Module:

[0040] The wavenumber calculation unit calculates the wavelength of the electromagnetic waves that carry energy / data. Fixed-point arithmetic of wavenumbers is implemented in hardware by using multiplier and divider IP cores built into the FPGA control unit. ,in, For wavenumbers, fixed-point arithmetic uses a 32-bit fixed-point format, with 8 integer bits and 24 decimal bits, and a precision error ≤ 10. -6 The computation time is ≤200ns.

[0041] The distance calculation unit adopts a parallel square root IP core array design, allocating independent distance calculation logic to each reconfigurable unit. Specifically, the distance calculation module simultaneously receives the input coordinates of the target energy / data transmitting unit, the reconfigurable unit, and the target energy / data receiving unit, calculates the distance from the energy / data transmitting unit to the reconfigurable unit, and calculates the distance from the reconfigurable unit to the target energy / data receiving unit. After performing the square operation of the difference between different coordinate components in parallel through hardware logic, the results are accumulated, and then the parallel square root IP core array is called to output the distance calculation result.

[0042] like Figure 3 As shown, the coordinates of the energy / data transmission unit are set as follows: The coordinates of the m-th target energy / data receiving unit are: The coordinates of the ij-th reconfigurable unit in the reconfigurable smart metasurface array are: In one example, the FPGA control unit receives the aforementioned coordinate information from the host computer, and the distance between the energy / data transmission unit and the ij-th reconfigurable unit is... The distance between the m-th target energy / data receiving unit and the ij-th reconfigurable unit is The distance calculation unit in this application adopts a parallel square root IP core array design, allocating independent distance calculation logic to each reconfigurable unit, while simultaneously receiving coordinate information and completing the calculation in parallel through hardware logic. After squaring and summing, the distance calculation result is output by calling the high-speed square root IP core of the FPGA control unit. The distance calculation time for N×N reconfigurable units does not exceed 50us (taking 256 units as an example), which is a significant improvement.

[0043] The basic parameter preprocessing module stores the calculation results in registers for use in subsequent calculations.

[0044] 2. Phase Angle and Real / Imaginary Part Accumulation Module:

[0045] The phase angle calculation unit calculates the phase angle corresponding to the phase difference between the ij-th reconfigurable unit and all target energy / data receiving units. The phase angle calculation unit adopts a "multiplication-modulo" hardware design, and the calculation process includes: obtaining wavenumbers from registers respectively. The distance between the ij-th reconfigurable unit and the m-th target energy / data receiving unit. First, the phase difference between the ij-th reconfigurable unit and each target energy / data receiving unit is obtained by multiplying the wave number with the distance from the ij-th reconfigurable unit to each target energy / data receiving unit using a multiplier. The phase difference is then achieved using a comparator and a subtractor. The modulus of the modulus, where the preset To preserve the fixed-point number of decimal places for the set precision, M parallel channels are used to synchronously calculate the phase angle corresponding to the phase difference between M target energy / data receiving units and any reconfigurable unit; preset... The fixed-point value is 6.283185307, with a precision of 24 decimal places, and the single-channel operation time does not exceed 200ns; it supports M-channel expansion and adopts parallel channel synchronous calculation, with the total time still ≤200ns.

[0046] The phase angle calculation unit also supports multiplying the negative wavenumber value with the distance from the ij-th reconfigurable unit to the energy / data transmission unit using a multiplier to obtain the phase difference between the ij-th reconfigurable unit and the energy / data transmission unit. .

[0047] The real-imaginary part accumulation and normalization unit uses a CORDIC IP core to calculate the sine and cosine values ​​of the phase angle, with a delay not exceeding 120ns. The real-imaginary part accumulation and normalization unit adopts a "parallel adder tree and divider" structure design. First, it synchronously completes the accumulation of the sine and cosine values ​​of the phase angle between the ij-th reconfigurable unit and all target energy / data receiving units through an 8-level adder tree of a set number of levels (each level with a delay ≤ 50ns), thus obtaining... and , , Then, a fixed-point divider (latency ≤ 30ns) is used to divide by M to achieve normalization, and the normalized real part is output. Normalized imaginary part and To the register, where, , The total execution time of this module is ≤60ns, avoiding the cumulative loop delay in software. The direct fixed-point divider in the hardware is optimized using shift subtraction operations, with a execution time of ≤10ns.

[0048] 3. Final Phase Calculation Module:

[0049] The final phase calculation module employs a hardware-based quadrant determination state machine and a CORDIC IP core fusion design. The quadrant determination state machine, based on a comparator, determines the sign of the normalized real and normalized imaginary parts to output a 2-bit state signal. Four combinations of these two state signals correspond to four quadrants, thus determining the quadrant. The CORDIC IP core, configured in arctan2 mode and calling the FPGA control unit, calculates the base arctan value based on the ratio of the input normalized imaginary to normalized real parts. ;

[0050] The basic arctan value is ± based on the state signal using a hardware selector. The correction, The default fixed-point number is 3.141592654. The addition / subtraction time does not exceed 5ns. Finally, the phase of the ij-th reconfigurable unit phase(i,j) is output.

[0051]

[0052] 4. Phase Correction and Quantization Module:

[0053] The phase correction unit receives the reference phase through a register. The reference phase is dynamically configured according to the transmission device, with a step size of 0.01. The phase difference between the ij-th reconfigurable unit and the energy / data transmission unit The phase of the ij-th reconfigurable unit phase(i,j); the reference phase After adding the phase phase(i,j) of the ij-th reconfigurable unit using an adder, a comparator and a subtractor are used to achieve the desired result. Modulus taking: The time taken is ≤10ns, and then with The corrected phase is obtained by performing subtraction using a subtractor. : ;and Since it is a negative value, it is actually equivalent to adding a positive value, which compensates for the phase delay from the source to the reconfigurable unit.

[0054] Quantization and matrix generation unit: Employing multiplier, rounding, and multiplier hardware logic, the phase correction is first performed. Multiply by 2 / , 2 / The hardware defaults to a fixed-point number of 0.636619772, with multiplication taking no more than 10ns. Rounding is then performed using a hardware circuit that adds 0.5 and truncates to the nearest integer, taking no more than 5ns. Finally, multiplication is performed... / 2, / 2 is preset to a fixed-point number of 1.570796327 in the hardware, the multiplication time does not exceed 10ns, and the modulo 2 is taken. Quantization phase is obtained :

[0055] ,in, Indicates rounding;

[0056] Quantization phase By dividing The " / 2, round to the nearest integer, modulo 4" operation is simplified in hardware to a right shift and AND operation, taking no more than 3ns, and outputs integer quantized phase matrix elements from 0 to 3. :

[0057] .

[0058] The elements of the quantization phase matrix are used to form the quantization phase matrix.

[0059] Control commands are generated based on the quantized phase matrix to form reconfigurable cells. These commands are then output to the reconfigurable smart metasurface array via a high-speed interface (such as SPI) to complete phase configuration.

[0060] Modulo 4 uses AND operation instead of subtraction to reduce FPGA resource usage, lower computation time, and ensure low latency.

[0061] This application breaks down the entire phase calculation process into multiple hardware computing modules. Through the parallel pipeline design of the FPGA control unit, a pipeline operation of "parameter input - distance calculation - phase solution - instruction output" is realized. The output data of the previous module enters the calculation of the next module immediately, with no waiting delay. The total time of the entire process does not exceed 800μs (including feedback judgment). Combined with the high-speed interface transmission time, the control delay is ultimately reduced to no more than 1ms, and the speed is improved by more than 5 times.

[0062] The phase angle calculation unit supports parallel channel configuration of M focal points. Through the dynamic reconfiguration feature of the FPGA control unit, the number of focal points can be flexibly switched according to the application scenario (such as single-point high-energy transmission / multi-point data distribution) without redesigning the hardware logic, making it more adaptable.

[0063] By building a hardware test platform (Xilinx KU115 FPGA, 16×16 reconfigurable smart metasurface array, wavelength λ=30mm, M=4 focal points), the key performance indicators of this application were tested. The results are as follows: the total delay from receiving the coordinate parameters from the host computer to the reconfigurable smart metasurface array completing phase configuration is 820μs (including 780μs for formula calculation + 40μs for command transmission), meeting the design target of ≤1ms; the energy concentration of the spatial focusing area (90% energy coverage radius) is not less than 5cm, the focusing error is 3.2%, and the error optimization exceeds 10%; the bit error rate is 8.5×10 at a data transmission rate of 100Mbps. -7 The energy transfer efficiency is 82%. During 72 hours of continuous operation, the computing module of the FPGA control unit has no logical errors. When the reconfigurable intelligent metasurface array unit fails (simulating the failure of one unit), the redundant logic replacement time does not exceed 20μs, and there is no transmission link interruption.

[0064] In the embodiments provided by this invention, it should be understood that the disclosed structures and methods can be implemented in other ways. For example, the structural embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, structures, or units, and may be electrical, mechanical, or other forms.

[0065] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0066] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0067] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A reconfigurable intelligent metasurface focusing and transmission device based on FPGA, characterized in that, include: The FPGA control unit serves as the central hub for algorithm deployment and control. It undertakes the hardware implementation of the entire phase calculation formula for the reconfigurable smart metasurface, and simultaneously completes the output of control commands for the reconfigurable smart array and the coordinated scheduling of energy / data transmission. The FPGA control unit adopts a modular parallel pipeline design, divided into multiple hardware computing modules. These modules achieve pipelined data transmission through register cascading, avoiding serial computation delays. The hardware computing modules include: a basic parameter preprocessing module containing wavenumber and distance calculation units; a phase angle and real / imaginary part accumulation and normalization module containing a phase angle calculation unit and a real / imaginary part accumulation and normalization unit; a final phase solving module; and a phase correction and quantization module containing a phase correction unit and a quantization and matrix generation unit. The wavenumber calculation unit, based on the wavelength λ of the input energy / data carrier electromagnetic wave, implements fixed-point wavenumber arithmetic in hardware using the multiplier and divider IP cores built into the FPGA control unit. ,in, The distance calculation unit employs a parallel square root IP core array design, allocating independent distance calculation logic to each reconfigurable unit. The distance calculation module simultaneously receives the input coordinates of the target energy / data transmitting unit, the reconfigurable unit, and the target energy / data receiving unit, calculating the distance from the energy / data transmitting unit to the reconfigurable unit and the distance from the reconfigurable unit to the target energy / data receiving unit. This is achieved through parallel hardware logic that squares the differences between different coordinate components, sums the results, and then calls the parallel square root IP core array to output the distance calculation result. The phase angle calculation unit calculates the phase angle corresponding to the phase difference between the ij-th reconfigurable unit and all target energy / data receiving units. The phase angle calculation unit uses a "multiplication, modulo" hardware design. First, a multiplier performs a product operation on the wavenumber and the calculated distance from the ij-th reconfigurable unit to each target energy / data receiving unit to obtain the phase difference between the ij-th reconfigurable unit and each target energy / data receiving unit. Then, a comparator and a subtractor are used to calculate the phase difference. The modulus of the modulus, where the preset To preserve the fixed-point number of decimal places for the set precision, M parallel channels are used to synchronously calculate the phase angles of M target energy / data receiving units. The real and imaginary part accumulation and normalization unit uses a CORDIC IP core to calculate the sine and cosine values ​​of the phase angles. The real and imaginary part accumulation and normalization unit adopts a "parallel adder tree and divider" structure design. First, the phase angle sine and cosine values ​​between the ij-th reconfigurable unit and all target energy / data receiving units are accumulated synchronously through an adder tree of a set number of levels to obtain the accumulated imaginary part. With cumulative real part The process then uses a fixed-point divider to normalize by M, outputting the normalized real and imaginary parts. Finally, the phase-solving module employs a hardware-based quadrant determination state machine and a CORDIC IP core fusion design. The quadrant determination state machine, based on a comparator, determines the sign of the normalized real and imaginary parts to output a 2-bit state signal. Four combinations of these two state signals correspond to four quadrants, thus determining the quadrant. The CORDIC IP core, configured in arctan2 mode on the FPGA control unit, calculates the fundamental arctan value based on the ratio of the input normalized imaginary to normalized real parts. The quadrant determination state machine, through a hardware selector, adjusts the fundamental arctan value based on the state signal. The phase correction unit receives the reference phase through a register. The reference phase is dynamically configured according to the transmission device, and the phase difference between the ij-th reconfigurable unit and the energy / data transmission unit is... The phase of the ij-th reconfigurable unit phase(i,j); the reference phase After adding the phase phase(i,j) of the ij-th reconfigurable unit, the phase difference is adjusted using a comparator and a subtractor. The mold is taken, and then combined with Perform a subtraction operation to obtain the corrected phase. The quantization and matrix generation unit employs multipliers, rounding, and multiplier hardware logic to first correct the phase. Multiply by 2 / π, then round using a hardware circuit that adds 0.5 and truncates to the nearest integer, finally multiply by π / 2 and take the modulus of 2π to obtain the quantized phase. Quantization phase The quantization phase matrix is ​​output through the operation of "dividing by π / 2, rounding, and taking the modulus of 4". ; The reconfigurable smart metasurface array adjusts the phase according to the quantization phase matrix output by the FPGA control unit to focus the energy / data receiving unit, thereby realizing the energy / data transmission between the energy / data transmitting unit and the energy / data receiving unit. The energy / data transmitting unit and the energy / data receiving unit transmit energy / data through a reconfigurable smart metasurface array; the energy / data transmitting unit and the energy / data receiving unit feed back the transmission link parameters to the FPGA control unit.

2. The FPGA-based reconfigurable intelligent metasurface focusing and transmission device according to claim 1, characterized in that, The phase angle calculation unit also supports multiplying the negative wavenumber value with the distance from the ij-th reconfigurable unit to the energy / data transmission unit using a multiplier to obtain the phase difference between the ij-th reconfigurable unit and the energy / data transmission unit.

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