Large-scale logic optimization multiplier verification method

Abstract

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

Description

TECHNICAL FIELD

[0001] The present application relates to a large-scale logic-optimized multiplier verification method based on integer programming and quantum ant colony algorithm, which is used for formal verification of large-scale logic-optimized integer multipliers, and particularly focuses on a method for generating a reference multiplier that can be used to verify the functional correctness of a complex multiplier design that has been logic-optimized, and belongs to the field of electronic design automation (EDA). BACKGROUND

[0002] Multipliers are fundamental components for high-performance arithmetic operations in modern computing systems, including artificial intelligence accelerators, CPUs, GPUs, and FPGA-based applications. To optimize efficiency, designers often employ logic optimization techniques to restructure and simplify the Boolean logic of multiplier designs. However, these optimizations can introduce subtle logic discrepancies, leading to functional deviations from expectations. Furthermore, the optimization process can blur the boundaries of original multiplier components, hindering the application of traditional verification methods. Therefore, formal verification of large-scale logic-optimized integer multipliers remains an important but insufficiently addressed challenge in both industry and academia.

[0003] Currently, there are three main formal verification methods for large-scale logic-optimized integer multipliers: BDD-based methods verify by constructing XOR circuits between test and reference multiplier outputs, but as described in [1] and [2], large multipliers can cause intermediate BDD structures to expand; SAT-based methods convert problems into conjunctive normal form for solving, and although the SAT-sweeping technique proposed in [3] and [4] has improved, it is limited in the absence of similar reference circuits; SCA methods represent logic gates as polynomials for verification, and [5] and [6] enable handling of unoptimized multipliers through techniques such as eliminating locally vanishing monomials, but logic optimization blurs the boundaries of atomic blocks, reducing their effectiveness. In recent years, hybrid SAT-SCA methods have become popular, [7] proposes a method to identify boundaries at different stages of multipliers, and [8] develops the RefSCAT framework to facilitate verification by generating reference multipliers, but still faces scalability challenges when dealing with large-scale designs.

[0004] In summary, existing technologies face four major problems when dealing with large-scale optimized multipliers: scalability limitations, component boundary blurring, low efficiency in generating reference multipliers, and lack of a unified framework.

[0005] REFERENCES

[0006] [1].Radmanovi′c,“Evaluation of binary decision diagrams complexityusing relative arithmetic width,”IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems,vol.42,no.10,pp.3469–3473,2023.

[0007] [2]D.Sahoo,S.Iyer,J.Jain,C.Stangier,A.Narayan,D.L.Dill,andE.A.Emerson,“A partitioning methodology for bdd-based verification,”in FormalMethods in Computer-Aided Design,A.J.Hu and A.K.Martin,Eds.Berlin,Heidelberg:Springer Berlin Heidelberg,2004,pp.399–413.

[0008] [3]A.Mishchenko,S.Chatterjee,R.Brayton,and N.Een,“Improvements tocombinational equivalence checking,”in Proceedings of the 2006IEEE / ACMInternational Conference on Computer-Aided Design,ser.ICCAD’06.New York,NY,USA:Association for Computing Machinery,2006,p.836–843.

[0009] [4]L.Amar′u,F.Marranghello,E.Testa,C.Casares,V.Possani,J.Luo,P.Vuillod,A.Mishchenko,and G.De Micheli,“Sat-sweeping enhanced for logicsynthesis,”in 2020 57th ACM / IEEE Design Automation Conference(DAC),2020,pp.1–6.

[0010] [5]A.Mahzoon,D. and R.Drechsler,“Revsca-2.0:Sca-based formalverification of nontrivial multipliers using reverse engineering and localvanishing removal,”IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems,vol.41,no.5,pp.1573–1586,2022.

[0011] [6]A.Mahzoon,D. and R.Drechsler,“Polycleaner:Clean yourpolynomials before backward rewriting to verify million-gate multipliers,”in2018IEEE / ACM International Conference on Computer-Aided Design(ICCAD),2018,pp.1–8.

[0012] [7]D.Kaufmann,A.Biere,and M.Kauers,“Verifying large multipliers bycombining sat and computer algebra,”in 2019Formal Methods in Computer AidedDesign(FMCAD),2019,pp.28–36.

[0013] [8] R. Li, L. Li, H. Yu, M. Fujita, W. Jiang, and Y. Ha, "Refscat: Formalverification of logic-optimized multipliers via automated reference multiplier generation and sca-sat synergy," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1–1, 2024. Summary of the Invention

[0014] The purpose of this invention is to address the scalability limitations faced by existing verification methods when dealing with large-scale optimized multipliers, enabling the rapid generation of reference multipliers with well-defined adder boundaries, thereby promoting efficient verification of optimized multipliers.

[0015] To achieve the above objectives, the technical solution of this invention discloses a large-scale logic-optimized multiplier verification method, characterized by employing a four-stage pipelined processing mode. The first stage is a partial adder tree recovery stage, where meaningful arithmetic structure information is recovered from the optimized multiplier using reverse engineering techniques to obtain a structured adder tree. The second stage is an architecture generation stage, where a reference multiplier with well-defined boundaries is generated using a three-layer decomposition strategy with the adder tree as input. The third stage is a functional verification stage, where the functional correctness of the reference multiplier is verified using symbolic computation algebra. The fourth stage is an equivalence check stage, where the logical equivalence between the optimized multiplier and the reference multiplier is checked using SAT solving techniques.

[0016] Preferably, the first stage includes the following steps:

[0017] The potential sub-circuits of logic-optimized multipliers represented in NAND-inverted phase diagram format are systematically extracted using the NAND-inverted phase diagram cutting enumeration technique.

[0018] The extracted sub-circuits are matched with a pre-built atomic block truth table library. If the output vector of a cutting combination matches exactly a truth table in the atomic block truth table library, the current cutting combination is identified as the corresponding atomic block.

[0019] Identify the partial product generation stage of the logic-optimized multiplier and recover any missing AND gates based on the input bit width and structural characteristics of the logic-optimized multiplier to ensure the integrity of the partial product generator structure.

[0020] A breadth-first search-based algorithm is used to systematically reconstruct the adder tree structure in the partial accumulator;

[0021] For parts that cannot be fully recovered, the algorithm counts the number of remaining partial products and the number of unresolved pins in each column, and represents the number of remaining partial products in the i-th column as RP. i , where is the number of partially product signals not processed by the existing adders, and the number of unresolved pins in the i-th column is represented as UP. i , where is the number of adder inputs that need to be reconnected.

[0022] Preferably, the second stage includes the following three sub-stages:

[0023] Sub-phase 1: Using the partial adder tree obtained in the first phase as input, without considering the specific connection details, allocate the optimal number of adders to each column of the multiplier to minimize the total number of adders. This outputs the number of adders allocated to each column of the multiplier in sub-phase 2.

[0024] Sub-phase two: Taking the number of adders allocated to each column of the multiplier obtained in sub-phase one as input, the large-scale connection design problem of all columns of the multiplier is decomposed into several relatively small-scale independent sub-problems. All columns of the multiplier are divided into several mutually independent column groups. The columns in each column group can be independently designed for microarchitecture, and there is no carry dependency between any two column groups.

[0025] Sub-phase three: Using the column set obtained in sub-phase three and the partial adder tree obtained in the first phase as input, the quantum-inspired ant colony optimization algorithm is used to find the optimal connection scheme for each adder while ensuring logical correctness, so as to obtain the complete reference multiplier architecture.

[0026] Preferably, for an N×N multiplier, sub-stage one includes the following steps:

[0027] Establish a complete ILP model with the objective function as follows:

[0028]

[0029] The set of constraints is as follows:

[0030]

[0031] The boundary condition is: no carry input in the initial column;

[0032] The optimal adder allocation scheme is obtained by solving the ILP model using a modern ILP solver. in:

[0033] The total number of additional adders allocated to the i-th column of the multiplier. The number of half-adders allocated to the i-th column of the multiplier. The number of full adders allocated to the i-th column of the multiplier;

[0034] This represents the number of remaining products in the i-th column of the multiplier;

[0035] This represents the number of unresolved pins in the i-th column of the multiplier;

[0036] The final output count of the i-th column of the multiplier;

[0037] Assign the result to all adders from column 0 to column 2N-1 of the multiplier.

[0038] Preferably, sub-stage two includes the following steps:

[0039] Natural grouping based on adder allocation pattern ensures no carry dependency between column groups, specifically including the following steps:

[0040] Let column group set G be empty set, and the current column group G curr It is an empty set, and the column index i is 0;

[0041] Iterate through each column of the multiplier, and for any i-th column, perform the following operation:

[0042] Case 1: If the number of adders in the i-th column is... If the value is greater than 0, then add column i to the current column group G. curr middle;

[0043] Case 2: If the number of adders in the i-th column is... If the value is 0, then further judgment is needed:

[0044] Sub-case 1: If the current column group G curr If it is not empty, first add column i to the current column group G. curr Then G curr Add to column group set G, then reset the current column group G. curr Empty;

[0045] Sub-case 2: If the current column group G curr If it is empty, then directly add the set of single elements containing column i to the column group set G;

[0046] For column groups in the column group set G that exceed a preset threshold T, further decomposition is performed, setting the micro-batch size to B, and processing each column group G in the column group set G. j Perform the following operations:

[0047] If column group G j If the size is greater than or equal to the threshold T, then the column group G will be... jThe data is decomposed into several micro-batches. The number of micro-batches is equal to the rounded-up result of dividing the column group size by the micro-batch size B. Each micro-batch is denoted as G. j The k-th subgroup, where the k-th microbatch The definition is as follows:

[0048] If k is less than the total number of micro-batches, then the kth micro-batch contains all columns starting from the (k-1)×B+1th position and ending at the k×Bth position;

[0049] If k equals the total number of microbatches, then the kth microbatch contains items from (k-1)×B+1 to column group G. j All columns ending at the last position;

[0050] The final output column set G is the scheduling result, containing several column sets G1, G2, ..., G m , where each G i They are all independent, processable column groups.

[0051] Preferably, sub-stage three includes the following steps:

[0052] For each column group G that belongs to the set of column groups G j Constructing Directed Graph CG j This is a directed graph CG j From the set of nodes V j The set of edges E j composition;

[0053] The CG of each directed graph is calculated using a quantum-inspired ant colony optimization algorithm. j The optimal solution;

[0054] The optimal solutions of the directed graphs corresponding to all column groups are integrated into a complete reference multiplier architecture, and synthesizable reference multiplier code is generated based on the complete reference multiplier architecture.

[0055] Preferably, the node set V j R is the set of the remaining partial product nodes. j Adder node set A j Unresolved pin node set U j Output node set O j Virtual node set and the carry node set C j The union of, where:

[0056] The set of remaining partial product nodes R j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0057] Adder node set A j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0058] Unresolved pin node set U j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0059] Output node set O j : Includes all forms such as The nodes, where column i belongs to column group G. j ;

[0060] Virtual node set Includes all forms such as The nodes, where column i belongs to column group G. j and Greater than 0;

[0061] Carry node set C j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0062] The edge set E j Define all possible connection relationships, E j Equal to the set of inner edges of the column With column edge set The union of the columns, where the set of inner edges is... The set of inter-column edges represents the probability of connections between nodes within the same column. Indicates the possibility of connections between nodes across columns.

[0063] Preferably, the quantum-inspired ant colony optimization algorithm calculates the current directed graph CG using the following steps. j The optimal solution:

[0064] Step 1: For directed graph CG j Each edge in the set E belongs to the edge set. j Edge e undergoes the following initialization operation:

[0065] Pheromone initialization: Set the pheromone value of edge e at the 0th iteration. Set to 1;

[0066] Quantum bit initialization: For each ant k, initialize the quantum state corresponding to edge e. Set as an equal-weight superposition of states 0 and 1

[0067] Step 2: Each ant k constructs solution S through a probabilistic selection mechanism. k ,in:

[0068] For the node set V j In node v, select M v The fan-shaped edge, where M v The value is determined based on the node type:

[0069] If node v is a virtual node Then M v Equal to the number of full adders in the i-th column

[0070] If node v belongs to the set of unresolved pin nodes U j Output node set O j Or the carry node set C j If any one of them is M, then M v It equals 1;

[0071] If node v belongs to the set of adder nodes A j And since the adder is a half-adder, then M v It equals 2;

[0072] If node v belongs to the set of adder nodes A j And since the adder is a full adder, then M v It equals 3;

[0073] In other cases, M v Equal to 0;

[0074] The edge selection probability follows the pheromone heuristic: for the j-th candidate fan-in edge e of node v j Its selection probability at the t-th iteration Equal to the pheromone value of that edge Divide by the sum of the pheromone values ​​of all optional fan-in edges of node v;

[0075] Step 3: Constructing the solution S k The following three mathematical constraints must be satisfied:

[0076] The first mathematical constraint—the flow conservation constraint: for the set of nodes V j For all nodes v, the out-degree minus the in-degree of node v must equal the supply value Supply(v) of that node, where Supply(v) is defined as follows:

[0077] If node v belongs to the set R of the residual partial product nodes j If , then Supply(v) equals 1;

[0078] If node v belongs to the set of unresolved pin nodes U j Or output node set O j If the expression is true, then Supply(v) equals -1;

[0079] If node v belongs to the set of adder nodes A j Or the carry node set C j If the expression is true, then Supply(v) equals 0;

[0080] If node v is a virtual node Then Supply(v) equals the number of full adders in the i-th column.

[0081] The second mathematical constraint—the uncombinable cycle constraint: Directed Graph (CG) j In solving S k Under the constraint that it must be a directed acyclic graph;

[0082] The third mathematical constraint—the soft-level constraint—minimizes the level difference penalty, the value of which is Penalty_level(S). k The calculation method is as follows: for the set A of all adder nodes j For node v in the array, calculate the sum of the absolute values ​​of the level differences between node v and all its fan-in nodes u;

[0083] Step 4, pheromone renewal and quantum evolution, wherein:

[0084] The pheromone update follows this rule: the pheromone value of edge e at the (t+1)th iteration. equal:

[0085] Subtract the evaporation rate ρ from 1, and multiply by the pheromone value of edge e at the t-th iteration. Add the sum of the contributions of all ants k from 1 to K, where:

[0086] The contribution of each ant k is equal to its qubit component. The square of the modulus, multiplied by the reciprocal of the fitness function, i.e., 1 divided by the fitness (S) of ant k. k );

[0087] The qubit evolves through a rotation gate: the state vector of the qubit with ant k on edge e at the (t+1)th iteration is equal to the product of a 2×2 rotation matrix and the state vector at the tth iteration. The first row of this 2×2 rotation matrix... Second line in, The rotation angle;

[0088] Step 5: The algorithm stops when any of the following conditions are met:

[0089] Condition 1: The current iteration number t is greater than or equal to the maximum iteration number T. max

[0090] Condition 2: Current optimal fitness best The value at the t-th iteration is equal to the value at the t-th iteration minus the stagnation threshold T. stag The value at the next iteration.

[0091] Preferably, in step 4, the fitness function Fitness(S) k ) is defined as:

[0092] If the solution is S k If both the first mathematical constraint and the second mathematical constraint are satisfied, then the fitness function is equal to the penalty value of the soft-level constraint, Penalty_level(S). k );

[0093] If the solution is S k If either the first or second mathematical constraint is not satisfied, the fitness function equals the large penalty constant M plus the violation count. count M is a large penalty constant.

[0094] Preferably, in step 4, the rotation angle The calculation formula is: the rotation step size Δθ multiplied by the result of the sign function, where the input parameters of the sign function are... and The product of these values, multiplied by a difference, is the fitness (S) of ant k. k Subtract the current best fitness best The difference, where the rotation step Δθ is equal to π divided by 400.

[0095] This invention proposes the RefSCAT-2.0 framework, a complete verification solution for large-scale logic-optimized multipliers. The core innovation of the RefSCAT-2.0 framework lies in its four-stage progressive verification strategy, transforming the traditional singular verification problem into four collaborative and progressively deepening processing stages. Each stage has clearly defined input / output interfaces and specific technical objectives. By organically combining advanced technologies such as reverse engineering, mathematical optimization, graph theory algorithms, and formal verification, it achieves efficient and reliable verification of large-scale optimized multipliers. Furthermore, this staged processing approach not only reduces the technical complexity of individual stages but, more importantly, achieves modularity and scalability in the verification process, providing a flexible technical path for handling multipliers of different sizes and complexities.

[0096] Compared with existing technical solutions, the present invention has the following beneficial effects:

[0097] The invention represents a significant breakthrough in verification capabilities, enabling the verification of all 124 cases in the 256-bit optimized multiplier benchmark suite, far surpassing existing methods (which can only solve 24 cases). The innovative three-stage decomposition strategy significantly reduces computational complexity, while the ILP algorithm optimizes resource allocation, multi-level scheduling balances computational load, and the QACO algorithm efficiently explores the design space. This makes the RefSCAT-2.0 framework provided by this invention the most effective solution for verifying large-scale logic-optimized multipliers to date. From a practical perspective, this invention fills the technological gap in verifying large-scale logic-optimized multipliers, providing crucial tool support for ensuring the reliability of critical computing systems such as AI chips, high-performance CPUs, and GPUs, and possesses significant industrial application value and economic benefits. Attached Figure Description

[0098] Figure 1 The complete verification process of the present invention is shown, including a partial adder tree recovery module, a reference multiplier generation module (including three sub-modules: ILP macroarchitecture generation, multi-level column scheduling, and QACO microarchitecture generation), an SCA verifier and a SAT verifier, as well as the data flow relationship between the modules.

[0099] Figure 2 The complete flow of the reference multiplier generation algorithm in RefSCAT-2.0 is demonstrated, including the collaborative relationship between the three main components (ILP macroarchitecture generation, multi-level column scheduling, and QACO microarchitecture generation);

[0100] Figure 3 The workflow of the multi-level column scheduler is demonstrated, including the operation process of two levels: column group scheduling and intra-group micro-batch scheduling.

[0101] Figure 4(a) in the diagram illustrates the six node types and their relationships in the column group diagram, including the residual product node, adder node, unresolved pin node, output node, virtual node, and carry node. Figure 4 (b) in the figure shows a detailed example of a column group diagram that includes both intra-column and inter-column edges. Figure 4 (c) in the diagram shows an example of an efficient connection solution that satisfies all constraints;

[0102] Figure 5 The detailed steps of the QACO microarchitecture generation algorithm are shown, including initialization, iterative optimization, and termination conditions. Detailed Implementation

[0103] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0104] This invention aims to address four major problems faced by existing technologies in handling large-scale optimized multipliers: scalability limitations, ambiguous component boundaries, low efficiency in reference multiplier generation, and lack of a unified framework, by developing an efficient reference multiplier generation algorithm, thereby achieving efficient verification of large-scale optimized multipliers.

[0105] To address this, this invention discloses a large-scale logic-optimized multiplier verification method, employing a four-stage pipelined processing mode of "recovery → architecture generation → functional verification → equivalence check". In the first stage, a structured adder tree is recovered from the optimized multiplier using reverse engineering techniques. In the second stage, a three-layer decomposition strategy is used to generate a reference multiplier with well-defined boundaries. In the third stage, symbolic computation algebra is used to verify the functional correctness of the reference multiplier. Finally, the logical equivalence between the optimized multiplier and the reference multiplier is checked using SAT solving techniques.

[0106] Phase 1: Partial Adder Tree Recovery

[0107] The macro-level goal of this stage is "structural reconstruction," which involves recovering meaningful arithmetic structure information from a deeply optimized, flat logic network. While logic optimization improves circuit performance, it also disrupts the original design hierarchy and module boundaries, making traditional verification methods difficult to apply. Through reverse engineering, this stage aims to re-identify and extract the basic building blocks of the multiplier, restoring its hierarchical adder tree structure to provide a structured design foundation for subsequent stages. This process does not require complete restoration of the original design, but rather the extraction of sufficient structural information to support the generation of a reference multiplier.

[0108] The first phase specifically includes the following steps:

[0109] Step 1, Atomic Block Detection and Identification:

[0110] A systematic approach using AIG cut enumeration is employed to extract potential sub-circuits of logic-optimized multipliers represented in AIG (And-Inverter Graph, a standard logic circuit representation format). The algorithm traverses all nodes in the AIG, calculating possible cut schemes for each node, with each cut defining the boundary of a sub-circuit.

[0111] The extracted sub-circuits are matched against a pre-built truth table library of atomic blocks, which contains standard representations of half-adders, full-adders, XOR gates, AND gates, and their various NPN (Negation-Permutation-Negation) equivalent variants. When the output vector of a cut combination exactly matches a truth table in the atomic block truth table library, the combination is identified as the corresponding atomic block (referring to basic logic components such as half-adders, full-adders, XOR gates, and AND gates).

[0112] In step 1, the logic-optimized multiplier undergoes complex optimization processes, including logic simplification, structural reorganization, and redundancy elimination. Its internal structure may differ significantly from the original design. The originally clear adder boundaries and hierarchical structure are blurred or eliminated during optimization, resulting in a flattened logic gate network. The AIG format provides a unified representation of two-input AND gates and inverters, facilitating subsequent structural analysis and component identification. The truth table is a table describing the input-output relationship of the logic function.

[0113] Step 2, PPG (Partial Product Generator, the first stage of the multiplier) structure restoration:

[0114] Identify the partial product generation stage of the logic-optimized multiplier, which mainly consists of AND gates. Recover any missing AND gates based on the input bit width and structural characteristics of the logic-optimized multiplier to ensure the integrity of the PPG structure.

[0115] Step 3, PPA adder tree reconstruction:

[0116] A systematic algorithm based on Breadth-First Search (BFS) is employed to reconstruct the adder tree structure in the Partial Product Accumulator (PPA), the second stage of the multiplier. The algorithm starts with adders at lower levels (close to the PPG output) and expands layer by layer to higher levels, automatically identifying valid adder connections. This process does not require prior knowledge of the specific PPA architecture type (such as a Wallace tree or Dadda tree); instead, it automatically infers the connection pattern by analyzing the data flow and constraints.

[0117] Step 4: Statistics on incomplete structures:

[0118] For the parts that cannot be fully recovered, the algorithm counts the number RP of the remaining partial products of each column. i and the number of unresolved pins UP i , among which, RP i UP represents the number of remaining partial products in the i-th column, and UP represents the number of partial product signals not processed by the existing adders. i The column represents the number of unresolved pins in the i-th column, and the column represents the number of adder inputs that need to be reconnected. These statistics reflect the impact of logic optimization on the original structure, providing important constraints and design guidance for subsequent reference multiplier generation.

[0119] Phase Two: Architecture Generation

[0120] Using the partial adder tree obtained in the first stage as input data, a complete reference multiplier is generated through three sub-stages.

[0121] Sub-phase 1: ILP Basic Macro Architecture Generation Phase

[0122] This sub-stage takes the partial adder tree obtained in the first stage as input to obtain the number of adders allocated to each column of the multiplier. Specifically, for the i-th column of the multiplier (i ranges from 0 to 2N-1, where N is the input bit width of the multiplier; for an N×N multiplier, there are a total of 2N columns to process), it determines how many additional adders are needed to complete the partial product compression. The macro-level goal is to determine the "skeleton" of the reference multiplier architecture through mathematical optimization methods. That is, without considering specific connection details, it allocates the optimal number of adders to each column to minimize the total number of adders, thus laying the foundation for subsequent detailed connection design. The tree structure of the partial adder tree contains key information extracted from the partial adder tree recovery stage, specifically including the remaining partial product count RP for each column. i and the number of unresolved pins UP i .

[0123] Sub-phase one specifically includes the following steps:

[0124] Step 101, Problem Modeling

[0125] set up The number of additional adders allocated to the i-th column (decision variable), where:

[0126]

[0127] In the formula: The total number of additional adders allocated to the i-th column is the main decision variable for this stage;

[0128] The number of half-adders allocated to the i-th column, each half-adder having 2 inputs, 1 carry output, and 1 carry output;

[0129] The number of full adders allocated to the i-th column, where each full adder has 3 inputs, 1 carry-out, and 1 output.

[0130] Step 102: Constraint Construction

[0131] Based on the fundamental principle of partial product compression in multipliers, each column must satisfy the input-output balance constraint.

[0132] For the i-th column of the multiplier, the input sources include:

[0133] The remaining product of the current column: indivual;

[0134] Carry from the previous column: indivual;

[0135] Total number of inputs:

[0136] in, The remaining partial product count in column i represents the number of partial product signals that still need to be processed after partial adder tree recovery.

[0137] For the i-th column of the multiplier, the output and cost include:

[0138] Half-adder overhead: Each half-adder consumes 2 inputs to produce 1 output, with a net overhead of... indivual;

[0139] Full adder overhead: Each full adder consumes 3 inputs to produce 1 output, net overhead is... indivual;

[0140] Unresolved pin consumption: indivual;

[0141] Column output: indivual;

[0142] in: The number of unresolved pins in the i-th column represents the number of adder inputs that need to be reconnected after partial adder tree recovery. The final output quantity of the i-th column is fixed at 1 to ensure that each column ultimately produces only one output signal.

[0143] Therefore, the equilibrium constraint equations are:

[0144]

[0145] Step 103: Linear Constraint Transformation and Mathematical Transformation

[0146] The above nonlinear constraints are transformed into a form that can be handled by linear programming. Because... and Two linear inequalities are obtained through mathematical transformations:

[0147] set up Then we have:

[0148]

[0149] The first inequality ensures that the number of adders allocated does not exceed the net number of inputs, and the second inequality ensures that there exists a feasible combination of half-adders / full adders to satisfy the constraints.

[0150] Step 104: Constructing the Integer Linear Programming Model:

[0151] Establish a complete ILP model with the objective function of minimizing the total number of multipliers and adders:

[0152]

[0153] Set of constraints:

[0154]

[0155] Boundary conditions: (Initial column has no carry input). Solve the model using a modern ILP solver (such as Google OR-Tools) to obtain the optimal adder allocation scheme.

[0156] Sub-phase two: Multi-level train scheduling phase

[0157] This sub-phase takes the number of adders allocated to each column of the multipliers output from sub-phase one as input. The macro-level goal is to solve a "divide and conquer" scheduling problem, decomposing the large-scale join design problem of 2N columns into multiple relatively small-scale independent subproblems. Through a clever grouping strategy, it ensures both the independence between groups (avoiding design complexity caused by carry dependencies) and controls the size of each group (ensuring the computational feasibility of microarchitecture generation), thereby significantly reducing the overall computational complexity and obtaining a set G of partitioned column groups, containing m mutually independent column groups {G1, G2, ..., G...}. m Each column group has columns with similar characteristics, allowing for independent microarchitectural design, while there are no carry dependencies between groups, thus supporting parallel processing.

[0158] Sub-phase two specifically includes the following steps:

[0159] Step 201, Column Group Scheduler (First-Level Scheduler):

[0160] Natural grouping based on adder allocation pattern ensures no carry dependency between column groups, specifically including the following steps:

[0161] Step 201-1, Initialization Phase: Set the column group set G to an empty set, and the current column group G... curr It is an empty set, and the column index i is 0;

[0162] Step 201-2, Loop Processing Phase: When i is less than 2N, perform the following operations:

[0163] Case 1: If the number of adders in the i-th column is... If the value is greater than 0, then add column i to the current column group G. curr middle;

[0164] Case 2: If the number of adders in the i-th column is... If the value is 0, then further judgment is needed:

[0165] Sub-case 1: If the current column group G curr If it is not empty, first add column i to the current column group G. curr Then G curr Add to column group set G, then reset the current column group G. curr empty

[0166] Sub-case 2: If the current column group G curr If the set is empty, the single-element set containing column i is directly added to the column group set G.

[0167] This strategy utilizes the number of adders Columns equal to 0 are used as natural partition points because these columns do not generate carry outputs, thus ensuring the independence between column groups. Mathematically, this is expressed as: for any two distinct column groups G...p and G q (All belong to the column group set G), for G p Any column i and G in q There is no carry dependency for any column j in the array.

[0168] Step 202, Intra-group micro-batch scheduler (second-level scheduling):

[0169] Large column groups exceeding a preset threshold T are further decomposed to balance computational complexity. The micro-batch size is set to B, and each column group G in the column group set G is processed... j Perform the following operations:

[0170] If column group G j If the size (i.e., the number of columns it contains) is greater than or equal to the threshold T, then the column group G is... j The data is decomposed into several micro-batches. The number of micro-batches is equal to the rounded-up result of dividing the column group size by the micro-batch size B. Each micro-batch is denoted as G. j The k-th subgroup, where the k-th microbatch The definition is as follows:

[0171] Case 1: If k is less than the total number of micro-batches, then the k-th micro-batch contains all columns starting from the (k-1)×B+1-th position and ending at the k×B-th position.

[0172] Case 2: If k equals the total number of micro-batches (i.e., the last micro-batch), then the k-th micro-batch contains items from (k-1)×B+1 to column group G. j All columns ending at the last position;

[0173] The final output scheduling result G contains several column groups G1, G2, ..., G m , where each G i They are all independent, processable column groups.

[0174] Sub-phase 3: QACO Basic Microarchitecture Generation Phase

[0175] The inputs to this sub-stage include: the column set G output from sub-stage two, where each column set G can be independently designed for microarchitecture; and detailed information about a portion of the adder tree, including structured information such as the remaining partial product of each column, the specific location of unresolved pins, and connection requirements. The macroscopic goal is to solve the design problem of "precise connection": after determining "how many adders to place" and "how to group them" in the first two stages, this stage aims to solve the complex combinatorial optimization problem of "how each adder is specifically connected." This problem is essentially a large-scale graph theory optimization problem, requiring the search for the optimal connection scheme while ensuring logical correctness. To this end, this invention introduces a quantum-inspired ant colony optimization algorithm. By simulating the parallelism of quantum computing and the heuristic search capability of the ant colony algorithm, it efficiently explores the vast design space and outputs a complete reference multiplier architecture. This architecture specifies in detail the type (half-adder or full adder), location, and precise connection relationship of each adder with other components, forming a functionally complete and structurally clear multiplier design.

[0176] Sub-phase three specifically includes the following steps:

[0177] Step 301: Constructing and Mathematically Representing the Column Group Diagram:

[0178] For each column group G that belongs to the set of column groups G j Constructing Directed Graph CG j This is a directed graph CG j From the set of nodes V j The set of edges E j Composition, represented as CG j Equal to (V) j E j ).

[0179] Node set V j It includes six types, namely V j Equal to the set of residual product nodes R j Adder node set A j Unresolved pin node set U j Output node set O j Virtual node set and the carry node set C j Union of:

[0180] The set of remaining partial product nodes R j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0181] Adder node set A j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0182] Unresolved pin node set U j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0183] Output node set O j : Includes all forms such as The nodes, where column i belongs to column group G. j ;

[0184] Virtual node set Includes all forms such as The nodes, where column i belongs to column group G. j and Greater than 0;

[0185] Carry node set C j : Includes all forms such as The nodes, where column i belongs to column group G. j The node index k ranges from 0 to...

[0186] Edge set E j Define all possible connection relationships, E j Equal to the set of inner edges of the column With column edge set The union of the columns, where the set of inner edges is... The set of inter-column edges represents the probability of connections between nodes within the same column. Indicates the possibility of connections between nodes across columns.

[0187] Step 302, Quantum-Inspired Ant Colony Optimization Algorithm (QACO), specifically includes the following steps:

[0188] Step 302-1, Initialization Phase:

[0189] For directed graph CG j Each edge in the set E belongs to the edge set. j Edge e undergoes the following initialization operation:

[0190] Pheromone initialization: Set the pheromone value of edge e at the 0th iteration. Set to 1;

[0191] Quantum bit initialization: For each ant k (k ranges from 1 to K), initialize the quantum state corresponding to edge e. Set as an equal-weight superposition of states 0 and 1 Specifically, the two components of a qubit and All equal to Satisfy the normalization condition: squared plus The square of is equal to 1, where and Let be the qubit component of the k-th ant on edge e, used for quantum-inspired search.

[0192] Step 302-2, Deconstruction process:

[0193] Each ant k constructs solution S through a probability selection mechanism. k For the node set V j For node v in the selection, M needs to be chosen. v The fan-shaped edge, where M v The value is determined based on the node type:

[0194] Scenario 1: If node v is a virtual node Then M v Equal to the number of full adders in the i-th column

[0195] Scenario 2: If node v belongs to the set of unresolved pin nodes U j Output node set O j Or the carry node set C j If any one of them is M, then M v It equals 1;

[0196] Case 3: If node v belongs to the adder node set A j And since the adder is a half-adder, then M v It equals 2;

[0197] Case 4: If node v belongs to the adder node set A j And since the adder is a full adder, then M v It equals 3;

[0198] Case 5: In other cases, M v Equal to 0;

[0199] The edge selection probability follows the pheromone heuristic: for the j-th candidate fan-in edge e of node v j Its selection probability at the t-th iteration Equal to the pheromone value of that edge Divide by the sum of the pheromone values ​​of all optional fan-in edges of node v (excluding edges in the taboo list).

[0200] Step 302-3, Solution evaluation and constraint check:

[0201] The constructed solution S k Three mathematical constraints must be satisfied:

[0202] The first mathematical constraint—the flow conservation constraint: for the set of nodes V j For all nodes v, the out-degree minus the in-degree of node v must equal the supply value Supply(v) of that node, where Supply(v) is defined as follows:

[0203] Case 1: If node v belongs to the set R of the residual partial product nodes j If , then Supply(v) equals 1;

[0204] Scenario 2: If node v belongs to the set of unresolved pin nodes U j Or output node set O j If the expression is true, then Supply(v) equals -1;

[0205] Case 3: If node v belongs to the adder node set A j Or the carry node set C j If the expression is true, then Supply(v) equals 0;

[0206] Case 4: If node v is a virtual node Then Supply(v) equals the number of full adders in the i-th column.

[0207] The second mathematical constraint—the uncombinable cycle constraint: Directed Graph (CG) j In solving S k Under the constraint that it must be a directed acyclic graph (DAG), that is, there is no directed path that starts from any node and returns to that node.

[0208] The third mathematical constraint—the soft-level constraint—minimizes the level difference penalty, the value of which is Penalty_level(S). k The calculation method is as follows: for the set A of all adder nodes j For node v, calculate the sum of the absolute values ​​of the level differences between node v and all its fan-in nodes u.

[0209] Step 302-4, Pheromone Update and Quantum Evolution:

[0210] The pheromone update follows this rule: the pheromone value of edge e at the (t+1)th iteration. equal:

[0211] Subtract the evaporation rate ρ from 1, and multiply by the pheromone value of edge e at the t-th iteration. Add the sum of the contributions of all ants k from 1 to K, where:

[0212] The contribution of each ant k is equal to its qubit component. The square of the modulus, multiplied by the reciprocal of the fitness function, i.e., 1 divided by the fitness (S) of ant k. k ), fitness function Fotness(S) k ) is defined as:

[0213] Case 1: If the solution S k If both the first and second mathematical constraints described above are satisfied, then the fitness function is equal to the penalty value of the soft-level constraint, Penalty_level(S). k );

[0214] Case 2: If the solution S k If either the first or second mathematical constraint described above is not satisfied, then the fitness function equals the large penalty constant M plus the violation count. count M is a large penalty constant used to ensure that the fitness value of the default solution is significantly higher than that of the feasible solution;

[0215] Evaporation rate ρ is the pheromone evaporation rate, used to control the degree of retention of historical information, and its value ranges from 0 to 1 in an open interval.

[0216] The qubit evolves through a rotation gate: the state vector of the qubit with ant k on edge e at the (t+1)th iteration is equal to the product of a 2×2 rotation matrix and the state vector at the tth iteration. The first row of this 2×2 rotation matrix... Second line in, The rotation angle is calculated as follows: the rotation step Δθ multiplied by the result of the sign function, where the input parameters of the sign function are... and The product of these values, multiplied by a difference, is the fitness (S) of ant k. k Subtract the current best fitness best The difference, where the rotation step Δθ is equal to π divided by 400.

[0217] Step 302-5, Convergence Judgment:

[0218] The algorithm termination condition is in the form of a logical OR: the algorithm stops when any of the following conditions are met:

[0219] Condition 1: The current iteration number t is greater than or equal to the maximum iteration number T. max

[0220] Condition 2: Current optimal fitnessbest The value at the t-th iteration is equal to the value at the t-th iteration minus the stagnation threshold T. stag The value at the next iteration indicates the algorithm's performance at time T. stag No better solution was found in the subsequent iterations, where T stag This is the threshold for determining when the algorithm stalls.

[0221] Step 303, Architecture Integration and Code Generation:

[0222] Integrate the optimal solutions of all column groups into a complete architecture: Let the complete reference multiplier architecture A be equal to all optimal solutions from the 1st column group to the mth column group. The union of the values. Finally, the complete reference multiplier architecture A is converted into Verilog hardware description language code, generating synthesizable reference multiplier code.

[0223] Phase 3: Functional Verification

[0224] This stage takes the complete reference multiplier architecture A generated in the second stage as input. The macro-level goal is to establish a mathematical proof of the reference multiplier's functional correctness, providing a reliable "gold standard" for subsequent equivalence verification. The SCA method, by converting the Boolean logic of the hardware circuit into a polynomial representation and using algebraic methods for formal verification, provides a mathematically rigorous guarantee of correctness. This step is crucial because only by ensuring the reference multiplier itself functions correctly can it serve as a reliable benchmark for verifying and optimizing the multiplier. The output of this stage is the functional correctness verification result of the reference multiplier, including a verification success flag, detailed verification logs, and possible error location information. If the verification is successful, it confirms that the reference multiplier is functionally equivalent to a standard N×N integer multiplication operation; if the verification fails, an error analysis report is provided to guide further corrections to the reference multiplier.

[0225] In this invention, the complete reference multiplier architecture A is represented in Verilog hardware description language, containing well-defined adder boundaries and a clear module hierarchy. The reference multiplier has good structured characteristics, where each adder component has well-defined input and output, facilitating polynomial modeling and verification analysis using symbolic computational algebra (SCA) methods.

[0226] Phase 4: Equivalence Check

[0227] The inputs for this stage are a reference multiplier verified as functionally correct by SCA and the original logic-optimized multiplier, both represented in AIG format. The macro-level objective is to verify the logical equivalence between the optimized multiplier and the reference multiplier using SAT solving technology, thereby confirming that the logic optimization process did not introduce functional errors. This verification employs a rigorous formal method, constructing a Boolean satisfaction problem for equivalence checking and solving it using a modern, efficient SAT solver. Compared to traditional simulation testing, SAT verification provides a completeness guarantee, meaning it can exhaustively check all possible input combinations. The output of this stage is the logical equivalence verification result between the two multipliers, including an equivalence judgment (equivalent or inequivalent), statistical information of the verification process (solution time, memory usage, number of SAT solver calls, etc.), and possible counterexamples. If the verification result is equivalent, the optimized multiplier is confirmed to be functionally correct; if inequivalence is found, specific counterexample inputs are provided, indicating test vectors where the two multipliers produce different outputs.

[0228] In this invention, the reference multiplier has a clear structure and well-defined module boundaries, while the optimized multiplier has undergone complex logic optimization. Its internal structure may differ significantly from the original design, but it should remain functionally equivalent.

[0229] The aforementioned large-scale logic-optimized multiplier verification method was implemented in C++ and evaluated on an AMD Ryzen Threadripper 3970X processor with 48GB of memory, using single-threaded execution. Adder allocation used the ILP solver in Google OR-Tools 9.6. In the column grouping scheduling algorithm, a predefined threshold of 120 and a batch size of 8 were used. The QACO microarchitecture generation algorithm had a maximum of 20,000 iterations, a no-improvement wait period of 500 iterations, and an evaporation rate of 0.45. SCA verification was initially performed using Amulet 2.2, and RevSCA-2.0 was used if it failed. The SAT scan process used Kissat 3.0.0 as the SAT solver. The timeout (TO) and memory usage exceeding the system allocatable limit (MO) thresholds for all methods were set to 4000 seconds and 48GB, respectively. This invention has been comprehensively evaluated on multiple multiplier benchmark sets, with a focus on a 256-bit optimized multiplier benchmark suite containing 124 multiplier instances with varying degrees of logic optimization. In terms of verification capability, the method disclosed in this invention exhibits significant advantages. This invention successfully verified all 124 test instances with a 100% success rate, while existing SCA-based methods (RevSCA) and hybrid methods (RefSCAT) can only verify 24 instances with a success rate of only 19.4%. More importantly, this invention can handle multipliers up to 512 bits, while existing methods typically fail when handling multipliers exceeding 128 bits. This invention also demonstrates good adaptability to various multiplier architectures. Experimental results show that the method disclosed in this invention can effectively handle various common combinations of multiplier components, including different types of partial accumulator adders (Wallace tree, Dadda tree) and final-stage adders (carry-lookahead adders, ripple-carry adders). This broad applicability enables this invention to verify multiplier implementations with different design styles and optimization strategies. In summary, the experimental results fully demonstrate the effectiveness and superiority of this invention in handling the verification problem of large-scale logic-optimized multipliers, successfully overcoming the limitations of existing methods in large-scale multiplier verification, and providing a reliable tool for the design and verification of high-performance computing systems.

Claims

1. A method for verifying large-scale logic-optimized multipliers, characterized in that, A four-stage pipeline processing model is adopted. The first stage is the partial adder tree recovery stage, which uses reverse engineering techniques to recover meaningful arithmetic structure information from the optimized multiplier to obtain a structured adder tree. The second stage is the architecture generation stage, which uses the adder tree as input and a three-level decomposition strategy to generate a reference multiplier with clear boundaries. The third stage is the functional verification stage, which uses symbolic computation algebra methods to verify the functional correctness of the reference multiplier. The fourth stage is the equivalence checking stage, which uses SAT solving techniques to check the logical equivalence between the optimized multiplier and the reference multiplier.

2. The method for verifying a large-scale logic-optimized multiplier as described in claim 1, characterized in that, The first stage includes the following steps: The potential sub-circuits of logic-optimized multipliers represented in NAND-inverted phase diagram format are systematically extracted using the NAND-inverted phase diagram cutting enumeration technique. The extracted sub-circuits are matched with a pre-built atomic block truth table library. If the output vector of a cutting combination matches exactly a truth table in the atomic block truth table library, the current cutting combination is identified as the corresponding atomic block. Identify the partial product generation stage of the logic-optimized multiplier and recover any missing AND gates based on the input bit width and structural characteristics of the logic-optimized multiplier to ensure the integrity of the partial product generator structure. A breadth-first search-based algorithm is used to systematically reconstruct the adder tree structure in the partial accumulator; For parts that cannot be fully recovered, the algorithm counts the number of remaining partial products and the number of unresolved pins in each column, and represents the number of remaining partial products in the i-th column as RP. i , where is the number of partially product signals not processed by the existing adders, and the number of unresolved pins in the i-th column is represented as UP. i , where is the number of adder inputs that need to be reconnected.

3. The method for verifying a large-scale logic-optimized multiplier as described in claim 1, characterized in that, The second phase includes the following three sub-phases: Sub-phase 1: Using the partial adder tree obtained in the first phase as input, without considering the specific connection details, allocate the optimal number of adders to each column of the multiplier to minimize the total number of adders. This outputs the number of adders allocated to each column of the multiplier in sub-phase 2. Sub-phase two: Taking the number of adders allocated to each column of the multiplier obtained in sub-phase one as input, the large-scale connection design problem of all columns of the multiplier is decomposed into several relatively small-scale independent sub-problems. All columns of the multiplier are divided into several mutually independent column groups. The columns in each column group can be independently designed for microarchitecture, and there is no carry dependency between any two column groups. Sub-phase three: Using the column set obtained in sub-phase three and the partial adder tree obtained in the first phase as input, the quantum-inspired ant colony optimization algorithm is used to find the optimal connection scheme for each adder while ensuring logical correctness, so as to obtain the complete reference multiplier architecture.

4. The method for verifying a large-scale logic-optimized multiplier as described in claim 3, characterized in that, For an N×N multiplier, sub-phase one includes the following steps: Establish a complete ILP model with the objective function as follows: The set of constraints is as follows: The boundary condition is: no carry input in the initial column; The optimal adder allocation scheme is obtained by solving the ILP model using a modern ILP solver. in: The total number of additional adders allocated to the i-th column of the multiplier. The number of half-adders allocated to the i-th column of the multiplier. The number of full adders allocated to the i-th column of the multiplier; This represents the number of remaining products in the i-th column of the multiplier; This represents the number of unresolved pins in the i-th column of the multiplier; The final output count of the i-th column of the multiplier; Assign the result to all adders from column 0 to column 2N-1 of the multiplier.

5. The method for verifying a large-scale logic-optimized multiplier as described in claim 4, characterized in that, Sub-phase two includes the following steps: Natural grouping based on adder allocation pattern ensures no carry dependency between column groups, specifically including the following steps: Let column group set G be empty set, and the current column group G curr It is an empty set, and the column index i is 0; Iterate through each column of the multiplier, and for any i-th column, perform the following operation: Case 1: If the number of adders in the i-th column is... If the value is greater than 0, then add column i to the current column group G. curr middle; Case 2: If the number of adders in the i-th column is... If the value is 0, then further judgment is needed: Sub-case 1: If the current column group G curr If it is not empty, first add column i to the current column group G. curr Then G curr Add to column group set G, then reset the current column group G. curr Empty; Sub-case 2: If the current column group G curr If it is empty, then directly add the set of single elements containing column i to the column group set G; For column groups in the column group set G that exceed a preset threshold T, further decomposition is performed, setting the micro-batch size to B, and processing each column group G in the column group set G. j Perform the following operations: If column group G j If the size is greater than or equal to the threshold T, then the column group G will be... j The data is decomposed into several micro-batches. The number of micro-batches is equal to the rounded-up result of dividing the column group size by the micro-batch size B. Each micro-batch is denoted as G. j The k-th subgroup, where the k-th microbatch The definition is as follows: If k is less than the total number of micro-batches, then the kth micro-batch contains all columns starting from the (k-1)×B+1th position and ending at the k×Bth position; If k equals the total number of microbatches, then the kth microbatch contains items from (k-1)×B+1 to column group G. j All columns ending at the last position; The final output column set G is the scheduling result, containing several column sets G1, G2, ..., G m , where each G i They are all independent, processable column groups.

6. The method for verifying a large-scale logic-optimized multiplier as described in claim 5, characterized in that, Sub-phase three includes the following steps: For each column group G that belongs to the set of column groups G j Constructing Directed Graph CG j This is a directed graph CG j From the set of nodes V j The set of edges E j composition; The CG of each directed graph is calculated using a quantum-inspired ant colony optimization algorithm. j The optimal solution; The optimal solutions of the directed graphs corresponding to all column groups are integrated into a complete reference multiplier architecture, and synthesizable reference multiplier code is generated based on the complete reference multiplier architecture.

7. The method for verifying a large-scale logic-optimized multiplier as described in claim 6, characterized in that, The node set V j R is the set of the remaining partial product nodes. j Adder node set A j Unresolved pin node set U j Output node set O j Virtual node set and the carry node set C j The union of, where: The set of remaining partial product nodes R j : Includes all forms like The nodes, where column i belongs to column group G. j The node index k ranges from 0 to... Adder node set A j : Includes all forms like The nodes, where column i belongs to column group G. j The node index k ranges from 0 to... Unresolved pin node set U j : Includes all forms like The nodes, where column i belongs to column group G. j The node index k ranges from 0 to... Output node set O j : Includes all forms like The nodes, where column i belongs to column group G. j ; Virtual node set Includes all forms such as The nodes, where column i belongs to column group G. j and Greater than 0; Carry node set C j : Includes all forms like The nodes, where column i belongs to column group G. j The node index k ranges from 0 to... The edge set E j Define all possible connection relationships, E j Equal to the set of inner edges of the column With the set of columns The union of the columns, where the set of inner edges is... The set of inter-column edges represents the probability of connections between nodes within the same column. Indicates the possibility of connections between nodes across columns.

8. The method for verifying a large-scale logic-optimized multiplier as described in claim 7, characterized in that, The quantum-inspired ant colony optimization algorithm calculates the current directed graph CG using the following steps. j The optimal solution: Step 1: For directed graph CG j Each edge in the set E belongs to the edge set. j Edge e undergoes the following initialization operation: Pheromone initialization: Set the pheromone value of edge e at the 0th iteration. Set to 1; Quantum bit initialization: For each ant k, initialize the quantum state corresponding to edge e. Set as an equal-weight superposition of states 0 and 1 Step 2: Each ant k constructs solution S through a probabilistic selection mechanism. k ,in: For the node set V j In node v, select M v The fan-shaped edge, where M v The value is determined based on the node type: If node v is a virtual node Then M v Equal to the number of full adders in the i-th column If node v belongs to the set of unresolved pin nodes U j Output node set O j Or the carry node set C j If any one of them is M, then M v It equals 1; If node v belongs to the set of adder nodes A j And since the adder is a half-adder, then M v It equals 2; If node v belongs to the set of adder nodes A j And since the adder is a full adder, then M v It equals 3; In other cases, M v Equals 0; The edge selection probability follows the pheromone heuristic: for the j-th candidate fan-in edge e of node v j Its selection probability at the t-th iteration Equal to the pheromone value of that edge Divide by the sum of the pheromone values ​​of all optional fan-in edges of node v; Step 3: Constructing the solution S k The following three mathematical constraints must be satisfied: The first mathematical constraint—the flow conservation constraint: for the set of nodes V j For all nodes v, the out-degree minus the in-degree of node v must equal the supply value Supply(v) of that node, where Supply(v) is defined as follows: If node v belongs to the set R of the residual partial product nodes j If , then Supply(v) equals 1; If node v belongs to the set of unresolved pin nodes U j Or output node set O j If the expression is true, then Supply(v) equals -1; If node v belongs to the set of adder nodes A j Or the carry node set C j If the expression is true, then Supply(v) equals 0; If node v is a virtual node Then Supply(v) equals the number of full adders in the i-th column. The second mathematical constraint—the uncombinable cycle constraint: Directed Graph (CG) j In solving S k Under the constraint that it must be a directed acyclic graph; The third mathematical constraint—the soft-level constraint—minimizes the level difference penalty, the value of which is Penalty_leval(S). k The calculation method is as follows: for the set A of all adder nodes j For node v in the array, calculate the sum of the absolute values ​​of the level differences between node v and all its fan-in nodes u; Step 4, pheromone renewal and quantum evolution, wherein: The pheromone update follows this rule: the pheromone value of edge e at the (t+1)th iteration. equal: Subtract the evaporation rate ρ from 1, and multiply by the pheromone value of edge e at the t-th iteration. Add the sum of the contributions of all ants k from 1 to K, where: The contribution of each ant k is equal to its qubit component. The square of the modulus, multiplied by the reciprocal of the fitness function, i.e., 1 divided by the fitness (S) of ant k. k ); The qubit evolves through a rotation gate: the state vector of the qubit with ant k on edge e at the (t+1)th iteration is equal to the product of a 2×2 rotation matrix and the state vector at the tth iteration. The first row of this 2×2 rotation matrix... Second line in, The rotation angle; Step 5: The algorithm stops when any of the following conditions are met: Condition 1: The current iteration number t is greater than or equal to the maximum iteration number T. max Condition 2: Current optimal fitness best The value at the t-th iteration is equal to the value at the t-th iteration minus the stagnation threshold T. stag The value at the next iteration.

9. The method for verifying a large-scale logic-optimized multiplier as described in claim 8, characterized in that, In step 4, the fitness function Fitness(S) k ) is defined as: If the solution is S k If both the first mathematical constraint and the second mathematical constraint are satisfied, then the fitness function is equal to the penalty value of the soft-level constraint, Penalty_level(S). k ); If the solution is S k If either the first or second mathematical constraint is not satisfied, the fitness function equals the large penalty constant M plus the violation count. count M is a large penalty constant.

10. The method for verifying a large-scale logic-optimized multiplier as described in claim 8, characterized in that, In step 4, the rotation angle The calculation formula is: the rotation step size Δθ multiplied by the result of the sign function, where the input parameters of the sign function are... and The product of these values, multiplied by a difference, is the fitness (S) of ant k. k Subtract the current best fitness best The difference, where the rotation step Δθ is equal to π divided by 400.

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