Automatic layout method for radiation-proof standard units

Abstract

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit design automation, and particularly relates to an automatic layout method of anti-radiation standard cells. BACKGROUND

[0002] In special application scenarios such as aerospace, nuclear power, military and high-energy physics experiments, electronic devices are long-term exposed to high radiation environment, which are easily affected by space radiation, and pose a potential threat to the stability and reliability of circuits. In order to ensure the normal operation of circuits in complex radiation environment, designing anti-radiation integrated circuits becomes a key technical means, and anti-radiation standard cells play a core role in improving the anti-radiation capability of the entire chip.

[0003] A standard cell library is composed of pre-designed combinational logic, sequential logic cells and physical cells, and is the basis for the automatic design and implementation of digital chips. The layout design of a standard cell usually includes two key steps: transistor layout and routing. The quality of the layout has a profound impact on the subsequent routing. A reasonable layout can effectively reduce the pressure in the routing process, improve the routing efficiency and reduce the risk of routing conflicts. With the continuous evolution of process nodes and the continuous improvement of integration, a single standard cell library often contains thousands of cells, which greatly increases the workload and complexity of layout design. However, the layout design of anti-radiation standard cells still mainly relies on manual drawing, and faces such outstanding problems as long design cycle, low efficiency and insufficient number of cells, which is difficult to meet the urgent needs of rapid iteration of current anti-radiation chips.

[0004] From the design method, anti-radiation reinforcement generally includes two technical paths of layout level reinforcement and circuit structure level reinforcement. Layout reinforcement targets all cells, reduces the risk of total ionizing dose (TID) and single event latch-up (SEL) by increasing transistor size and adding well contact protection bands, among which the introduction of protection bands has the most significant impact on transistor layout. The active layer and metal layer of the protection band must meet the minimum DRC (Design Rule Check) distance between the surrounding MOS (Metal Oxide Semiconductor) device layers, and usually in order to ensure anti-radiation performance, a set of protection bands needs to be inserted at regular intervals. Structural reinforcement mainly targets sequential logic cells, and uses redundant latches, structural replacement or increases the distance between sensitive nodes to alleviate functional failure caused by single event effects (SEE).

[0005] Although the existing automatic layout method has developed in general standard cell design, it still has many limitations in the anti-radiation application scene. They lack modeling of anti-radiation physical mechanism and targeted optimization strategy, and it is difficult to realize the collaborative design of layout and protection requirements.

[0006] Therefore, the existing anti-radiation standard cell library automatic layout technology urgently needs a more efficient and more adaptive intelligent optimization method to cope with the actual needs of complex design constraints and rapid iteration in the radiation environment.

[0007] In recent years, reinforcement learning (RL) as a learning method based on the interaction between agents and the environment, through trial and error optimization strategy, has shown good prospects in complex fields such as layout optimization. Compared with traditional rule-based or heuristic algorithm methods, reinforcement learning has stronger adaptability and strategy generalization ability, and can complete complex action sequence decision-making without relying on templates, which is a powerful tool for solving anti-radiation layout automation problems. SUMMARY

[0008] The present application aims to provide an anti-radiation standard cell automatic layout method to solve the technical problem of low design efficiency of the existing anti-radiation standard cell layout design relying on manual design.

[0009] To solve the above technical problems, the specific technical scheme of an anti-radiation standard cell automatic layout method of the present application is as follows: An anti-radiation standard cell automatic layout method includes two reinforcement learning stages: the first stage trains a device layout strategy model to generate a preliminary device layout result; the second stage independently trains a guard band insertion strategy model based on the preliminary device layout result to meet anti-radiation design rules and reduce future wiring difficulty.

[0010] Further, the method includes the following steps: Step 1: First, parse the input CDL file, extract the type, size and electrical connection relationship of the MOS device, and construct a circuit diagram structure containing node features and connection relationships as a state representation for reinforcement learning environment modeling, Step 2: First stage: device layout strategy training; In the first stage, the action space is composed of device placement coordinates, device numbers and flip states. Each action contains a triple: device number, coordinate and flip flag. The flip operation means that the source and drain of the MOS tube are interchanged, which can adjust the pin direction without changing the function of the device. The layout strategy automatically masks illegal placement behavior through a dynamic action mask mechanism, and explores the influence of different flip combinations on the overall layout quality during the sampling process; Step 3: Second stage: guard band insertion strategy training; The action space of the second stage is a candidate insertion point set, the action represents the selection of the guard band insertion position and the insertion order in a specific area, the guard band insertion strategy simulates the comprehensive influence of inserting the guard band on the HPWL, DRC constraint and wire density when the action is executed, adjusts the strategy preference through the reward function, and generates an insertion scheme with the minimum layout disturbance and the optimal cost.

[0011] Further, the two stages respectively optimize the strategy in the respective state space and action space, and both stages use the Maskable PPO algorithm, and the reward function is set according to artificial design experience.

[0012] Further, the step 2 comprises the following steps: Step 2.1: reading a CDL file and design rules, analyzing device types, sizes and connection relationships, and constructing a graph structure; Step 2.2: initializing a layout reinforcement learning environment, including a state space, an action space, a reward function and an action mask; Step 2.3: generating an action mask according to the current state, which is used to shield illegal placement behavior; Step 2.4: sampling an action and executing device placement, and recording the flipped state and coordinates; Step 2.5: calculating a reward value, encouraging the alignment of the upper and lower gates, the alignment of the adjacent source and drain, and the shortest connection path, and punishing layout conflicts; Step 2.6: updating a layout strategy network model.

[0013] Step 2.7: if the layout is not completed, returning to step 2.3; otherwise, entering the second stage.

[0014] Further, the step 3 comprises the following steps: Step 3.1: initializing a second-stage reinforcement learning environment, and loading the first-stage layout result; Step 3.2: extracting a candidate insertion point set according to the existing device distribution and design rules; Step 3.3: generating an action mask and sampling a guard band insertion action; Step 3.4: calculating a reward, including HPWL increase, DRC violation risk and wire density influence; Step 3.5: updating a guard band insertion strategy model; Step 3.6: if the guard band distance constraint is not satisfied, returning to step 10; otherwise, outputting a final layout result.

[0015] The anti-radiation standard cell automatic layout method has the following advantages: the device layout and the protection band insertion task are divided and cooperated by the two-stage reinforcement learning structure, the optimization targets are decoupled, the training interference is avoided, and the adaptability of the insertion band strategy to the generated layout is improved. Finally, the system can automatically output a high-quality layout result containing device position, flip flag and protection band insertion information according to the input CDL file, significantly improve the layout efficiency and design compliance of the anti-radiation standard cell, and have good engineering practicability and universality. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is an anti-radiation standard cell layout schematic diagram. Figure 2 It is an anti-radiation standard cell automatic layout process. DETAILED DESCRIPTION

[0017] In order to better understand the purpose, structure and function of the present application, the anti-radiation standard cell automatic layout method will be further described in detail below in combination with the drawings.

[0018] The anti-radiation standard cell layout schematic diagram is shown in Figure 1, wherein the red area is the active layer and the blue area is the Poly (polysilicon) layer. The layout position of the MOS tube is marked in the figure, and the protection band (marked in green) for radiation protection is also marked. The spacing required by the design rules is also marked in the figure, including the spacing between the active layers and the spacing between the Poly layer and the active layer of the protection band. These spacings must meet the layout design rules.

[0019] As shown in Figure 1, the anti-radiation standard cell automatic layout method of the present application includes two reinforcement learning stages: the first stage trains the device layout strategy model to generate a preliminary device layout result; the second stage independently trains the protection band insertion strategy model based on the preliminary device layout result to meet the anti-radiation design rules and reduce the future wiring difficulty. Figure 2

[0020] Specifically, the steps include: Step 1: First, parse the input CDL (Circuit Description Language) file, extract the type, size and electrical connection relationship of the MOS device, build a circuit diagram structure containing node features and connection relationship as a state representation for reinforcement learning environment modeling. The two stages optimize the strategy in their respective state space and action space, and both stages use Maskable PPO algorithm, and set the reward function according to the artificial design experience.

[0021] Step 2: First stage: device layout strategy training; ​In the first phase, the action space consists of device placement coordinates, device number, and flip state. Each action contains a triplet (device number, coordinates, flip flag). A flip operation refers to the interchange of the source and drain of a MOSFET, which can adjust the pin orientation without changing the device's function, thereby shortening the HPWL (Half-Perimeter Wirelength, used to evaluate chip layout), reducing the overall width of standard cells, or improving local congestion. The layout strategy automatically masks illegal placement behavior through a dynamic action masking mechanism and explores the impact of different flip combinations on the overall layout quality during sampling.

[0022] Step 2.1: Read the CDL file and design rules, parse the device types, dimensions and connection relationships, and construct the graph structure.

[0023] Step 2.2: Initialize the layout reinforcement learning environment, including the state space, action space, reward function, and action mask.

[0024] Step 2.3: Generate an action mask based on the current state to block illegal placement behavior.

[0025] Step 2.4: Sample the device and place it, recording the flip state and coordinates.

[0026] Step 2.5: Calculate the reward value to encourage gate top-bottom alignment, source-drain proximity alignment, and connection of the shortest path, and to penalize layout conflicts.

[0027] Step 2.6: Update the layout strategy network model.

[0028] Step 2.7: If the layout is not complete, return to step 2.3; otherwise, proceed to the second stage.

[0029] Step 3: Second Phase: Training on Protective Tape Insertion Strategy; The action space in the second stage is a set of candidate insertion points. The action represents selecting the insertion position and order of the guard strip in a specific area. When executing the action, the guard strip insertion strategy simulates the combined impact of inserting the guard strip on HPWL, DRC constraints, and connection density. The strategy preference is adjusted through a reward function to generate the insertion scheme with the minimum layout disturbance and optimal cost.

[0030] Step 3.1: Initialize the second-stage reinforcement learning environment and load the layout results from the first stage.

[0031] Step 3.2: Extract the set of candidate insertion points based on the existing device distribution and design rules.

[0032] Step 3.3: Generate an action mask and sample interpolated actions.

[0033] Step 3.4: Calculate the reward, including HPWL increase, DRC violation risk, and wire density impact.

[0034] Step 3.5: Update the guard band strategy model.

[0035] Step 3.6: If the guard band distance constraint is not met, return to step 10; otherwise, output the final layout result.

[0036] The present application can automatically avoid illegal actions, reasonably control the guard band distance, effectively reduce the complexity of manual design, improve the layout generation efficiency of the anti-radiation standard cell library, and is suitable for complex anti-radiation design scenarios, and has good engineering application value and promotion prospect.

[0037] It can be understood that the present application is described through some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to these features and embodiments without departing from the spirit and scope of the present application. In addition, under the guidance of the present application, these features and embodiments can be modified to adapt to specific conditions and materials without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.

Claims

1. A method for automatic layout of radiation-resistant standard cells, characterized in that, It includes two reinforcement learning phases: the first phase trains the device placement strategy model to generate preliminary device placement results; the second phase independently trains the guard band insertion strategy model based on this to meet radiation resistance design rules and reduce future wiring difficulty.

2. The automatic layout method for radiation-resistant standard cells according to claim 1, characterized in that, The method includes the following steps: Step 1: First, parse the input CDL file to extract the type, size, and electrical connections of the MOS devices. Construct a circuit diagram structure containing node features and connection relationships as a state representation for reinforcement learning environment modeling. Step 2: First stage: Component placement strategy training; In the first stage, the action space consists of device placement coordinates, device number, and flip state. Each action contains a triplet: device number, coordinates, and flip flag. The flip operation refers to the interchange of the source and drain of the MOSFET. The pin direction can be adjusted without changing the device function. The layout strategy automatically shields illegal placement behavior through a dynamic action mask mechanism and explores the impact of different flip combinations on the overall layout quality during the sampling process. Step 3: Second Phase: Training on Protective Tape Insertion Strategy; The action space in the second stage is a set of candidate insertion points. The action represents the selection of the guard strip insertion position and insertion order in a specific area. When the insertion strategy executes the action, it simulates the comprehensive impact of inserting the guard strip on HPWL, DRC constraints and connection density. The strategy preference is adjusted through the reward function to generate the insertion scheme with the minimum layout disturbance and the optimal cost.

3. The automatic layout method for radiation-resistant standard cells according to claim 1, characterized in that, The two stages perform policy optimization in their respective state and action spaces. Both stages use the Maskable PPO algorithm, and the reward function is set based on human design experience.

4. The automatic layout method for radiation-resistant standard cells according to claim 1, characterized in that, Step 2 includes the following steps: Step 2.1: Read the CDL file and design rules, parse the device types, dimensions and connection relationships, and construct the graph structure; Step 2.2: Initialize the layout reinforcement learning environment, including the state space, action space, reward function, and action mask; Step 2.3: Generate an action mask based on the current state to block illegal placement behavior; Step 2.4: Perform sampling and device placement, and record the flipping state and coordinates; Step 2.5: Calculate the reward value to encourage gate top-bottom alignment, source-drain proximity alignment, and connection of the shortest path, and to penalize layout conflicts; Step 2.6: Update the layout strategy network model; Step 2.7: If the layout is not complete, return to step 2.3; otherwise, proceed to the second stage.

5. The automatic layout method for radiation-resistant standard cells according to claim 1, characterized in that, Step 3 includes the following steps: Step 3.1: Initialize the second-stage reinforcement learning environment and load the layout results from the first stage; Step 3.2: Extract the set of candidate insertion points based on the existing device distribution and design rules; Step 3.3: Generate an action mask and sample interpolation actions; Step 3.4: Calculate the rewards, including HPWL increase, DRC violation risk, and the impact of connection density; Step 3.5: Update the insertion strategy model; Step 3.6: If the protection zone distance constraint is not met, return to step 10; otherwise, output the final layout result.

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