Wafer processing method and wafer

Abstract

The invention provides a wafer processing method and a wafer, and the processing method comprises the steps: S1, carrying out the rough machining of the edge of a to-be-processed first wafer, and enabling a first chamfering part and a second chamfering part to be in an asymmetric chamfering shape; s2, the surface of the first chamfering part, the surface of the second chamfering part and the surface of the transition chamfering part are polished according to preset polishing parameters; s3, the extension direction of the positioning edge is detected in real time, the preset polishing parameters are adjusted based on the extension direction of the positioning edge, and the step S2 is executed again till a target wafer is obtained; wherein the included angle formed by the extending direction of the positioning edge of the target wafer and the crystal orientation of the target wafer is smaller than or equal to 0.01 degree, and the roughness of the first chamfer part, the second chamfer part and the transition chamfer part of the target wafer is smaller than or equal to 1 nm. By adopting the wafer processing method provided by the invention, the angular deviation of the positioning edge is reduced, and the product quality is improved.

Description

Technical Field

[0001] This invention relates to the field of wafer edge processing technology, and more particularly to a wafer processing method and a wafer. Background Technology

[0002] In the field of semiconductor wafer fabrication, the wafer flat is a straight section on the outer edge of the wafer. It is used to mark the wafer's crystal orientation, providing a precise alignment reference for subsequent critical processes such as photolithography, etching, and dicing, ensuring positioning accuracy during wafer fabrication. The chamfered structure formed by the flat is not only an important morphological feature of the wafer edge, but also plays a crucial role in the wafer's mechanical strength, surface cleanliness, and adaptability to subsequent automated processing, making it a key element in ensuring the overall quality of the wafer.

[0003] However, traditional wafer positioning edge chamfering and its processing technology generally use a single T-shaped chamfer or R-shaped chamfer, which has the following defects.

[0004] First, the wafer positioning edge direction of traditional processing deviates significantly from the wafer's crystal orientation angle, typically around ±0.1°. This leads to alignment errors between the wafer and the processing equipment during high-precision alignment processes such as photolithography, resulting in uneven etching and reduced cleavage surface flatness (e.g., the laser resonator surface becomes rough due to alignment deviation).

[0005] Secondly, the inconsistency in the width of the chamfer surface causes errors in the automated processing equipment when identifying the crystal orientation of the wafer, which ultimately affects the accuracy of wafer cutting and reduces the yield of finished products.

[0006] In addition, traditional processes can easily generate mechanical stress at the wafer edge, leading to microcracks and reducing the wafer's mechanical strength. At the same time, traditional processes cannot achieve high-precision smoothing of the wafer edge. The rough edge surface not only easily adsorbs particulate contaminants, but also causes stress concentration, further increasing the risk of wafer breakage during subsequent processing or use.

[0007] It should be noted that the above description of the background technology is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of the present invention. Summary of the Invention

[0008] The purpose of this invention is to disclose a wafer processing method and a wafer, which can solve the aforementioned technical problems, reduce the positioning edge angle deviation, improve the alignment accuracy of the wafer in processes such as photolithography, ensure the smoothness of the etched surface and cleavage surface, improve the consistency of the chamfer area, eliminate equipment recognition errors, improve cutting accuracy, and improve the mechanical strength of the wafer edge, avoiding microcracks and particle adsorption.

[0009] To achieve the above objectives, in a first aspect, the present invention provides a wafer processing method, comprising the following steps:

[0010] S1. Roughly process the edge of the first wafer to be processed to form a second wafer having a first chamfer, a second chamfer, and a transition chamfer; wherein, one side edge of the second wafer has a straight positioning edge, the first chamfer and the second chamfer are asymmetrical chamfer shapes, and the second wafer also includes a platform portion, the first chamfer, the platform portion, the transition chamfer and the second chamfer are connected in sequence;

[0011] S2. Polish the surfaces of the first chamfer, the second chamfer, and the transition chamfer according to the preset polishing parameters;

[0012] S3. Real-time detection of the extension direction of the positioning edge and adjustment of the preset polishing parameters based on the extension direction of the positioning edge, return to execute S2, until the target wafer is obtained;

[0013] Wherein, the angle between the extension direction of the positioning edge of the target wafer and the crystal orientation of the target wafer is less than or equal to 0.01°, and the roughness of the first chamfer, the second chamfer, and the transition chamfer of the target wafer is less than or equal to 1nm.

[0014] As a further improvement of the present invention, in addition to real-time detection of the extension direction of the positioning edge, it also includes:

[0015] Real-time detection of the crystal orientation of the current second wafer;

[0016] The adjustment of the preset polishing parameters based on the extension direction of the positioning edge includes:

[0017] The preset polishing parameters are adjusted based on the crystal orientation and the extension direction.

[0018] As a further improvement of the present invention, polishing the surfaces of the first chamfered portion, the second chamfered portion, and the transition chamfered portion includes:

[0019] The first surface, the first chamfered portion, the second chamfered portion, and the transition chamfered portion are polished using a chemical mechanical polishing process to obtain a first surface, a first chamfered portion, a second chamfered portion, and a transition chamfered portion with a roughness of 1-10 nm.

[0020] The surfaces of the first chamfer, the second chamfer, and the transition chamfer are polished using femtosecond laser technology or argon ion beam polishing technology to obtain a first chamfer, a second chamfer, and a transition chamfer with a roughness ≤1nm.

[0021] As a further improvement of the present invention, the femtosecond laser process includes: polishing the first surface, the surface of the first chamfered portion, the surface of the second chamfered portion, and the surface of the transition chamfered portion using a femtosecond laser with a wavelength of 1020-1040nm; wherein the pulse width of the femtosecond laser is 100-200fs, the repetition frequency is 1kHz, and the scanning speed is 0.1-0.2mm / s.

[0022] As a further improvement of the present invention, the argon ion beam polishing process includes: introducing argon gas and an auxiliary gas into a vacuum environment, ionizing the argon gas to form argon ions that bombard the first surface, the surface of the first chamfered portion, the surface of the second chamfered portion, and the surface of the transition chamfered portion; wherein the flow rate ratio of the argon gas to the auxiliary gas is 1:1 to 2:1, and the power density of the ionized argon gas is 0.5 to 1 W / cm³. 2 The scanning speed is 0.5 to 1 mm / s.

[0023] In a second aspect, the present invention also provides a wafer, the wafer being processed by the processing method described in any one of the first aspects, the wafer comprising: a wafer body, the wafer body comprising a first surface and a second surface that are distributed opposite to each other along a first direction;

[0024] A positioning edge is provided on one side edge of the wafer body;

[0025] The positioning edge is constructed into an edge structure, the edge structure comprising:

[0026] The first chamfer portion connected to the first surface;

[0027] The second chamfer portion connected to the second surface;

[0028] A platform portion and a transition chamfer portion are formed between the first chamfer portion and the second chamfer portion and are arranged sequentially from top to bottom along the first direction.

[0029] As a further improvement of the present invention, the first chamfered portion is an R-shaped chamfer, and the second chamfered portion is a T-shaped chamfer;

[0030] And / or, the transition chamfer is an R-shaped chamfer.

[0031] As a further improvement of the present invention, the radius of curvature of the first chamfer is 0.15 to 0.25 mm, the angle formed by the second chamfer and the plane containing the second surface is 20° to 50°, and the radius of curvature of the transition chamfer is 0.05 to 0.15 mm.

[0032] As a further improvement of the present invention, the first chamfered portion terminates at the first chamfer boundary along the first direction, and the circumferential tangent at the junction of the first chamfered portion and the platform portion forms an upper chamfer with the first chamfer boundary, wherein the upper chamfer is 10° to 50°.

[0033] As a further improvement of the present invention, the height of the platform portion along the first direction is 0.03 to 0.1 mm; the width of the first chamfer portion along the second direction is 0.05 to 0.5 mm, and the width of the second chamfer portion along the second direction is 0.05 to 0.5 mm; the second direction is perpendicular to the first direction.

[0034] Compared with existing technologies, the beneficial effects of this invention are as follows: The edge of the first wafer to be processed, which has a positioning edge, is rough-machined to form a second wafer containing a first chamfer, a second chamfer, a transition chamfer, and a platform. The asymmetrical chamfer shapes of the first and second chamfers solve the crystal orientation identification error caused by inconsistent chamfer widths in traditional processes, and provide clear geometric markings for automated processing equipment, improving crystal orientation identification and cutting accuracy, and increasing finished product yield. The surfaces of the first chamfer, the second chamfer, and the transition chamfer of the second wafer are polished according to preset polishing parameters, reducing the surface roughness of the first chamfer, the transition chamfer, and the second chamfer. During the polishing process, the extension direction of the positioning edge is detected in real time. The relationship between the extension direction of the positioning edge and the preset reference relationship with the crystal orientation of the target wafer is compared to adjust the preset polishing parameters and return to the polishing step. This process continues until the angle between the extension direction of the positioning edge and the crystal orientation of the target wafer is less than or equal to 0.01°, thus obtaining the target wafer. This eliminates alignment errors in high-precision alignment processes such as photolithography and avoids uneven etching surfaces and rough cleavage surfaces. Simultaneously, the surfaces of the first chamfer, the second chamfer, and the transition chamfer are polished in multiple rounds to achieve a roughness of less than or equal to 1 nm. This reduces mechanical stress and microcracks at the wafer edges caused by traditional processes, enhances the wafer's mechanical strength, and prevents particle adsorption and stress concentration on rough surfaces, reducing the risk of wafer breakage in subsequent processing. Attached Figure Description

[0035] Figure 1This is a flowchart of the wafer fabrication method disclosed in this invention;

[0036] Figure 2 This is a top view of the wafer;

[0037] Figure 3 for Figure 2 A partial cross-sectional view of a wafer cut along the DD direction;

[0038] Figure 4 for Figure 3 A schematic diagram showing that the second chamfered portion forms an angle α with the plane containing the second surface, wherein the circumferential tangent at the junction of the first chamfered portion and the platform portion forms an upper chamfer α with the boundary of the first chamfered portion. Detailed Implementation

[0039] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. However, it should be noted that these embodiments are not intended to limit the present invention. All equivalent changes or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are within the scope of protection of the present invention.

[0040] The accompanying drawings in this invention are not strictly drawn to scale, and the specific dimensions of each structure can be determined according to actual needs. The drawings described in this invention are merely structural schematic diagrams. The lines shown in the accompanying drawings of this invention can be understood as components with a certain actual thickness.

[0041] Please combine Figures 1 to 3 , Figure 1 This is a flowchart of the wafer fabrication method disclosed in this invention. Figure 2 This is a top view of the wafer. Figure 3 for Figure 2 A partial cross-sectional view of a wafer cut along the DD direction. The wafer fabrication method includes the following steps:

[0042] S1. The edge of the first wafer to be processed is rough processed to form a second wafer having a first chamfer 12, a second chamfer 15 and a transition chamfer 14; wherein, one side edge of the second wafer has a straight positioning edge 4, the first chamfer 12 and the second chamfer 15 are asymmetrical chamfer shapes, the second wafer also includes a platform portion 13, and the first chamfer 12, the platform portion 13, the transition chamfer 14 and the second chamfer 15 are connected in sequence.

[0043] The material of the first wafer can be gallium nitride, its thickness can be 380-420μm, and the length of the positioning edge 4 can be 16mm.

[0044] S2. Polish the surfaces of the first chamfered portion 12, the second chamfered portion 15, and the transition chamfered portion 14 according to the preset polishing parameters.

[0045] S3. Real-time detection of the extension direction of positioning edge 4.

[0046] After polishing, the extension direction of positioning edge 4 is detected in real time.

[0047] S4. Determine whether the angle formed by the extension direction of the positioning edge 4 of the target wafer 100 and the crystal orientation of the target wafer 100 is less than or equal to 0.01°, and determine whether the roughness of the first chamfer 12, the second chamfer 15 and the transition chamfer 14 is less than or equal to 1nm.

[0048] S5. If the angle between the extension direction of the positioning edge 4 of the target wafer 100 and the crystal orientation of the target wafer 100 is greater than 0.01, or the roughness of the first chamfer 12, the second chamfer 15 and the transition chamfer 14 is greater than 1nm, then the preset polishing parameters are adjusted based on the extension direction of the positioning edge 4, and the process returns to execute S2.

[0049] S6. If the angle between the extension direction of the positioning edge 4 of the target wafer 100 and the crystal orientation of the target wafer 100 is less than or equal to 0.01°, and the roughness of the first chamfer 12, the second chamfer 15 and the transition chamfer 14 of the target wafer 100 is less than or equal to 1nm, then the target wafer is obtained.

[0050] The wafer processing method disclosed in this invention firstly involves rough processing the edge of a first wafer with a positioning edge 4 to be processed, forming a second wafer containing a first chamfer 12, a second chamfer 15, a transition chamfer 14, and a platform 13. The first chamfer 12, the platform 13, the transition chamfer 14, and the second chamfer 15 are connected sequentially from top to bottom along a first direction, and the first chamfer 12 and the second chamfer 15 are asymmetrical chamfer shapes. This solves the crystal orientation identification error caused by the inconsistent width of the wafer chamfer surface in traditional processing, and provides clear geometric markings for automated processing equipment (i.e., the asymmetrical chamfer shapes of the first chamfer 12 and the second chamfer 15), improving crystal orientation identification and cutting accuracy, and increasing the yield of finished products.

[0051] Secondly, according to preset polishing parameters, the surfaces of the first chamfer 12, the second chamfer 15, and the transition chamfer 14 of the second wafer are polished to reduce the surface roughness of the three (i.e., the first chamfer 12, the transition chamfer 14, and the second chamfer 15). During the polishing process, the extension direction of the positioning edge 4 is detected in real time, and the preset reference relationship between the extension direction of the positioning edge 4 and the crystal orientation of the target wafer 100 is compared to adjust the preset polishing parameters and return to step S2 until the angle formed by the extension direction of the positioning edge 4 and the crystal orientation of the target wafer 100 is less than or equal to 0.01°, so as to obtain the target wafer 100, eliminate the alignment error of the wafer 100 in high-precision alignment processes such as photolithography, and avoid uneven etching surfaces and rough cleavage surfaces (such as the surface of a laser resonator cavity). Meanwhile, the surfaces of the first chamfer 12, the second chamfer 15, and the transition chamfer 14 are polished in multiple rounds to achieve a roughness of less than or equal to 1 nm, thereby reducing mechanical stress and microcracks at the wafer edge in traditional processing, enhancing the mechanical strength of the wafer, and preventing particles from adsorbing and stress concentration on the rough surface, thus reducing the risk of wafer breakage in subsequent processing.

[0052] In some examples, the first chamfer 12, the second chamfer 15, and the transition chamfer 14 formed in step S1 are all in their original final shape and have already formed a basic outline. In the roughing stage, a diamond grinding wheel can be used for preliminary shaping. A five-axis linkage grinding machine is used to ensure geometric machining accuracy. The upper axis drives the grinding wheel's revolution, the lower axis drives the grinding wheel's feed, the left and right axes limit the grinding wheel's oscillation, and the rear axis drives the grinding wheel's lifting and lowering. The machining equipment used for roughing is not a point of invention in this application and is not described in detail in this embodiment.

[0053] The roughing time should be controlled within 60% to 70% of the total processing time. During the roughing stage, excess material can be quickly removed, ensuring that the dimensions of the first chamfer 12 or the second chamfer 15 formed after roughing are close to the target dimensions and basic surface morphology, thereby improving overall processing efficiency. If the roughing time is less than 60% of the total processing time, insufficient material removal will result in a large amount of remaining material needing to be processed during the finishing stage. This will not only prolong the total processing time but also increase the polishing cost in subsequent step S2 and reduce processing accuracy due to excessive load during the finishing stage. If the roughing time exceeds 70% of the total processing time, insufficient machining allowance for finishing will result in an inability to correct surface errors from the roughing process (e.g., minor chipping, dimensional deviations, large roughness, etc.) during the finishing stage, thus affecting the final accuracy.

[0054] In some examples, the surfaces of the first chamfer 12, the second chamfer 15, and the transition chamfer 14 are polished, including:

[0055] S21: The surfaces of the first surface 11, the first chamfer 12, the second chamfer 15, and the transition chamfer 14 are polished using a chemical mechanical polishing process to obtain the first surface 11, the first chamfer 12, the second chamfer 15, and the transition chamfer 14 with a roughness of 1-10 nm.

[0056] S22: Polish the surfaces of the first chamfer 12, the second chamfer 15, and the transition chamfer 14 using femtosecond laser technology or argon ion beam polishing technology to obtain the first chamfer 12, the second chamfer 15, and the transition chamfer 14 with a roughness ≤1nm.

[0057] First, a chemical mechanical polishing (CMP) process is used to treat the surfaces of the first surface 11, the first chamfer 12, the second chamfer 15, and the transition chamfer 14. Through the synergistic effect of chemical etching and mechanical polishing, the surface damage layer (such as microcracks and mechanical stress layer) remaining from the roughing process in step S1 is efficiently removed, while the surface is initially smoothed, so that the roughness of the above surfaces is controlled within the range of 1-10 nm. Subsequently, a second polishing process is performed on the surfaces of the first chamfer 12, the second chamfer 15, and the transition chamfer 14 using femtosecond laser technology or argon ion beam polishing technology. This fully utilizes the high-precision removal characteristics of the above two processes, and the surface roughness of the above chamfers is stably controlled within ≤1 nm.

[0058] In one embodiment, the femtosecond laser process includes polishing the surfaces of the first surface 11, the first chamfered portion 12, the second chamfered portion 15, and the transition chamfered portion 14 using a femtosecond laser with a wavelength of 1020–1040 nm; wherein the pulse width of the femtosecond laser is 100–200 fs, the repetition frequency is 1 kHz, and the scanning speed is 0.1–0.2 mm / s.

[0059] The argon ion beam polishing process includes: introducing argon gas and an auxiliary gas into a vacuum environment, ionizing the argon gas to form argon ions that bombard the surfaces of the first surface 11, the first chamfered portion 12, the second chamfered portion 15, and the transition chamfered portion 14; wherein the flow rate ratio of argon gas to auxiliary gas is 1:1 to 2:1, and the power density of the ionized argon gas is 0.5 to 1 W / cm³. 2 The scanning speed is 0.5–1 mm / s. Oxygen can be used as the auxiliary gas.

[0060] This invention effectively reduces over-polishing of the first surface 11, the first chamfer 12, the second chamfer 15, and the transition chamfer 14 during chemical mechanical polishing by using femtosecond laser technology and ion beam figuring (IBF) technology, significantly improving the surface quality and edge morphology of the wafer 100 and meeting the requirements of high-precision processing.

[0061] In some examples, the crystal orientation of the target wafer 100 (i.e., the preset standard wafer orientation) is aligned with the angle of the preset standard extension direction of the positioning edge (or can be understood as the crystal orientation of the target wafer 100 being parallel to the preset standard extension direction of the positioning edge). The preset standard extension direction of the positioning edge is set based on the preset standard wafer orientation (i.e., the orientation that the target wafer 100 needs to achieve). If the second wafer, the processing object in step S2, has no initial crystal orientation deviation (i.e., the actual crystal orientation of the second wafer is completely consistent with the preset standard wafer orientation), then the actual crystal orientation of the second wafer can provide a correct setting reference for the preset standard extension direction of the positioning edge. At this time, the standard extension direction of the positioning edge set based on this correct reference can maintain a preset alignment relationship (e.g., parallel) with the actual crystal orientation of the second wafer, and there is no angular deviation between them.

[0062] Therefore, during the polishing process of the surfaces of the first chamfered portion 12, the second chamfered portion 15, and the transition chamfered portion 14 according to the preset polishing parameters, the extension direction of the positioning edge 4 is monitored in real time. By detecting the angular deviation between the extension direction of the positioning edge 4 and the preset standard extension direction of the positioning edge, the preset polishing parameters are adjusted based on the angular deviation. After adjustment, the process returns to step S2, and polishing continues according to the adjusted polishing parameters. The cycle of steps S2 and S3 is repeated until the angle formed by the extension direction of the positioning edge 4 and the preset standard extension direction of the positioning edge is less than or equal to 0.01°. At the same time, the surfaces of the first chamfered portion 12, the second chamfered portion 15, and the transition chamfered portion 14 achieve a roughness of less than or equal to 1nm after multiple rounds of polishing. Finally, the target wafer 100 is obtained, and the angle formed by the extension direction of the positioning edge 4 contained in the target wafer 100 and the preset standard wafer orientation is less than or equal to 0.01°.

[0063] In some examples, while detecting the extension direction of positioning edge 4 in real time, the process also includes: detecting the crystal orientation of the current second wafer in real time; adjusting preset polishing parameters based on the extension direction of positioning edge 4, including: adjusting preset polishing parameters based on crystal orientation and extension direction. The preset standard extension direction of positioning edge is based on the preset standard crystal orientation of wafer (i.e., the crystal orientation that the target wafer 100 needs to achieve). If the second wafer being processed in step S2 has an initial crystal orientation deviation (i.e., the actual crystal orientation of the second wafer deviates from the preset standard crystal orientation of wafer), then the preset standard extension direction of positioning edge cannot provide a correct setting reference, resulting in an angular deviation between the preset standard extension direction of positioning edge and the actual crystal orientation of the second wafer. If the initial crystal orientation deviation of the second wafer cannot be detected, it is impossible to correctly determine whether the preset standard extension direction of the positioning edge is parallel to the actual crystal orientation of the second wafer. Therefore, when detecting the angular deviation between the extension direction of the positioning edge 4 and the preset standard extension direction of the positioning edge, it is equivalent to adjusting the preset polishing parameters with an incorrect angular deviation, resulting in the extension direction of the positioning edge 4 forming an angle of less than or equal to 0.01° with the incorrect crystal orientation of the second wafer. This does not truly solve the problem of the large angular deviation between the extension direction of the positioning edge 4 and the crystal orientation of the target wafer 100.

[0064] This embodiment detects the crystal orientation of the second wafer (i.e., the actual crystal orientation of the second wafer) in real time while detecting the extension direction of the positioning edge 4, determines whether the actual crystal orientation of the second wafer deviates from the preset standard crystal orientation of the wafer, and identifies the initial crystal orientation deviation of the second wafer. This avoids the problem of adjusting the preset polishing parameters based on the preset standard extension direction of the positioning edge, which has an angular deviation from the actual crystal orientation of the second wafer, due to the inability to detect the initial crystal orientation deviation of the second wafer, resulting in the problem of adjusting the preset polishing parameters with an incorrect angular deviation. Furthermore, by real-time detection of the actual crystal orientation of the second wafer, and by adjusting the preset polishing parameters based on the angular deviation between the actual crystal orientation of the second wafer and the preset standard crystal orientation, as well as the angular deviation between the extension direction of the positioning edge 4 and the preset standard extension direction of the positioning edge, the preset standard extension direction of the positioning edge can be dynamically corrected according to the actual crystal orientation of the second wafer. This ensures that the preset standard extension direction of the positioning edge always maintains a preset alignment relationship (e.g., parallel) with the actual crystal orientation of the second wafer, avoiding angular deviation between the preset standard extension direction of the positioning edge and the actual crystal orientation of the second wafer. This ensures that the adjustment of the polishing parameters is always aimed at making the preset standard extension direction of the positioning edge parallel to the actual crystal orientation of the second wafer, and ultimately achieving the parallelism between the preset standard extension direction of the positioning edge and the preset standard crystal orientation of the wafer, so that the angle formed by the extension direction of the positioning edge 4 and the crystal orientation of the target wafer 100 is less than or equal to 0.01°, completely solving the problem of large angular deviation between the extension direction of the positioning edge 4 and the crystal orientation of the target wafer 100.

[0065] In some examples, the actual extension direction of the positioning edge 4 is measured by a laser interferometer, and the actual extension direction angle measurement value (i.e., the angle data of the actual extension direction of the positioning edge 4) is obtained. This accurately detects the slight deviation of the actual extension direction of the positioning edge 4, avoiding misjudgment of the actual extension direction deviation of the positioning edge 4 due to insufficient detection accuracy. Then, the difference between the actual extension direction angle measurement value and the preset extension direction standard value (i.e., the preset angle data of the standard extension direction of the positioning edge) is calculated to obtain the extension direction deviation value. This quantifies the degree of deviation between the actual extension direction of the positioning edge 4 and the preset extension direction, providing accurate directional reference data for subsequent polishing parameter adjustments, and ensuring that the adjustment of the actual extension direction of the positioning edge 4 approaches the preset extension direction.

[0066] In some examples, the crystal orientation of the current second wafer is detected by an X-ray diffractometer and the actual measured value of the crystal orientation (i.e., the angle data of the actual crystal orientation of the second wafer) is obtained. The initial crystal orientation deviation that may exist in the second wafer is accurately detected. The crystal orientation deviation value is obtained by further calculating the difference between the actual measured value of the crystal orientation and the preset crystal orientation standard value (i.e., the angle data of the preset standard crystal orientation of the wafer). This identifies whether the actual crystal orientation of the second wafer deviates from the final target crystal orientation (i.e., the preset crystal orientation standard value), and completely solves the problem of large deviation of the crystal orientation angle between the extension direction of the positioning edge 4 and the target wafer 100.

[0067] By adjusting the polishing parameters based on the extension direction deviation value, it can be ensured that the extension direction of the positioning edge 4 continuously approaches the preset extension direction standard value; by adjusting the polishing parameters based on the crystal orientation deviation value, it can be ensured that the actual crystal orientation of the wafer gradually approaches the preset crystal orientation standard value, ultimately achieving that the preset positioning edge standard extension direction is parallel to the actual crystal orientation of the second wafer, and both (i.e., the preset positioning edge standard extension direction and the actual crystal orientation of the second wafer) are parallel to the preset wafer standard crystal orientation, ensuring that the angle formed between the actual extension direction of the positioning edge 4 and the crystal orientation of the target wafer 100 is less than or equal to 0.01°, completely solving the problems of photolithography alignment error, uneven etching surface, and rough laser resonator cavity surface caused by large angular deviation between the positioning edge and the target crystal orientation in traditional processes.

[0068] In some examples, a laser interferometer is used to measure the actual extension direction of positioning edge 4 to obtain the actual extension direction angle measurement value; an X-ray diffractometer is used to detect the crystal orientation of the current second wafer to obtain the actual crystal orientation measurement value; the difference between the actual crystal orientation measurement value and the actual extension direction angle measurement value is calculated to obtain the current deviation value; and the preset polishing parameters are adjusted based on the current deviation value.

[0069] Furthermore, a mapping table is pre-established to correspond to the deviation value (i.e., the difference between the actual crystal orientation of the wafer and the actual extension direction of the positioning edge 4) and the polishing parameters. During actual use, the current deviation value is queried from the mapping table to obtain the corresponding polishing parameters, which are then used as the adjusted preset polishing parameters. The obtained polishing parameters are input into the control system of the polishing equipment (e.g., a PLC control system). The polishing equipment automatically adjusts parameters such as polishing pressure, rotation speed, and time, performing a single polishing adjustment. After adjustment, the detection process of the laser interferometer and X-ray diffractometer is repeated to recalculate the current deviation value. If the deviation value is less than or equal to 0.01°, the polishing parameter adjustment is deemed satisfactory, and subsequent polishing processes continue (e.g., maintaining the current polishing parameters while optimizing the roughness of the wafer chamfer). If the deviation value is greater than 0.01°, the new current deviation value is queried again from the mapping table to obtain the corresponding polishing parameters, and the adjustment process is repeated until the deviation value is less than or equal to 0.01°.

[0070] Through the aforementioned dynamic measurement and feedback, for second wafers that do not meet the processing requirements, further fine-tuning can be performed using femtosecond laser technology (or argon ion beam polishing). Based on the current deviation value, the corresponding parameters are looked up in the mapping table, and parameters such as the wavelength, pulse width, and scanning speed of the femtosecond laser (or the gas flow ratio, power density, and scanning speed of argon ion beam polishing) are adjusted. Fine-tuning corrects the alignment deviation between the crystal orientation and the positioning edge, as well as the roughness of the chamfered area, until the dual judgment criteria are met. For second wafers that meet the processing requirements, their corresponding polishing parameters can be stored as standard parameters in the mapping table. When subsequently performing chamfering on wafers of the same material and specifications, these standard parameters can be directly called to set the preset polishing parameters, eliminating the need for repeated parameter trial and error and calibration. This effectively shortens the processing cycle of wafers of the same type and improves the efficiency and consistency of batch processing.

[0071] On the other hand, based on the specific implementation of the wafer processing method disclosed in the foregoing embodiments, the present invention also discloses a wafer, which is processed by the wafer processing method in the foregoing embodiments.

[0072] The wafer fabrication method disclosed in this embodiment is the same as described above and will not be repeated here. Figures 2-4 As shown, wafer 100 includes: wafer body 10 and positioning edge 4 disposed on one side edge of wafer body 10.

[0073] The wafer body 10 includes a first surface 11 and a second surface 16 that are distributed opposite to each other along a first direction 1. The first surface 11 is formed above the wafer 100, and the second surface 16 is formed below the wafer 100, with the first surface 11 and the second surface 16 being parallel.

[0074] The positioning edge 4 is constructed into an edge structure 3, which includes a first chamfer 12, a second chamfer 15, a platform 13, and a transition chamfer 14. The first chamfer 12 is connected to the first surface 11, the second chamfer 15 is connected to the second surface 16, and the platform 13 and the transition chamfer 14 are formed between the first chamfer 12 and the second chamfer 15 and are arranged sequentially from top to bottom along the first direction 1.

[0075] The first chamfer 12 and the second chamfer 15 are asymmetrical chamfer shapes to solve the crystal orientation identification error caused by the inconsistent width of the wafer chamfer surface in traditional processing. By making the first chamfer 12 and the second chamfer 15 asymmetrical chamfer shapes, clear geometric markings are provided for automated processing equipment, improving crystal orientation identification and cutting accuracy, and increasing the yield of finished products.

[0076] The surface roughness of the first chamfer 12, the second chamfer 15, and the transition chamfer 14 is all less than or equal to 1 nm, so as to reduce the mechanical stress and microcracks at the wafer edge in conventional processing, enhance the mechanical strength of the wafer, avoid the adsorption of particles and stress concentration on the rough surface, and reduce the risk of wafer breakage in subsequent processing.

[0077] The angle between the extension direction of positioning edge 4 and the crystal orientation of wafer 100 is less than or equal to 0.01°, so as to eliminate the alignment error of wafer 100 in high-precision alignment processes such as photolithography, and avoid uneven etching surface and rough cleavage surface (such as laser resonator cavity surface).

[0078] In some examples, the first chamfer 12 is an R-shaped chamfer, the second chamfer 15 is a T-shaped chamfer, and / or the transition chamfer 14 is an R-shaped chamfer.

[0079] The platform portion 13 is parallel to the first direction 1, thereby forming an annular curved surface. The first chamfer portion 12 terminates at the first chamfer boundary 132 along the first direction 1, and the surface of the bottom 121 of the first chamfer portion 12 along the first direction 1 has a natural and smooth transition with the surface of the platform portion 13.

[0080] One end of the first chamfer 12 smoothly transitions to the first surface 11, while the other end seamlessly connects to the platform portion 13. This disperses the mechanical stress at the edge of the wafer 100, preventing stress concentration between the platform portion 13 and the first chamfer 12, and reducing the risk of microcracks during rough machining and subsequent polishing. The T-shaped chamfer structure of the second chamfer 15 differs significantly in shape from the R-shaped chamfer structure of the first chamfer 12. Automated equipment can quickly distinguish between the first chamfer 12 and the second chamfer 15 by recognizing the characteristic differences between the T-shaped and R-shaped chamfers, further improving the accuracy of crystal orientation identification.

[0081] The bottom of the transition chamfer 14 and the surface of the second chamfer 15 transition smoothly and naturally. At the same time, the transition chamfer 14 is configured as an R-shaped chamfer, so that the transition chamfer 14 forms a gradient chamfer effect and a smooth transition between the platform 13 and the second chamfer 15. This avoids stress concentration between the platform 13 and the second chamfer 15, and especially avoids the sharp shape formed when the platform 13 and the second chamfer 15 are directly adjacent. It also avoids stress concentration at the junction of the platform 13 and the second chamfer 15, further avoiding edge chipping of the wafer 100, improving the overall quality of the wafer 100, and improving the accuracy of subsequent processes. It is suitable for edge structure 3 processing and forming of large-size wafers. Therefore, cracks or chipping at the edge structure 3 caused by slight external forces (e.g., mechanical contact, thermal stress caused by temperature changes during wafer transfer at different semiconductor equipment stations / areas) are avoided during subsequent processing (e.g., semiconductor processes such as thin film deposition, photolithography, ion implantation, etc.) or the transfer stage of the wafer handling by the robot, thus effectively preventing the wafer 100 from breaking.

[0082] In some examples, the radius of curvature of the first chamfer 12 is 0.15–0.25 mm, the angle α formed by the plane containing the second chamfer 15 and the second surface 16 is 20°–50°, and the radius of curvature of the transition chamfer 14 is 0.05–0.15 mm. The first chamfer 12 terminates at the first chamfer boundary 132 along the first direction 1, and the circumferential tangent 122 at the junction of the first chamfer 12 and the platform portion 13 forms an upper chamfer b with the first chamfer boundary 132, the upper chamfer b being 10°–50°. The circumferential tangent 122 lies in a vertical plane (not shown) perpendicular to the center direction of the wafer 100, and the vertical plane is perpendicular to the plane containing the wafer 100. In this example, the upper chamfer b is an acute angle, and the entire first chamfer 12 is located radially inside the annular contour formed by the platform 13 and is in a recessed state; thereby, the edge structure 3 can be prevented from protruding radially outward, thereby reducing the direct collision stress with other objects (such as wafer boxes, robotic arms) and avoiding edge chipping.

[0083] The radius of curvature R1 of the first chamfer 12 is 0.15 to 0.25 mm. The radius of curvature R1 of the first chamfer 12 should not be too large to avoid the edge of the wafer 100 from exceeding the clamping range of the positioning groove or chuck of the semiconductor device (not shown), thereby preventing the wafer 100 from shifting or slipping during transmission, or from rubbing against the components of the semiconductor device to generate scratches and other process defects.

[0084] Furthermore, the angle α formed by the plane containing the second chamfer 15 and the second surface 16 is 40° to 50°, and the upper chamfer b is 15° to 20°, which can be any integer or non-integer angle.

[0085] The height h of the platform portion 13 along the first direction 1 is 0.03 to 0.1 mm; the width 21 of the first chamfer portion 12 along the second direction 2 is 0.05 to 0.5 mm, and the width 20 of the second chamfer portion 15 along the second direction 2 is 0.05 to 0.5 mm; the second direction 2 is perpendicular to the first direction 1. The width 21 of the first chamfer portion 12 along the second direction 2 and the width 20 of the second chamfer portion 15 along the second direction 2 refer to the length formed by the orthographic projection of each chamfer portion from the center of the wafer 100 onto the plane where the wafer 100 is located.

[0086] Furthermore, the width 21 of the first chamfered portion 12 along the second direction 2 is 0.05 to 0.1 mm, and the width 20 of the second chamfered portion 15 along the second direction 2 is 0.1 to 0.2 mm, and can be any integer or non-integer.

[0087] By employing the technical solution provided by this invention, wafers with a positioning edge direction angle accuracy of up to within 0.01° (i.e., the angle formed by the extension direction of positioning edge 4 and the crystal orientation of the target wafer is less than or equal to 0.01°) can be obtained. This effectively solves the problems of large positioning edge direction angle deviation and inconsistent chamfer width in traditional chamfering processes, ensuring smooth etching and cleavage surfaces. It also effectively reduces the identification error of the crystal orientation of the wafer's upper surface by automated equipment, improving cutting accuracy and product quality. Simultaneously, the use of a composite processing technology (including roughing, chemical mechanical polishing, finishing, and dynamic feedback calibration steps) reduces surface roughness and obtains a chamfer of a specific shape, releasing stress and solving the problem of microcracks caused by mechanical stress in traditional chamfering processes. This effectively improves the surface quality and mechanical strength of the wafer.

[0088] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

[0089] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0090] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for processing a wafer, characterized in that, The processing method includes the following steps: S1. Roughly process the edge of the first wafer to be processed to form a second wafer having a first chamfer, a second chamfer, and a transition chamfer; wherein, one side edge of the second wafer has a straight positioning edge, the first chamfer and the second chamfer are asymmetrical chamfer shapes, the second wafer also includes a platform portion, and the first chamfer, the platform portion, the transition chamfer and the second chamfer are connected in sequence; S2. Polish the surfaces of the first chamfered portion, the second chamfered portion, and the transition chamfered portion according to preset polishing parameters; S3. Real-time detection of the extension direction of the positioning edge and adjustment of the preset polishing parameters based on the extension direction of the positioning edge, return to execute S2, until the target wafer is obtained; Wherein, the angle between the extension direction of the positioning edge of the target wafer and the crystal orientation of the target wafer is less than or equal to 0.01°, and the roughness of the first chamfer, the second chamfer, and the transition chamfer of the target wafer is less than or equal to 1 nm.

2. The processing method according to claim 1, characterized in that, In addition to real-time detection of the extension direction of the positioning edge, it also includes: Real-time detection of the crystal orientation of the current second wafer; The adjustment of the preset polishing parameters based on the extension direction of the positioning edge includes: The preset polishing parameters are adjusted based on the crystal orientation and the extension direction.

3. The processing method according to claim 1, characterized in that, Polishing the surfaces of the first chamfered portion, the second chamfered portion, and the transition chamfered portion includes: The first surface, the first chamfered portion, the second chamfered portion, and the transition chamfered portion are polished using a chemical mechanical polishing process to obtain a first surface, a first chamfered portion, a second chamfered portion, and a transition chamfered portion with a roughness of 1-10 nm. The surfaces of the first chamfer, the second chamfer, and the transition chamfer are polished using femtosecond laser technology or argon ion beam polishing technology to obtain a first chamfer, a second chamfer, and a transition chamfer with a roughness ≤1nm.

4. The processing method according to claim 3, characterized in that, The femtosecond laser process includes polishing the first surface, the surface of the first chamfered portion, the surface of the second chamfered portion, and the surface of the transition chamfered portion using a femtosecond laser with a wavelength of 1020–1040 nm; wherein the pulse width of the femtosecond laser is 100–200 fs, the repetition frequency is 1 kHz, and the scanning speed is 0.1–0.2 mm / s.

5. The processing method according to claim 3, characterized in that, The argon ion beam polishing process includes: introducing argon gas and an auxiliary gas into a vacuum environment, ionizing the argon gas to form argon ions that bombard the first surface, the surface of the first chamfered portion, the surface of the second chamfered portion, and the surface of the transition chamfered portion; wherein the flow rate ratio of the argon gas to the auxiliary gas is 1:1 to 2:1, and the power density of the ionized argon gas is 0.5 to 1 W / cm³. 2 The scanning speed is 0.5 to 1 mm / s.

6. A wafer, characterized in that, The wafer is obtained by the processing method according to any one of claims 1-5, and the wafer comprises: A wafer body, the wafer body comprising a first surface and a second surface that are distributed opposite to each other along a first direction; A positioning edge is provided on one side edge of the wafer body; The positioning edge is constructed into an edge structure, the edge structure comprising: The first chamfer portion connected to the first surface; The second chamfer portion connected to the second surface; A platform portion and a transition chamfer portion are formed between the first chamfer portion and the second chamfer portion and are arranged sequentially from top to bottom along the first direction.

7. The wafer according to claim 6, characterized in that, The first chamfer is an R-shaped chamfer, and the second chamfer is a T-shaped chamfer; And / or, the transition chamfer is an R-shaped chamfer.

8. The wafer according to claim 7, characterized in that, The radius of curvature of the first chamfer is 0.15 to 0.25 mm, the angle between the second chamfer and the plane containing the second surface is 20° to 50°, and the radius of curvature of the transition chamfer is 0.05 to 0.15 mm.

9. The wafer according to claim 8, characterized in that, The first chamfered portion terminates at the first chamfer boundary along the first direction, and the circumferential tangent at the junction of the first chamfered portion and the platform portion forms an upper chamfer with the first chamfer boundary, wherein the upper chamfer is 10° to 50°.

10. The wafer according to claim 9, characterized in that, The height of the platform portion along the first direction is 0.03 to 0.1 mm; the width of the first chamfer portion along the second direction is 0.05 to 0.5 mm, and the width of the second chamfer portion along the second direction is 0.05 to 0.5 mm; the second direction is perpendicular to the first direction.

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