Chip testing method and device and computer equipment

Abstract

The invention relates to a chip testing method and device and computer equipment. The method comprises the following steps: performing a chip test based on a test thread to obtain test data; storing the test data into a temporary file based on a test thread, and continuing to execute the next chip test after the test data is written; and writing the test data in the temporary file into a target file based on a data writing thread, the test thread and the data writing thread being parallel threads. By adopting the method, the test efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chip testing method, device and computer equipment. BACKGROUND

[0002] When testing mass-produced electronic chips, the tester software writes test data into a basic data file after testing is completed. The basic data file is a data format file. Chip testing and data writing are serial operations. After the tester writes the basic data file, the tester will accept the next start test signal from an online tester or a probe station.

[0003] However, in the process of testing mass-produced electronic chips, the tester software performs serial operations of testing and test data writing, which causes the tester software to fail to respond in time after the online tester or the probe station sends a next test signal, thereby reducing the testing efficiency of the tester. SUMMARY

[0004] Therefore, it is necessary to provide a chip testing method, device and computer equipment capable of improving testing efficiency to solve the above technical problems.

[0005] In a first aspect, the present application provides a chip testing method, which comprises:

[0006] performing chip testing based on a test thread to obtain test data;

[0007] storing the test data in a temporary file based on the test thread, and continuing to perform next chip testing after the test data is written;

[0008] writing the test data in the temporary file into a target file based on a data writing thread, wherein the test thread and the data writing thread are parallel threads.

[0009] In one embodiment, the method further comprises:

[0010] after the test data is written, sending a data writing request to the data writing thread through inter-thread communication, wherein the data writing request is used to trigger the data writing thread to write current test data in the temporary file into the target file.

[0011] In one embodiment, after the test data in the temporary file is written into the target file based on the data writing thread, the method further comprises:

[0012] sending a write completion signal of the temporary file to the test thread through inter-thread communication;

[0013] The method further comprises, before the test thread stores the test data into the temporary file:

[0014] In a case that the chip test is not the first test and the test thread does not receive the write completion signal corresponding to the temporary file of the last test, waiting for the write completion signal;

[0015] In a case that the chip test is not the first test and the test thread receives the write completion signal corresponding to the temporary file of the last test, continuing the step of storing the test data into the temporary file by the test thread.

[0016] In one of the embodiments, the temporary file is a json file.

[0017] In one of the embodiments, the temporary file includes a plurality of temporary files, each of which is used to store a type of data; the method further comprises:

[0018] classifying the test data to obtain a plurality of types of data;

[0019] The step of storing the test data into the temporary file by the test thread comprises:

[0020] storing each of the types of data into a corresponding temporary file in series according to a test order by the test thread;

[0021] The step of writing the test data in the temporary file into a target file by the data writing thread comprises:

[0022] writing the test data in each of the temporary files into a corresponding table of the target file in series according to the test order by the data writing thread, wherein one of the temporary files corresponds to one of the tables in the target file.

[0023] In one of the embodiments, the step of performing chip test by the test thread to obtain test data comprises:

[0024] testing at least one chip under test in a work station to obtain test data corresponding to each of the chips under test;

[0025] The step of storing the test data into the temporary file by the test thread comprises:

[0026] storing the test data corresponding to each of the chips under test into the temporary file by the test thread.

[0027] In one of the embodiments, after the step of performing chip test by the test thread to obtain test data, the method further comprises:

[0028] receiving display configuration information of test data through a graphical user interface;

[0029] controlling display of the test data based on the display configuration information.

[0030] In one embodiment, the controlling display of the test data based on the display configuration information comprises:

[0031] when the display configuration information indicates not to display test data, not displaying the test data;

[0032] when the display configuration information indicates to display summary information of the test data, displaying the summary information of the test data, the summary information comprising a station where a chip under test is located, Bin information of the station where the chip under test is located, and a test result;

[0033] when the display configuration information indicates to display each parameter of the test data, displaying each parameter of the test data.

[0034] In a second aspect, the present application further provides a chip testing device, the device comprising:

[0035] a testing module configured to perform chip testing based on a testing thread to obtain test data;

[0036] a first writing module configured to store the test data into a temporary file based on the testing thread, and continue to perform next chip testing after the test data is written;

[0037] a second writing module configured to write the test data in the temporary file into a target file based on a data writing thread, wherein the testing thread and the data writing thread are parallel threads.

[0038] In a third aspect, the present application further provides a computer device comprising a memory and a processor, the memory storing a computer program, and the processor implementing steps of the method described in any one of the above embodiments when executing the computer program.

[0039] The chip testing method, device and computer device described above perform chip testing based on a testing thread to obtain test data, store the test data into a temporary file based on the testing thread, and continue to perform next chip testing after the test data is written; and write the test data in the temporary file into a target file based on a data writing thread, wherein the testing thread and the data writing thread are parallel threads. In this way, the test data is first written into the temporary file instead of the target file, reducing time consumption, and the testing thread and the data writing thread are parallel threads, so that writing the test data into the target file does not affect the normal testing process, and the testing efficiency can be improved. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a diagram illustrating the application environment of a chip testing method in one embodiment;

[0042] Figure 2 This is a flowchart illustrating a chip testing method in one embodiment;

[0043] Figure 3 This is a schematic diagram of a graphical user interface in one embodiment;

[0044] Figure 4 This is a flowchart illustrating a chip testing method in another embodiment;

[0045] Figure 5 This is a structural block diagram of a chip testing device in one embodiment;

[0046] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0049] The chip testing method provided in this application embodiment can be applied to, for example... Figure 1The application environment shown. Among them, the handler or the probe station is in communication connection with the tester, the handler or the probe station can send the test signal to the tester, after the tester receives the test signal, the chip is tested based on the test thread, and the test data is obtained; the test data is stored into the temporary file based on the test thread, and after the test data is written, the next chip test is continued; the test data in the temporary file is written into the target file based on the data writing thread, wherein the test thread and the data writing thread are parallel threads, so that the test data is written into the temporary file first, instead of being written into the target file, reducing the time consumption, and the test thread and the data writing thread are parallel threads, so that the test data written into the target file does not affect the normal test process, and the test efficiency can be improved.

[0050] In an exemplary embodiment, as shown in Figure 2 , a chip testing method is provided, which is applied to the tester in Figure 1 for example, including the following steps S202 to S206. Among them:

[0051] S202: based on the test thread, the chip is tested, and the test data is obtained.

[0052] After the tester receives the test signal of the handler or the probe station, the chip is tested based on the test thread, and the test data is obtained, wherein the test data can include various types of data, such as BoadInfo, DataInfo, HBinInfo, LotInfo, ParamInfo, SBinInfo, SumInfo, UserDefine, etc. Here each represents a class.

[0053] Among them, after the test machine completes a test processing, it can also perform subsequent tests, for example, continue to receive the test signal sent by the handler or the probe station. In some other optional embodiments, the tester can receive multiple test signals at a time, and sort the test signals for processing in turn, wherein the test signal sorting method can be based on the test time of the test signal, or based on the priority of the test signal, which is not limited here.

[0054] S204: based on the test thread, the test data is stored into the temporary file, and after the test data is written, the next chip test is continued.

[0055] The temporary file is relative to the test thread, and the temporary file only records the test data of the test signal corresponding to the station chip.

[0056] In some optional embodiments, the temporary file is a json file. The temporary file is a text file in json format, and only records the test data of the chip of the station corresponding to the test signal.

[0057] In other embodiments, one test signal can indicate to test multiple chips of the stations at the same time, that is, to test multiple chips to obtain test data of the multiple chips, and the test data of the multiple chips can be stored in one temporary file or in multiple temporary files respectively, that is, the temporary file can correspond to a station (that is, a chip under test).

[0058] After the test data is stored in the temporary file, the test machine can continue to process the next chip test in the test thread, that is, to process the next test signal sent by the handler or the probe station.

[0059] S206: Based on the data writing thread, write the test data in the temporary file into the target file, wherein the test thread and the data writing thread are parallel threads.

[0060] The target file corresponds to a persistent storage, for example, the target file can be a file in a database, and the target file is used to store all test data.

[0061] After the test data is stored in the temporary file, the processing of the data writing thread is triggered, and based on the data writing thread, the test data in the temporary file is written into the target file.

[0062] The test thread and the data writing thread are parallel threads, and while the data writing thread writes the test data in the temporary file into the target file, the test thread can continue the next test, so that the operation of writing the temporary file into the target file is separately placed in the data writing thread, and is executed in parallel with the next chip test, and does not affect the execution of the next chip test, thereby improving the test efficiency.

[0063] The chip test method described above, based on the test thread to test the chip to obtain test data, based on the test thread to store the test data in the temporary file, and after the test data is written, the next chip test is continued; based on the data writing thread, the test data in the temporary file is written into the target file, wherein the test thread and the data writing thread are parallel threads, so that the test data is first written into the temporary file instead of the target file, which reduces the time consumption, and the test thread and the data writing thread are parallel threads, so that the test data writing into the target file does not affect the normal test process, and the test efficiency can be improved.

[0064] In one of the optional embodiments, the method further comprises: after the test data is written, sending a data writing request to the data writing thread through inter-thread communication, the data writing request being used to trigger the data writing thread to write the current test data in the temporary file to the target file.

[0065] The test thread and the data writing thread exchange data through inter-thread communication, for example, the test and the temporary file writing can be cooperated by using a semaphore to write the target file.

[0066] After the test data is written, the test thread sends a data writing request to the data writing thread through a semaphore to trigger the data writing thread to write the current test data in the temporary file to the target file.

[0067] In some optional embodiments, the semaphore can be a kernel object, and the data writing thread can be provided with a target function, such as the Windows system's WaitForSingleObject function, to wait for the semaphore sent by the test thread to trigger the processing of the data writing request.

[0068] In the above embodiments, inter-thread communication is used to realize the communication between the test thread and the data writing thread to trigger the data writing thread to write the current test data in the temporary file to the target file.

[0069] In some optional embodiments, based on the data writing thread, after the test data in the temporary file is written to the target file, the method comprises: sending a writing completion signal of the temporary file to the test thread through inter-thread communication; and based on the test thread storing the test data into the temporary file, the method further comprises: in a case where the chip test is not the first test and the test thread does not receive the writing completion signal corresponding to the temporary file of the last test, waiting for the writing completion signal; and in a case where the chip test is not the first test and the test thread receives the writing completion signal corresponding to the temporary file of the last test, continuing to execute the step of storing the test data into the temporary file based on the test thread.

[0070] The test thread and the data writing thread exchange data through inter-thread communication, for example, the test thread can be informed of the writing completion by the data writing thread after the temporary file is written to the target file.

[0071] After the data writing thread writes the temporary file to the target file, a writing completion signal can be sent to the test thread through a semaphore to trigger the test thread to write new test data into the temporary file.

[0072] In some alternative embodiments, the semaphore can be a kernel object, and the test thread can be configured with a target function, such as the WaitForSingleObject function built into the Windows system, to wait for the semaphore sent by the data writing thread to trigger the test thread to write new test data to a temporary file.

[0073] When the second test is completed and the second test data is ready to be written to the temporary file, it needs to wait for the completion signal of the previous temporary file writing to the target file. If the sum of the execution time of the test program in the test thread (i.e., the test time) and the temporary file writing time (i.e., the time for the test data to be written to the temporary file) is less than the target file writing time (i.e., the time for the temporary file to be written to the target file), it will wait for the temporary file to be written to the target file to complete.

[0074] In the case of the first chip test, no write completion signal will be received. After the test is completed, the test data is directly stored in a temporary file. In some optional embodiments, the test data can be stored while the test is being performed, that is, the test steps and the steps of storing the test data in the temporary file can be performed in parallel.

[0075] If the chip test is not the first test and the test thread has not received the write completion signal corresponding to the temporary file of the previous test, wait for the write completion signal. This avoids storing new test data in the temporary file, which would cause the temporary file storage to be messy.

[0076] If the chip test is not the first test, and the test thread has received the write completion signal corresponding to the temporary file of the previous test, that is, the temporary file is currently empty, the test data obtained from the new test can be stored in the temporary file.

[0077] In the above embodiment, before writing the temporary file after the chip test is completed, the system waits for the write completion signal of the data writing thread, thereby ending the data writing process of the data writing thread and preventing the test data from affecting the previous target file writing.

[0078] In one optional embodiment, the temporary files include multiple temporary files, each used to store a type of data; the method further includes: classifying the test data to obtain multiple types of data; storing the test data into the temporary files based on the test thread, including: storing each type of data into the corresponding temporary file sequentially according to the test order based on the test thread; and writing the test data in the temporary files into the target file based on the data writing thread, including: writing the test data in each temporary file into the corresponding table of the target file sequentially according to the test order based on the data writing thread, wherein one temporary file corresponds to one table in the target file.

[0079] The test data can include multiple types of data, such as BoadInfo, DataInfo, HBinInfo, LotInfo, ParamInfo, SBinInfo, SumInfo, and UserDefine. In this embodiment, the test data can be classified into multiple types of data based on the attributes of the test data itself, and each temporary file is used to store one type of data.

[0080] In this application, after obtaining the test data, the test data is classified, and then each type of data is stored in the corresponding temporary file in series based on the test thread according to the test order. For example, one test can include multiple types of data, and these types of data are stored in the corresponding temporary file in series according to the test order. The test order can be the execution data of the test, that is, the generation order of the test data, that is, the generation order of the type of data.

[0081] The target file includes multiple tables, and each table corresponds to a temporary file. Based on the data writing thread, the temporary files can be written into the tables of the target file in series according to the test data. For example, the first temporary file is written into the first table of the target file, and then the second temporary file is written into the second table of the target file, and so on, until each temporary file is written into the corresponding table of the target file.

[0082] In the above embodiment, one or more chips to be tested, test data is stored in the corresponding temporary file according to the type, and is written into the target file one by one. After one type of data is written, the next type of data is written. The test data is written in series one by one, which is stored in the target file according to the classification, and is convenient for subsequent calling of test data.

[0083] In some optional embodiments, based on the test thread, the chip test is performed to obtain test data, including: testing the chip to be tested in at least one station to obtain test data corresponding to each chip to be tested; and storing the test data in the temporary file based on the test thread, including: storing the test data corresponding to each chip to be tested in the temporary file based on the test thread.

[0084] In this application, multiple stations can be included, and one station corresponds to one chip to be tested. Therefore, multiple chips to be tested can be tested simultaneously to obtain multiple sets of test data, which are stored in different temporary files. The test data corresponding to each chip to be tested is stored in the temporary file based on the test thread, so as to facilitate subsequent writing of the test data in the temporary file into the target file.

[0085] In the above embodiment, parallel testing of chips can be realized.

[0086] In some optional embodiments, after performing chip testing based on a test thread and obtaining test data, the method further includes: receiving display configuration information for the test data through a graphical user interface; and controlling the display of the test data based on the display configuration information.

[0087] Since displaying test data requires refreshing the interface, this can impact the testing machine's productivity. To address this, test data display configuration information can be pre-configured to control the display. For example, during testing, the display configuration information can be configured to not display test data, preventing data display from affecting testing efficiency. In some optional embodiments, to obtain partial test results, the display configuration information can be configured to display only a summary of the test data, without showing each parameter. This allows obtaining the corresponding test results while minimizing the impact of data display on testing efficiency.

[0088] In some optional embodiments, the display of test data is controlled based on the display configuration information, including: not displaying test data when the display configuration information indicates that test data should not be displayed; displaying summary information of test data when the display configuration information indicates that summary information of test data should be displayed, the summary information including the station where the chip under test is located, the sub-bin information of the station, and the test results; and displaying each parameter of the test data when the display configuration information indicates that each parameter of the test data should be displayed.

[0089] For ease of understanding, combined with Figure 3 As shown, Figure 3 This is a schematic diagram of a graphical user interface in one embodiment. In this embodiment, configuration information can be configured for display. For example, in the menu bar StationA->BinLightA and StationB->BinLightB, the display of BinLight (summary information) and Show test data (each parameter) can be controlled. By default, they are not displayed, meaning that the summary information and each parameter are not displayed, i.e., the test data is not displayed. Only the station that is displayed can choose whether to display BinLight. BinLight displays summary information for multiple workstations. The summary information includes the workstation where the chip under test is located, the sub-Bin information of the workstation, and the test results (e.g., Pass / Fail information). The sub-Bin information refers to the identifier of the failure item of the chip under test in the workstation, for example... Figure 3 The number 6 in the summary information indicates that a certain test item was failed when the chip under test was executed at the current workstation. When the test result is "fail", the corresponding Site color in BinLight is red; when the test result is "pass", the corresponding Site color in BinLight is green.

[0090] In addition, the Show test data is a check item for displaying all parameter test data. When checked, the data of each parameter is displayed. When unchecked, the data interface becomes gray and no longer updates the test data, only the BinLight information is updated.

[0091] In the above embodiment, the data of each parameter is not displayed, the Bin information display of each station is increased, the time consumption of refreshing the interface in the test thread is reduced, and the time consumption of testing the chip by the test machine is reduced.

[0092] For the convenience of understanding, combined with Figure 4 , as shown in Figure 4 is a flowchart of chip testing in another embodiment, which is divided into a test thread and a data writing thread.

[0093] In the test thread, the test program is executed to obtain test data, and the test result can be obtained based on the test data. Then, based on the display configuration information, it is determined whether to display the summary information and each parameter, and the default is not to display. Subsequently, it is detected whether the writing completion signal is received. If yes, the test data is written into the temporary file, otherwise, it is continuously detected whether the writing completion signal is received. It should be noted that, regardless of whether the writing completion signal is received, the test data is written into the temporary file in the first test. After the writing is completed, the data writing request is sent to the data writing thread.

[0094] In the data writing thread, it is judged whether the data writing request is received. If yes, the temporary file is read and parsed, the temporary file is written into the target file, and after the writing is completed, the writing completion signal is sent to the test thread.

[0095] In the above embodiment, the test data is stored in the temporary file, the temporary file is written in the json format, the time consumption of writing the file is small, the time consumption of file writing in the test thread is reduced, and the time consumption of testing the chip by the test machine is reduced. The data of each parameter is not displayed, the Bin information display of each station is increased, the time consumption of refreshing the interface in the test thread is reduced, and the time consumption of testing the chip by the test machine is reduced.

[0096] It should be understood that although each step in the flowchart involved in the above embodiments is shown in sequence according to the arrow, the steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowchart involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential, but can be alternately or alternately executed with at least some of the other steps or steps or stages in the other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0097] Based on the same inventive concept, the embodiments of the present application also provide a chip testing device for implementing the above-mentioned chip testing method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more chip testing device embodiments provided below can refer to the limitations of the chip testing method in the above text, which will not be repeated here.

[0098] In one exemplary embodiment, as shown in Figure 5 a chip testing device is provided, comprising: a test module 501, a first write module 502 and a second write module 503, wherein:

[0099] The test module 501 is configured to perform chip testing based on a test thread to obtain test data.

[0100] The first write module 502 is configured to store the test data in a temporary file based on the test thread, and continue to perform the next chip testing after the test data is written.

[0101] The second write module 503 is configured to write the test data in the temporary file to a target file based on a data write thread, wherein the test thread and the data write thread are parallel threads.

[0102] In one of the optional embodiments, the above device further comprises:

[0103] The first thread communication module is configured to send a data write request to the data write thread through inter-thread communication after the test data is written, and the data write request is used to trigger the data write thread to write the current test data in the temporary file to the target file.

[0104] In one of the optional embodiments, the above device further comprises:

[0105] The second thread communication module is configured to send a write completion signal of the temporary file to the test thread through inter-thread communication.

[0106] The detection module is configured to, in a case where the chip test is not the first test and the test thread does not receive the write completion signal corresponding to the temporary file of the last test, wait for the write completion signal; and in a case where the chip test is not the first test and the test thread receives the write completion signal corresponding to the temporary file of the last test, continue to execute the step of storing the test data into the temporary file based on the test thread.

[0107] In one of the optional embodiments, the temporary file is a json file.

[0108] In one of the optional embodiments, the temporary file includes a plurality of temporary files, each of which is used to store a type of data; and the apparatus further includes:

[0109] The classification module is configured to classify the test data to obtain a plurality of types of data.

[0110] The first write module 502 is further configured to store each type of data into a corresponding temporary file in a serial manner according to the test order based on the test thread.

[0111] The second write module 503 is further configured to write the test data in each temporary file into a corresponding table of the target file in a serial manner according to the test order based on the data write thread, wherein one temporary file corresponds to one table in the target file.

[0112] In one of the optional embodiments, the test module 501 is further configured to test the chips to be tested in at least one station to obtain test data corresponding to each chip to be tested.

[0113] The first write module 502 is further configured to store the test data corresponding to each chip to be tested into a temporary file based on the test thread.

[0114] In one of the optional embodiments, the apparatus further includes a display module configured to receive display configuration information of the test data through a graphical user interface, and control display of the test data based on the display configuration information.

[0115] In one of the optional embodiments, the display module is further configured to, in a case where the display configuration information indicates not to display the test data, not display the test data; in a case where the display configuration information indicates to display summary information of the test data, display the summary information of the test data, the summary information including a station where the chip to be tested is located and a test result; and in a case where the display configuration information indicates to display each parameter of the test data, display each parameter of the test data.

[0116] Each module in the chip testing apparatus can be implemented by software, hardware, or a combination thereof, in whole or in part. Each module can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be invoked by the processor to perform the operations corresponding to each module.

[0117] In an exemplary embodiment, a computer device, which can be a terminal, is provided, and an internal structure diagram of the computer device can be as shown in Figure 6 The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to perform wired or wireless communication with external terminals. The wireless communication can be achieved through WIFI, mobile cellular network, near field communication (NFC), or other technologies. The computer program is executed by the processor to implement a chip testing method. The display unit of the computer device is configured to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, a trackball, or a touchpad arranged on the shell of the computer device, or an external keyboard, a touchpad, a mouse, or the like.

[0118] Those skilled in the art can understand that Figure 6 The structure shown in the above description is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. Specifically, the computer device can include more or fewer components than those shown in the diagram, or combine certain components, or have a different arrangement of components.

[0119] In an embodiment, a computer device is also provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in each method embodiment.

[0120] In an embodiment, a computer readable storage medium is provided, and a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to implement the steps in the above method embodiments.

[0121] In an embodiment, a computer program product is provided, and the computer program product comprises a computer program, and the computer program is executed by a processor to implement the steps in the above method embodiments.

[0122] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with relevant regulations.

[0123] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0124] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0125] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A chip testing method, characterized in that, The method includes: Chip testing is performed based on test threads to obtain test data; The test data is stored in a temporary file based on the test thread, and the next chip test is executed after the test data is written. Based on the data writing thread, the test data in the temporary file is written to the target file, wherein the test thread and the data writing thread are parallel threads.

2. The method according to claim 1, characterized in that, The method further includes: After the test data is written, a data write request is sent to the data writing thread via inter-thread communication. The data write request is used to trigger the data writing thread to write the current test data in the temporary file to the target file.

3. The method according to claim 1, characterized in that, The step of writing the test data from the temporary file to the target file based on the data writing thread includes: The temporary file is written to the test thread via inter-thread communication; Before storing the test data in a temporary file based on the test thread, the method further includes: If the chip test is not the first test and the test thread has not received the write completion signal corresponding to the temporary file of the previous test, wait for the write completion signal; If the chip test is not the first test, and the test thread receives the write completion signal corresponding to the temporary file of the previous test, the step of storing the test data into the temporary file based on the test thread continues.

4. The method according to any one of claims 1-3, characterized in that, The temporary file is a JSON file.

5. The method according to any one of claims 1-3, characterized in that, The temporary files include multiple files, each of which is used to store a type of data; the method further includes: The test data is classified into multiple categories. The step of storing the test data in a temporary file based on the test thread includes: Based on the test thread, each type of data is stored sequentially in the test order and stored in the corresponding temporary file. The step of writing test data from the temporary file to the target file based on the data writing thread includes: Based on the data writing thread, the test data in each of the temporary files is sequentially written into the corresponding table of the target file according to the test order, wherein one of the temporary files corresponds to one of the tables in the target file.

6. The method according to any one of claims 1 to 3, characterized in that, The chip testing based on the test thread, to obtain test data, includes: Test the chip under test in at least one workstation to obtain test data for each chip under test. The step of storing the test data in a temporary file based on the test thread includes: Based on the test thread, the test data corresponding to each chip under test is stored in a temporary file.

7. The method according to any one of claims 1 to 3, characterized in that, After obtaining test data through chip testing based on the test thread, the process further includes: Receive test data display configuration information through a graphical user interface; Based on the display configuration information, the display of the test data is controlled.

8. The method according to claim 7, characterized in that, The step of controlling the display of the test data based on the display configuration information includes: If the display configuration information indicates that test data should not be displayed, the test data will not be displayed. When the display configuration information indicates that the summary information of the test data is to be displayed, the summary information of the test data is displayed, and the summary information includes the station where the chip under test is located, the sub-bin information of the station, and the test results; If the display configuration information indicates that each parameter of the test data should be displayed, then each parameter of the test data should be displayed.

9. A chip testing device, characterized in that, The device includes: The test module is used to perform chip testing based on test threads and obtain test data; The first writing module is used to store the test data into a temporary file based on the test thread, and continue to execute the next chip test after the test data is written. The second writing module is used to write test data from the temporary file to the target file based on the data writing thread, wherein the test thread and the data writing thread are parallel threads.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1-8.

Images