Integrated bootstrap circuit for power converter

Abstract

The invention relates to an integrated bootstrap circuit for a power converter. Semiconductor devices and integrated circuits implementing power converters are described. An integrated circuit may include a power stage, a driver, and a bootstrap circuit. The driver may be configured to drive the power stage. The bootstrap circuit may be configured to drive a high-side switch in the power stage during a start-up process. The bootstrap circuit may include a capacitor and a diode. The power stage, driver, and bootstrap circuit may be integrated on the same silicon. The capacitor may be implemented by at least one trench capacitor.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and packages, and more specifically, to power converters having integrated bootstrap circuitry. Background Technology

[0002] Power converters or voltage converters (such as buck converters and boost converters) can be used to convert an input voltage into an output voltage with different voltage levels. A buck converter or voltage reducer can convert an input voltage to a lower voltage. A boost converter or voltage increaser can convert an input voltage to a higher voltage. A buck-boost converter can boost or reduce an input voltage. A voltage converter may include multiple switches that can be turned on and off by a pulse width modulation (PWM) control signal. The duty cycle of the PWM control signal can define the output voltage of the voltage converter. When a voltage converter is connected to a load, the load can draw a specific amount of current to request a specific amount of power, and the voltage converter can perform voltage conversion to produce an output voltage that can deliver the power requested by the load. The current drawn by the load can be sensed and fed back to the controller of the power converter, and the controller can report the sensed current to a host processor so that the host processor can run various applications, such as optimizing the performance of the load. Summary of the Invention

[0003] In one embodiment, an integrated circuit for implementing a power converter is generally described. The integrated circuit may include a power stage, a driver, and a bootstrap circuit. The driver may be configured to drive the power stage. The bootstrap circuit may be configured to drive a high-side switch in the power stage during startup. The bootstrap circuit may include a capacitor and a diode. The power stage, driver, and bootstrap circuit may be integrated on the same silicon. The capacitor may be implemented using at least one of a planar capacitor and a trench capacitor. The diode may be implemented using at least one of a planar diode and a trench diode.

[0004] In one embodiment, a voltage regulator is generally described. The voltage regulator may include an integrated circuit and a controller configured to control the integrated circuit. The integrated circuit may include a power stage, a driver, and a bootstrap circuit. The driver may be configured to drive the power stage. The bootstrap circuit may be configured to drive a high-side switch in the power stage during startup. The bootstrap circuit may include a capacitor and a diode. The power stage, driver, and bootstrap circuit may be integrated on the same silicon. The capacitor may be implemented using at least one of a planar capacitor and a trench capacitor. The diode may be implemented using at least one of a planar diode and a trench diode.

[0005] In one embodiment, an integrated circuit for implementing a power converter is generally described. The integrated circuit may include a power stage, a driver, and a bootstrap circuit. The driver may be configured to drive the power stage. The bootstrap circuit may be configured to drive a high-side switch in the power stage during startup. The bootstrap circuit may include a capacitor and a diode. The power stage, driver, and bootstrap circuit may be integrated on the same silicon. The capacitor may be implemented using at least one trench capacitor.

[0006] The above overview is merely illustrative and is not intended to be limiting in any way. Other aspects, embodiments, and features will become clear from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. In the drawings, similar reference numerals indicate the same or functionally similar elements. Attached Figure Description

[0007] Figure 1 The illustration shows an example of a system that may include a power converter with integrated bootstrap circuitry in one embodiment.

[0008] Figure 2 This is a cross-sectional view illustrating an embodiment of an integrated bootstrap circuit.

[0009] Figure 3 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit.

[0010] Figure 4 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit.

[0011] Figure 5 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit.

[0012] Figure 6 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit.

[0013] Figure 7 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit.

[0014] Figure 8 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit.

[0015] Figure 9 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Detailed Implementation

[0016] In the following description, numerous specific details (such as particular structures, components, materials, dimensions, processing steps, and techniques) are set forth in order to provide an understanding of various embodiments of this application. However, those skilled in the art will understand that various embodiments of this application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring this application.

[0017] Figure 1 The illustration shows an example of a system that may include a power converter with integrated bootstrap circuitry, according to one embodiment. According to a non-limiting example, Figure 1 System 100 in this context can be a power conversion system. As used herein, the terms block, module, circuit, system, etc., can refer to various hardware, firmware, and software components, or combinations thereof.

[0018] System 100 may include at least a controller 114 and an integrated circuit (IC) 116. IC 116 may include driver circuitry (or drivers) 130, a power stage 132, and various other components. In one or more embodiments, IC 116 may also include memory devices, such as memory devices and registers. Controller 114 may include one or more semiconductor devices implementing, for example, a microcontroller, which includes hardware such as various analog and digital circuit components. Controller 114 may include, for example, a processor, a central processing unit (CPU), a field-programmable gate array (FPGA), or any other circuitry configured to control and operate various aspects of power stage 132. Controller 114 is configured to control various aspects of system 100. In one or more embodiments, a host computer may provide input to controller 114 for various aspects of operating system 100.

[0019] Controller 114 can be configured to execute instructions, which may include firmware, software, and configuration data, which may be embedded in or accessible from local memory within controller 114, or at least partially downloaded from a host computer. Controller 114 can also be configured to generate control signals (such as PWM signals, e.g., Figure 1 The controller 114 receives the PWM signal and converts it into drive signals, which may be the gate voltages of the switches in the power stage 132. The controller 114 can also be configured to monitor various parameters related to the operation of the system 100 and, based on the monitored parameters, determine whether to adjust the PWM signal to regulate the on and off times of the switches in the power stage 132.

[0020] Power stage 132 may include at least one pair of switches Q1, Q2. Switches Q1, Q2 may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). In one or more embodiments, switches Q1 and Q2 may be N-type MOSFETs. Switch Q1 may be arranged in series between the input voltage VIN and the switching node SW. In one embodiment, the input voltage VIN may be a direct current (DC) voltage provided by a battery or power source. Switch Q2 may be arranged in series between the switching node SW and ground. Driver circuit 130 may use a PWM signal provided by controller 114 to generate a drive signal and use the drive signal to alternately drive switches Q1, Q2. As a result of alternately driving switches Q1, Q2, an output voltage VOUT may be output from the switching node SW. Inductor L may be connected between the switching node SW and the load 104. The output voltage VOUT may supply power to the load 104. The load 104 may be, for example, a central processing unit (CPU), a multiprocessor unit (MPU), a computer, or other electronic components that require power to operate.

[0021] IC 116 may also include a diode DBOOT and a capacitor CBOOT. The capacitor CBOOT may be a bootstrap capacitor connected between the power supply Vdd and the driver 130. In an embodiment where switch Q1 is an N-type MOSFET, the diode DBOOT and capacitor CBOOT may be used as a boost circuit. When switch Q1 is off and switch Q2 is on, node SW will be close to or below ground, and capacitor CBOOT may be charged by the power supply Vdd, which is above ground. When switch Q1 is on and switch Q2 is off, node SW will rise to a voltage VIN, which may be greater than voltage Vdd. This causes current flow through diode DBOOT to stop when diode DBOOT becomes reverse biased. The capacitor CBOOT may then discharge to provide the output of the bootstrap voltage VBST to the driver to drive switch Q1. In one aspect, controller 114 may operate system 100 in normal operating mode, in low-power mode, or shut down system 100. When the low-power mode of system 100 is enabled, various connection paths between components in system 100 can be shut off or disconnected, and / or various functions can be disabled to minimize current flow within system 100, thereby conserving energy and power. For example, if a specific component is not needed, it can be shut off during low-power mode to conserve power. To transition from low-power mode or from shutdown back to normal operating mode, system 100 may undergo a startup process. The startup process of system 100 may include biasing various components, turning on switch Q1, reconnecting disconnected paths, or other actions required for system 100 to operate in normal operating mode. The bootstrap voltage VBST provided by capacitor CBOOT may need to be at a level sufficient to turn on switch Q1 to allow system 100 to restart operation in normal operating mode. Figure 1 The diagram shows multiple nodes N1, N2, and N3. Node N1 is the node between CBOOT and the switch node SW, node N2 is the node between CBOOT and the cathode of diode DBOOT, and node N3 is the node between the anode of diode DBOOT and the power supply Vdd.

[0022] On one hand, a conventional power conversion system includes a driver and power stage within an IC package, and a bootstrap circuitry located outside and separate from the IC package. Discrete diodes and discrete capacitors can be connected to the IC package using traces on a printed circuit board (PCB). The bootstrap circuitry may include a diode (DBOOT) and a capacitor (CBOOT) as discrete devices, which may occupy a relatively large area on the PCB. For more detail herein, the diode (DBOOT) and capacitor (CBOOT) can be integrated as part of IC 116, such that the DBOOT, CBOOT, driver 130, and power stage 132 can be integrated or mounted as a monolithic IC or mounted on a monolithic silicon chip. To integrate the DBOOT and CBOOT within the same IC package as the driver 130 and power stage 132, the DBOOT and CBOOT can be implemented using different types of diodes and capacitors, allowing the DBOOT and CBOOT to be integrated within the IC package. In one or more embodiments, different combinations of planar PN diodes, planar Schottky diodes, junction barrier Schottky diodes, trench MOS barrier Schottky diodes, trench MOS barrier PN diodes, planar capacitors, and trench capacitors can be used to implement DBOOT and CBOOT.

[0023] Figure 2 This is a cross-sectional view illustrating an embodiment of an integrated bootstrap circuit. Figure 2 The description can be found here. Figure 1 The components shown in the image. Figure 2 In the embodiments shown, one or more PN diodes may be used to implement bootstrap diodes (e.g., DBOOT), and one or more planar MOS capacitors may be used to implement bootstrap capacitors (e.g., CBOOT). Figure 2 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 2 The example shown illustrates an N-well 202 that can be part of IC 116. The N-well 202 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 202 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 202 can also be an N-epitaxial layer. The N-well 202 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0024] Figure 1The bootstrap capacitor CBOOT shown can be implemented by one or more planar capacitors formed of dielectric 206, electrode 208, and N-well 202. In one or more embodiments, the N-well 202 can serve as one of the conductive plates of the planar capacitor. Dielectric 206 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. Electrode 208 can be formed of, for example, highly conductive materials (such as doped polycrystalline silicon or metals (e.g., aluminum, copper, etc.)). In one embodiment, dielectric 206 can have a thickness that depends on the voltage Vdd. (Refer to...) Figure 1 Node N1 can contact electrode 208.

[0025] A diode DBOOT can be implemented using one or more P+ diffusion regions 210 and N-wells 202. The P+ diffusion region 210 can be created by P-type diffusion in the vacancy regions of the N-well 202. The P+ diffusion region 210 can be formed of a doped material (such as boron, aluminum, or gallium). By forming the P+ diffusion region 210 in the N-well 202, a PN junction can be formed between the P+ diffusion region 210 and the N-well 202 to realize the diode DBOOT. The P+ diffusion region 210 can be the anode of the diode DBOOT, and the N-well 202 can be the cathode of the diode DBOOT. Contacts 212 (e.g., ohmic contacts) can be disposed on top of the P+ diffusion region 210 to connect the diode DBOOT to other components. (See reference...) Figure 1 Node N3 can contact contact 212, allowing the anode of diode DBOOT to be connected to Vdd.

[0026] One or more N+ diffusion regions 204 can be formed in the N-well 202. The N+ diffusion regions 204 can be created by N-type diffusion in the vacancy regions of the N-well 202. The N+ diffusion regions 204 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 204 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can contact N+ diffusion region 204 to connect the cathode of diode DBOOT (e.g., N-well 202) to capacitor CBOOT.

[0027] Figure 3 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 3 The description can be found here. Figure 1 and Figure 2 The components shown in the image. Figure 3In the embodiments shown, one or more planar Schottky diodes can be used to implement bootstrap diodes (e.g., DBOOT), and one or more planar MOS capacitors can be used to implement bootstrap capacitors (e.g., CBOOT). Figure 3 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 3 The example shown illustrates an N-well 302 that can be part of IC 116. The N-well 302 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 302 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 302 can also be an N-epitaxial layer. The N-well 302 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0028] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more planar capacitors formed of dielectric 306, electrode 308, and N-well 302. In one or more embodiments, the N-well 302 can serve as one of the conductive plates of the planar capacitor. Dielectric 306 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. Electrode 308 can be formed of, for example, highly conductive materials (such as doped polycrystalline silicon or metals (e.g., aluminum, copper, etc.)). In one embodiment, dielectric 306 can have a thickness that depends on the voltage Vdd. (Refer to...) Figure 1 Node N1 can contact electrode 308.

[0029] A planar Schottky diode (DBOOT) can be implemented using one or more planar Schottky diodes. To create a planar Schottky diode, one or more metal contacts 312 can be formed on the N-well 302. The metal contacts 312 can be Schottky contacts, which can be metal-semiconductor contacts that create a Schottky barrier with an N-type semiconductor (such as the N-well 302). In one or more embodiments, the metal contacts 312 can be titanium, cobalt, or platinum contacts. On one hand, a Schottky barrier is formed when the metal contacts the N-type semiconductor and the work function of the metal (e.g., the minimum energy required to extract an electron) is greater than the work function of the N-type semiconductor. Therefore, the work function of the material forming the metal contacts 312 is greater than the work function of the material forming the N-well 302. The metal contacts 312 can be used as the anode of the DBOOT diode, and the N-well 302 can be used as the cathode of the DBOOT diode. (Refer to...) Figure 1 Node N3 can contact metal contact 312, allowing the anode of diode DBOOT to be connected to Vdd.

[0030] One or more N+ diffusion regions 304 can be formed in the N-well 302. The N+ diffusion regions 304 can be created by N-type diffusion in the vacancy regions of the N-well 302. The N+ diffusion regions 304 can be formed from doped materials such as nitrogen, phosphorus, or arsenic. The N+ diffusion regions 304 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can contact the N+ diffusion region 304 to connect the cathode of diode DBOOT (e.g., N-well 302) to capacitor CBOOT. In one aspect, when with... Figure 2 Compared to the PN junction diode in the embodiments shown, the Schottky diode can turn on at a lower voltage and switch faster.

[0031] Figure 4 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 4 The description can be found here. Figures 1 to 3 The components shown in the image. Figure 4 In the embodiments shown, one or more planar junction-barrier Schottky diodes can be used to implement bootstrap diodes (e.g., DBOOT), and one or more planar MOS capacitors can be used to implement bootstrap capacitors (e.g., CBOOT). Figure 4 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 4The example shown illustrates an N-well 402 that can be part of IC 116. The N-well 402 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 402 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 402 can also be an N-epitaxial layer. The N-well 402 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0032] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more planar capacitors formed of dielectric 406, electrode 408, and N-well 402. In one or more embodiments, the N-well 402 can serve as one of the conductive plates of the planar capacitor. Dielectric 406 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. Electrode 408 can be formed of, for example, highly conductive materials (such as doped polycrystalline silicon or metals (e.g., aluminum, copper, etc.)). In one embodiment, dielectric 406 can have a thickness that depends on the voltage Vdd. For example, the thickness of dielectric 406 increases with increasing Vdd, such that the capacitor CBOOT can be thick enough to block voltages greater than Vdd. (See reference...) Figure 1 Node N1 can contact electrode 408.

[0033] The diode DBOOT can be implemented by one or more planar junction barrier Schottky (JBS) diodes. A P+ diffusion region 414 can be formed in some exposed portions of the N-well 402 (such as portions not covered by dielectric 406). The P+ diffusion region 414 can be formed of a doped material (such as aluminum, boron, or gallium). After forming the P-type diffusion region 414, one or more metal contacts 412 can be formed across the N-well 402 and the P-type diffusion region 414. The metal contacts 412 can be ohms on top of the P-type diffusion region 414 and form a PN junction diode and a Schottky diode on top of the N-well 402. The metal contacts 412 contacting the N-well 402 and the P-diffusion region 414 can form JBS diodes. The metal contacts 412 can be Schottky contacts, which can be metal-semiconductor contacts that create a Schottky barrier with the N-type semiconductor (such as the N-well 402). In one or more embodiments, the metal contacts 412 can be titanium, cobalt, or platinum contacts. The P+ diffusion region 414 can be formed to protect the relatively fragile edges of the metal contact 412 from breakage. On the one hand, a Schottky barrier is formed when the metal contacts an N-type semiconductor and the work function of the metal (e.g., the minimum energy required to extract an electron) is greater than the work function of the N-type semiconductor. Therefore, the work function of the material forming the metal contact 412 is greater than the work function of the material forming the N-well 402. By forming the P+ diffusion region 414 in the N-well 402, a PN junction can be formed around a Schottky diode formed by the metal contact 412 and the N-well 402. The spacing between the P+ diffusion regions 414 can be defined to optimize barrier and conduction. The metal contact 412 can be used as the anode of the diode DBOOT, and the N-well 402 can be used as the cathode of the diode DBOOT. (Refer to...) Figure 1 Node N3 can contact the metal contact 412, allowing the anode of diode DBOOT to be connected to Vdd.

[0034] One or more N+ diffusion regions 404 can be formed in the N-well 402. The N+ diffusion regions 404 can be created by N-type diffusion in the vacancy regions of the N-well 402. The N+ diffusion regions 404 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 404 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can contact the N+ diffusion region 404 to connect the cathode of diode DBOOT (e.g., N-well 402) to capacitor CBOOT.

[0035] Figure 5 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 5 The description can be found here. Figure 1 and Figure 4 The components shown in the image. Figure 5In the embodiments shown, one or more planar Schottky diodes can be used to implement bootstrap diodes (e.g., DBOOT), and one or more planar MOS capacitors can be used to implement bootstrap capacitors (e.g., CBOOT). Figure 5 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 5 The example shown illustrates an N-well 502 that can be part of IC 116. The N-well 502 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 502 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 502 can also be an N-epitaxy layer. The N-well 502 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0036] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more trench capacitors. These one or more trench capacitors can be formed inside the N-well 502. The dielectric 506, electrode 508, and N-well 502 can realize the trench capacitor. Figure 5 The embodiment shown depicts a trench capacitor, but any number of trench capacitors can be formed provided there is sufficient space in the N-well 502. In one or more embodiments, the N-well 502 can serve as one of the conductive plates of the trench capacitor. The dielectric 506 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. The electrode 508 can be formed of, for example, a highly conductive material (such as doped polycrystalline silicon or a metal (e.g., aluminum, copper, etc.)). In one embodiment, the dielectric 506 can have a thickness that depends on the voltage Vdd. For example, the thickness of the dielectric 506 increases with increasing Vdd, such that the capacitor CBOOT can be thick enough to block voltages greater than Vdd. In one embodiment, the vertical depth of the trench capacitor can be less than the vertical depth of the N-well region 502. (Refer to...) Figure 1 Node N1 can contact electrode 508. Compared to embodiments using planar capacitors, trench capacitors can reduce the amount of surface area occupied by capacitor components on the surface of IC 116, and the three-dimensional (3D) nature of trench capacitors can provide more capacitance per unit area on the surface of IC 116.

[0037] A planar Schottky diode (DBOOT) can be implemented using one or more planar Schottky diodes. To create a planar Schottky diode, one or more metal contacts 512 can be formed on an N-well 502. The metal contacts 512 can be Schottky contacts, which can be metal-semiconductor contacts that create a Schottky barrier with an N-type semiconductor (such as N-well 502). In one or more embodiments, the metal contacts 512 can be titanium, cobalt, or platinum contacts. On one hand, a Schottky barrier is formed when the metal contacts an N-type semiconductor and the work function of the metal (e.g., the minimum energy required to extract an electron) is greater than the work function of the N-type semiconductor. Therefore, the work function of the material forming the metal contacts 512 is greater than the work function of the material forming the N-well 502. The metal contacts 512 can be used as the anode of the DBOOT diode, and the N-well 502 can be used as the cathode of the DBOOT diode. (Refer to...) Figure 1 Node N3 can contact the metal contact 512, allowing the anode of diode DBOOT to be connected to Vdd.

[0038] One or more N+ diffusion regions 504 can be formed in the N-well 502. The N+ diffusion regions 504 can be created by N-type diffusion in the vacancy regions of the N-well 502. The N+ diffusion regions 504 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 504 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can be in contact with N+ diffusion region 504 to connect the cathode of diode DBOOT (e.g., N-well 502) to capacitor CBOOT.

[0039] Figure 6 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 6 The description can be found here. Figure 1 and Figure 5 The components shown in the image. Figure 6 In the embodiments shown, one or more trench-type Schottky diodes can be used to implement bootstrap diodes (e.g., DBOOT), and one or more trench-type MOS capacitors can be used to implement bootstrap capacitors (e.g., CBOOT). Figure 6 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 6The example shown illustrates an N-well 602 that can be part of IC 116. The N-well 602 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 602 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 602 can also be an N-epitaxial layer. The N-well 602 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0040] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more trench capacitors. These trench capacitors can be formed inside the N-well 602. The dielectric 606, electrode 608, and N-well 602 can realize the trench capacitor. Figure 6 In the embodiment shown, two trench capacitors are illustrated, but any number of trench capacitors can be formed as long as there is sufficient space in the N-well 602. In one or more embodiments, the N-well 602 can be used as one of the conductive plates of the trench capacitor. The dielectric 606 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. The electrode 608 can be formed of, for example, a highly conductive material (such as doped polycrystalline silicon or a metal (e.g., aluminum, copper, etc.)). In one embodiment, the dielectric 606 can have a thickness that depends on the voltage Vdd. For example, the thickness of the dielectric 606 increases with increasing Vdd, such that the capacitor CBOOT can be thick enough to block voltages greater than Vdd. See also... Figure 1 Node N1 can contact electrode 608. Compared to embodiments using planar capacitors, trench capacitors can reduce the amount of surface area occupied by capacitor components on the surface of IC 116, and the three-dimensional (3D) nature of trench capacitors can provide more capacitance per unit area on the surface of IC 116.

[0041] A DBOOT diode can be implemented using one or more trench Schottky diodes. To create a trench Schottky diode, one or more metal contacts 612 can be formed in the vacant regions or openings of the N-well 602. The metal contacts 612 can be Schottky contacts, which can be metal-semiconductor contacts that create a Schottky barrier with an N-type semiconductor (such as the N-well 602). In one or more embodiments, the metal contacts 612 can be titanium, cobalt, or platinum contacts. On one hand, a Schottky barrier is formed when the metal contacts the N-type semiconductor and the work function of the metal (e.g., the minimum energy required to extract an electron) is greater than the work function of the N-type semiconductor. Therefore, the work function of the material forming the metal contacts 612 is greater than the work function of the material forming the N-well 602. The metal contacts 612 can be used as the anode of the DBOOT diode, and the N-well 602 can be used as the cathode of the DBOOT diode. (Refer to...) Figure 1 Node N3 can contact the metal contact 612, allowing the anode of diode DBOOT to be connected to Vdd. The depth of the Schottky trench or metal contact 612 can be similar to or different from the depth of the trench capacitor or electrode 608.

[0042] One or more N+ diffusion regions 604 can be formed in the N-well 602. The N+ diffusion regions 604 can be created by N-type diffusion in the vacancy regions of the N-well 602. The N+ diffusion regions 604 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 604 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can contact the N+ diffusion region 604 to connect the cathode of diode DBOOT (e.g., N-well 602) to capacitor CBOOT.

[0043] Figure 7 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 7 The description can be found here. Figure 1 and Figure 6 The components shown in the image. Figure 7 In the embodiments shown, one or more trench-type MOS barrier Schottky diodes can be used to implement bootstrap diodes (e.g., DBOOT), and one or more trench-type MOS capacitors can be used to implement bootstrap capacitors (e.g., CBOOT). Figure 7 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 7The example shown illustrates an N-well 702 that can be part of IC 116. The N-well 702 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 702 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 702 can also be an N-epitaxial layer. The N-well 702 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0044] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more trench capacitors. One or more trench capacitors can be formed in the vacant regions or openings of the N-well 702. The dielectric 706, electrode 708, and N-well 702 can realize the trench capacitor. Figure 7 In the embodiment shown, three trench capacitors are illustrated, but any number of trench capacitors can be formed as long as there is sufficient space in the N-well 702. In one or more embodiments, the N-well 702 can be used as one of the conductive plates of the trench capacitor. The dielectric 706 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. The electrode 708 can be formed of, for example, a highly conductive material (such as doped polycrystalline silicon or a metal (e.g., aluminum, copper, etc.)). In one embodiment, the dielectric 706 can have a thickness that depends on the voltage Vdd. For example, the thickness of the dielectric 706 increases with increasing Vdd, such that the capacitor CBOOT can be thick enough to block voltages greater than Vdd. See also... Figure 1 Node N1 can contact electrode 708. Compared to embodiments using planar capacitors, trench capacitors can reduce the amount of surface area occupied by capacitor components on the surface of IC 116, and the three-dimensional (3D) nature of trench capacitors can provide more capacitance per unit area on the surface of IC 116.

[0045] exist Figure 7In the embodiment shown, the diode DBOOT can be implemented by one or more trench-type metal-oxide-semiconductor (MOS) barrier Schottky (TMBS) diodes. To create the TMBS diode, trench capacitors formed by dielectric 706 and electrodes 708 are spaced apart by an equal distance W, where the distance W can be predefined based on one or more specific criteria. One or more metal contacts 712 can be formed on the N-well 702 and above the space between the trench capacitors. In one embodiment, the distance W can be predefined by selecting a value that causes the trench capacitors separated by the interval W to create a depletion-type MOS field-effect transistor (depletion-type MOSFET) below the P+ diffusion region 710 to increase the diode breakdown voltage while reducing the surface area occupied by DBOOT on the N-well 702. The P+ diffusion region 710 and the depletion-type MOSFET formed below the metal contacts 712 and N-well 702 can form the TMBS diode.

[0046] The metal contact 712 may be a Schottky contact, which can be a metal-semiconductor contact that creates a Schottky barrier with an N-type semiconductor (such as N-well 702). In one or more embodiments, the metal contact 712 may be a titanium, cobalt, or platinum contact. In one aspect, a Schottky barrier is formed when the metal contacts the N-type semiconductor and the work function of the metal (e.g., the minimum energy required to extract an electron) is greater than the work function of the N-type semiconductor. Therefore, the work function of the material forming the metal contact 712 is greater than the work function of the material forming the N-well 702. The metal contact 712 can be used as the anode of a diode DBOOT, and the N-well 702 can be used as the cathode of the diode DBOOT. (Refer to...) Figure 1 Node N3 can contact the metal contact 712, allowing the anode of diode DBOOT to be connected to Vdd.

[0047] One or more N+ diffusion regions 704 can be formed in the N-well 702. The N+ diffusion regions 704 can be created by N-type diffusion in the vacancy regions of the N-well 702. The N+ diffusion regions 704 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 704 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can contact the N+ diffusion region 704 to connect the cathode of diode DBOOT (e.g., N-well 702) to capacitor CBOOT.

[0048] Figure 8 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 8 The description can be found here. Figure 1 and Figure 7 The components shown in the image. Figure 8In the embodiments shown, one or more trench-type MOS barrier PN diodes can be implemented as bootstrap diodes (e.g., DBOOT), and one or more trench-type MOS capacitors can be implemented as bootstrap capacitors (e.g., CBOOT). Figure 8 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 8 The example shown illustrates an N-well 802 that can be part of IC 116. The N-well 802 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 802 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 802 can also be an N-epitaxial layer. The N-well 802 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0049] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more trench capacitors. One or more trench capacitors can be formed in the vacant regions or openings of the N-well 802. The dielectric 806, electrode 808, and N-well 802 can realize the trench capacitor. Figure 8 In the embodiment shown, three trench capacitors are illustrated, but any number of trench capacitors can be formed provided there is sufficient space in the N-well 802. The dielectric 806 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thus allowing for higher capacitance values ​​in smaller device sizes. The electrode 808 can be formed of, for example, a highly conductive material (such as doped polycrystalline silicon or a metal (e.g., aluminum, copper, etc.)). In one embodiment, the dielectric 806 can have a thickness that depends on the voltage Vdd. For example, the thickness of the dielectric 806 increases with increasing Vdd, allowing the capacitor CBOOT to be thick enough to block voltages greater than Vdd. (See reference...) Figure 1 Node N1 can contact electrode 808. Compared to embodiments using planar capacitors, trench capacitors can reduce the amount of surface area occupied by capacitor components on the surface of IC 116, and the three-dimensional (3D) nature of trench capacitors can provide more capacitance per unit area on the surface of IC 116.

[0050] exist Figure 8In the embodiment shown, the diode DBOOT can be implemented by one or more trench-type metal-oxide-semiconductor (MOS) barrier PN (TMBPN) diodes. To create the TMBPN diode, trench capacitors formed by dielectric 806 and electrodes 808 are spaced apart by an equal distance W, where the distance W can be predefined based on one or more specific criteria. One or more P+ diffusion regions 810 can be created by P-type diffusion in vacant regions of the N-well 802 within the space defined by the distance W. The P+ diffusion regions 810 can be formed of a doped material such as aluminum, boron, or gallium. By forming the P+ diffusion regions 810 in the N-well 802, a PN junction can be formed between the P+ diffusion regions 810 and the N-well 802. One or more ohmic contacts 812 can be formed on top of the P+ diffusion regions 810 to connect the TMBPN diode to node N3. In one embodiment, the distance W can be predefined by selecting a value that allows trench capacitors separated by a gap W to create a depletion-type MOS field-effect transistor (depletion-type MOSFET) below the P+ diffusion region 810 to increase the diode breakdown voltage while reducing the surface area occupied by the DBOOT on the N-well 802. The P+ diffusion region 810 and the depletion-type MOSFET formed below the metal contact 812 and the N-well 802 can form a TMBPN diode. (Refer to...) Figure 1 Node N3 can contact contact 812, allowing the anode of diode DBOOT to be connected to Vdd.

[0051] One or more N+ diffusion regions 804 can be formed in the N-well 802. The N+ diffusion regions 804 can be created by N-type diffusion in the vacancy regions of the N-well 802. The N+ diffusion regions 804 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 804 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can contact the N+ diffusion region 804 to connect the cathode of diode DBOOT (e.g., N-well 802) to capacitor CBOOT.

[0052] Figure 9 This is a cross-sectional view illustrating another embodiment of an integrated bootstrap circuit. Figure 9 The description can be found here. Figure 1 and Figure 8 The components shown in the image. Figure 9 In the embodiments shown, one or more trench-type MOS junction barrier Schottky diodes can be used to implement bootstrap diodes (e.g., DBOOT), and one or more trench MOS capacitors can be used to implement bootstrap capacitors (e.g., CBOOT). Figure 9 The image shows a cross-sectional view of a portion of IC 116, including DBOOT and CBOOT. Figure 9The example shown illustrates an N-well 902 that can be part of IC 116. The N-well 902 can be formed in an open substrate surface region (e.g., an opening or trench) in a P-type substrate (e.g., a substrate made of P-type silicon), which can be the substrate of IC 116, using techniques such as diffusion or ion implantation. In one or more embodiments, the N-well 902 can be formed by implanting dopant atoms (such as phosphorus or arsenic). In some embodiments, the N-well 902 can also be an N-epitaxial layer. The N-well 902 can isolate bootstrap circuit components (such as CBOOT and DBOOT) from the rest of IC 116.

[0053] Figure 1 The bootstrap capacitor CBOOT shown can be implemented by one or more trench capacitors. One or more trench capacitors can be formed in the vacant regions or openings of the N-well 902. The dielectric 906, electrode 908, and N-well 902 can realize the trench capacitor. Figure 9 In the embodiment shown, three trench capacitors are illustrated, but any number of trench capacitors can be formed as long as there is sufficient space in the N-well 902. In one or more embodiments, the N-well 902 can be used as one of the conductive plates of the trench capacitor. The dielectric 906 can be formed of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or various high-k dielectrics (such as hafnium dioxide (HfO2), aluminum oxide (Al2O3)). Note that high-k dielectrics can increase the capacitance per unit area, thereby allowing for higher capacitance values ​​in smaller device sizes. The electrode 908 can be formed of, for example, a highly conductive material (such as doped polycrystalline silicon or a metal (e.g., aluminum, copper, etc.)). In one embodiment, the dielectric 906 can have a thickness that depends on the voltage Vdd. For example, the thickness of the dielectric 906 increases with increasing Vdd, such that the capacitor CBOOT can be thick enough to block voltages greater than Vdd. (See also...) Figure 1 Node N1 can contact electrode 908. Compared to embodiments using planar capacitors, trench capacitors can reduce the amount of surface area occupied by capacitor components on the surface of IC 116, and the three-dimensional (3D) nature of trench capacitors can provide more capacitance per unit area on the surface of IC 116.

[0054] exist Figure 9In the embodiment shown, the diode DBOOT can be implemented by one or more trench metal-oxide-semiconductor (MOS) barrier junction Schottky (TMBJBS) diodes. One or more P+ diffusion regions 910 can be created by P-type diffusion within an N-well 902 defined by a distance W, where the distance W can be predefined based on one or more specific criteria. The P+ diffusion region 910 can be formed of a doped material such as aluminum, boron, or gallium. By forming the P+ diffusion region 910 in the N-well 902, a PN junction can be formed between the P+ diffusion region 910 and the N-well 902. After forming the P-type diffusion region 910, one or more metal contacts 912 can be formed across the N-well 902 and the P-type diffusion region 910. The metal contacts 912 can be ohms on top of the P-type diffusion region 910 and form a PN junction diode and a Schottky diode on top of the N-well 902. One or more metal contacts 912 can be formed on top of the P+ diffusion region 910. The P+ diffusion region 910 can be configured such that the metal contact 912 can contact the N-well 902. In one embodiment, a distance W can be predefined by selecting a value that allows trench capacitors separated by a gap W to create a depletion-type MOS field-effect transistor (depletion-type MOSFET) below the P+ diffusion region 910 to increase the diode breakdown voltage while reducing the surface area occupied by the DBOOT on the N-well 902. The P+ diffusion region 910 and the depletion-type MOSFET formed below the metal contact 912 and the N-well 902 can form a TMJBS diode. By forming the P+ diffusion region 910 in the N-well 902, a PN junction can surround the Schottky diode formed by the metal contact 912 and the N-well 902. The spacing between the P+ diffusion regions 910 can be defined to optimize blocking and conduction.

[0055] The metal contact 912 may be a Schottky contact, which can be a metal-semiconductor contact that creates a Schottky barrier with an N-type semiconductor (such as N-well 902). In one or more embodiments, the metal contact 912 may be a titanium, cobalt, or platinum contact. In one aspect, a Schottky barrier is formed when the metal contacts the N-type semiconductor and the work function of the metal (e.g., the minimum energy required to extract an electron) is greater than the work function of the N-type semiconductor. Therefore, the work function of the material forming the metal contact 912 is greater than the work function of the material forming the N-well 902. The metal contact 912 can be used as the anode of a diode DBOOT, and the N-well 902 can be used as the cathode of the diode DBOOT. (See also...) Figure 1 Node N3 can contact the metal contact 912, allowing the anode of diode DBOOT to be connected to Vdd.

[0056] One or more N+ diffusion regions 904 can be formed in the N-well 902. The N+ diffusion regions 904 can be created by N-type diffusion in the vacancy regions of the N-well 902. The N+ diffusion regions 904 can be formed of a doped material (such as nitrogen, phosphorus, or arsenic). The N+ diffusion regions 904 can be used as contacts with other components. (See reference...) Figure 1 Node N2 can be contacted with N+ diffusion region 904 to connect the cathode of diode DBOOT (e.g., N-well 902) to capacitor CBOOT.

[0057] In one embodiment, the IC package 1000 including IC 116 may be a monolithic IC including a voltage regulator and a bootstrap circuit, the bootstrap circuit including a bootstrap capacitor CBOOT and a bootstrap diode DBOOT, such as Figures 1 to 9 As shown in the diagram. By including a bootstrap capacitor CBOOT and a bootstrap diode DBOOT in IC 116, it is not necessary to use pins to connect discrete capacitors and diodes to the voltage regulator IC in the IC package.

[0058] Among the various embodiments illustrated herein, those utilizing planar capacitors are relatively easy to manufacture because planar capacitor manufacturing technologies are generally readily available. Furthermore, the manufacture of planar capacitors can utilize gate-level oxides, which does not introduce additional process complexity, thus providing relatively high-quality capacitors. In some examples, if IC116 does not have sufficient surface area, the number and size of planar capacitors can be limited, resulting in limited capacitance. Embodiments utilizing trench capacitors can provide higher capacitance per unit area compared to planar capacitors. Trench capacitors can be relatively more complex to manufacture and may also have higher wafer costs compared to planar capacitors. Therefore, the various embodiments presented herein provide the flexibility to integrate bootstrap circuitry with voltage regulators in a single IC package. Integrating bootstrap circuitry with voltage regulators in a single IC package preserves board area on the PCB and allows for higher capacitance in the bootstrap circuitry while using the same board area as conventional systems utilizing discrete bootstrap circuitry.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or variations thereof, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0060] All means or steps plus functional elements (if any) in the following claims are intended to include corresponding structures, materials, actions, and equivalents that perform a function in combination with other claimed elements. Embodiments of the disclosed invention have been shown for illustrative and descriptive purposes, but these embodiments are not intended to be exclusive or limited to the disclosed forms of the invention. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described to best explain the principles and practical application of the invention and to enable others skilled in the art to understand that the invention has various embodiments with various modifications suitable for the particular intended use.

Claims

1. An integrated circuit, comprising: Power stage; A driver configured to drive the power stage; A bootstrap circuit, configured to drive the high-side switch in the power stage during startup, includes a capacitor and a diode, wherein: The power stage, the driver, and the bootstrap circuit are integrated on the same silicon. The capacitor is implemented by at least one of a planar capacitor and a trench capacitor; and The diode is implemented by at least one of a planar diode and a trench diode.

2. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one planar capacitor; and The diode is implemented by at least one planar diode including a PN junction diode.

3. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one planar capacitor; and The diode is implemented by at least one planar diode, including a Schottky diode.

4. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one planar capacitor; and The diode is implemented by at least one planar diode, including a junction barrier Schottky diode.

5. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one planar diode including a PN junction diode.

6. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench diode, including a trench Schottky diode.

7. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench metal-oxide-semiconductor barrier Schottky diode.

8. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench metal-oxide-semiconductor barrier PN junction diode.

9. The integrated circuit according to claim 1, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench metal-oxide-semiconductor junction barrier Schottky diode.

10. A voltage regulator, comprising: integrated circuit; A controller configured to control the integrated circuit; The integrated circuit includes: Power stage; A driver configured to drive the power stage; A bootstrap circuit, configured to drive the high-side switch in the power stage during startup, includes a capacitor and a diode, wherein: The power stage, the driver, and the bootstrap circuit are integrated on the same silicon. The capacitor is implemented by at least one of a planar capacitor and a trench capacitor; and The diode is implemented by at least one of a planar diode and a trench diode.

11. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one planar capacitor; and The diode is implemented by at least one planar diode including a PN junction diode.

12. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one planar capacitor; and The diode is implemented by at least one planar diode, including a Schottky diode.

13. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one planar capacitor; and The diode is implemented by at least one planar diode, including a junction barrier Schottky diode.

14. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one planar diode including a PN junction diode.

15. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench diode, including a trench Schottky diode.

16. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench metal-oxide-semiconductor barrier Schottky diode.

17. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench metal-oxide-semiconductor barrier PN junction diode.

18. The voltage regulator according to claim 10, wherein: The capacitor is implemented by at least one trench capacitor; and The diode is implemented by at least one trench metal-oxide-semiconductor junction barrier Schottky diode.

19. An integrated circuit, comprising: Power stage; A driver configured to drive the power stage; A bootstrap circuit, configured to drive the high-side switch in the power stage during startup, includes a capacitor and a diode, wherein: The power stage, the driver, and the bootstrap circuit are integrated on the same silicon. as well as The capacitor is implemented by at least one trench capacitor.

20. The integrated circuit of claim 19, wherein the diode is implemented by at least one of a planar diode and a trench diode.

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