A timing calibration method and a timing calibration system

Abstract

The embodiment of the application discloses a timing calibration method and a timing calibration system. The timing calibration method is applied to a digital-to-analog converter, the digital-to-analog converter comprises a plurality of sub digital-to-analog converters, the timing calibration system of the digital-to-analog converter comprises a host computer, a plurality of timing calibration subsystems corresponding to the plurality of sub digital-to-analog converters one by one, the timing calibration subsystem comprises a delay adjustable unit, a sampling unit, a flip-flop and a register, and the timing calibration method is executed by the host computer. The timing calibration method comprises the following steps: receiving a control instruction; controlling the sub digital-to-analog converter to continuously output high and low levels according to the control instruction, and reading data output by the sub digital-to-analog converter multiple times; determining a delay duration of the delay adjustable unit based on the data read multiple times, so as to calibrate the timing between the sub digital-to-analog converter and the sampling unit and the timing between the sub digital-to-analog converters. The timing calibration method and the timing calibration system provided by the embodiment of the application can realize timing calibration.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to timing calibration technology, and in particular to a timing calibration method and a timing calibration system. BACKGROUND

[0002] Timing of a device, such as timing of a digital-to-analog converter, is essential in the working process of the digital-to-analog converter. The digital-to-analog converter adopts multiple sub digital-to-analog converters to improve the overall conversion rate. If there is a deviation in the timing of each sub digital-to-analog converter, the output waveform result of the digital-to-analog converter will be affected. Therefore, it is necessary to calibrate the output timing of each sub digital-to-analog converter in the digital-to-analog converter. SUMMARY

[0003] Embodiments of the present application provide a timing calibration method and a timing calibration system to realize timing calibration.

[0004] In a first aspect, embodiments of the present application provide a timing calibration method, which is applied to a digital-to-analog converter, the digital-to-analog converter includes multiple sub digital-to-analog converters, a timing calibration system of the digital-to-analog converter includes a host computer and multiple timing calibration subsystems corresponding to the multiple sub digital-to-analog converters one by one, the timing calibration subsystem includes a delay adjustable unit, a sampling unit, a flip-flop, and a register, the sub digital-to-analog converter, the delay adjustable unit, the register, and the host computer are electrically connected in sequence, the sub digital-to-analog converter, the sampling unit, the flip-flop, and the register are electrically connected in sequence, the delay adjustable unit is electrically connected with the sampling unit, and the timing calibration method is executed by the host computer; the timing calibration method includes:

[0005] receiving a control instruction;

[0006] controlling the sub digital-to-analog converter to continuously output high and low levels according to the control instruction, and reading data output by the sub digital-to-analog converter multiple times;

[0007] determining a delay duration of the delay adjustable unit based on the data read multiple times, so as to calibrate timing between the sub digital-to-analog converter and the sampling unit, and timing between each of the sub digital-to-analog converters.

[0008] Optionally, the delay adjustable unit includes a first delay adjustable sub-unit and a second delay adjustable sub-unit, the first delay adjustable sub-unit, the second delay adjustable sub-unit, and the sub digital-to-analog converter are electrically connected in sequence, the first delay adjustable sub-unit is electrically connected with the sampling unit, and the first delay adjustable sub-unit and the second delay adjustable sub-unit are both electrically connected with the register.

[0009] determining a delay duration of the second delay adjustable sub-unit based on the average value, so as to calibrate a timing between the sub-digital-to-analog converters and the sampling unit.

[0010] determining an average value of the multiple read data according to the multiple read data;

[0011] determining a delay duration of the second delay adjustable sub-unit based on the average value, so as to calibrate a timing between the sub-digital-to-analog converters and the sampling unit.

[0012] Optionally, the multiple read data is read when the delay duration of the second delay adjustable sub-unit is controlled to be a preset minimum duration.

[0013] determining a delay duration of the second delay adjustable sub-unit based on the average value, so as to calibrate a timing between the sub-digital-to-analog converters and the sampling unit.

[0014] the delay duration of the second delay adjustable sub-unit is gradually increased by a preset step size from the preset minimum duration;

[0015] when the delay duration is increased by the preset step size each time, the operation of reading data multiple times is repeated to obtain the average value of the multiple read data, until the delay duration of the second delay adjustable sub-unit reaches a preset maximum duration, and multiple average values are obtained.

[0016] determining the delay duration of the second delay adjustable sub-unit according to the multiple average values.

[0017] Optionally, after the delay duration of the second delay adjustable sub-unit is determined, the method further comprises:

[0018] adjusting the delay duration of the first delay adjustable sub-unit of each sub-digital-to-analog converter according to a waveform output by each sub-digital-to-analog converter, so as to calibrate a timing between the sub-digital-to-analog converters.

[0019] Optionally, the average value is within a range of 0-1.

[0020] Optionally, the preset minimum duration is greater than zero and less than a preset threshold value, a time corresponding to a rising edge of a clock signal of the second delay adjustable sub-unit is a first time, a time corresponding to a falling edge of the clock signal is a second time, and the preset threshold value is a smaller one of the first time and the second time.

[0021] In a second aspect, an embodiment of the present application provides a timing calibration system, which is a timing calibration system of a digital-to-analog converter, the digital-to-analog converter comprising a plurality of sub digital-to-analog converters, the timing calibration system comprising: a host computer, a plurality of timing calibration subsystems corresponding to the plurality of sub digital-to-analog converters one by one, the timing calibration subsystem comprising a delay adjustable unit, a sampling unit, a flip-flop, and a register, the sub digital-to-analog converter, the delay adjustable unit, the register, and the host computer being electrically connected in sequence, the sub digital-to-analog converter, the sampling unit, the flip-flop, and the register being electrically connected in sequence, the delay adjustable unit being electrically connected to the sampling unit, and the timing calibration method of the first aspect being executed by the host computer.

[0022] Optionally, the delay adjustable unit comprises a first delay adjustable subunit and a second delay adjustable subunit, the first delay adjustable subunit, the second delay adjustable subunit, and the sub digital-to-analog converter being electrically connected in sequence, the first delay adjustable subunit being electrically connected to the sampling unit, and the first delay adjustable subunit and the second delay adjustable subunit both being electrically connected to the register.

[0023] Optionally, the first delay adjustable subunit and the second delay adjustable subunit are of the same structure, the first delay adjustable subunit comprising a buffer and a plurality of switches, and an output end of the buffer being electrically connected to the plurality of switches.

[0024] Optionally, the first delay adjustable subunit further comprises a current source, and the current source is electrically connected to the switches.

[0025] The timing calibration method and the timing calibration system provided by the embodiment of the present application are applied to a digital-to-analog converter, the digital-to-analog converter comprising a plurality of sub digital-to-analog converters, a timing calibration system of the digital-to-analog converter comprising a host computer and a plurality of timing calibration subsystems corresponding to the plurality of sub digital-to-analog converters one by one, the timing calibration subsystem comprising a delay adjustable unit, a sampling unit, a flip-flop, and a register, the sub digital-to-analog converter, the delay adjustable unit, the register, and the host computer being electrically connected in sequence, the sub digital-to-analog converter, the sampling unit, the flip-flop, and the register being electrically connected in sequence, the delay adjustable unit being electrically connected to the sampling unit, and the timing calibration method being executed by the host computer; the timing calibration method comprising: receiving a control instruction; controlling the sub digital-to-analog converter to continuously output high and low levels according to the control instruction, and reading data output by the sub digital-to-analog converter multiple times; determining a delay duration of the delay adjustable unit based on the data read multiple times, so as to calibrate the timing between the sub digital-to-analog converter and the sampling unit, and the timing between the plurality of sub digital-to-analog converters. The timing calibration method and the timing calibration system provided by the embodiment of the present application achieve timing calibration by controlling the sub digital-to-analog converter to continuously output high and low levels, reading data output by the sub digital-to-analog converter multiple times, and determining the delay duration of the delay adjustable unit based on the data read multiple times. Attached Figure Description

[0026] Figure 1 This is a flowchart of a timing calibration method provided in Embodiment 1 of the present invention;

[0027] Figure 2 This is a schematic diagram of an average value variation curve provided in Embodiment 1 of the present invention;

[0028] Figure 3 This is a schematic diagram of another average value change curve provided in Embodiment 1 of the present invention;

[0029] Figure 4 This is a flowchart of a timing calibration method provided in Embodiment 2 of the present invention;

[0030] Figure 5 This is a flowchart of another timing calibration method provided in Embodiment 2 of the present invention;

[0031] Figure 6 This is a schematic diagram of the structure of a timing calibration system provided in Embodiment 3 of the present invention;

[0032] Figure 7 This is a schematic diagram of the structure of a delay-adjustable subunit provided in Embodiment 3 of the present invention. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0034] Example 1

[0035] Figure 1 This is a flowchart of a timing calibration method provided in Embodiment 1 of the present invention. This embodiment can be applied to timing calibration of digital-to-analog converters (DACs), etc. The DAC includes multiple sub-DACs. The timing calibration system of the DAC includes a host computer and multiple timing calibration subsystems corresponding one-to-one with the multiple sub-DACs. The timing calibration subsystem includes a delay-adjustable unit, a sampling unit, a trigger, and a register. The sub-DACs, the delay-adjustable unit, the register, and the host computer are electrically connected in sequence. The delay-adjustable unit is electrically connected to the sampling unit. The timing calibration method is executed by the host computer. The timing calibration method specifically includes the following steps:

[0036] Step 110: Receive control commands.

[0037] The control instruction can be inputted to the host computer from outside, and the control instruction can be a signal instruction requiring timing calibration.

[0038] In step 120, the sub-digital-to-analog converter is controlled to continuously output high and low levels according to the control instruction, and the data outputted by the sub-digital-to-analog converter is read multiple times.

[0039] Specifically, the sub-digital-to-analog converter is calibrated in timing by the corresponding timing calibration subsystem and the host computer, and the sub-digital-to-analog converter is electrically connected to the corresponding timing calibration subsystem. The host computer can be communicatively connected to the input end of each sub-digital-to-analog converter through an interface such as a high-speed serial interface, to control the sub-digital-to-analog converter to continuously output a high and low level signal such as 01010101, which has a stable timing relationship with the working clock of the corresponding sampling unit of the sub-digital-to-analog converter.

[0040] In step 130, the delay duration of the delay adjustable unit is determined based on the data read multiple times, to calibrate the timing between the sub-digital-to-analog converter and the sampling unit, and the timing between each sub-digital-to-analog converter.

[0041] For example, the data read multiple times can be data read thousands of times. According to the data read multiple times, the average value of the data read multiple times is determined, for example, the host computer reads data one thousand times, and determines the average value of the data read one thousand times. If the data read each time is 1, the average value is 1, if the data read each time is 0, the average value is 0, if five hundred times of data read is 1 and five hundred times of data read is 0, the average value is 0.5. The control word of the delay adjustable unit is determined based on the average value, and the control word of the delay adjustable unit has a corresponding relationship with the delay duration of the delay adjustable unit.

[0042] Figure 2 is a schematic diagram of an average value change curve provided by the first embodiment of the present application, Figure 3 is a schematic diagram of another average value change curve provided by the first embodiment of the present application. Referring to Figure 2 and Figure 3, the average value ranges from 0 to 1, when the opening time of the sampling unit, that is, the sampling time, is in the time region of the stable low level output of the corresponding sub-digital-to-analog converter, the obtained average value is 0; if the opening time of the sampling unit is in the time region of the stable high level output of the corresponding sub-digital-to-analog converter, the obtained average value is 1; if the opening time of the sampling unit is in the high-low level conversion edge of the corresponding sub-digital-to-analog converter, due to the influence of clock jitter and metastability and other factors, the closer the opening time of the sampling unit to the high level region, the larger the average value, and the closer the opening time of the sampling unit to the low level region, the smaller the average value. For example, when the opening time of the sampling unit is in the corresponding sub-digital-to-analog converter output signal conversion from low level to high level, the control word of the delay adjustable unit corresponds to the converted high level region in the range of 1.5-2; when the opening time of the sampling unit is in the corresponding sub-digital-to-analog converter output signal conversion from high level to low level, the control word of the delay adjustable unit corresponds to the converted low level region in the range of 1.5-2. According to the relationship between the average value and the control word, the delay duration of the delay adjustable unit is adjusted to calibrate the timing between the sub-digital-to-analog converter and the corresponding sampling unit, and the timing between each sub-digital-to-analog converter.

[0043] The timing calibration method provided by the embodiment comprises: receiving a control instruction; controlling the sub-digital-to-analog converter to continuously output high and low levels according to the control instruction, and reading the data output by the sub-digital-to-analog converter multiple times; determining the delay duration of the delay adjustable unit based on the data read multiple times to calibrate the timing between the sub-digital-to-analog converter and the sampling unit, and the timing between each sub-digital-to-analog converter. The timing calibration method provided by the embodiment controls the sub-digital-to-analog converter to continuously output high and low levels, and reads the data output by the sub-digital-to-analog converter multiple times; determines the delay duration of the delay adjustable unit based on the data read multiple times, thereby realizing timing calibration.

[0044] Embodiment two

[0045] Figure 4 is a flowchart of a timing calibration method provided by the embodiment two of the application, the embodiment can be applicable to timing calibration of a digital-to-analog converter and the like, the digital-to-analog converter comprises a plurality of sub-digital-to-analog converters, a timing calibration system of the digital-to-analog converter comprises an upper computer and a plurality of timing calibration subsystems corresponding to the plurality of sub-digital-to-analog converters one by one, the timing calibration subsystem comprises a delay adjustable unit, a sampling unit, a flip-flop, a register, the sub-digital-to-analog converter, the delay adjustable unit, the register and the upper computer are electrically connected in sequence, the sub-digital-to-analog converter, the sampling unit, the flip-flop and the register are electrically connected in sequence, the delay adjustable unit is electrically connected with the sampling unit, and the timing calibration method is executed by the upper computer; the timing calibration method specifically comprises the following steps:

[0046] Step 210, receiving a control instruction.

[0047] The control instruction can be inputted from outside to the host computer, and the control instruction can be a signal instruction requiring timing calibration.

[0048] In an embodiment, the delay adjustable unit comprises a first delay adjustable sub-unit and a second delay adjustable sub-unit, the first delay adjustable sub-unit, the second delay adjustable sub-unit and the sub-digital-to-analog converter are electrically connected in sequence, the first delay adjustable sub-unit is electrically connected with the sampling unit, and the first delay adjustable sub-unit and the second delay adjustable sub-unit are both electrically connected with the register.

[0049] In step 220, according to the control instruction, the sub-digital-to-analog converter is controlled to continuously output high and low levels, and the data outputted by the sub-digital-to-analog converter is read multiple times.

[0050] Specifically, the sub-digital-to-analog converter is calibrated in timing by the corresponding timing calibration subsystem and the host computer, and the sub-digital-to-analog converter is electrically connected with the corresponding timing calibration subsystem. The host computer can be in communication connection with the input end of each sub-digital-to-analog converter through an interface such as a high-speed serial interface, so as to control the sub-digital-to-analog converter to continuously output a high and low level signal, i.e. 01010101, which has a stable timing relationship with the working clock of the corresponding sampling unit of the sub-digital-to-analog converter.

[0051] In step 230, the average value of the data read multiple times is determined according to the data read multiple times.

[0052] Specifically, if the opening time of the sampling unit, i.e. the sampling time, is in the time region of the stable output low level of the corresponding sub-digital-to-analog converter, the average value obtained is 0; if the opening time of the sampling unit is in the time region of the stable output high level of the corresponding sub-digital-to-analog converter, the average value obtained is 1; if the opening time of the sampling unit is in the high-low level conversion edge of the corresponding sub-digital-to-analog converter, due to the influence of clock jitter and metastability and other factors, the closer the opening time of the sampling unit to the high level region, the larger the average value, and the closer the opening time of the sampling unit to the low level region, the smaller the average value. Exemplarily, if the data read each time is 1, the average value is 1, if the data read each time is 0, the average value is 0, if the data read M / 2 times (M is an even number) in M times of reading is 1, and the data read M / 2 times is 0, the average value is 0.5.

[0053] In step 240, the delay time length of the second delay adjustable sub-unit is gradually increased by a preset step length from the preset minimum time length.

[0054] In this system, the minimum preset duration is greater than zero and less than a preset threshold. The time corresponding to the rising edge of the clock signal of the second adjustable delay sub-unit is the first time, and the time corresponding to the falling edge of the clock signal is the second time. The preset threshold is the smaller of the first time and the second time. For example, when the first time is less than the second time, the preset threshold is the first time, i.e., the time corresponding to the rising edge of the clock signal. When the second time is less than the first time, the preset threshold is the second time, i.e., the time corresponding to the falling edge of the clock signal.

[0055] Step 250: Repeat the data reading operation multiple times as the delay time increases by a preset step size, and obtain the average value of the data read multiple times until the delay time of the second delay adjustable subunit reaches the preset maximum time, and obtain multiple average values.

[0056] The average value ranges from 0 to 1. The delay duration of the second delay adjustable subunit is increased by a preset step size to obtain an average value.

[0057] Step 260: Determine the delay duration of the second delay adjustable subunit based on the various average values ​​to calibrate the timing between the sub-digital-to-analog converter and the corresponding sampling unit.

[0058] Specifically, the sampling unit is activated when the signal output from the corresponding digital-to-analog converter transitions from a low level to a high level, according to... Figure 2 The relationship between the average value and the control word of the delay-adjustable unit is shown. The control word can be determined by the average value. The host computer can adjust the delay duration of the delay-adjustable unit by controlling the control word of the delay-adjustable unit, thereby calibrating the timing between the sub-digital-to-analog converter and the corresponding sampling unit.

[0059] Step 270: Based on the waveform output by the digital-to-analog converter, adjust the delay duration of the first delay adjustable sub-unit of each sub-digital-to-analog converter to calibrate the timing between each sub-digital-to-analog converter.

[0060] Specifically, after determining the delay duration of the second adjustable delay sub-unit, timing calibration is performed between the sub-digital-to-analog converters and their corresponding sampling units. This completes the timing calibration of each sub-digital-to-analog converter. Then, based on the overall output waveform of the digital-to-analog converter, the delay duration of the first adjustable delay sub-unit of each sub-digital-to-analog converter can be directly adjusted, thereby calibrating the timing between the sub-digital-to-analog converters. The overall output waveform of the digital-to-analog converter is derived from the combined output waveforms of each sub-digital-to-analog converter, and the timing errors between the sub-digital-to-analog converters are reflected in the overall output waveform of the digital-to-analog converter.

[0061] Figure 5 This is a flowchart of another timing calibration provided in Embodiment 2 of the present invention. (See reference) Figure 5The digital-to-analog converter includes K sub-digital-to-analog converters, k represents the kth sub-digital-to-analog converter, the range of the control word is 0-N, and M represents the maximum number of readings. Figure 5 The operation of determining the control word according to each average value, that is, the operation of step 260, and the operation of adjusting the delay duration according to the waveform output by each sub-DAC, that is, the operation of step 270, can be specifically referred to steps 210-270, and will not be described here again.

[0062] It should be noted that the sizes of the parameters in the embodiment can be determined according to actual timing calibration requirements, and are not limited here.

[0063] The timing calibration method provided in the embodiment controls the sub-digital-to-analog converter to continuously output high and low levels, and reads the data output by the sub-digital-to-analog converter multiple times; determines the average value of the data read multiple times according to the data read multiple times, determines the delay duration of the delay adjustable unit based on the average value, and realizes timing calibration by adjusting the delay duration of the delay adjustable unit.

[0064] Embodiment three

[0065] Figure 6 is a structural schematic diagram of a timing calibration system provided in embodiment three of the application. The timing calibration system is a timing calibration system of a digital-to-analog converter, which can be referred to Figure 6 The digital-to-analog converter includes a plurality of sub-digital-to-analog converters DAC, and the timing calibration system includes: an upper computer 10, a plurality of timing calibration subsystems 20 corresponding to the plurality of sub-digital-to-analog converters one by one, the timing calibration subsystem 20 including a delay adjustable unit 21, a sampling unit 22, a flip-flop 23, a register 24, the sub-digital-to-analog converter DAC, the delay adjustable unit 21, the register 24 and the upper computer 10 being electrically connected in sequence, the sub-digital-to-analog converter DAC, the sampling unit 22, the flip-flop 23, the register 24 being electrically connected in sequence, the delay adjustable unit 21 being electrically connected with the sampling unit 22, and the timing calibration method described in any embodiment of the application being executed by the upper computer.

[0066] Exemplarily, the digital-to-analog converter includes four sub-digital-to-analog converters DAC, and the timing calibration system includes four timing calibration subsystems 20, each sub-digital-to-analog converter DAC corresponding to one timing calibration subsystem 20, and the sub-digital-to-analog converter DAC being electrically connected with the delay adjustable unit 21, the sampling unit 22, the flip-flop 23 and the register 24 in the corresponding timing calibration subsystem 20. The digital-to-analog converter can be a time-interleaved digital-to-analog converter, and the specific process of timing calibration of the digital-to-analog converter by the upper computer can be referred to any embodiment described above, and will not be described here again.

[0067] It should be noted that the above digital-to-analog converter includes four sub-digital-to-analog converters, and the specific number of sub-digital-to-analog converters included in the digital-to-analog converter can be determined according to the actual needs of the digital-to-analog converter, and is not limited herein.

[0068] Optionally, the delay adjustable unit 21 includes a first delay adjustable sub-unit 201 and a second delay adjustable sub-unit 202, the first delay adjustable sub-unit 201, the second delay adjustable sub-unit 202 and the sub-digital-to-analog converter DAC are sequentially electrically connected, the first delay adjustable sub-unit 201 is electrically connected with the sampling unit 22, and the first delay adjustable sub-unit 201 and the second delay adjustable sub-unit 202 are both electrically connected with the register 24.

[0069] Specifically, the first delay adjustable sub-unit 201 can be electrically connected with the second delay adjustable sub-unit 202 through a buffer, and the first delay adjustable sub-unit 201 can be electrically connected with the sampling unit 22 through a buffer. The host computer 10 adjusts the delay duration of the second delay adjustable sub-unit 202 to calibrate the timing between the sub-digital-to-analog converter and the corresponding sampling unit 22, and then adjusts the delay duration of the first delay adjustable sub-unit 201 to calibrate the timing between the sub-digital-to-analog converters, and the specific process can refer to any of the above embodiments, which will not be repeated here.

[0070] Optionally, the first delay adjustable sub-unit 201 and the second delay adjustable sub-unit 202 are of the same structure, the first delay adjustable sub-unit 201 includes a buffer B and a plurality of switches, and the output end of the buffer D is electrically connected with the plurality of switches.

[0071] Specifically, the buffer B can be one or a plurality of cascades, or can be replaced by other delay circuits. Figure 7 is a structural schematic diagram of a delay adjustable sub-unit provided by the third embodiment of the present application. Referring to Figure 7The delay adjustable subunit comprises a buffer B and a plurality of switches, the switches comprise a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3, a fourth MOS tube Q4 and a plurality of groups of switches, each group of switches comprises two MOS tubes. One input end of the buffer B inputs a first positive signal VI1+, another input end of the buffer B inputs a first negative signal VI1-, one output end of the buffer B outputs a second positive signal VI2+, and another output end of the buffer B outputs a second negative signal VI2-. The gate of the first MOS tube Q1 inputs the first positive signal VI1+, the gate of the second MOS tube Q2 inputs the first negative signal VI1-, the gate of the third MOS tube Q3 inputs the second positive signal VI2+, and the gate of the fourth MOS tube Q4 inputs the second negative signal VI2-. The first pole of the first MOS tube Q1 and the first pole of the third MOS tube Q3 both serve as one output end of the delay adjustable subunit, and the first pole of the second MOS tube Q2 and the first pole of the fourth MOS tube Q4 both serve as another output end of the delay adjustable subunit. The second pole of the first MOS tube Q1 and the second pole of the second MOS tube Q2 are both connected to the first end of each group of switches, the second pole of the third MOS tube Q3 and the second pole of the fourth MOS tube Q4 are both connected to the second end of each group of switches, and the control end of each group of switches inputs a control signal. Each group of switches comprises two MOS tubes, the gates of the two MOS tubes of the same group of switches input control signals of opposite levels, for example, N+1 groups of switches, the control signals are D0, D0 ， , D1, D1 ， , …, DN, DN ， , the first pole of one of the two MOS tubes of the same group of switches is electrically connected to the first MOS tube Q1 and the second MOS tube Q2, the first pole of the other MOS tube is electrically connected to the third MOS tube Q3 and the fourth MOS tube Q4, and the second poles of the two MOS tubes of the same group of switches are grounded through a power supply such as a current source.

[0072] Further, the delay adjustable unit is a programmable adjustable delay unit, and high-precision delay step can be realized. When the control signals D0, D1, …, DN are low, the delay is the minimum value, that is, the delay time is the minimum; when the control signals D0, D1, …, DN are high, the delay is the maximum value, that is, the delay time is the maximum; when at least one of the control signals D0, D1, …, DN is high and at least one is low, the delay time is between the minimum value and the maximum value, the more the number of low control signals, the closer the delay time is to the minimum value, the more the number of high control signals, the closer the delay time is to the maximum value, the delay range of the delay adjustable subunit is between the minimum value and the maximum value, and the delay adjustment step is the ratio of the difference between the maximum value and the minimum value to N.

[0073] In addition, the input impedance of the MOS transistor is extremely high, the gate of the MOS transistor is isolated from the substrate by a silicon dioxide insulation layer, and almost no current flows through the gate, so the input impedance can reach 10 10 Ω or more, which can effectively reduce the power consumption of the signal source. The switching speed of the MOS transistor is fast, since the MOS transistor is a voltage-controlled type (the conduction channel is controlled by the electric field), there is no need to inject carriers like a transistor, so the switching speed of the on and off is extremely fast (nanosecond level), which is suitable for high-frequency circuits and high-speed switching applications. The MOS transistor has low power consumption, when the MOS transistor is off, there is no current at the gate, only a small leakage current exists, and the static power consumption is extremely low; when the MOS transistor is on, the on-resistance is small (which can be as low as milliohm level), and the on-loss is small, especially in the large current scenario, the efficiency advantage is obvious. The MOS transistor has good thermal stability, when the temperature rises, the on-resistance of the MOS transistor will increase, causing the current to automatically decrease, forming a negative feedback, reducing the risk of thermal runaway, and being suitable for high-power application scenarios. The MOS transistor is easy to drive, the gate of the MOS transistor only needs to be driven by voltage, without the need for large current, and the driving circuit design is simple, which can be directly controlled by the host computer through the register without the need for a complex driving amplification circuit. The MOS transistor has low noise, since there is no minority carrier storage effect and base current noise, the noise coefficient of the MOS transistor is low, which is suitable for circuits sensitive to noise. The structure of the MOS transistor is compact, the integration degree is high, the manufacturing process is simple, the occupied area is small, and it is easy to be mass-produced, which is beneficial to the miniaturization and high performance of the delay adjustable unit.

[0074] Reference Figure 7 Optionally, the delay adjustable sub-unit further comprises a current source I, and the current source I is electrically connected with the switch.

[0075] Specifically, the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 are electrically connected with a plurality of current sources I through switches. The current of each current source can be consistent or set in other proportions. The number of current sources and the number of switches can be very high, and the number of current sources and the number of switches are only limited by the area of the delay adjustable unit and the parasitic introduced by layout and wiring. Meanwhile, adjusting the current weight distribution of the current source can also achieve high-precision and wide-range delay adjustment, so the delay adjustable unit can realize ultra-high-precision delay adjustment without being limited by the conversion rate of the digital-to-analog converter. At the same time, if there is a greater demand for delay adjustment range, the buffer can be cascaded with multiple buffers or other delay structures can be directly used to cover the design requirements.

[0076] The timing calibration system provided by the embodiment belongs to the same inventive concept as the timing calibration method provided by any embodiment of the application, has corresponding beneficial effects, and the detailed technical details of the timing calibration system provided by the embodiment are described in the timing calibration method provided by any embodiment of the application.

[0077] Embodiment Four

[0078] The fourth embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a host computer to implement a timing calibration method provided by the embodiments of the present application. The method comprises the following steps:

[0079] receiving a control instruction;

[0080] controlling the sub-digital-to-analog converter to continuously output high and low levels according to the control instruction, and reading data output by the sub-digital-to-analog converter multiple times;

[0081] determining a delay duration of the delay adjustable unit based on the data read multiple times, so as to calibrate the timing between the sub-digital-to-analog converter and the sampling unit, and the timing between the sub-digital-to-analog converters.

[0082] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, be but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus or device.

[0083] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, in which a computer readable program code is borne. Such a propagated data signal can take on multiple forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and that can transmit, propagate or transport a program for use by or in connection with an instruction execution system, apparatus or device.

[0084] The program code contained in the computer readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0085] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0086] It is to be understood that the above description is merely a preferred embodiment of the application and the applied technical principles. Those skilled in the art will appreciate that various obvious changes, reconfigurations, combinations and substitutions can be made to the specific embodiments described herein without departing from the scope of the application. Therefore, although the application has been described in detail by the above embodiments, the application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the application, and the scope of the application is determined by the appended claims.

Claims

1. A method of timing calibration, characterized by, The timing calibration method is applied to a digital-to-analog converter, the digital-to-analog converter comprises a plurality of sub digital-to-analog converters, a timing calibration system of the digital-to-analog converter comprises a host computer, a plurality of timing calibration subsystems corresponding to the plurality of sub digital-to-analog converters one by one, the timing calibration subsystems comprise a delay adjustable unit, a sampling unit, a flip-flop, a register, the sub digital-to-analog converters, the delay adjustable unit, the register and the host computer are sequentially electrically connected, the sub digital-to-analog converters, the sampling unit, the flip-flop and the register are sequentially electrically connected, the delay adjustable unit is electrically connected with the sampling unit, and the timing calibration method is executed by the host computer; the timing calibration method comprises: receiving a control instruction; controlling the sub digital-to-analog converter to continuously output high and low levels according to the control instruction, and reading data output by the sub digital-to-analog converter multiple times; determining a delay duration of the delay adjustable unit based on the multiple times of reading data, so as to calibrate the timing between the sub digital-to-analog converter and the sampling unit and the timing between each of the sub digital-to-analog converters; the delay adjustable unit comprises a first delay adjustable subunit and a second delay adjustable subunit, the first delay adjustable subunit, the second delay adjustable subunit and the sub digital-to-analog converter are sequentially electrically connected, the first delay adjustable subunit is electrically connected with the sampling unit, and the first delay adjustable subunit and the second delay adjustable subunit are both electrically connected with the register; the determining of the delay duration of the delay adjustable unit based on the multiple times of reading data comprises: determining an average value of the multiple times of reading data according to the multiple times of reading data; determining a delay duration of the second delay adjustable subunit based on the average value, so as to calibrate the timing between the sub digital-to-analog converter and the sampling unit.

2. The timing calibration method of claim 1, wherein, the multiple times of reading data are data read when the delay duration of the second delay adjustable subunit is controlled to be a preset minimum duration; the determining of the delay duration of the second delay adjustable subunit based on the average value comprises: controlling the delay duration of the second delay adjustable subunit to gradually increase by a preset step length from the preset minimum duration; when the delay duration increases by a preset step length each time, repeatedly reading data multiple times to obtain the average value of the multiple times of reading data, until the delay duration of the second delay adjustable subunit reaches a preset maximum duration, and a plurality of average values are obtained; determining the delay duration of the second delay adjustable subunit according to the plurality of average values.

3. The timing calibration method of claim 1, wherein, after the determining of the delay duration of the second delay adjustable subunit, comprising: adjusting the delay duration of the first delay adjustable subunit of each of the sub digital-to-analog converters according to waveforms output by each of the sub digital-to-analog converters, so as to calibrate the timing between each of the sub digital-to-analog converters.

4. The timing calibration method of claim 1, wherein, the range of the average value is 0-1.

5. The timing calibration method of claim 2, wherein, The preset minimum time length is greater than zero and less than a preset threshold, a time corresponding to a rising edge of a clock signal of the second delay adjustable subunit is a first time, a time corresponding to a falling edge of the clock signal is a second time, and the preset threshold is a smaller one of the first time and the second time.

6. A timing calibration system, characterized by, The timing calibration system is a timing calibration system of a digital-to-analog converter, the digital-to-analog converter includes a plurality of sub digital-to-analog converters, and the timing calibration system includes a host computer and a plurality of timing calibration subsystems corresponding to the plurality of sub digital-to-analog converters in one-to-one correspondence. The timing calibration subsystem includes a delay adjustable unit, a sampling unit, a flip-flop, and a register. The sub digital-to-analog converter, the delay adjustable unit, the register, and the host computer are electrically connected in sequence. The sub digital-to-analog converter, the sampling unit, the flip-flop, and the register are electrically connected in sequence. The delay adjustable unit is electrically connected with the sampling unit. The timing calibration method of any one of claims 1-5 is executed by the host computer.

7. The timing calibration system of claim 6, wherein, The delay adjustable unit includes a first delay adjustable subunit and a second delay adjustable subunit. The first delay adjustable subunit, the second delay adjustable subunit, and the sub digital-to-analog converter are electrically connected in sequence. The first delay adjustable subunit is electrically connected with the sampling unit. The first delay adjustable subunit and the second delay adjustable subunit are electrically connected with the register.

8. The timing calibration system of claim 7, wherein, The first delay adjustable subunit and the second delay adjustable subunit are of the same structure. The first delay adjustable subunit includes a buffer and a plurality of switches. The output end of the buffer is electrically connected with the plurality of switches.

9. The timing calibration system of claim 8, wherein, The first delay adjustable subunit further includes a current source. The current source is electrically connected with the switches.

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