A crystal chip testing method

Abstract

The present application relates to a kind of crystal vibration chip test methods, comprising the following steps: constructing the digital twin model of crystal vibration chip, and inserting scan chain therein;Scan chain's scan output and the electrical signal of crystal vibration are fused into multidimensional crystal vibration feature;Normal sample is injected into the digital twin model by scan chain, obtain the multidimensional crystal vibration feature under the condition of no fault as training data, train over-complete dictionary;Fault sample is injected into the digital twin model by scan chain, obtain the multidimensional crystal vibration feature under different fault types, and then the reconstruction error corresponding to each fault type is calculated as fault fingerprint using over-complete dictionary;The crystal vibration chip is scanned and tested, and the reconstruction error is calculated using over-complete dictionary according to the multidimensional crystal vibration feature obtained by testing, and then the measured reconstruction error is compared with the fault fingerprint to obtain chip test result.The present application can improve the detection precision and accuracy of crystal vibration chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a crystal oscillator chip testing method. BACKGROUND

[0002] As the clock heart of electronic systems, the performance of crystal oscillator chips directly affects the stability of communication, calculation, navigation and other fields. With the application of 5G, AIoT and other technologies, crystal oscillator chips are gradually developing towards complexity and integration from single clock output. The existing high-end crystal oscillator chips and high-end sensor chips based on crystal oscillator chips have frequency division / multiplier functions integrated inside to output multiple frequency clocks. Traditional crystal oscillator chip testing methods based on threshold value method and frequency spectrum analysis method have exposed problems of sample scarcity, fuzzy positioning and insufficient precision when facing such crystal oscillators. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a crystal oscillator chip testing method that can improve the detection precision and accuracy of crystal oscillator chips.

[0004] The technical solution adopted by the present application to solve the technical problem is to provide a crystal oscillator chip testing method, comprising the following steps:

[0005] A digital twin model of the crystal oscillator chip is constructed, and a scan chain is inserted into the digital twin model;

[0006] The scan output of the scan chain and the electrical signal of the crystal oscillator are fused into multi-dimensional crystal oscillator features;

[0007] Normal samples are injected into the digital twin model through the scan chain to obtain the multi-dimensional crystal oscillator features under no-fault conditions as training data, and a redundant dictionary is trained;

[0008] Fault samples are injected into the digital twin model through the scan chain to obtain the multi-dimensional crystal oscillator features under different fault types, and then the reconstruction error corresponding to each fault type is calculated as a fault fingerprint using the redundant dictionary;

[0009] The crystal oscillator chip is scanned and tested, the reconstruction error is calculated using the redundant dictionary according to the multi-dimensional crystal oscillator features obtained by testing, and then the measured reconstruction error is compared with the fault fingerprint to obtain a chip testing result.

[0010] Further, the electrical signal of the crystal oscillator includes a clock output signal.

[0011] Further, the electrical signal of the crystal oscillator further includes a control voltage signal of a voltage-controlled oscillator and a peak detection voltage signal.

[0012] Further, the fusing of the scan output of the scan chain and the electrical signal of the crystal oscillator into the multi-dimensional crystal oscillator feature includes:

[0013] Obtaining the frequency of each clock output signal to obtain clock frequency data;

[0014] Sampling the control voltage signal and the peak detection voltage signal based on the test clock to obtain control voltage data and peak detection voltage data;

[0015] Fusing the scan output of the scan chain, the control voltage data and the peak detection voltage data, and the clock frequency data into the multi-dimensional crystal oscillator feature.

[0016] Further, the constructing of the digital twin model of the crystal oscillator chip includes:

[0017] Using a SPICE model to describe an analog module;

[0018] Using an RTL model to describe a digital module.

[0019] Further, before the step of injecting normal samples into the digital twin model through the scan chain, the method further includes the step of synthesizing the digital twin model into a gate-level netlist after being inserted into the scan chain.

[0020] Further, when injecting fault samples, the method further includes the step of constructing an analog test module to synchronously inject analog fault samples into the analog module.

[0021] Further, the analog fault samples are synchronously injected with the normal samples.

[0022] Further, the comparing of the reconstructed error measured in practice with the fault fingerprint to obtain the chip test result includes:

[0023] Judging whether the reconstructed error measured in practice is less than a set threshold value;

[0024] If it is less than the set threshold value, the crystal oscillator chip is considered to be normal;

[0025] Otherwise, the closest fault fingerprint is found to obtain the corresponding fault type.

[0026] Beneficial effects

[0027] Compared with the prior art, the present application has the following advantages and positive effects: the present application reproduces the real behavior of the crystal oscillator chip through a digital twin model, enhances testability in combination with a scan chain, covers mixed signal fault modes by using multi-dimensional feature fusion, establishes a normal mode template through an over-complete dictionary, and finally realizes fault detection and classification through a reconstruction error comparison, thereby converting the implicit faults of the chip into quantifiable feature errors, solving the problems of difficult detection of analog faults and difficult differentiation of multi-source faults in traditional crystal oscillator testing, and thereby improving the detection precision and accuracy of the crystal oscillator chip. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a flowchart of the embodiment of the present application;

[0029] Figure 2 is a test flowchart of the embodiment of the present application for a chip that has been taped out. DETAILED DESCRIPTION

[0030] The present application will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present application and not used to limit the scope of the present application. Furthermore, it should be understood that after reading the content taught by the present application, those skilled in the art can make various modifications or changes to the present application, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0031] The embodiment of the present application relates to a crystal oscillator chip anomaly detection method based on scan chain fault injection and dictionary learning, as shown in Figure 1 mainly includes:

[0032] a digital twin model of the crystal oscillator chip is constructed and inserted into a scan chain;

[0033] a chip test model based on dictionary learning is constructed;

[0034] in a simulation environment, a training sample set is constructed through scan chain fault injection;

[0035] the chip test model is trained;

[0036] in a test environment, PIN output data of the crystal oscillator chip is collected, and a detection result is obtained by using the trained chip test model.

[0037] The core module of the crystal oscillator chip in the embodiment includes:

[0038] a voltage-controlled oscillator (VCO): generates an original high-frequency signal, and the output frequency stability directly affects the frequency division and frequency multiplication results;

[0039] Phase-locked loop (PLL): Achieve frequency multiplication function through feedback control, which contains phase frequency detector (PFD), charge pump (CP), loop filter (LF) and other components inside;

[0040] Divider: Divide high-frequency signals into multiple low-frequency signals (such as 1 / 2, 1 / 4, 1 / 8 division), which is usually realized by cascading flip-flops;

[0041] Multiplier: Multiply low-frequency signals to high-frequency signals through nonlinear devices.

[0042] Crystal oscillator chip contains analog and digital mixed signal modules, and a single type of model cannot fully reflect its real behavior, so a mixed signal modeling method can be used to model the analog and digital modules in the chip:

[0043] Among them, the analog module includes VCO and PLL, etc. The SPICE (Simulation Program with Integrated Circuit Emphasis) model is used to accurately describe the voltage and current characteristics, frequency response, noise characteristics and other continuous time behaviors of the analog circuit based on the layout parameters and process parameters of the crystal oscillator chip;

[0044] The digital module includes the counting logic and control logic of the frequency divider, etc. The RTL (Register Transfer Level) model is used to describe the register transfer behavior of digital logic through hardware description language, including discrete event behavior of frequency dividers, etc.

[0045] After completing the independent modeling of analog and digital modules, the model cascade is realized through a mixed signal simulation platform (such as Cadence Spectre) to form a complete digital twin model of the crystal oscillator chip.

[0046] To enhance the testability of the model, scan chains are inserted between key registers of the digital module (such as the output register of the frequency divider and the state register of the control logic). The scan chain is composed of cascaded scan flip-flops, and the test vector is injected and the internal state is read serially through the scan input (Scan In) and scan output (Scan Out) interfaces. The insertion of the scan chain complies with the IEEE 1149.1 (JTAG) standard to ensure compatibility with test equipment.

[0047] The multi-dimensional crystal oscillator features are obtained by fusing the scan output of the scan chain and the electrical signals of the crystal oscillator. Among them, the electrical signals of the crystal oscillator include the clock output signal, and in some preferred embodiments, the control voltage signal of the voltage-controlled oscillator and the peak detection voltage signal can also be included to obtain more accurate fault localization results.

[0048] The clock output signal can be extracted through the clock output port (CLK_OUT pin) of the digital twin model, and its frequency can be calculated using a frequency counter to obtain the clock frequency data;

[0049] The control voltage signal of the voltage-controlled oscillator (VCO) ) and peak detection voltage signal ( To simulate a continuous signal, synchronous sampling is required using a test clock. Aligning the sampling time with the shift operation of the scan chain (i.e., completing one voltage sampling and one scan chain shift per test clock cycle) yields a discrete control voltage data sequence. , , ..., } and peak detection voltage data sequence { , , ..., The test clock is generated by the test control module of the digital twin model, and its frequency is a division of the crystal oscillator clock.

[0050] The serial scan data output by the scan chain within the test clock cycle is concatenated with the clock frequency data, control voltage data sequence, and peak detection voltage data sequence to form a multidimensional crystal oscillator feature vector X = [scan output vector | clock frequency | ...]. Sequence | sequence].

[0051] To facilitate subsequent calculations, the dimensionality of the multidimensional crystal oscillator feature vector can be reduced. For example, the scan output vector can be converted to hexadecimal, and other vectors can also be converted according to the synchronization principle.

[0052] In the digital twin model, normal test vectors, such as the normal counting sequence of the frequency divider and the legal state transition sequence of the control logic, are injected into the digital module through a scan chain. Simultaneously, normal operating conditions are injected into the analog module through the simulation test module. The digital twin model is then run to collect multi-dimensional crystal oscillator characteristics for each test cycle. To form a normal sample set .

[0053] With normal sample set A complete dictionary has been trained as input. Specifically, the K-SVD algorithm can be used, by applying an overcomplete dictionary. Alternating iterative optimization with sparse coding, normal samples are sparsely represented as linear combinations of dictionary atoms. The specific method is as follows:

[0054] For all normal samples Solve using the OMP algorithm to satisfy... sparsity coefficient ;

[0055] Fixed sparsity coefficient By minimizing the reconstruction error Update dictionary The atoms; for each atom Only keep all The Middle For samples with non-zero bits, update using Singular Value Decomposition (SVD). This forms the optimal orthogonal basis for the corresponding subspace;

[0056] Repeat the above two steps until a complete dictionary is found. The change is less than the set threshold or the reconstruction error no longer decreases significantly.

[0057] overcomplete dictionary after training It can capture the intrinsic correlation of multidimensional features under normal conditions.

[0058] To address the fault types of crystal oscillator chips, fault test vectors (such as logic function failures or timing violations) are injected into digital modules via a scan chain. Furthermore, the fault injection process employs a method of injecting one type of fault at a time, in order to decouple different faults.

[0059] In some preferred embodiments, a simulated fault (such as parameter drift caused by process fluctuations) can be injected into the simulation module by constructing a simulation test module, while normal samples are synchronously injected into the digital module through a scan chain to achieve the localization of the simulated fault. It is important to note that the sample injection must be strictly synchronized in time, that is, the digital vector and simulation parameters must be modified simultaneously within the same test clock cycle to ensure that the fault characteristics and normal characteristics are time-aligned.

[0060] Collect multidimensional crystal oscillator characteristics under various fault types Utilizing a complete dictionary Calculate its reconstruction error:

[0061]

[0062] in, Number the fault type. for exist Sparse coding on This refers to the type of fault. Fault fingerprints.

[0063] like Figure 2 As shown, when performing scan testing on the crystal oscillator chip after fabrication, test vectors are injected into the chip's scan chain through the test equipment (ATE), and scan output, clock frequency, and other parameters are acquired simultaneously. Signals and The signal is used to generate the measured multi-dimensional features in the same time window and sampling manner as in the training phase .

[0064] Using the trained over-complete dictionary Calculate the reconstruction error of

[0065]

[0066] Where, is the sparse representation coefficient of

[0067] By comparing with the error threshold, it can be determined whether the chip is faulty. The error threshold can be set according to the maximum reconstruction error of the normal sample, usually taking 2-3 times the standard deviation to avoid misjudgment.

[0068] For faulty chips, the type of fault can be located by comparing with each fault fingerprint .

[0069] The specific determination steps are as follows:

[0070] If is less than the set threshold , it is considered that the chip is not faulty and the test is passed;

[0071] If is greater than the set threshold , calculate the similarity of with each fault fingerprint , and select the fault type corresponding to the fault fingerprint with the largest similarity as the test result; the similarity calculation can use the Euclidean distance, and the fault type corresponding to the fault fingerprint with the smallest distance is selected as the test result.​​

Claims

1. A crystal oscillator chip testing method, characterized by, The method comprises the following steps: a digital twin model of a crystal oscillator chip is constructed, and a scan chain is inserted into the digital twin model; scan outputs of the scan chain and electrical signals of the crystal oscillator are fused into multi-dimensional crystal oscillator features; normal samples are injected into the digital twin model through the scan chain, and the multi-dimensional crystal oscillator features under a fault-free condition are obtained as training data to train an overcomplete dictionary; fault samples are injected into the digital twin model through the scan chain, and the multi-dimensional crystal oscillator features under different fault types are obtained, and then the reconstruction error corresponding to each fault type is calculated as a fault fingerprint by using the overcomplete dictionary; the crystal oscillator chip is subjected to scan testing, the reconstruction error is calculated by using the overcomplete dictionary according to the multi-dimensional crystal oscillator features obtained by testing, and then the measured reconstruction error is compared with the fault fingerprint to obtain a chip test result.

2. The crystal oscillator chip testing method according to claim 1, wherein The electrical signals of the crystal oscillator include clock output signals.

3. The crystal oscillator chip testing method according to claim 2, wherein The electrical signals of the crystal oscillator further include a control voltage signal of a voltage-controlled oscillator and a peak detection voltage signal.

4. The crystal oscillator chip testing method according to claim 3, wherein The fusion of the scan outputs of the scan chain and the electrical signals of the crystal oscillator into the multi-dimensional crystal oscillator features comprises: frequencies of each clock output signal are obtained to obtain clock frequency data; the control voltage signal and the peak detection voltage signal are sampled based on a test clock to obtain control voltage data and peak detection voltage data; the scan outputs of the scan chain, the control voltage data and the peak detection voltage data, and the clock frequency data are fused into the multi-dimensional crystal oscillator features.

5. The crystal oscillator chip testing method according to claim 1, wherein The construction of the digital twin model of the crystal oscillator chip comprises: an analog module is described by using a SPICE model; a digital module is described by using an RTL model.

6. The crystal oscillator chip testing method according to claim 5, wherein Before the step of injecting normal samples into the digital twin model through the scan chain, a step of synthesizing the digital twin model after the insertion of the scan chain into a gate-level netlist is further included.

7. The crystal oscillator chip testing method according to claim 5, wherein When injecting fault samples, a step of constructing an analog test module to synchronously inject analog fault samples into the analog module is further included.

8. The crystal oscillator chip testing method according to claim 7, wherein The analog fault samples are synchronously injected with the normal samples.

9. The crystal oscillator chip testing method according to claim 1, wherein The comparison of the measured reconstruction error with the fault fingerprint to obtain the chip test result comprises: it is judged whether the actually measured reconstruction error is less than a set threshold value; if the actually measured reconstruction error is less than the set threshold value, it is considered that the crystal oscillator chip is normal; otherwise, the closest fault fingerprint is found to obtain a corresponding fault type.

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