Instrument distributed redundant bus control system capable of enhancing fault countermeasure capability

Abstract

The invention relates to the technical field of instrument redundancy control, in particular to an instrument distributed redundancy bus control system capable of enhancing fault confrontation capability. According to the technical scheme, the system comprises a communication bus, an operation sub-controller, a master controller and at least one redundant sub-controller, the master controller interacts with all the sub-controllers through the communication bus, and when the operation sub-controller executes a control task, an instruction execution time sequence of the control task is output through the communication bus; the master controller determines the performance consumption degree of execution components on the operation sub-controllers according to the instruction execution time sequence; according to the performance consumption degree, obtaining the execution consumption cost of the corresponding component for executing the instruction corresponding to the control task; and when the execution consumption cost is greater than the bearing upper limit of the corresponding component, outputting a distribution instruction to the redundant sub-controller through the communication bus to execute the processing sub-task of the control task. According to the technical scheme, the accuracy of redundancy control of the intensive integrated controller and the fault confrontation capability of the whole system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of instrument redundant control, and particularly relates to an instrument distributed redundant bus control system with enhanced fault resistance. BACKGROUND

[0002] The distributed redundant bus is a system that physically and logically distributes bus communication paths and control system functions, and ensures that the entire system can maintain normal communication and control functions even if part of the channels or nodes fail through multiple independent bus channels and multiple distributed control nodes.

[0003] The core design idea of the distributed redundant bus is to eliminate any single point failure in the system. That is, by deploying redundant hardware in the bus, when part of the hardware fails, the remaining redundant devices replace the failed devices, thereby ensuring the overall stability of the bus, and through address mapping, the address of the failed device is switched to the backup redundant device, thereby reducing the required time for maintenance and replacement of the failed device, and in the case where the maintenance conditions of the partial failure are not met on site, the integrity of the system function is ensured.

[0004] The prior art determines the current bus failure device by the effectiveness of the signal transmission of the device and the temperature environment of the device location to determine whether the device has an abnormal condition, but for a single small component in a dense integrated controller, the failure scale caused by the failure is small, and the intermittent occurrence of the failure is hidden, so the accuracy of the abnormal device positioning through conduction and environmental parameters is low. SUMMARY

[0005] To solve the technical problem of how to improve the accuracy of redundant control of dense integrated controllers, the purpose of the present application is to provide an instrument distributed redundant bus control system with enhanced fault resistance, and the technical solution is as follows: The embodiment of the present application provides an instrument distributed redundant bus control system with enhanced fault resistance, which comprises: a communication bus; a running sub-controller connected to the communication bus, the running sub-controller being used for executing control tasks and outputting instruction execution timing of the control tasks through the communication bus; a total controller connected to the communication bus, the total controller being used for determining performance consumption degree of the executed components on the running sub-controller according to the instruction execution timing, obtaining execution consumption cost of the corresponding components for executing the control tasks according to the performance consumption degree, and outputting a distribution instruction through the communication bus when the execution consumption cost is greater than the upper limit of the corresponding components; At least one redundant sub-controller connected to the communication bus, the redundant sub-controller being configured to execute processing sub-tasks of the control task according to the distribution instruction to realize distributed redundant scheduling of the control task.

[0006] In an optional embodiment, the performance consumption degree of the execution component on the running sub-controller is determined according to the instruction execution time sequence, including: extracting and processing execution time of the same instruction in the instruction execution time sequence to obtain a time consumption index representing performance consumption of the corresponding execution component in the time dimension; extracting and processing required bandwidth of the same instruction in the instruction execution time sequence to obtain a bandwidth consumption index representing performance consumption of the corresponding execution component in the bandwidth dimension; obtaining the performance consumption degree of the corresponding execution component according to the time consumption index and the bandwidth consumption index of each execution component.

[0007] In an optional embodiment, the execution time of the same instruction in the instruction execution time sequence is extracted and processed to obtain a time consumption index representing performance consumption of the corresponding execution component in the time dimension, including: extracting execution time of each execution component under the same instruction in the instruction execution time sequence, and calculating a time difference value of the first execution time of each execution component and the second execution time of other execution components; obtaining the time consumption index of the current execution component in executing the corresponding instruction according to a ratio of an average value of all time difference values of the current execution component to time required by the current execution component in executing a single instruction.

[0008] In an optional embodiment, the required bandwidth of the same instruction in the instruction execution time sequence is extracted and processed to obtain a bandwidth consumption index representing performance consumption of the corresponding execution component in the bandwidth dimension, including: obtaining required bandwidth of each execution component in executing current instruction implementation data processing in the instruction execution time sequence, and bus bandwidth of the communication bus; obtaining the bandwidth consumption index of the corresponding execution component according to a ratio of the required bandwidth of each execution component to the bus bandwidth.

[0009] In an optional embodiment, the execution consumption cost of the corresponding execution component in executing the corresponding instruction of the control task is obtained according to the performance consumption degree, including: obtaining a performance consumption ratio of the corresponding execution component according to a ratio of the performance consumption degree of each execution component in executing the corresponding instruction to the maximum performance consumption degree thereof; obtaining the execution consumption cost of the corresponding execution component according to an absolute value of a difference between the load rate and the performance consumption ratio of each execution component in executing the corresponding instruction.

[0010] In an alternative embodiment, when the execution cost is greater than the upper limit of the corresponding component, the distribution instruction is output through the communication bus, including: The execution cost is arranged according to the execution order of each component when each execution instruction is executed, so as to obtain an execution cost sequence representing multiple executions of the corresponding execution instruction; The maximum value data of the execution cost sequence is extracted and processed to obtain a blocking parameter representing the blocking degree of the corresponding execution component under the execution instruction; When the blocking parameter is greater than a preset blocking threshold, the distribution instruction is output to the communication bus according to the blocking parameter and the distribution number of the redundant sub-controller.

[0011] In an alternative embodiment, the maximum value data of the execution cost sequence is extracted and processed to obtain a blocking parameter representing the blocking degree of the corresponding execution component under the execution instruction, including: The maximum value data of the execution cost sequence is extracted using a multi-scale peak finding model, and the position of each maximum value is determined as a high-cost load point; The blocking feature is analyzed according to all high-cost load points and corresponding maximum execution cost, so as to obtain the blocking parameter of the corresponding execution component under the execution instruction.

[0012] In an alternative embodiment, the blocking feature is analyzed according to all high-cost load points and corresponding maximum execution cost, so as to obtain the blocking parameter of the corresponding execution component under the execution instruction, including: The blocking coefficient is obtained according to the cost difference, average consumption cost and consumption cost standard deviation of two adjacent maximum execution costs; The blocking parameter of the corresponding execution component under the execution instruction is obtained according to the sum of all blocking coefficients between two adjacent high-cost load points.

[0013] In an alternative embodiment, the distribution instruction is output to the communication bus according to the blocking parameter and the distribution number of the redundant sub-controller, including: The instruction distribution ratio is determined by the upward rounding calculation of the ratio of the blocking parameter to the distribution number; The number of instructions is obtained according to the instruction distribution ratio and the total number of instructions of the control task; The corresponding instructions are distributed to the communication bus according to the number of instructions, so that the redundant sub-controller executes the corresponding processing sub-task.

[0014] In an alternative embodiment, before the total controller outputs the distribution instruction to the communication bus, it is also used for: The prior address list is broadcasted on the communication bus, and the redundancy processing unit of the redundant sub-controller is configured according to the received response result, so that the redundancy processing unit is in a standby state of taking over the processing sub-tasks in real time.

[0015] The application has the following advantages: The technical scheme of the application comprises a communication bus, a running sub-controller, a total controller and at least one redundant sub-controller, the total controller and each sub-controller interact through the communication bus, the running sub-controller outputs the instruction execution time sequence of a control task through the communication bus when executing the control task; the total controller determines the performance consumption degree of an executing component on the running sub-controller according to the instruction execution time sequence; and obtains the execution consumption cost of the corresponding component executing the corresponding instruction of the control task according to the performance consumption degree; when the execution consumption cost is greater than the upper limit of the bearing of the corresponding component, the distribution instruction is output to the redundant sub-controller to execute the processing sub-task of the control task through the communication bus, so as to realize the distributed redundancy scheduling of the control task. The technical scheme can obtain the instant resource pressure under the current instruction based on the performance consumption degree of the component, and trigger the redundant sub-controller to process or switch, so as to reduce the failure caused by excessive load of the component, and further improve the accuracy of the redundancy control of the dense integrated controller and the fault resistance of the whole system. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, and the advantages thereof, below briefly introduces the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0017] Figure 1 The structure diagram of the instrument distributed redundancy bus control system for enhancing the fault resistance provided by one embodiment of the present application; Figure 2 The running flowchart of the total controller provided by one embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to further illustrate the technical means and effects adopted by the present application to achieve the predetermined application purpose, the following describes the instrument distributed redundancy bus control system for enhancing the fault resistance according to the present application, its specific implementation, structure, features and effects in detail by combining with the drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. In addition, the specific features, structures or characteristics in one or more embodiments can be combined in any suitable form.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0020] The application provides a specific scheme of an instrument distributed redundant bus control system with enhanced fault resistance.

[0021] Please refer to Figure 1 , Figure 1 A structure diagram of an instrument distributed redundant bus control system with enhanced fault resistance is provided for an embodiment of the application. The control system comprises a communication bus, a running sub-controller, a total controller and at least one redundant sub-controller. The total controller and each sub-controller communicate with each other through the communication bus.

[0022] The communication bus can be configured based on actual requirements, for example, as an RS485 bus or a CAN (Controller Area Network) bus. Please continue to refer to Figure 1 When configured as a CAN bus, the total controller and each sub-controller are connected based on CAN_L and CAN_H. It can be understood that the running sub-controller is the smallest unit of the distributed sub-controller cluster. The running sub-controller needs to be designed and manufactured according to the general requirements of the instrument (temperature collection, control output, signal collection, etc.). Since the number of control devices, the number of collected signals and the number of output signals required by each instrument are different, the number of sub-controllers used by the instrument can be configured according to the signal collection, output control and input signal required by the instrument.

[0023] The running sub-controller is used to execute the control task of the instrument. Of course, it can also implement a data processing task or a signal processing task. When executing the control task, the instruction execution time sequence of the control task is output through the communication bus. The instruction execution time sequence is the corresponding relationship between the task instructions of the control task and the execution time. Based on the instruction execution time sequence, the execution time of each instruction can be determined. The instruction execution time sequence can also include the execution bandwidth of each instruction. As can be seen from the figure, the components used by this type of running sub-controller are mostly SMD (Surface Mount Device), and the integrated chips soldered on the PCB (Printed Circuit Board) are distributed relatively densely. It is difficult to capture the integrated circuits that have failed due to running overload by using conventional temperature detection methods. It should be noted that the running overload failure can be caused by insufficient computing bandwidth due to excessive computing load, or by an overload failure caused by complex signal processing, which is not limited specifically herein.

[0024] To improve the fault resistance of such instruments, at least one redundant sub-controller needs to be added, which is used to execute processing sub-tasks of control tasks according to the distribution instructions issued by the master controller, so as to realize distributed redundant scheduling of control tasks. The plurality of redundant sub-controllers can be installed by stacking plastic columns and connected to the master controller through the communication bus. After the connection is completed, the master controller broadcasts a priori hardware address list of each circuit unit to the communication bus. When each hardware node compares the address list broadcast by the communication bus, address comparison verification is implemented. The hardware of the current address sends a response signal to the master controller address. After the master controller receives the response signal of the address, it regards it as available hardware, so that the redundant processing unit is in standby state that can take over processing sub-tasks at any time. The redundant processing unit is a unit circuit for realizing a certain function of the redundant sub-controller, such as a filtering processing unit, a calculation processing unit, a thyristor switching unit, etc. The master controller judges that the current redundant sub-controller is normal based on the fact that all addresses in the address list are successfully compared, that is, it can be used.

[0025] At this point, the initialization of the redundant bus control system is completed, the overload judgment of the running sub-controller, and the cooperative processing or switching of the redundant sub-controller are implemented based on the master controller. The running process of the master controller will be described in detail below.

[0026] Please refer to Figure 2 , Figure 2 is a flow chart of the master controller, which specifically includes: S11, determine the performance consumption degree of the executing component on the running sub-controller according to the instruction execution time sequence.

[0027] Specifically, when the performance consumption of the executing component on the running sub-controller is too high, the master controller and the running sub-controller cannot communicate normally and timely, which may cause bus failure. The essence of bus failure is that there is an abnormal component on the running sub-controller, which causes the component to be unable to output normal information, so as to cause fluctuations in the information transmission in the program execution process, and transmission of error information causes the equipment and instrument to be unable to work normally. Therefore, in the process of program execution, after the calculation data of each component is transmitted to the communication bus for verification, the deviation occurred is used to judge the reliability of the calculation result of the component, and the execution aggregation of the current component is further counted, and the abnormal aggregation scale of the component is combined with the distribution adjustment of the remaining program.

[0028] The running sub-controller receives the execution instruction of the control task sent by the total controller based on the communication bus, for example, executes a certain instruction L, and the execution of the instruction L needs to be executed by the current sub-controller through each component to execute the content required by the execution instruction, so as to complete the control of the actual device by the execution instruction. Therefore, different components required in the execution instruction calculate the data required by each step of the instruction, but the difficulty of the execution of the instruction part allocated to different components is different, mainly reflected in the processing time and the processing performance consumption, so the current instruction L needs to count the performance occupation of each component in the execution process of the instruction, and the performance consumption degree of each component by the current instruction is obtained.

[0029] For example, when the CPU (Central Processing Unit, Central Processing Unit) needs to execute a data reading task at the memory address 0x1234, a plurality of steps need to be executed, and each step has a corresponding execution instruction.

[0030] Firstly, the CPU outputs the memory address 0x1234 contained in the instruction to the communication bus according to the decoding result.

[0031] Secondly, the control unit of the CPU sends a "memory reading" instruction signal to the memory again through the communication bus.

[0032] Thirdly, the memory controller recognizes the address 0x1234 again and locates the corresponding physical storage unit, and prepares the data (assuming 0x55AA) stored therein.

[0033] Fourthly, memory→data bus→CPU. The memory controller transmits the data 0x55AA in the address 0x1234 to the communication bus. The data bus interface in the CPU again reads the data from the communication bus.

[0034] Fifthly, the data 0x55AA is transmitted to the target register R1 specified by the instruction through the data channel in the CPU.

[0035] Sixthly, the instruction execution is completed, and the value of the register R1 becomes 0x55AA.

[0036] In the execution process of the memory data reading, the sending signal task executed by the CPU needs a longer time to execute the instruction than the data reading replacement operation executed by the memory, and the bandwidth occupied by the data replacement in the execution process is more than the bandwidth of the CPU sending signal, so the performance consumption of the instruction part executed by the memory is higher. The performance consumption degree can be determined based on the timing data of the memory execution.

[0037] Exemplarily, the step S11 includes sub-steps S11-1 to S11-3, which are specifically described as follows: S11-1. Extract and process the execution time of the same instructions in the instruction execution sequence to obtain a time consumption index characterizing the performance consumption of the corresponding component in the time dimension. The time consumed by a component to execute the same instruction varies under different load conditions; the lower the load, the less time is consumed; conversely, the higher the load, the more time is consumed. Based on this characteristic of the component, a time consumption index can be evaluated in the time dimension of performance consumption.

[0038] Furthermore, extracting the execution time of the same instruction from the instruction execution sequence allows us to measure the load differences of different components in the time dimension. The main controller obtains the execution time of each executing component under the current instruction from the instruction execution sequence, selects the first execution time of the current component, and compares it pairwise with the second execution time of the corresponding other components to obtain multiple time difference values. By calculating the average of these time differences, we can reflect the degree of time difference of the component relative to other components when executing the same instruction; the ratio of this average time difference value to the time required for the current component to execute a single instruction yields the time consumption index of the component. The larger this index, the more significant the performance consumption of the component in the time dimension, and the more likely it is to become a bottleneck in instruction execution.

[0039] Taking the execution of the current task instruction L on component p as an example, The time consumption metric for executing instruction L on component p. The time consumption metric characterizes the execution time of the current instruction L on component p. , and instruction L in the remaining components Execution time The time difference is calculated, and all components that have executed the current instruction L are traversed to obtain the average time difference. The time t required for the current component to perform one calculation p The ratio is as follows: A larger time consumption index indicates that the current component p spends more time executing instruction L. Therefore, compared with the time required for execution, it indicates how many calculations the current component p needs to perform to complete the calculation task for instruction L. The more calculations performed, the greater the performance consumption of component p.

[0040] S11-2, extract and process the required bandwidth of the same instruction in the instruction execution sequence to obtain a bandwidth consumption index representing the performance consumption of the corresponding component in the bandwidth dimension. This sub-step is used to evaluate the occupation of the system bandwidth resource by each component when executing the same instruction. When implementing the bandwidth dimension performance consumption evaluation, the total controller extracts the data processing bandwidth required by each execution component when processing the instruction in the instruction execution sequence, and simultaneously obtains the bus bandwidth of the communication bus as a reference. For each component, the required bandwidth is calculated by the ratio of the bus bandwidth, and the bandwidth consumption index of the component is obtained. The larger the bandwidth consumption index, the higher the proportion of bandwidth resource occupied by the component under the current instruction. Since the bus bandwidth is limited, the component may cause communication delay due to bandwidth congestion, thereby affecting the overall execution efficiency. Through this sub-step, the performance consumption of different components in the bandwidth dimension can be quantified.

[0041] Further, the required bandwidth of the component p for executing the current instruction L to implement data processing is denoted as , the bus bandwidth of the communication bus is denoted as , and the bandwidth consumption index is The larger the bandwidth consumption index, the greater the calculation amount of the current component, the greater the data transmission amount (the fraction may be greater than 1), indicating that the current component p needs to occupy more transmission resources of the communication bus when executing the current instruction L.

[0042] S11-3, obtain the performance consumption degree of the corresponding component according to the time consumption index and the bandwidth consumption index of each execution component. After obtaining the time consumption index and the bandwidth consumption index, this sub-step comprehensively processes the two to obtain an accurate performance consumption degree. The total controller takes the consumption of each component in the time dimension and the bandwidth dimension as input parameters, and obtains the corresponding performance consumption degree by using weighted or normalized processing. The performance consumption degree can represent the resource occupation of a component when executing the corresponding instruction, considering both the execution time and the bandwidth occupation proportion.

[0043] It can be understood that the performance consumption degree of the corresponding component can be obtained based on the product of the time consumption index and the bandwidth consumption index. Of course, those skilled in the art can also adjust the weight proportion of time and bandwidth according to different application scenarios to realize a performance consumption measurement that is more in line with actual needs. The performance consumption degree is used as a basic parameter for subsequent calculation of execution consumption cost to support fault risk identification and redundancy scheduling decision.

[0044] At this point, the performance consumption degree of the execution component on the running sub-controller has been obtained based on the above method, and step S12 is entered.

[0045] S12, obtaining, according to the performance consumption degree, an execution consumption cost of the corresponding component for executing the control task corresponding instruction.

[0046] Specifically, in the process of implementing instrument control, the intensive resource requirement brought by the instruction is reflected in the high load rate of the component type corresponding to the resource. For example, a memory-intensive instruction requires a long time of large data throughput from the memory, at this time, the load rate of the remaining components is at a normal level, thereby showing the difference in performance consumption degree of different components in the execution process of the current instruction. Based on this difference, the execution consumption cost is analyzed and obtained.

[0047] For example, the current component executes data read output, and the read rate currently reaches a peak of 100 Mb / s, but the communication bus bandwidth is only 30 Mb / s (i.e. 30 Mb per second), and the calculation component can process 25 Mb of data per second. At this time, the component p is in a high load situation, and the influence of its performance consumption is more conducted to the remaining components. Therefore, by correlating the performance consumption degree of the components in the execution process of the current execution instruction L, the execution consumption cost of each component for instruction L can be obtained. Based on the correlation characteristics between the performance consumption degree and the execution consumption cost of each component, a data analysis model can be constructed, which can also be a convolutional neural network model. The execution consumption cost is obtained based on the analysis result of the performance consumption degree by the model.

[0048] Exemplarily, step S12 includes sub-steps S12-1 to S12-2, which are specifically described as follows: S12-1, obtaining, according to the ratio of the performance consumption degree of each execution component for executing the corresponding instruction to the maximum performance consumption degree, the performance consumption ratio of the corresponding execution component. The performance consumption degree of the execution component p for executing the corresponding instruction L is denoted as , the maximum performance consumption degree is denoted as , and the performance consumption ratio is denoted as After the performance consumption ratio of the execution component is calculated, it can be normalized to make the performance consumption ratio within a predetermined range.

[0049] S12-2, obtaining, according to the absolute value of the difference between the load rate of each execution component for executing the corresponding instruction and the performance consumption ratio, the execution consumption cost of the corresponding execution component. The load rate of the component for executing the corresponding instruction is denoted as which can be directly obtained through the communication bus and can be represented as a percentage without unit. The execution consumption cost of the execution component p is denoted as Based on the formula: The greater the execution consumption cost, the greater the actual load of the current component, and the more computing performance is consumed in the execution of the instruction L, thereby increasing the execution cost. The computing exception of the current component in a high-load computing state can be compared with the most abnormal scale in the execution of the current instruction to determine whether the performance exception consumption of the current component is significant.

[0050] At this point, the execution consumption cost of the corresponding component has been obtained based on the above method, and step S13 is entered.

[0051] S13, when the execution consumption cost is greater than the upper limit of the corresponding component, output the distribution instruction through the communication bus.

[0052] Specifically, each component can set a corresponding upper limit of the load, which can be determined according to the brand, model, type and design parameters of the component. For example, different models of CPUs or memory chips have differences in clock frequency, cache size, bandwidth support capability, so the corresponding safe load threshold is different. Those skilled in the art can set the corresponding load upper limit for each type of component according to the factory manual, design specification, or through long-term running of measured data.

[0053] When the execution consumption cost q calculated by the total controller in the previous step exceeds the corresponding load upper limit, it indicates that the component has a significant risk of overload under the current control task. At this time, the total controller broadcasts a distribution instruction to the redundant sub-controllers in the system through the communication bus, which contains task identification, sub-task content to be migrated, data context information, priority, etc. After receiving the distribution instruction, the redundant sub-controllers take over part or all of the control sub-tasks according to the corresponding redundancy configuration to share the running pressure of the overloaded component. Through real-time triggering based on the load upper limit threshold, the instrument system can complete the task redistribution before the component fails completely, thereby reducing the probability of failure and ensuring the continuity and reliability of the overall control task.

[0054] It should be noted that the abnormal consumption cost accumulation of the component load during multiple instruction execution processes will be manifested as fluctuations in the working condition stability of the component. This fluctuation feature is caused by the continuous running of instructions on each sub-controller. Some components may have a large number of instruction execution links, and due to the continuous high-load use of the current component, the risk of failure from the current component is increased. Therefore, the bus control system should avoid the failure of the component, distribute the to-be-executed instructions among multiple redundant sub-controllers, and balance the safety redundancy between the sub-controllers.

[0055] Exemplarily, the step S13 comprises sub-steps S13-1 to S13-3, which are specifically described as follows: S13-1, arranging execution consumption cost of each component according to execution order of each execution instruction to obtain an execution cost sequence representing multiple executions of the corresponding execution instruction. Based on this sub-step, accumulated execution cost can be analyzed in the time dimension to analyze whether there is a persistent high load situation of the component. After receiving the instruction execution sequence output by the running sub-controller, the total controller will calculate the execution consumption cost of each execution instruction according to the execution order of the components. By arranging the cost of each component of the same instruction in the order of multiple executions, an execution cost sequence is obtained. The sequence can reflect the consumption change of each component of the instruction in different execution periods, and provide a data basis for identifying potential load aggregation points. For example, the execution consumption cost q of the components in the execution process of the instruction L is sorted according to the component order, and the execution cost sequence Q is obtained.

[0056] S13-2, performing maximum value data extraction and processing on the execution cost sequence to obtain a blocking parameter representing the blocking degree of the corresponding execution component under the execution instruction. This sub-step can identify the high load point with the greatest impact on system performance from the execution cost sequence. The total controller extracts the maximum value from the sequence data, that is, detects the local maximum value point in the cost sequence through an algorithm, and takes these high cost points as possible blocking points. The total controller calculates a comprehensive blocking parameter according to the prominence (such as the difference from the adjacent mean value), frequency of occurrence and distribution density of these maximum value points. The greater the value of the parameter, the more likely the component becomes a performance bottleneck of the system during execution of the instruction, thereby affecting the overall scheduling performance.

[0057] The blocking parameter of the component can be obtained in the following manner, which specifically comprises: First, a multiscale peak finding model is used to extract the maximum value data of the execution cost sequence, and the positions of each maximum value are determined as high-cost load points. The multiscale peak finding algorithm (AMPD, Automatic Multiscale Peak Detection) can be used to extract the positions of each maximum value cost in the current execution cost sequence Q, and the positions are taken as high-cost load points.

[0058] The second step involves performing blocking feature analysis based on all high-cost load points and their corresponding maximum execution costs to obtain the blocking parameters of the corresponding execution components during instruction execution. After obtaining the execution cost sequence, the central controller uses all high-cost load points and their corresponding maximum execution costs as input samples to construct a blocking feature vector. This vector may include indicators such as peak amplitude, peak spacing, frequency of occurrence, mean difference between adjacent windows, and standard deviation of fluctuation. The feature vector is then processed using a pre-set or trained blocking analysis model. The blocking analysis model can be a statistical learning model (such as support vector machine or logistic regression) or a lightweight neural network model, used to classify or regress the blocking risk of different components. The results output by the blocking analysis model integrate the distribution patterns and extreme value characteristics of multiple high-cost load points into unified blocking parameters. This processing method not only improves the accuracy of single calculations but also adaptively identifies load patterns in complex scenarios, allowing the blocking parameters to better reflect the true risk level of components during instruction execution, thus providing a more reliable decision-making basis for subsequent redundancy scheduling.

[0059] Furthermore, the blocking coefficient can be obtained based on the cost difference, average cost, and standard deviation of the cost between two adjacent maximum execution costs; the blocking parameters of the corresponding execution component during instruction execution can be obtained by summing all blocking coefficients between two adjacent high-cost load points. The maximum execution cost corresponding to the high-cost load point is denoted as... , The blocking parameters can be calculated based on the following formula.

[0060] In the formula: The current instruction L has a very high execution cost. Blocking parameters corresponding to high-cost load points; To maximize the cost of execution The first adjacent maximum execution cost in the sequential order The quantity of the cost q between them The maximum execution cost in the current instruction L. Compared to the cost of the i-th execution point extracted from the current load point... The difference in cost between them, where i is a natural number greater than 1. , These are the average cost and standard deviation of the cost, calculated for all instructions executed by the current component.

[0061] Extremely high execution cost Update the instruction L that was executed at the corresponding load point. For example, if a new instruction L21 is executed, the execution cost will be greatly increased. The executed instruction corresponding to the load point can be 1, 3, 4, 5, 11, 20, the executed instruction not including L21 in the current blocking parameter calculation, and the blocking parameter of instruction L21 is calculated Then, the executed instruction is updated to 1, 3, 4, 5, 11, 20, 21, and the iterative update is completed.

[0062] S13-3, when the blocking parameter is greater than the preset blocking threshold, outputting a distribution instruction to the communication bus according to the blocking parameter and the distribution number of the redundant sub-controllers. After obtaining the blocking parameter, the total controller compares it with the preset blocking threshold. When the blocking parameter is greater than the blocking threshold, it indicates that the component has been in a high-risk state for a long time, and task redistribution is needed. The total controller generates a corresponding distribution instruction according to the size of the blocking parameter and the distribution number of the redundant sub-controllers in the current system, and sends it to the redundant sub-controllers through the communication bus. The distribution instruction needs to specify the processing sub-tasks that need to be migrated and the corresponding redundant sub-controllers to realize the redistribution of task load and the scheduling of redundancy. This method not only reduces the running pressure of the overloaded component, but also effectively improves the stability and fault resistance of the whole system.

[0063] For example, after updating each blocking parameter, the number of instructions NL that need to be executed concurrently by the load point at the current time is obtained through the communication bus. When the current blocking parameter is greater than 0.85, the remaining instruction number is distributed to the remaining sub-controllers. The ratio of the blocking parameter to the distribution number can be calculated by taking the integer part of the result to determine the instruction distribution ratio. Then, the number of instructions of the distribution instruction is obtained according to the instruction distribution ratio and the total number of control tasks. Then, the corresponding instructions are distributed to the communication bus according to the number of instructions, so that the redundant sub-controllers execute the corresponding processing sub-tasks. For example, if there are HX redundant sub-controllers, the number of instructions allocated to a single redundant sub-controller is , , is the total number of instructions, and HX is the distribution number of the redundant sub-controllers, which is not equal to 0 and only represents the logical meaning of the parameter, that is, the larger the distribution number of the redundant sub-controllers, the smaller the number of instructions allocated to a single redundant sub-controller, is the blocking parameter of the high-cost load point. The instructions are distributed to each redundant sub-controller until the distribution is completed.

[0064] It should be noted that the above-mentioned order of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0065] The various embodiments described in this specification are presented by way of example, and each embodiment is not necessarily composed of all features described with respect to other embodiments.

Claims

1. An instrument distributed redundant bus control system with enhanced fault tolerance, characterized in that, The system includes: Communication bus; A running sub-controller is connected to the communication bus. The running sub-controller is used to execute control tasks and outputs the instruction execution timing of the control tasks via the communication bus. A main controller is connected to the communication bus. The main controller is used to determine the performance consumption of the execution components on the running sub-controller according to the instruction execution timing; and to obtain the execution cost of the corresponding component executing the instruction corresponding to the control task according to the performance consumption; when the execution cost is greater than the upper limit of the corresponding component, the main controller outputs an allocation instruction through the communication bus. At least one redundant sub-controller is connected to the communication bus. The redundant sub-controller is used to execute the processing sub-tasks of the control task according to the allocation instructions, so as to realize the distributed redundant scheduling of the control task.

2. The instrument distributed redundant bus control system with enhanced fault tolerance capability according to claim 1, characterized in that, Determining the performance consumption of the execution components on the running sub-controller based on the instruction execution timing includes: The execution time of the same instruction in the instruction execution sequence is extracted and processed to obtain a time consumption index that characterizes the performance consumption of the corresponding component in the time dimension. The required bandwidth of the same instruction in the instruction execution sequence is extracted and processed to obtain a bandwidth consumption index that characterizes the performance consumption of the corresponding component in the bandwidth dimension. Based on the time consumption and bandwidth consumption metrics of each execution component, the performance consumption of the corresponding component is obtained.

3. The instrument distributed redundant bus control system for enhanced fault tolerance as described in claim 2, characterized in that, The execution time of identical instructions in the instruction execution sequence is extracted and processed to obtain time consumption indicators characterizing the performance consumption of the corresponding components in the time dimension, including: Extract the execution time of each execution component under the same instruction from the instruction execution timing sequence, and calculate the time difference between the first execution time of each execution component and the second execution time of other execution components; The time consumption index of the current component in executing the corresponding instruction is obtained by comparing the average of all time differences of the current component with the time required for the current component to execute a single instruction.

4. The instrument distributed redundant bus control system with enhanced fault tolerance capability according to claim 2, characterized in that, The required bandwidth of the same instructions in the instruction execution sequence is extracted and processed to obtain a bandwidth consumption index characterizing the performance consumption of the corresponding component in the bandwidth dimension, including: Obtain the bandwidth required for each execution component to perform data processing for the current instruction in the instruction execution timing sequence, as well as the bus bandwidth of the communication bus; The bandwidth consumption index of the corresponding execution component is obtained based on the ratio of the required bandwidth of each execution component to the bus bandwidth.

5. The instrument distributed redundant bus control system for enhanced fault tolerance as described in claim 1, characterized in that, The execution cost of the corresponding component executing the instruction corresponding to the control task is obtained based on the performance consumption level, including: The performance consumption ratio of a given execution component is obtained by comparing the performance consumption of each execution component in executing the corresponding instruction with its maximum performance consumption. The execution cost of the corresponding execution component is obtained by the absolute value of the difference between the load rate of each execution component executing the corresponding instruction and the performance consumption ratio.

6. The instrument distributed redundant bus control system for enhanced fault tolerance as described in claim 1, characterized in that, When the execution cost exceeds the capacity limit of the corresponding component, an allocation instruction is output via the communication bus, including: The execution cost is arranged according to the execution order of each component when each instruction is executed, so as to obtain the execution cost sequence representing the multiple executions of the corresponding instruction; The execution cost sequence is subjected to maximum data extraction and processing to obtain the blocking parameters that characterize the degree of blocking of the corresponding execution components under the execution instructions; When the blocking parameter is greater than a preset blocking threshold, an allocation command is output to the communication bus based on the blocking parameter and the number of redundant sub-controllers.

7. The instrument distributed redundant bus control system for enhanced fault tolerance as described in claim 6, characterized in that, The execution cost sequence is subjected to maximum data extraction and processing to obtain blocking parameters that characterize the degree of blocking of the corresponding execution components under the execution instructions, including: A multi-scale peak lookup model is used to extract maximum data from the execution cost sequence, and the location of each maximum value is determined as a high-cost load point. Blocking characteristic analysis is performed based on all high-cost load points and their corresponding maximum execution costs to obtain the blocking parameters of the corresponding execution components during instruction execution.

8. The instrument distributed redundant bus control system with enhanced fault tolerance capability according to claim 7, characterized in that, Blocking characteristic analysis is performed based on all high-cost load points and their corresponding maximum execution costs to obtain the blocking parameters of the corresponding execution components during instruction execution, including: The blocking coefficient is obtained based on the cost difference between two adjacent maximum execution costs, the average cost, and the standard deviation of the cost. Based on the summation of all blocking coefficients between two adjacent high-cost load points, the blocking parameters of the corresponding execution device during instruction execution are obtained.

9. The instrument distributed redundant bus control system for enhanced fault tolerance as described in claim 6, characterized in that, Based on the blocking parameters and the number of redundant sub-controllers, an allocation instruction is output to the communication bus, including: The ratio of the blocking parameter to the distribution quantity is rounded up and the result is determined as the instruction allocation ratio; The number of instructions to be allocated is obtained based on the instruction allocation ratio and the total number of instructions for the control task; The corresponding instructions are allocated to the communication bus according to the number of instructions, so that the redundant sub-controller can execute the corresponding processing sub-task.

10. The instrument distributed redundant bus control system for enhanced fault tolerance as described in claim 1, characterized in that, Before outputting allocation instructions to the communication bus, the main controller is also used to: The communication bus broadcasts a priori address list and configures the redundant processing unit of the redundant sub-controller according to the received response results, so that the redundant processing unit is in a standby state to take over the processing sub-task in real time.

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