Control device, drive system, and vehicle
By setting the initial state circuit to determine the establishment state of the reference voltage, the problem of inaccurate reference voltage is solved, ensuring the reliability and accuracy of drive control.
Patent Information
- Application Number
- CN202511200689.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-25
- Publication Date
- 2025-12-26
AI Technical Summary
Traditional solutions suffer from inaccurate reference voltages during the initial power-on phase when the reference voltage is not fully established, which affects the reliability of drive control.
The initial state circuit determines the reference voltage output by the reference voltage generation circuit and outputs different state control signals to the voltage comparison circuit before the initial state is fully established, so as to avoid inaccurate reference voltage affecting the drive control.
This improves the reliability of voltage monitoring, ensures the effectiveness of drive control, and avoids erroneous drive operations when the reference voltage is not fully established.
Smart Images
Figure CN121209331A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a control device, drive system and vehicle. Background Technology
[0002] In some driving scenarios, to ensure the driving capability of the driving device (such as the emitter driver chip of VCSEL; VCSEL stands for Vertical-Cavity Surface-Emitting Laser, a light source used in optical communication and photosensing), the driving device is typically activated only after the power supply voltage reaches a certain value. To achieve this, a corresponding control device is usually set up to monitor the power supply voltage based on a reference voltage. Upon meeting the monitoring conditions, the device outputs a corresponding driving control signal to activate its driving function.
[0003] However, traditional solutions do not take into account the fact that the reference voltage is not fully established at the beginning of power-on, which leads to inaccurate reference voltage and reduces the reliability of voltage monitoring based on the reference voltage, ultimately affecting the effect of drive control. Summary of the Invention
[0004] This application provides a control device, a drive system, and a vehicle, which includes a reference voltage generation circuit, a voltage comparison circuit, and an initial state circuit. The initial state circuit can determine the reference voltage output by the reference voltage generation circuit and output different state control signals to the voltage comparison circuit when the reference voltage is not fully established and when it is fully established. This allows the voltage comparison circuit to directly output a drive control signal indicating that the drive has stopped when the reference voltage is not fully established, thereby at least partially solving the above-mentioned technical problems.
[0005] To achieve the above objectives, according to a first aspect of this application, a control device is provided, comprising a reference voltage generating circuit, a voltage comparison circuit, and an initial state circuit.
[0006] The initial state circuit is electrically connected to the reference voltage generation circuit and the voltage comparison circuit respectively. It is used to output a first state control signal to the voltage comparison circuit when the reference voltage output by the reference voltage generation circuit is not fully established, and to output a second state control signal to the voltage comparison circuit when the reference voltage is fully established.
[0007] The voltage comparison circuit is also electrically connected to the reference voltage generation circuit and is used to be electrically connected to the power supply and the drive device respectively. When the first state control signal is received, it is used to output a first drive control signal indicating that the drive has stopped, and when the second state control signal is received, it outputs a first drive control signal indicating that the drive has stopped or a second drive control signal indicating that the drive has started, based on the reference voltage and the power supply voltage of the power supply.
[0008] Optionally, the reference voltage generation circuit includes a startup module and a reference voltage generation module;
[0009] The startup module and the reference voltage generation module are respectively used for electrical connection to the power supply;
[0010] The startup module is also electrically connected to the reference voltage generation module, and is used to output startup current to the reference voltage generation module according to the power supply voltage.
[0011] The reference voltage generation module is also electrically connected to the voltage comparison circuit and the initial state circuit, respectively, and is used to output a reference voltage to the voltage comparison circuit and the initial state circuit according to the power supply voltage and the starting current of the power supply.
[0012] Optionally, the reference voltage generation module includes a first PMOS transistor, a second PMOS transistor, a first NPN transistor, a second NPN transistor, a first resistor, and a second resistor;
[0013] The source of the first PMOS transistor and the source of the second PMOS transistor are respectively used to be electrically connected to the power supply. The gate of the first PMOS transistor is electrically connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor, the collector of the first NPN transistor and the startup module. The drain of the second PMOS transistor is electrically connected to the collector of the second NPN transistor.
[0014] The base of the first NPN transistor is electrically connected to the base of the second NPN transistor, the voltage comparator circuit, and the initial state circuit, respectively. The emitter of the first NPN transistor is electrically connected to the first terminal of the second resistor and the emitter of the second NPN transistor through the first resistor. The second terminal of the second resistor is used for grounding.
[0015] Optionally, the startup module includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, and a second NMOS transistor;
[0016] The source of the third PMOS transistor is electrically connected to the power supply. The gate of the third PMOS transistor is electrically connected to the drain of the third PMOS transistor and the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is electrically connected to the drain of the fourth PMOS transistor and the source of the fifth PMOS transistor.
[0017] The gate of the fifth PMOS transistor and the gate of the first NMOS transistor are electrically connected to the base of the first NPN transistor, respectively. The drain of the fifth PMOS transistor is electrically connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, respectively. The drain of the second NMOS transistor is electrically connected to the collector of the first NPN transistor. The source of the first NMOS transistor and the source of the second NMOS transistor are respectively used for grounding.
[0018] Optionally, the voltage comparison circuit includes a comparison module and a NAND logic module;
[0019] The comparison module is electrically connected to the reference voltage generation circuit and the NAND logic module, and is also used to be electrically connected to the power supply. It is used to output comparison control signals to the NAND logic module according to the power supply voltage and the reference voltage.
[0020] The NAND logic module is also electrically connected to the initial state circuit and is used to be electrically connected to the drive device. It is used to output a first drive control signal to the drive device when a first state control signal is received, and to output a first drive control signal or a second drive control signal to the drive device according to the comparison control signal when a second state control signal is received.
[0021] Optionally, the comparator module includes a third resistor, a fourth resistor, a fifth resistor, a sixth PMOS transistor, a comparator, and a first inverter;
[0022] The first terminal of the third resistor and the source of the sixth PMOS transistor are respectively used to connect to the power supply. The second terminal of the third resistor is connected to the drain of the sixth PMOS transistor and is connected to the first terminal of the fifth resistor and the non-inverting input terminal of the comparator through the fourth resistor. The second terminal of the fifth resistor is used to ground. The inverting input terminal of the comparator is connected to the reference voltage generation circuit. The output terminal of the comparator is connected to the gate of the sixth PMOS transistor and the NAND logic module through the first inverter.
[0023] Optionally, the NAND logic module includes a second inverter, a NAND gate, and a third inverter;
[0024] The first input terminal of the NAND gate is electrically connected to the comparator module through the second inverter, the second input terminal of the NAND gate is electrically connected to the initial state circuit, and the output terminal of the NAND gate is used to be electrically connected to the driving device through the third inverter.
[0025] Optionally, the NAND logic module may also include a first delay unit;
[0026] The output of the NAND gate is electrically connected to the third inverter through the first delay unit.
[0027] Optionally, the first delay unit includes a seventh PMOS transistor, a third NMOS transistor, a sixth resistor, and a first capacitor;
[0028] The gates of the seventh PMOS transistor and the third NMOS transistor are electrically connected to the output of the NAND gate, respectively. The source of the seventh PMOS transistor is electrically connected to the power supply. The drain of the seventh PMOS transistor is electrically connected to the drain of the third NMOS transistor, the input of the third inverter, and the first terminal of the first capacitor through the sixth resistor. The source of the third NMOS transistor and the second terminal of the first capacitor are grounded.
[0029] Optionally, the initial state circuit includes a reference voltage sampling module and a state control module;
[0030] The reference voltage sampling module is electrically connected to the reference voltage generation circuit and the state control module respectively, and is used to sample the reference voltage and output the sampled voltage to the state control module.
[0031] The state control module is also electrically connected to the voltage comparison circuit and is used to connect to the power supply. It is used to output a first state control signal or a second state control signal to the voltage comparison circuit based on the power supply voltage and the sampled voltage.
[0032] Optionally, the reference voltage sampling module includes a seventh resistor and an eighth resistor;
[0033] The first end of the seventh resistor is electrically connected to the reference voltage generating circuit, the second end of the seventh resistor is electrically connected to the first end of the eighth resistor and the status control module, and the second end of the eighth resistor is used for grounding.
[0034] Optionally, the state control module includes an eighth PMOS transistor, a ninth PMOS transistor, a ninth resistor, a fourth NMOS transistor, and a fourth inverter;
[0035] The source of the eighth PMOS transistor and the source of the ninth PMOS transistor are respectively used to connect to the power supply. The gate of the eighth PMOS transistor is respectively connected to the gate of the ninth PMOS transistor, the drain of the eighth PMOS transistor, and the first end of the ninth resistor. The drain of the ninth PMOS transistor is respectively connected to the input of the fourth inverter and the drain of the fourth NMOS transistor. The second end of the ninth resistor and the source of the fourth NMOS transistor are respectively used to ground. The output of the fourth inverter is connected to the voltage comparator circuit.
[0036] Optionally, the state control module may also include a second delay unit;
[0037] The drain of the ninth PMOS transistor is electrically connected to the fourth inverter through the second delay unit.
[0038] Optionally, the second delay unit includes a tenth PMOS transistor, a fifth NMOS transistor, a tenth resistor, and a second capacitor;
[0039] The gate of the tenth PMOS transistor and the gate of the fifth NMOS transistor are electrically connected to the drain of the ninth PMOS transistor, respectively. The source of the tenth PMOS transistor is used to connect to the power supply. The drain of the tenth PMOS transistor is connected to the drain of the fifth NMOS transistor, the input terminal of the fourth inverter, and the first terminal of the second capacitor through the tenth resistor, respectively. The source of the fifth NMOS transistor and the second terminal of the second capacitor are used to ground, respectively.
[0040] According to a second aspect of this application, a drive system is provided, including a drive device and a control device in any of the above embodiments.
[0041] According to a third aspect of this application, a vehicle is provided, including the control device in any of the above embodiments, or including the drive system in any of the above embodiments.
[0042] The control device in this application includes a reference voltage generation circuit, a voltage comparison circuit, and an initial state circuit. The initial state circuit can judge the reference voltage output by the reference voltage generation circuit and output different state control signals to the voltage comparison circuit when the reference voltage is not fully established and when it is fully established. This allows the voltage comparison circuit to directly output a drive control signal indicating that the drive has stopped when the reference voltage is not fully established, thereby avoiding inaccurate reference voltage when outputting the corresponding drive control signal based on voltage comparison, improving the reliability of voltage monitoring, and ensuring the effect of drive control.
[0043] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0046] Figure 1 This is a schematic diagram of the structure of the control device provided in an exemplary embodiment of this application;
[0047] Figure 2 This is a schematic diagram of the specific circuit of the driving device provided in the exemplary embodiments of this application;
[0048] Figure 3This is a schematic diagram of the specific structure of the control device including the reference voltage generation circuit provided in the exemplary embodiment of this application;
[0049] Figure 4 This is a schematic diagram of a reference voltage generation circuit provided in an exemplary embodiment of this application.
[0050] Figure 5 This is a schematic diagram of the specific structure of the control device provided in the exemplary embodiment of this application, which further includes a voltage comparison circuit;
[0051] Figure 6 This is a schematic diagram of a voltage comparison circuit provided in an exemplary embodiment of this application.
[0052] Figure 7 This is a schematic diagram of the structure for generating bias voltage provided in an exemplary embodiment of this application;
[0053] Figure 8 This is a schematic diagram of the specific structure of the control device provided in the exemplary embodiment of this application, which further includes an initial state circuit;
[0054] Figure 9 This is a schematic diagram of the initial state circuit provided in an exemplary embodiment of this application;
[0055] Figure 10 This is a simulation diagram provided in an exemplary embodiment of this application. Detailed Implementation
[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0057] According to the first aspect of this application, Figure 1 As shown, a control device is provided, including a reference voltage generation circuit, a voltage comparison circuit, and an initial state circuit.
[0058] The reference voltage generation circuit is used to connect electrically to the power supply and output a reference voltage vref based on the power supply voltage VDD.
[0059] The initial state circuit is electrically connected to both the reference voltage generation circuit and the voltage comparison circuit. It outputs a state control signal ctrl to the voltage comparison circuit based on the reference voltage vref output by the reference voltage generation circuit. Specifically, when the reference voltage vref is not fully established, the state control signal ctrl is in the first state, which can be understood as the first state control signal. Similarly, when the reference voltage vref is fully established, the state control signal ctrl is in the second state, which can be understood as the second state signal.
[0060] In this process, it can be understood that after the control device is powered on, the reference voltage generation circuit starts working and outputs a reference voltage vref. As the establishment process progresses, the amplitude of the reference voltage vref continuously increases until it reaches a stable value, at which point it is determined that the voltage has been fully established; otherwise, it is determined that the voltage has not been fully established. The initial state circuit can then perform threshold judgments based on the amplitude of the reference voltage vref, thereby outputting different state control signals ctrl. For example, when the reference voltage vref has not reached a stable value, the initial state circuit outputs the first state control signal ctrl to convey the information "the reference voltage vref has not been fully established" to the voltage comparison circuit; conversely, when the reference voltage vref reaches a stable value, the initial state circuit outputs the second state control signal ctrl to convey the information "the reference voltage vref has been fully established" to the voltage comparison circuit.
[0061] The voltage comparison circuit is also electrically connected to the reference voltage generation circuit and is used to be electrically connected to the power supply and the drive device respectively. When the state control signal ctrl of the first state is connected, it is used to output a drive control signal UVLO (which can be understood as the first drive control signal, corresponding to the first state of the drive control signal UVLO) to the drive device, which represents stopping the drive; and when the state control signal ctrl of the second state is connected, it outputs a drive control signal UVLO (which represents stopping the drive) or a drive control signal UVLO (which can be understood as the second drive control signal, corresponding to the second state of the drive control signal UVLO) to the drive device according to the reference voltage vref and the power supply voltage VDD.
[0062] As mentioned above, the initial state circuit can output a first-state state control signal ctrl to the voltage comparator circuit when the reference voltage vref is not fully established. Therefore, when the voltage comparator circuit receives the first-state state control signal ctrl, it directly outputs a drive control signal UVLO indicating that the drive has stopped, thereby avoiding incorrect voltage comparison operations based on the reference voltage vref when it is not fully established, and thus preventing the drive device from starting the drive function when the power supply voltage VDD has not reached the target value.
[0063] Furthermore, as mentioned above, the initial-state circuit can output a second-state state control signal ctrl to the voltage comparator circuit when the reference voltage vref is fully established. Therefore, when the second-state state control signal ctrl is input, the voltage comparator circuit can perform its voltage comparison operation, thereby further determining whether the power supply voltage VDD has reached the target value based on the input power supply voltage VDD and the reference voltage vref. If the power supply voltage VDD has reached but not reached the target value, a drive control signal UVLO indicating a stop to drive is output to the drive device; if the power supply voltage VDD has reached the target value, a drive control signal UVLO indicating a start to drive is output to the drive device.
[0064] like Figure 2 As shown, taking a VCSEL emitter driver chip as an example, the driver chip includes resistors R21 and R22, Schmitt trigger B11 and B12, AND gate U11 and NAND gate U12, drive amplifier unit DRIVE, PMOS transistor Q11 and NMOS transistor Q12.
[0065] In this embodiment, AND gate U11 is connected to the drive control signal UVLO and the over-temperature protection signal OTP output by the control device. If the second state of the drive control signal UVLO is high and the over-temperature protection signal OTP is high when the temperature does not exceed the temperature threshold, then the drive chip can start the drive function only when both the drive control signal UVLO and the over-temperature protection signal OTP are high. In this way, the drive output signals OUTH and OUTL are output according to the connected power supply voltage VDD, drive input signals IN+ and IN-.
[0066] The control device in this application includes a reference voltage generation circuit, a voltage comparison circuit, and an initial state circuit. The initial state circuit can judge the reference voltage output by the reference voltage generation circuit and output different state control signals to the voltage comparison circuit when the reference voltage is not fully established and when it is fully established. This allows the voltage comparison circuit to directly output a drive control signal indicating that the drive has stopped when the reference voltage is not fully established, thereby avoiding inaccurate reference voltage when outputting the corresponding drive control signal based on voltage comparison, improving the reliability of voltage monitoring, and ensuring the effect of drive control.
[0067] like Figure 3 As shown, optionally, the reference voltage generation circuit includes a startup module and a reference voltage generation module.
[0068] The startup module and the reference voltage generation module are respectively used to be electrically connected to the power supply to access the power supply voltage VDD.
[0069] The startup module is also electrically connected to the reference voltage generation module, and is used to output startup current to the reference voltage generation module according to the power supply voltage VDD.
[0070] The reference voltage generation module is also electrically connected to the voltage comparison circuit and the initial state circuit, respectively, and is used to output the reference voltage vref to the voltage comparison circuit and the initial state circuit according to the power supply voltage VDD and the starting current of the power supply.
[0071] Specifically, such as Figure 4 As shown, the reference voltage generation module includes a first PMOS transistor M1, a second PMOS transistor M2, a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, and a second resistor R2. The startup module includes a third PMOS transistor M6, a fourth PMOS transistor M7, a fifth PMOS transistor M8, a first NMOS transistor M9, and a second NMOS transistor M5.
[0072] The source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 are respectively connected to the power supply to receive the power supply voltage VDD. The gate of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2, the drain of the first PMOS transistor M1, the collector of the first NPN transistor Q1, and the drain of the second NMOS transistor M5. The drain of the second PMOS transistor M2 is connected to the collector of the second NPN transistor Q2. The base of the first NPN transistor Q1 is connected to the base of the second NPN transistor Q2, the voltage comparator circuit, the initial state circuit, the gate of the fifth PMOS transistor M8, and the gate of the first NMOS transistor M9 to output the reference voltage vref. The emitter of the first NPN transistor Q1 is connected to the first terminal of the second resistor R2 and the emitter of the second NPN transistor Q2 through the first resistor R1. The second terminal of the second resistor R2 is grounded.
[0073] The source of the third PMOS transistor M6 is electrically connected to the power supply to receive the power supply voltage VDD. The gate of the third PMOS transistor M6 is electrically connected to the drain of the third PMOS transistor M6 and the source of the fourth PMOS transistor M7. The gate of the fourth PMOS transistor M7 is electrically connected to the drain of the fourth PMOS transistor M7 and the source of the fifth PMOS transistor M8. The drain of the fifth PMOS transistor M8 is electrically connected to the drain of the first NMOS transistor M9 and the gate of the second NMOS transistor M5. The source of the first NMOS transistor M9 and the source of the second NMOS transistor M5 are grounded.
[0074] In this structure, the first PMOS transistor M1 and the second PMOS transistor M2 form a current mirror structure with the same drain current. The size ratio of the first NPN transistor Q1 to the second NPN transistor Q2 is 8:1. The collector current I of the first NPN transistor Q1 is...C1 = Collector current I of the second NPN transistor Q2 C2 = Current I of the first resistor R1 R1 The current I in the second resistor R2 R2 =I R1 +I C2 =2I R1 Since the voltage across R1 is the base-emitter voltage V of the second NPN transistor Q2 BE2 -The base-emitter voltage V of the first NPN transistor Q1 BE1 Then IR1 = (VBE2 - VBE1) / R1, which gives vref = I R2 *R2+V BE2 =2*I R1 *R2+V BE2 =2(V BE2 -V BE1 )*R2 / R1+V BE2 ; Due to V BE2 With a negative temperature coefficient, V BE2 -V BE1 With a positive temperature coefficient, a temperature-independent reference voltage vref can be obtained by adjusting the ratio of R1 and R2. When the reference voltage vref is not established, the third PMOS transistor M6, the fourth PMOS transistor M7, and the fifth PMOS transistor M8 are turned on, which turns on the second NMOS transistor M5 and provides the startup current to enable the reference voltage generation module to start up.
[0075] like Figure 5 As shown, optionally, the voltage comparison circuit includes a comparison module and a NAND logic module.
[0076] The comparison module is electrically connected to the reference voltage generation circuit and the NAND logic module, and is also used to connect to the power supply. It is used to output a comparison control signal comp to the NAND logic module based on the power supply voltage VDD and the reference voltage vref.
[0077] The NAND logic module is also electrically connected to the initial state circuit and is used to be electrically connected to the drive device. It is used to output the drive control signal UVLO of the first state to the drive device when the state control signal ctrl of the first state is connected, and to output the drive control signal UVLO of the first state or the drive control signal UVLO of the second state to the drive device according to the comparison control signal comp when the state control signal ctrl of the second state is connected.
[0078] Specifically, such as Figure 6As shown, the comparison module includes a third resistor R6, a fourth resistor R7, a fifth resistor R8, a sixth PMOS transistor M17, a comparator U1, and a first inverter B1. The NAND logic module includes a second inverter B2, a NAND gate U2, a first delay unit composed of a seventh PMOS transistor M13, a third NMOS transistor M14, a sixth resistor R10, and a first capacitor C2, and a third inverter B4.
[0079] The first terminal of the third resistor R6 and the source of the sixth PMOS transistor M17 are electrically connected to the power supply to receive the power supply voltage VDD. The second terminal of the third resistor R6 is electrically connected to the drain of the sixth PMOS transistor M17 and, through the fourth resistor R7, is electrically connected to the first terminal of the fifth resistor R8 and the non-inverting input terminal of comparator U1 to output voltage vin to comparator U1 through voltage division. The second terminal of the fifth resistor R8 is grounded. The inverting input terminal of comparator U1 is electrically connected to the reference voltage generation circuit to receive the reference voltage vref. The output terminal of comparator U1 is electrically connected to the gate of the sixth PMOS transistor M17 and the input terminal of the second inverter B2 through the first inverter B1.
[0080] The output of the second inverter B2 is electrically connected to the first input of the NAND gate U2. The second input of the NAND gate U2 is electrically connected to the initial state circuit to receive the state control signal ctrl. The gates of the seventh PMOS transistor M13 and the third NMOS transistor M14 are electrically connected to the output of the NAND gate U2. The source of the seventh PMOS transistor M13 is electrically connected to the power supply to receive the power supply voltage VDD. The drain of the seventh PMOS transistor M13 is electrically connected to the drain of the third NMOS transistor M14, the first terminal of the first capacitor C2, and the input of the Schmitt trigger U4 through the sixth resistor R10. The output of the Schmitt trigger U4 is electrically connected to the input of the third inverter B4. The output of the third inverter B4 is electrically connected to the driving device to output the drive control signal UVLO. The source of the third NMOS transistor M14 and the second terminal of the first capacitor C2 are grounded.
[0081] The power supply voltage VDD is discharged through a resistor string consisting of the third resistor R6, the fourth resistor R7, and the fifth resistor R8.
[0082] As the power supply voltage VDD increases, the gate voltage of the sixth PMOS transistor M17 is high, and the sixth PMOS transistor M17 is turned off. At this time, the voltage at the non-inverting input of comparator U1... When vin > vref, the comparator U1 outputs a high level. After passing through the first inverter B1 and the second inverter B2, a high level is output to the first input terminal of the NAND gate U2. At this time, if the state control signal ctrl is in the second state (i.e., the reference voltage vref is fully established) and is high, the NAND gate U2 outputs a low level. After passing through the first delay unit composed of the seventh PMOS transistor M13, the third NMOS transistor M14, the sixth resistor R10, and the first capacitor C2, the Schmitt trigger U4, and the third inverter B4, the output drive control signal UVLO becomes high, and the drive device starts the drive function, and the corresponding turn-on threshold voltage
[0083] During the process of the power supply voltage VDD decreasing, the gate voltage of the sixth PMOS transistor M17 is low, and the sixth PMOS transistor M17 is turned on. At this time, the voltage at the non-inverting input terminal of the comparator U1 When vin < vref, the comparator U1 outputs a low level. After passing through the first inverter B1 and the second inverter B2, a low level is output to the first input terminal of the NAND gate U2, causing the NAND gate U2 to output a high level. After passing through the first delay unit composed of the seventh PMOS transistor M13, the third NMOS transistor M14, the sixth resistor R10, and the first capacitor C2, the Schmitt trigger U4, and the third inverter B4, the output drive control signal UVLO becomes low, and the drive device stops the drive function, and the corresponding turn-off threshold voltage
[0084] It can be seen that obviously V_OFF < V_ON, so as to ensure that the drive control signal UVLO is only turned off when the power supply voltage VDD is less than the turn-off threshold voltage V_OFF, avoiding the output level of the drive control signal UVLO from oscillating repeatedly near the threshold. At the same time, connecting the Schmitt trigger U4 and the third inverter B4 at the output terminal of the first delay unit for output shaping can filter out the influence of noise on the drive control signal UVLO.
[0085] Such as Figure 6 and Figure 7 As shown, optionally, the comparison module further includes an NMOS transistor M3 and a PMOS transistor M4. The drain of the NMOS transistor M3 is electrically connected to the power supply to access the power supply voltage VDD. The source of the NMOS transistor M3 is electrically connected to the gate of the NMOS transistor M3, the source of the PMOS transistor M4, and the power supply terminal of the comparator U1 to output a bias voltage vbias. The gate of the PMOS transistor M4 is electrically connected to the collector of the second NPN transistor Q2, and the drain of the PMOS transistor M4 is electrically connected to the base of the second NPN transistor Q2.
[0086] Such as Figure 8As shown, optionally, the initial state circuit includes a reference voltage sampling module and a state control module.
[0087] The reference voltage sampling module is electrically connected to the reference voltage generation circuit and the state control module, respectively, and is used to sample the reference voltage vref and output the sampled voltage vpd to the state control module.
[0088] The status control module is also electrically connected to the voltage comparator circuit and is used to connect to the power supply. It outputs a status control signal UVLO to the voltage comparator circuit based on the power supply voltage VDD and the sampling voltage vpd.
[0089] Specifically, such as Figure 9 As shown, the reference voltage sampling module includes a seventh resistor R3 and an eighth resistor R4, and the state control module includes an eighth PMOS transistor M10, a ninth PMOS transistor M11, a ninth resistor R5, a fourth NMOS transistor M12, a second delay unit composed of a tenth PMOS transistor M15, a fifth NMOS transistor M16, a tenth resistor R9, and a second capacitor C1, as well as a fourth inverter B3.
[0090] The first end of the seventh resistor R3 is electrically connected to the reference voltage generating circuit to receive the reference voltage vref. The second end of the seventh resistor R3 is electrically connected to the first end of the eighth resistor R4 and the gate of the fourth NMOS transistor M12. The second end of the eighth resistor R4 is used for grounding.
[0091] The source of the eighth PMOS transistor M10 and the source of the ninth PMOS transistor M11 are respectively used to be electrically connected to the power supply to connect to the power supply voltage VDD. The gate of the eighth PMOS transistor M10 is electrically connected to the gate of the ninth PMOS transistor M11, the drain of the eighth PMOS transistor M10 and the first terminal of the ninth resistor R5. The drain of the ninth PMOS transistor M11 is electrically connected to the drain of the fourth NMOS transistor M12, the gate of the tenth PMOS transistor M15 and the gate of the fifth NMOS transistor M16. The second terminal of the ninth resistor R5 and the source of the fourth NMOS transistor M12 are respectively used to ground.
[0092] The source of the tenth PMOS transistor M15 is electrically connected to the power supply to receive the power supply voltage VDD. The drain of the tenth PMOS transistor M15 is electrically connected to the drain of the fifth NMOS transistor M16, the input of Schmitt trigger U3, and the first terminal of the second capacitor C1 through the tenth resistor R9. The output of Schmitt trigger U3 is electrically connected to the input of the fourth inverter B3. The output of the fourth inverter B3 is electrically connected to the voltage comparator circuit to output the status control signal ctrl. The source of the fifth NMOS transistor M16 and the second terminal of the second capacitor C1 are respectively used for grounding.
[0093] Specifically, the reference voltage vref is sampled by voltage division using the seventh resistor R3 and the eighth resistor R4 to obtain the sampled voltage. By adjusting the ratio of R3 to R4, the sampling voltage vpd is made greater than the threshold voltage of the fourth NMOS transistor M12 after the reference voltage vref is fully established. At this time, the fourth NMOS transistor M12 is turned on.
[0094] Specifically, the bias current is provided by the eighth PMOS transistor M10 and the ninth resistor R5, and then mirrored to the fourth NMOS transistor M12 through a current mirror composed of the eighth PMOS transistor M10 and the ninth PMOS transistor M11. When the fourth NMOS transistor M12 is turned on, the voltage vst becomes low. After passing through the second delay unit composed of the tenth PMOS transistor M15, the fifth NMOS transistor M16, the tenth resistor R9, and the second capacitor C1, the reference voltage vref is fully established, enhancing its stability. When the voltage vst becomes low, the fourth inverter B3 outputs a high level, unlocking the output logic of the NAND gate U2, so that the drive control signal UVLO can be output according to the magnitude of the power supply voltage VDD.
[0095] The simulation results of the control device in this application are as follows: Figure 10 As shown in the simulation graph, the horizontal axis represents time in milliseconds (ms) and ranges from 0 ms to 15 ms, while the vertical axis represents voltage in volts (V) and ranges from 0 V to 5 V. Figure 10 VDD is the power supply voltage, which increases linearly from 0V to 5V within the range of 0ms to 5ms, and decreases linearly from 5V to 0V within the range of 10ms to 15ms. Vref is the reference voltage, which gradually establishes itself as VDD rises and is fully established in 2.2ms, and de-establishes itself as VDD falls in 12.8ms. Vst is the reference establishment signal, which goes low at 2.1ms as the reference is almost fully established, and becomes relatively low at 12.9ms as the reference voltage begins to fall. UVLO is the drive control signal, which changes from low to high when VDD rises to 4.185mV to enable the drive function, and changes from high to low when VDD falls to 4.1mV to disable the drive function. As can be seen from the simulation diagram, VST will only go low after VRef is basically fully established. After the aforementioned delay, the drive control signal UVLO can be enabled only after the reference voltage VRef is fully established, which ensures the stability of the initial state during the VDD establishment process and avoids the situation of logic undervoltage false triggering.
[0096] According to a second aspect of this application, a drive system is provided, including a drive device and a control device in any of the above embodiments.
[0097] The drive system in this application includes a control device comprising a reference voltage generation circuit, a voltage comparison circuit, and an initial state circuit. The initial state circuit can determine the reference voltage output by the reference voltage generation circuit and output different state control signals to the voltage comparison circuit when the reference voltage is not fully established and when it is fully established. This allows the voltage comparison circuit to directly output a drive control signal indicating that the drive has stopped when the reference voltage is not fully established, thereby avoiding inaccurate reference voltage when outputting the corresponding drive control signal based on voltage comparison, improving the reliability of voltage monitoring, and ensuring the effectiveness of drive control.
[0098] According to a third aspect of this application, a vehicle is provided, including the control device in any of the above embodiments, or including the drive system in any of the above embodiments.
[0099] The control device included in the vehicle of this application is equipped with a reference voltage generation circuit, a voltage comparison circuit, and an initial state circuit. The initial state circuit can judge the reference voltage output by the reference voltage generation circuit and output different state control signals to the voltage comparison circuit when the reference voltage is not fully established and when it is fully established. This allows the voltage comparison circuit to directly output a drive control signal indicating that the drive has stopped when the reference voltage is not fully established, thereby avoiding inaccurate reference voltage when outputting the corresponding drive control signal based on voltage comparison, improving the reliability of voltage monitoring, and ensuring the effect of drive control.
[0100] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0102] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0103] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. In the embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant content of other embodiments. Any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A control device characterized by comprising: The reference voltage generating circuit, the voltage comparison circuit and the initial state circuit are provided. The initial state circuit is electrically connected with the reference voltage generating circuit and the voltage comparison circuit, and is configured to output a first state control signal to the voltage comparison circuit when the reference voltage output by the reference voltage generating circuit is not completely established, and output a second state control signal to the voltage comparison circuit when the reference voltage is completely established. The voltage comparison circuit is also electrically connected with the reference voltage generating circuit, and is configured to be electrically connected with a power supply and a driving device, and output a first driving control signal representing stop driving to the driving device when the first state control signal is connected, and output the first driving control signal representing stop driving or a second driving control signal representing start driving to the driving device according to the reference voltage and a power voltage of the power supply when the second state control signal is connected.
2. The control device according to claim 1, characterized by The reference voltage generating circuit comprises a start module and a reference voltage generating module. The start module and the reference voltage generating module are configured to be electrically connected with the power supply. The start module is also electrically connected with the reference voltage generating module, and is configured to output a start current to the reference voltage generating module according to a power voltage of the power supply. The reference voltage generating module is also electrically connected with the voltage comparison circuit and the initial state circuit, and is configured to output the reference voltage to the voltage comparison circuit and the initial state circuit according to the power voltage of the power supply and the start current.
3. The control device of claim 2, wherein The reference voltage generating module comprises a first PMOS tube, a second PMOS tube, a first NPN triode, a second NPN triode, a first resistor and a second resistor. The source of the first PMOS tube and the source of the second PMOS tube are configured to be electrically connected with the power supply, the gate of the first PMOS tube is electrically connected with the gate of the second PMOS tube, the drain of the first PMOS tube, the collector of the first NPN triode and the start module, the drain of the second PMOS tube is electrically connected with the collector of the second NPN triode. The base of the first NPN triode is electrically connected with the base of the second NPN triode, the voltage comparison circuit and the initial state circuit, the emitter of the first NPN triode is electrically connected with the first end of the second resistor and the emitter of the second NPN triode through the first resistor, and the second end of the second resistor is configured to be grounded.
4. The control device according to claim 3, characterized by The start module comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube. The source of the third PMOS tube is configured to be electrically connected with the power supply, the gate of the third PMOS tube is electrically connected with the drain of the third PMOS tube and the source of the fourth PMOS tube, and the gate of the fourth PMOS tube is electrically connected with the drain of the fourth PMOS tube and the source of the fifth PMOS tube. The gate of the fifth PMOS tube and the gate of the first NMOS tube are electrically connected with the base of the first NPN triode respectively, the drain of the fifth PMOS tube is electrically connected with the drain of the first NMOS tube and the gate of the second NMOS tube respectively, the drain of the second NMOS tube is electrically connected with the collector of the first NPN triode, and the source of the first NMOS tube and the source of the second NMOS tube are grounded respectively.
5. The control device of claim 1, wherein The voltage comparison circuit comprises a comparison module and a NAND logic module; The comparison module is electrically connected with the reference voltage generation circuit and the NAND logic module and is used for being electrically connected with the power supply, and outputs a comparison control signal to the NAND logic module according to the power supply voltage and the reference voltage; The NAND logic module is also electrically connected with the initial state circuit and is used for being electrically connected with the driving device, outputs the first driving control signal to the driving device when the first state control signal is accessed, and outputs the first driving control signal or the second driving control signal to the driving device according to the comparison control signal when the second state control signal is accessed.
6. The control device of claim 5, wherein The comparison module comprises a third resistor, a fourth resistor, a fifth resistor, a sixth PMOS tube, a comparator and a first inverter; The first end of the third resistor and the source of the sixth PMOS tube are used for being electrically connected with the power supply respectively, the second end of the third resistor is electrically connected with the drain of the sixth PMOS tube and is electrically connected with the first end of the fifth resistor and the non-inverted input end of the comparator through the fourth resistor respectively, the second end of the fifth resistor is grounded, the inverted input end of the comparator is electrically connected with the reference voltage generation circuit, and the output end of the comparator is electrically connected with the gate of the sixth PMOS tube and the NAND logic module through the first inverter.
7. The control device of claim 6, wherein The NAND logic module comprises a second inverter, a NAND gate and a third inverter; The first input end of the NAND gate is electrically connected with the comparison module through the second inverter, the second input end of the NAND gate is electrically connected with the initial state circuit, and the output end of the NAND gate is used for being electrically connected with the driving device through the third inverter.
8. The control device of claim 7, wherein The NAND logic module further comprises a first delay unit; The output end of the NAND gate is electrically connected with the third inverter through the first delay unit.
9. The control device of claim 8, wherein The first delay unit comprises a seventh PMOS tube, a third NMOS tube, a sixth resistor and a first capacitor; The gate of the seventh PMOS tube and the gate of the third NMOS tube are electrically connected with the output end of the NAND gate respectively, the source of the seventh PMOS tube is used for being electrically connected with the power supply, the drain of the seventh PMOS tube is electrically connected with the drain of the third NMOS tube, the input end of the third inverter and the first end of the first capacitor through the sixth resistor respectively, and the source of the third NMOS tube and the second end of the first capacitor are grounded respectively.
10. The control device of claim 1, wherein The initial state circuit comprises a reference voltage sampling module and a state control module; The reference voltage sampling module is electrically connected with the reference voltage generating circuit and the state control module, and is configured to sample the reference voltage and output a sampling voltage to the state control module. The state control module is also electrically connected with the voltage comparison circuit and configured to be electrically connected with the power supply, and is configured to output the first state control signal or the second state control signal to the voltage comparison circuit according to the power supply voltage and the sampling voltage.
11. The control device of claim 10, wherein The reference voltage sampling module comprises a seventh resistor and an eighth resistor. The first end of the seventh resistor is electrically connected with the reference voltage generating circuit, the second end of the seventh resistor is electrically connected with the first end of the eighth resistor and the state control module respectively, and the second end of the eighth resistor is configured to be grounded.
12. The control device of claim 11, wherein, The state control module comprises an eighth PMOS tube, a ninth PMOS tube, a ninth resistor, a fourth NMOS tube and a fourth inverter. The source of the eighth PMOS tube and the source of the ninth PMOS tube are configured to be electrically connected with the power supply respectively, the gate of the eighth PMOS tube is electrically connected with the gate of the ninth PMOS tube, the drain of the eighth PMOS tube and the first end of the ninth resistor respectively, the drain of the ninth PMOS tube is electrically connected with the input end of the fourth inverter and the drain of the fourth NMOS tube respectively, the second end of the ninth resistor and the source of the fourth NMOS tube are configured to be grounded respectively, and the output end of the fourth inverter is electrically connected with the voltage comparison circuit.
13. The control device of claim 12, wherein, The state control module further comprises a second delay unit. The drain of the ninth PMOS tube is electrically connected with the fourth inverter through the second delay unit.
14. The control device of claim 13, wherein The second delay unit comprises a tenth PMOS tube, a fifth NMOS tube, a tenth resistor and a second capacitor. The gate of the tenth PMOS tube and the gate of the fifth NMOS tube are electrically connected with the drain of the ninth PMOS tube respectively, the source of the tenth PMOS tube is configured to be electrically connected with the power supply, the drain of the tenth PMOS tube is electrically connected with the drain of the fifth NMOS tube, the input end of the fourth inverter and the first end of the second capacitor through the tenth resistor respectively, and the source of the fifth NMOS tube and the second end of the second capacitor are configured to be grounded respectively.
15. A drive system characterized by, The control device comprises a driving device and the control device according to any one of claims 1 to 14.
16. A vehicle characterized by comprising: The control device comprises the control device according to any one of claims 1 to 14, or the driving system according to claim 15.