Memory control method and storage device

Abstract

The invention provides a memory control method and a storage device. The method comprises the following steps: in a first data arrangement period, executing a first data arrangement operation and a first host write-in operation on a memory module; obtaining a first write-in data volume corresponding to the first host write-in operation; determining a speed critical value according to the first write-in data volume; in a second data arrangement period, performing a second data arrangement operation and a second host write operation on the memory module, the second data arrangement period occurring after the first data arrangement period; and in the second data arrangement period, based on the speed critical value, limiting the data writing speed corresponding to the second host writing operation. Therefore, the operation stability of the storage device can be improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory control method and storage device. Background Technology

[0002] In storage devices such as solid-state drives (SSDs), garbage collection (GC) is a critical background operation for maintaining storage availability. When the host continuously writes data to the storage device at high speed, conflicts may occur if garbage collection is also being performed internally within the storage device. For example, when the host's write rate is too high, the garbage collection process will be significantly delayed due to resource preemption, leading to the exhaustion of available free blocks, resulting in a precipitous drop in write performance or even write operation timeouts. Subsequently, when the storage device needs to perform large-scale garbage collection due to high load or severe fragmentation, foreground write requests may be blocked for a long time while waiting for garbage collection to release available space, severely impacting system stability and preventing data from being written for an extended period.

[0003] Therefore, resolving the resource competition between writing and garbage collection is an urgent problem that needs to be addressed. Summary of the Invention

[0004] The present invention provides a memory control method and a storage device, which can improve the above-mentioned problems and thereby improve the operational stability of the storage device.

[0005] Embodiments of the present invention provide a memory control method for a storage device, wherein the storage device includes a memory module, and the memory control method includes: in a first data defragmentation cycle, performing a first data defragmentation operation and a first host write operation on the memory module; obtaining a first write data amount corresponding to the first host write operation; determining a speed threshold based on the first write data amount; in a second data defragmentation cycle, performing a second data defragmentation operation and a second host write operation on the memory module, wherein the second data defragmentation cycle occurs after the first data defragmentation cycle; and in the second data defragmentation cycle, limiting the data write speed corresponding to the second host write operation based on the speed threshold.

[0006] An embodiment of the present invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: perform a first data defragmentation operation and a first host write operation on the memory module in a first data defragmentation cycle; obtain a first write data amount corresponding to the first host write operation; determine a speed threshold based on the first write data amount; perform a second data defragmentation operation and a second host write operation on the memory module in a second data defragmentation cycle, wherein the second data defragmentation cycle occurs after the first data defragmentation cycle; and limit the data write speed corresponding to the second host write operation based on the speed threshold in the second data defragmentation cycle.

[0007] Based on the above, in the first data preparation cycle, the first data preparation operation and the first host write operation can be executed synchronously on the memory module. After obtaining the first amount of data written corresponding to the first host write operation, the speed threshold can be dynamically determined based on the first amount of data written. Subsequently, in the second data preparation cycle, the second data preparation operation and the second host write operation can be executed on the memory module. In particular, in the second data preparation cycle, the data write speed corresponding to the second host write operation can be limited based on this speed threshold. Therefore, the technical problem of resource contention caused by host write and data preparation within the storage device, which cannot be solved by conventional methods, can be effectively improved, thereby enhancing the operational stability of the storage device. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of the first data processing cycle and the second data processing cycle according to an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram illustrating the addition of an idle time interval in the second data processing cycle according to an embodiment of the present invention;

[0013] Figure 6 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Detailed Implementation

[0014] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0015] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0016] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0017] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0018] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0019] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0020] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0022] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0023] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuitry), which is not limited by the present invention.

[0024] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0025] In one embodiment, an entity unit may include one or more entity erasure units. Furthermore, an entity unit may include multiple sub-entity units. For example, a sub-entity unit may include one or more entity programmable units. In one embodiment, an entity unit may include one or more virtual blocks. Each virtual block may include multiple entity erasure units.

[0026] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors contained in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be considered as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0028] In one embodiment, a physical erase unit may include multiple physical programmed units. The multiple physical programmed units in a physical erase unit can be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to the multiple physical programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these physical programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0029] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)~301(A) and 301(A+1)~301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)~301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0030] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0031] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0033] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0035] In one embodiment, the memory control circuit 23 can perform a host write operation on the memory module 122. This host write operation is used to write (i.e. store) data from the host system 11 (also referred to as host write data) into the memory module 122.

[0036] In one embodiment, the memory control circuit 23 may receive a write instruction from the host system. This write instruction instructs data (also referred to as first data) from the host system 11 to be written to a specific logical unit (also referred to as a first logical unit). Based on this write instruction, the memory control circuit 23 may perform a corresponding host write operation. For example, in this host write operation, the memory control circuit 23 may extract at least one physical unit (also referred to as a first physical unit) from the idle area 32 and map the first physical unit to the first logical unit. Simultaneously, the memory control circuit 23 may write the first data to the first physical unit in response to the aforementioned write instruction. This completes one host write operation. In one embodiment, the first physical unit is also referred to as an open unit.

[0037] In one embodiment, the memory control circuit 23 can initiate a data compaction procedure. After initiating the data compaction procedure, the memory control circuit 23 can perform a data compaction operation on the memory module 122. This data compaction operation is used to move (or copy) data (e.g., valid data) from one physical unit (also called a source unit) in the memory module 122 to another physical unit (also called a target unit) in the memory module 122. In one embodiment, this data compaction operation refers to a garbage collection (GC) operation.

[0038] In one embodiment, the purpose of initiating the data defragmentation procedure is to free up more idle physical units in the memory module 122, which is equivalent to increasing the total number of physical units (e.g., physical units 301(A+1) to 301(B)) in the idle area 32. For example, the memory control circuit 23 may initiate the data defragmentation procedure before the physical units in the idle area 32 are exhausted, in order to avoid the physical units in the idle area 32 being exhausted or insufficient due to continuous host write operations. Once the physical units in the idle area 32 are exhausted or insufficient, the memory control circuit 23 will be unable to continue performing host write operations.

[0039] In one embodiment, the memory control circuit 23 can obtain (e.g., monitor) the total number of physical units (i.e., idle physical units) in the idle area 32. The memory control circuit 23 can determine whether the total number of idle physical units is less than a threshold (also called a first trigger threshold). For example, this first trigger threshold can be 10 or other positive integers. If the total number of idle physical units is less than the first trigger threshold, the memory control circuit 23 can initiate a data defragmentation procedure. However, if the total number of idle physical units is not less than the first trigger threshold, the memory control circuit 23 may not initiate a data defragmentation procedure.

[0040] In one embodiment, during the data processing operation, the memory control circuit 23 may select at least one physical unit from the data area 31 as the source unit. For example, the memory control circuit 23 may select at least one physical unit from physical units 301(1) to 301(A) in the data area 31 as the source unit. Furthermore, during the data processing operation, the memory control circuit 23 may select at least one physical unit from the idle area 32 as the target unit. For example, the memory control circuit 23 may select at least one physical unit from physical units 301(A+1) to 301(B) in the idle area 32 as the source unit.

[0041] In one embodiment, after identifying the source cell, during the data processing operation, the memory control circuit 23 may instruct the memory module 122 to move (or copy) valid data from the source cell to the target cell. If the valid data in a certain entity cell that is the source cell has been completely moved or copied to the target cell, the memory control circuit 23 may associate this entity cell with the idle area 32 and may instruct the memory module 122 to erase this entity cell. This achieves the purpose of releasing new idle entity cells and increasing the total number of idle entity cells.

[0042] In one embodiment, the aforementioned data processing operation may also include loss balancing operation, bad block replacement operation, or hot and cold data classification operation, and the type of data processing operation is not limited to these.

[0043] Specifically, the loss balancing operation is used to simultaneously balance the losses of multiple entity units during the aforementioned data processing operation, for example, increasing the utilization rate of entity units with lower loss levels and / or decreasing the utilization rate of entity units with higher loss levels.

[0044] The bad block replacement operation is used to perform bad block replacement synchronously during the aforementioned data cleanup operation. This involves moving data from physical units (also known as bad blocks) with a damage level (or bit error rate) higher than the threshold to other physical units with a lower damage level for storage, and setting physical units with a damage level (or bit error rate) higher than the threshold (i.e., bad blocks) to no longer be used (e.g., no new data can be written to them).

[0045] In addition, the cold / hot data classification operation is used to simultaneously classify and store the data to be stored as cold / hot data during the aforementioned data processing operations. For example, cold data is stored in a dedicated physical unit for storing cold data, and hot data is stored in a dedicated physical unit for storing hot data. The cold / hot data can be defined according to practical needs.

[0046] In one embodiment, after initiating the data smoothing program, the memory control circuit 23 can perform one or more data smoothing operations within one operating cycle (also referred to as a data smoothing cycle). Furthermore, after initiating the data smoothing program, the memory control circuit 23 can detect whether a specific condition is met. If this specific condition is not met, the memory control circuit 23 can maintain the data smoothing program in the initiated state. However, if this specific condition has been met, the memory control circuit 23 can terminate the data smoothing program.

[0047] In one embodiment, in response to the termination of the data cleanup process, the memory control circuit 23 may cease performing any data cleanup operations until the data cleanup process is restarted.

[0048] In one embodiment, after the data defragmentation program is started, the memory control circuit 23 can continuously determine whether the total number of entity units (i.e., idle entity units) in the idle area 32 has reached a threshold (also called a second trigger threshold). This second trigger threshold can be greater than or equal to the first trigger threshold. For example, this second trigger threshold can be 10 or other positive integers. If the total number of idle entity units reaches the second trigger threshold, the memory control circuit 23 can terminate the current data defragmentation program. However, if the total number of idle entity units does not reach the second trigger threshold, the memory control circuit 23 can maintain the current data defragmentation program in the started state.

[0049] In one embodiment, after the data defragmentation program is initiated, the memory control circuit 23 can alternately execute the aforementioned host write operation and the aforementioned data defragmentation operation within a data defragmentation cycle. In one embodiment, alternating the execution of the host write operation and the data defragmentation operation within a data defragmentation cycle can also be considered as simultaneously executing the host write operation and the data defragmentation operation within the same data defragmentation cycle (i.e., not just executing one of the host write operation and the data defragmentation operation). This avoids significant delays in host writes caused by prolonged execution of the data defragmentation operation, thereby reducing the user experience.

[0050] Traditionally, after the data processing program is started, the memory control circuit 23 can formulate data writing rules to determine how to synchronously or alternately execute host write operations and data processing operations within a data processing cycle. For example, whenever a predetermined amount of host write data (i.e., data from the host system 11) is written to the memory module 122, a predetermined amount of data processing data (i.e., data collected through the aforementioned data processing operation) is written to the memory module 122. This ensures that host write operations and data processing operations within the storage device 12 are executed alternately or synchronously after the data processing program is started.

[0051] However, the problem encountered in practice is that in some cases (such as when the host system 11 writes a large amount of data in a short period of time and / or when the idle physical units in the memory module 122 are about to be exhausted and cannot be replenished to a sufficient number), even if the host write operation and data defragmentation operation are alternately executed with the predetermined amount of data written as the switching benchmark, after the data defragmentation program has been started for a period of time, not only will the main purpose of accelerating the release of idle physical units not be achieved, but it may even cause the host write speed to lose stability (for example, it is still writing at full speed one second, and suddenly stops writing the next second because the idle physical units are exhausted).

[0052] In one embodiment, the memory control circuit 23 can dynamically adjust the data write speed corresponding to the host write operation in the next data compaction cycle based on the amount of host write data in one or more previous data compaction cycles. This improves the aforementioned problems and enhances the operational stability of the storage device 12.

[0053] In one embodiment, the memory control circuit 23 may perform a data processing operation (also referred to as the first data processing operation) and a host write operation (also referred to as the first host write operation) on the memory module 122 within a data processing cycle (also referred to as the first data processing cycle). The first data processing operation is used to perform the transfer of valid data within the memory module 122 (e.g., transferring valid data from a source cell in the memory module 122 to a target cell in the memory module 122) during the first data processing cycle. Furthermore, the first host write operation is used to write data from the host system 11 (i.e., host write data) into the memory module 122 during the first data processing cycle.

[0054] In one embodiment, the memory control circuit 23 can obtain the amount of data written corresponding to the first host write operation (also referred to as the first write data amount). The first write data amount reflects the total amount of host write data written to the memory module 122 through the first host write operation during the first data processing cycle.

[0055] In one embodiment, the memory control circuit 23 can monitor the usage of the instruction cache (or instruction queue) used to cache write instructions from the host system 11 during the first data defragmentation cycle. The memory control circuit 23 can then determine a first write data amount based on this usage. For example, the first write data amount can be directly correlated with the total number of write instructions from the host system 11 cached in the instruction cache (or instruction queue) during the first data defragmentation cycle. In one embodiment, the memory control circuit 23 can convert this total number into the first write data amount.

[0056] In one embodiment, after acquiring the first amount of data to be written, the memory control circuit 23 can determine a speed threshold based on the first amount of data to be written. For example, the memory control circuit 23 can determine this speed threshold based on the first amount of data to be written and the duration of the first data processing cycle.

[0057] In one embodiment, the memory control circuit 23 can obtain the aforementioned speed threshold according to the following formula (1).

[0058] Vs=Wd / Tc (1)

[0059] In formula (1), Vs represents the aforementioned speed threshold, Wd represents the first amount of data written, and Tc represents the duration of the first data processing cycle. It should be noted that formula (1) can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0060] In one embodiment, it is assumed that after leaving the first data processing cycle, the memory control circuit 23 enters another data processing cycle (also referred to as the second data processing cycle). In the second data processing cycle, the memory control circuit 23 may perform a data processing operation (also referred to as the second data processing operation) and a host write operation (also referred to as the second host write operation) on the memory module 122. Specifically, the second data processing operation is used to perform the transfer of valid data within the memory module 122 (e.g., transferring valid data from a source cell in the memory module 122 to a target cell in the memory module 122) during the second data processing cycle. Furthermore, the second host write operation is used to write data from the host system 11 (i.e., host write data) into the memory module 122 during the second data processing cycle.

[0061] In one embodiment, after obtaining the aforementioned speed threshold, during the second data processing cycle, the memory control circuit 23 can limit the data write speed corresponding to the second host write operation based on this speed threshold. For example, during the second data processing cycle, the memory control circuit 23 can use this speed threshold as a speed limiting target to control the data write speed corresponding to the second host write operation, that is, to limit the data write speed corresponding to the second host write operation to no higher than (e.g., less than or equal to) this speed threshold. In other words, the memory control circuit 23 can only regulate the data write speed of the second host write operation according to the speed threshold, but due to the inherent settings of the memory, the actual data write speed may still exceed the speed threshold when the host write volume is large. In addition, it should be noted that this speed threshold is not used to limit the data write speed corresponding to the second data processing operation.

[0062] Figure 4 This is a schematic diagram illustrating the first data processing cycle and the second data processing cycle according to an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, it is assumed that at time point T(1), the memory control circuit 23 initiates a data smoothing procedure (also referred to as the first data smoothing procedure). After initiating the first data smoothing procedure, during the operation cycle P(1) (i.e., the first data smoothing cycle), the memory control circuit 23 may interleave data smoothing operations and host write operations. Then, at time point T(2), the memory control circuit 23 terminates the first data smoothing procedure. Therefore, the duration of the first data smoothing procedure is ΔT(1).

[0063] In one embodiment, the memory control circuit 23 can obtain the duration length ΔT(1) of the operation cycle P(1) based on time points T(1) and T(2). For example, the memory control circuit 23 can obtain the duration length ΔT(1) of the operation cycle P(1) based on the difference between time points T(1) and T(2) (i.e., ΔT(1) = T(2) - T(1)).

[0064] In one embodiment, after the first data defragmentation procedure ends, it is assumed that at time point T(3), the memory control circuit 23 restarts the data defragmentation procedure (also referred to as the second data defragmentation procedure). After starting the second data defragmentation procedure, during the operation cycle P(2) (i.e., the second data defragmentation cycle), the memory control circuit 23 can interleave data defragmentation operations and host write operations. In terms of time, the operation cycle P(2) occurs after the operation cycle P(1). Then, at time point T(4), the memory control circuit 23 ends the second data defragmentation procedure. Therefore, the duration of the second data defragmentation procedure is ΔT(2).

[0065] In one embodiment, the memory control circuit 23 can determine a speed threshold based on the amount of data written (i.e., the first amount of data written) corresponding to at least one host write operation performed in the operation cycle P(1) and the duration ΔT(1) of the operation cycle P(1). For example, the memory control circuit 23 can substitute the first amount of data written and ΔT(1) into formula (1) to obtain the speed threshold Vs.

[0066] In one embodiment, after obtaining the speed threshold Vs, the memory control circuit 23 can limit the data write speed corresponding to the host write operation (i.e., the second host write operation) performed in the operation cycle P(2) based on the speed threshold Vs. For example, after obtaining the speed threshold Vs, the memory control circuit 23 can limit the data write speed corresponding to the host write operation performed in the operation cycle P(2) to no higher than this speed threshold.

[0067] by Figure 4 For example, traditionally, if the data write speed corresponding to the host write operation in operation cycle P(2) is not limited, in some cases, such as when the host system 11 stores a large amount of data in a short period of time, even if the data compaction operation is performed synchronously (actually interleaved) in operation cycle P(2), the replenishment speed of the idle entity unit still cannot keep up with the consumption speed of the idle entity unit. Even if a static control mechanism is adopted (for example, after writing a predetermined amount of host write data, a predetermined amount of valid data is moved through the data compaction operation to release the idle entity unit), there is still a high probability that this problem cannot be improved.

[0068] However, in Figure 4 In the embodiment, after dynamically obtaining the speed threshold value (e.g., speed threshold value Vs) corresponding to the operation cycle P(1), the data write speed corresponding to the host write operation in the operation cycle P(2) is dynamically controlled based on this speed threshold value, which can effectively improve the above-mentioned problems. For example, by controlling the data write speed corresponding to the host write operation in the operation cycle P(2) to be no higher than this speed threshold value as much as possible, the total amount of host write data stored in the operation cycle P(2) can be dynamically suppressed while ensuring that the data write speed of the host write operation remains stable and slightly declines. On the other hand, the extra write bandwidth in the operation cycle P(2) can be allocated to the data processing operation (the write bandwidth here can also refer to the processing time in the operation cycle P(2), that is, the time ratio of the host write operation and the data processing operation in the operation cycle P(2), so as to improve the execution efficiency of the data processing operation (e.g., ensuring that the release rate of the idle unit is higher than the consumption rate of the idle unit). Thus, the operational stability of the storage device 12 is further improved.

[0069] In one embodiment, during the second data defragmentation cycle, the memory control circuit 23 may establish an idle time interval after completing a data write operation (also referred to as the first sub-write operation) in the second host write operation. Specifically, during this idle time interval, the memory control circuit 23 may prohibit any host write operations. However, during this idle time interval, the data defragmentation operation can be performed normally without being affected.

[0070] In one embodiment, after the aforementioned idle time interval, the memory control circuit 23 may begin executing the next data write operation (also referred to as the second sub-write operation) in the second host write operation. Thus, by dynamically setting an additional idle time interval to suppress the total amount of host write data stored in the second data preparation cycle, the technical effect of dynamically controlling the data write speed corresponding to the host write operation in the second data preparation cycle based on a speed threshold can be achieved.

[0071] Figure 5 This is a schematic diagram illustrating the addition of an idle time interval in the second data processing cycle, as shown in an embodiment of the present invention. Please refer to... Figure 5 , continuing Figure 4 In the embodiment, it is assumed that the operation period P(2) (i.e. the second data processing period) includes the time range between time point T(3) and T(4).

[0072] In one embodiment, between time points T(5) and T(6), the memory control circuit 23 performs a host write operation HW(1) (i.e., the first sub-write operation) on the memory module 122. For example, the duration of the host write operation HW(1) is ΔT(3).

[0073] In one embodiment, after completing the host write operation HW(1), the memory control circuit 23 may establish an idle time interval between time points T(6) and T(7). For example, the duration of this idle time interval is ΔT(4). In particular, during this idle time interval, the memory control circuit 23 may prohibit any host write operation, but data processing operations or other non-host write operations may be performed normally without being affected.

[0074] In other words, between time points T(6) and T(7), the memory control circuit 23 can perform a data sorting operation DM(1) on the memory module 122 to accelerate the release of idle memory units.

[0075] In one embodiment, the memory control circuit 23 can determine the duration of the idle time interval based on the amount of data written (also known as the second amount of data written) corresponding to the first sub-write operation and the aforementioned speed threshold.

[0076] by Figure 5 For example, the memory control circuit 23 can determine the duration length ΔT(4) based on the amount of data written (i.e., the second amount of data written) corresponding to the host write operation HW(1) and the previously determined speed threshold. For example, the amount of data written corresponding to the host write operation HW(1) can be positively correlated with the duration length ΔT(4). That is, if the amount of data written corresponding to the host write operation HW(1) is larger, it means that the amount of host write data stored in the memory module 122 between time points T(5) and T(6) is larger, and the duration length ΔT(4) is also longer.

[0077] In one embodiment, the memory control circuit 23 may determine the duration of the dynamically set idle time interval according to the following formula (2).

[0078] Ts=Ws / Vs (2)

[0079] In formula (2), Ts represents the duration of the dynamically set idle time interval, and Ws represents the amount of data written in the second phase. Figure 5Taking the idle time interval between time points T(6) and T(7) as an example, the memory control circuit 23 can substitute the amount of data written (i.e., the second amount of data written) corresponding to the host write operation HW(1) and the previously determined speed threshold Vs into formula (2) to obtain the duration length ΔT(4). It should be noted that formula (2) can also be adjusted according to practical needs, and the present invention does not limit it.

[0080] In one embodiment, after time point T(7) and between time points T(7) and T(8), the memory control circuit 23 may perform a host write operation HW(2) (i.e., a second sub-write operation) on the memory module 122. For example, the duration of the host write operation HW(2) is ΔT(5).

[0081] In one embodiment, after completing the host write operation HW(2), the memory control circuit 23 may establish another idle time interval between time points T(8) and T(9). For example, the duration of this idle time interval is ΔT(6). In particular, during this idle time interval, the memory control circuit 23 may prohibit any host write operation, but the data defragmentation operation can be performed normally without being affected.

[0082] In other words, between time points T(8) and T(9), the memory control circuit 23 can perform a data sorting operation DM(2) on the memory module 122 to accelerate the release of idle memory units.

[0083] In one embodiment, the memory control circuit 23 can substitute the amount of data written (i.e., the second amount of data written) corresponding to the host write operation HW(2) and the previously determined speed threshold Vs into formula (2) to obtain the duration length ΔT(6). It should be noted that if the amount of data written corresponding to the host write operation HW(2) is different from the amount of data written corresponding to the host write operation HW(1), then the duration length ΔT(6) may be different from the duration length ΔT(4).

[0084] And so on, in Figure 5 In this embodiment, the memory control circuit 23 can dynamically set one or more additional idle time intervals during the operation cycle P(2). This achieves the technical effect of dynamically controlling (e.g., reducing) the data write speed corresponding to the host write operation during the operation cycle P(2).

[0085] In one embodiment, the duration of a set idle time interval is positively correlated with the decrease in data write speed corresponding to the second host write operation and / or the increase in performance of the second data defragmentation operation. That is, the longer the duration of a set idle time interval, the greater the decrease in data write speed corresponding to the second host write operation, and the better the performance of the second data defragmentation operation. In other words, when the memory cannot limit the actual write speed of host write operations performed in T(5) to T(6) and T(7) to T(8), the host write speed of the entire data defragmentation cycle can be controlled by designing the idle time interval.

[0086] by Figure 5 For example, the duration lengths ΔT(4) and / or ΔT(6) are positively correlated with the decrease in the overall data write speed corresponding to the host write operation performed in operation cycle P(2) and the overall performance of the data processing operation performed in operation cycle P(2). That is, if the duration lengths ΔT(4) and / or ΔT(6) increase, the decrease in the overall data write speed corresponding to the host write operation performed in operation cycle P(2) will also increase accordingly, and the overall performance of the data processing operation performed in operation cycle P(2) will also increase accordingly (due to the extended execution time of the data processing operations DM(1) and / or DM(2)).

[0087] In one embodiment, by dynamically adjusting the duration of at least one idle time interval, the memory control circuit 23 can achieve an optimal balance between maintaining the performance of host write operations and the performance of data processing operations during the second data processing cycle, thereby increasing the operational stability of the storage device 12.

[0088] It should be noted that, since the time ΔT(3) and ΔT(5) for each host write operation during the data preparation cycle are extremely short and almost identical, and are the data instructions retrieved in one write operation (such as retrieving up to 48 4K data at a time), they can be excluded from the calculation in order to reduce the occupation of computing resources.

[0089] In one embodiment, the memory control circuit 23 may update an evaluation value (also known as a time consumption evaluation value) based on the duration of the first data processing cycle. For example, the updated time consumption evaluation value may reflect the average duration of at least one past data processing cycle. Then, the memory control circuit 23 may determine whether to limit the data write speed corresponding to the second host write operation in the second data processing cycle based on whether this time consumption evaluation value is greater than a threshold value (also known as a time consumption threshold).

[0090] In one embodiment, the memory control circuit 23 can compare the updated time-consuming assessment value with a time-consuming threshold. If the updated time-consuming assessment value is greater than the time-consuming threshold, it indicates that the average duration of at least one past data processing cycle is relatively long (i.e., the total number of idle physical units in the memory module 122 may be insufficient for a long period). In this case, in response to the updated time-consuming assessment value being greater than the time-consuming threshold, the memory control circuit 23 can allow, in the second data processing cycle, to limit the data write speed corresponding to the second host write operation based on the aforementioned speed threshold. Thus, when there is a real need to improve the performance of the data processing operation, the host write operation executed synchronously within the data processing cycle can be precisely slowed down.

[0091] On the other hand, if the updated time-consuming assessment value is not greater than the time-consuming threshold, it indicates that the average duration of at least one past data processing cycle is relatively short (i.e., the total number of idle physical units in memory module 122 may still be sufficient). In this case, in response to the updated time-consuming assessment value not being greater than the time-consuming threshold, memory control circuit 23 may not limit the data write speed corresponding to the second host write operation based on the aforementioned speed threshold during the second data processing cycle (equivalent to maintaining the normal data write speed corresponding to the second host write operation). Thus, unnecessary restrictions (e.g., speed reduction) on the host write speed can be avoided when the total number of idle physical units in memory module 122 is still sufficient.

[0092] In one embodiment, the memory control circuit 23 may determine whether to limit the data write speed corresponding to the second host write operation in the second data processing cycle based on the speed threshold, depending on whether the total number of idle physical blocks in the memory module 122 is less than a trigger threshold (also known as a third trigger threshold).

[0093] In one embodiment, if the total number of idle physical blocks in memory module 122 is less than a third trigger threshold, it indicates that the total number of idle physical units in memory module 122 is about to be exhausted or has reached a warning threshold. In this case, in response to the total number of idle physical blocks in memory module 122 being less than the third trigger threshold, memory control circuit 23 may allow, during the second data preparation cycle, to limit the data write speed corresponding to the second host write operation based on the aforementioned speed threshold. Thus, it is also possible to precisely reduce the host write speed operation executed synchronously during the data preparation cycle when there is a genuine need to improve the execution efficiency of the data preparation operation.

[0094] On the other hand, if the total number of idle physical blocks in memory module 122 is not less than the third trigger threshold, it indicates that the total number of idle physical units in memory module 122 may still be sufficient. In this case, in response to the total number of idle physical blocks in memory module 122 being not less than the third trigger threshold, memory control circuit 23 may not limit the data write speed corresponding to the second host write operation during the second data processing cycle based on the aforementioned speed threshold (equivalent to maintaining the normal data write speed corresponding to the second host write operation). Thus, unnecessary restrictions (e.g., speed reduction) on the host write speed can also be avoided when the total number of idle physical units in memory module 122 is still sufficient.

[0095] In one embodiment, if the interval between the first data processing cycle and the second data processing cycle is close, that is, the interval between T(2) and T(3) is close, in order to avoid frequent changes in the host write speed, this segment can still maintain the initial speed threshold of the first data processing cycle. Specifically, it can be referred to whether the idle entity unit of the memory module is at the fourth trigger threshold. If it is below the fourth trigger threshold, the speed threshold of the previous data processing cycle can be maintained between T(2) and T(3). If not, the normal host write speed is maintained.

[0096] In one embodiment, after the second data processing cycle, the memory control circuit 23 can also obtain the amount of data written corresponding to the second host write operation (also referred to as the third amount of data written). The third amount of data written reflects the total amount of host write data written to the memory module 122 during the second data processing cycle through the second host write operation. Then, the memory control circuit 23 can update the aforementioned speed threshold based on the third amount of data written and the duration of the second data processing cycle.

[0097] Because the host write speed for the entire data consolidation cycle is adjusted by regulating the idle time interval during the second data consolidation cycle, when the amount of host write data is large and the data consolidation demand is low, the host write operations in the second data consolidation cycle will seamlessly continue after the idle time interval and end with a single sub-write operation. Therefore, the new speed threshold calculated for the entire second data consolidation cycle will be higher than the speed threshold calculated for the first data consolidation cycle. Conversely, if the amount of host write data is small and the data consolidation demand is high, the data consolidation operation will occupy most of the time in the second data consolidation cycle, resulting in a smaller new speed threshold calculated for the first data consolidation cycle. Therefore, the speed threshold for the second data consolidation cycle will dynamically change according to the actual situation to further adjust the next data consolidation cycle.

[0098] In one embodiment, the memory control circuit 23 can set a previously obtained speed threshold as a first speed threshold. The memory control circuit 23 can also set a speed threshold obtained based on the third amount of data written and the duration of the second data compaction cycle as a second speed threshold. For example, the second speed threshold can also be obtained according to the above formula (1). Then, the memory control circuit 23 can take the average (or weighted average) of the first and second speed thresholds as the updated speed threshold. This updated speed threshold can then be used to control the data write speed corresponding to the host write operation in the next data compaction cycle. Thus, over time, the speed threshold can be stably adjusted according to the current operating environment of the storage device 12, thereby also contributing to improving the operational stability of the storage device 12.

[0099] Figure 6 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Please refer to... Figure 6 In step S601, during the first data preparation cycle, a first data preparation operation and a first host write operation are performed on the memory module. In step S602, the first write data amount corresponding to the first host write operation is obtained. In step S603, a speed threshold is determined based on the first write data amount. In step S604, during the second data preparation cycle, a second data preparation operation and a second host write operation are performed on the memory module, wherein the second data preparation cycle occurs after the first data preparation cycle. In step S605, during the second data preparation cycle, the data write speed corresponding to the second host write operation is limited based on the speed threshold.

[0100] However, Figure 6 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 6 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 6 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0101] In summary, the memory control method and storage device proposed in this invention can use parameters (or parameter changes) monitored during past data compaction cycles to control the data write speed corresponding to host write operations in the next data compaction cycle. Therefore, an optimal balance can be achieved between the performance of host write operations and the performance of data compaction operations in subsequent data compaction cycles, thereby improving the operational stability of the storage device.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that, For a storage device, wherein the storage device includes a memory module, and the memory control method includes: During the first data processing cycle, a first data processing operation and a first host write operation are performed on the memory module; Obtain the first write data volume corresponding to the first host write operation; Determine the speed threshold based on the first amount of data written; In the second data defragmentation cycle, a second data defragmentation operation and a second host write operation are performed on the memory module, wherein the second data defragmentation cycle occurs after the first data defragmentation cycle; and During the second data processing cycle, the data writing speed corresponding to the second host write operation is limited based on the speed threshold.

2. The memory control method according to claim 1, wherein the step of determining the speed threshold based on the first amount of data written includes: The speed threshold is determined based on the first amount of data written and the duration of the first data processing cycle.

3. The memory control method according to claim 1, wherein in the second data processing cycle, the step of limiting the data write speed corresponding to the second host write operation based on the speed threshold includes: During the second data processing cycle, the speed threshold is used as the speed limit target to control the data writing speed corresponding to the second host write operation.

4. The memory control method according to claim 1, wherein in the second data processing cycle, the step of limiting the data write speed corresponding to the second host write operation based on the speed threshold includes: During the second data processing cycle, after completing the first sub-write operation in the second host write operation, an idle time interval is established. as well as After the idle time interval has elapsed, the second sub-write operation in the second host write operation is executed.

5. The memory control method according to claim 4, wherein during the idle time interval, any host write operation is prohibited.

6. The memory control method according to claim 4, further comprising: The duration of the idle time interval is determined based on the amount of second written data corresponding to the first sub-write operation and the speed threshold.

7. The memory control method according to claim 1, wherein the speed threshold is not used to limit the data write speed corresponding to the second data defragmentation operation.

8. The memory control method according to claim 1, further comprising: Update the time consumption assessment value based on the duration of the first data processing cycle; as well as Based on whether the time consumption assessment value is greater than the time consumption threshold, it is determined whether, during the second data processing cycle, the data writing speed corresponding to the second host write operation is limited based on the speed threshold.

9. The memory control method according to claim 1, further comprising: Based on whether the total number of idle physical blocks in the memory module is less than the trigger threshold, it is determined whether, during the second data consolidation cycle, the data write speed corresponding to the second host write operation is limited based on the speed threshold.

10. The memory control method according to claim 1, further comprising: Obtain the third write data volume corresponding to the second host write operation; as well as The speed threshold is updated based on the third amount of data written and the duration of the second data processing cycle.

11. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to: During the first data processing cycle, a first data processing operation and a first host write operation are performed on the memory module; Obtain the first write data volume corresponding to the first host write operation; Determine the speed threshold based on the first amount of data written; In the second data defragmentation cycle, a second data defragmentation operation and a second host write operation are performed on the memory module, wherein the second data defragmentation cycle occurs after the first data defragmentation cycle; as well as During the second data processing cycle, the data writing speed corresponding to the second host write operation is limited based on the speed threshold.

12. The storage device of claim 11, wherein the operation of the memory controller determining the speed threshold based on the first amount of written data includes: The speed threshold is determined based on the first amount of data written and the duration of the first data processing cycle.

13. The storage device of claim 11, wherein the operation of the memory controller, during the second data compaction cycle, limiting the data write speed corresponding to the second host write operation based on the speed threshold includes: During the second data processing cycle, the speed threshold is used as the speed limit target to control the data writing speed corresponding to the second host write operation.

14. The storage device of claim 11, wherein the operation of the memory controller, during the second data compaction cycle, limiting the data write speed corresponding to the second host write operation based on the speed threshold includes: During the second data processing cycle, after the first sub-write operation in the second host write operation is completed, an idle time interval is established. as well as After the idle time interval has elapsed, the second sub-write operation in the second host write operation is executed.

15. The storage device of claim 14, wherein the memory controller prohibits any host write operations during the idle time interval.

16. The storage device of claim 14, wherein the memory controller is further configured to: The duration of the idle time interval is determined based on the amount of second written data corresponding to the first sub-write operation and the speed threshold.

17. The storage device of claim 11, wherein the speed threshold is not used to limit the data write speed corresponding to the second data defragmentation operation.

18. The storage device of claim 11, wherein the memory controller is further configured to: Update the time consumption assessment value based on the duration of the first data processing cycle; and Based on whether the time consumption assessment value is greater than the time consumption threshold, it is determined whether, during the second data processing cycle, the data writing speed corresponding to the second host write operation is limited based on the speed threshold.

19. The storage device of claim 11, wherein the memory controller is further configured to: Based on whether the total number of idle physical blocks in the memory module is greater than the block threshold, it is determined whether, during the second data processing cycle, the data write speed corresponding to the second host write operation is limited based on the speed threshold.

20. The storage device of claim 11, wherein the memory controller is further configured to: Obtain the third write data volume corresponding to the second host write operation; and The speed threshold is updated based on the third amount of data written and the duration of the second data processing cycle.

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