Electronic device, data transmission system and data transmission method

Abstract

The application provides an electronic device, a data transmission system and a data transmission method, which can be applied to the technical field of computers. The electronic device comprises a firmware storage circuit; a management controller comprises a first processor core, a second processor core, a first peripheral circuit and a second peripheral circuit, the first processor core is connected with the firmware storage circuit and the first peripheral circuit, the second processor core is connected with the first peripheral circuit and the second peripheral circuit; a general data interface is connected with the second peripheral circuit; the first processor core receives first serial port data from the firmware storage circuit, and provides the first serial port data and second serial port data generated by the first processor core itself to the first peripheral circuit; the first peripheral circuit independently receives and stores the first serial port data and the second serial port data; the second processor core reads the first serial port data and the second serial port data from the first peripheral circuit; and the second peripheral circuit converts and outputs the first serial port data and the second serial port data.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically to an electronic device, a data transmission system, and a data transmission method. Background Technology

[0002] In the operation of modern enterprises and data centers, servers, as core computing resources, undertake multiple tasks such as data processing, storage, and network services. Throughout the development of server technology, serial port data from different firmware versions has always been the core basis for technicians to obtain hardware status and locate faults.

[0003] However, currently, when acquiring serial port data from different firmware, an additional serial port converter is usually used to receive different serial port data. When receiving data, only one physical serial port is usually kept open to output data, which makes it impossible to acquire different serial port data at the same time, resulting in low data acquisition efficiency. Summary of the Invention

[0004] In view of the above problems, this application provides an electronic device, a data transmission system, and a data transmission method.

[0005] According to a first aspect of this application, an electronic device is provided, comprising: a firmware storage circuit; a management controller including a first processor core, a second processor core, a first peripheral circuit, and a second peripheral circuit, wherein the first processor core is connected to the firmware storage circuit and the first peripheral circuit, and the second processor core is connected to the first peripheral circuit and the second peripheral circuit; and a general-purpose data interface connected to the second peripheral circuit; wherein the first processor core is configured to receive first serial port data from the firmware storage circuit and provide the first serial port data and second serial port data generated by the first processor core itself to the first peripheral circuit; the first peripheral circuit is configured to independently receive and store the first serial port data and the second serial port data; the second processor core is configured to read the first serial port data and the second serial port data from the first peripheral circuit and provide them to the second peripheral circuit; and the second peripheral circuit is configured to convert the first serial port data and the second serial port data into a predetermined protocol format and output them through the general-purpose data interface.

[0006] A second aspect of this application provides a data transmission system, comprising: an electronic device; a debugging device, the debugging device including a universal data interface matching the universal data interface of the electronic device, the universal data interface of the debugging device being connected to the universal data interface of the electronic device; and a universal data transmission line, the universal data interface of the debugging device being connected to the universal data interface of the electronic device via the universal data transmission line.

[0007] A third aspect of this application provides a data transmission method executed by an electronic device. The data transmission method includes: a first processor core in a management controller receiving first serial port data from a firmware storage circuit, generating second serial port data, and providing the first and second serial port data to a first peripheral circuit; the first peripheral circuit independently receiving and storing the first and second serial port data; a second processor core reading the first and second serial port data from the first peripheral circuit and providing them to the second peripheral circuit; and the second peripheral circuit converting the first and second serial port data into a predetermined protocol format and outputting it through a general data interface.

[0008] According to embodiments of this application, by configuring a second processor core, a first peripheral circuit, and a second peripheral circuit in the management controller, and connecting them with a universal data interface, the electronic device can transmit first serial port data and second serial port data in parallel to external devices through the universal data interface. Compared to using a serial-to-serial cable for time-sharing transmission, the electronic device supports universal data interface connections, eliminating the need for a dedicated data converter and improving ease of use; furthermore, it achieves parallel output from both serial ports, improving debugging and maintenance efficiency. Attached Figure Description

[0009] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A structural block diagram of an electronic device according to an embodiment of this application is shown;

[0011] Figure 2 A structural block diagram of an electronic device according to another embodiment of this application is shown;

[0012] Figure 3 A structural block diagram of an electronic device according to yet another embodiment of this application is shown;

[0013] Figure 4 A structural block diagram of an electronic device according to another embodiment of this application is shown;

[0014] Figure 5 A structural block diagram of a data transmission system according to an embodiment of this application is shown;

[0015] Figure 6 A flowchart of a data transmission method according to an embodiment of this application is shown;

[0016] Figure 7 A flowchart of a data transmission method according to an embodiment of this application is shown;

[0017] Figure 8 A flowchart of a data transmission method according to an embodiment of another application is shown. Detailed Implementation

[0018] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0020] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0021] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0022] In server hardware architecture, the Baseboard Management Controller (BMC) and the Basic Input / Output System (BIOS) are the core management and control units. The BMC is responsible for server hardware monitoring, remote management, and fault alarm functions, and its serial port output includes key data such as system operation logs, hardware status information, and remote control command feedback. The BIOS is responsible for hardware initialization and operating system booting processes after the server powers on, and its serial port output includes debugging data such as hardware initialization logs, startup fault reports, and configuration parameter information. In scenarios such as server production debugging, factory testing, and maintenance troubleshooting, technicians need to obtain serial port data from the BMC and BIOS to analyze hardware status and locate fault causes. Therefore, the output method of serial port data directly affects the efficiency of server debugging and maintenance.

[0023] In related technologies, the serial port data output schemes of server BMC and BIOS rely on external hardware switching and dedicated cables, which have the following drawbacks:

[0024] (1) Reliance on external serial port cable: The relevant technology requires the use of external serial port conversion device to realize the conversion between physical serial port and debugging host interface, which has problems such as poor compatibility, inconvenience of carrying, high cost and easy damage.

[0025] (2) Efficiency problem of single serial port time-sharing output: Related technologies realize the time-sharing output of BMC and BIOS serial ports through serial port switching, which cannot acquire data from both at the same time, resulting in cumbersome debugging process, high risk of data loss, and delayed operation and maintenance response.

[0026] (3) Additional hardware costs and integration issues: Using a separate serial port converter to achieve dual serial port output requires additional hardware modules, which increases the space occupied on the circuit board and the hardware cost, and does not meet the requirements of high integration and low cost of the server.

[0027] (4) Traditional serial port switching schemes cannot guarantee that the serial port is always outputting BMC or BIOS serial port data. During stress testing, the serial port data becomes messy and unusable.

[0028] In view of this, embodiments of this application provide an electronic device, a data transmission system, and a data transmission method. The electronic device includes a firmware storage circuit; a management controller, including a first processor core, a second processor core, a first peripheral circuit, and a second peripheral circuit, wherein the first processor core is connected to the firmware storage circuit and the first peripheral circuit, and the second processor core is connected to the first peripheral circuit and the second peripheral circuit; and a general-purpose data interface connected to the second peripheral circuit. The first processor core is used to receive first serial port data from the firmware storage circuit and provide the first serial port data and second serial port data generated by the first processor core itself to the first peripheral circuit. The first peripheral circuit is used to independently receive and store the first and second serial port data. The second processor core is used to read the first and second serial port data from the first peripheral circuit and provide them to the second peripheral circuit. The second peripheral circuit is used to convert the first and second serial port data into a predetermined protocol format and output it through the general-purpose data interface. This electronic device can be applied to various types of servers such as rack servers, blade servers, and high-density servers.

[0029] Figure 1 A structural block diagram of an electronic device 1000 according to an embodiment of this application is shown.

[0030] like Figure 1As shown, the electronic device 1000 of this embodiment includes: a firmware storage circuit 100; a management controller 200, including a first processor core 210, a second processor core 220, a first peripheral circuit 230, and a second peripheral circuit 240, wherein the first processor core 210 is connected to the firmware storage circuit 100 and the first peripheral circuit 230, and the second processor core 220 is connected to the first peripheral circuit 230 and the second peripheral circuit 240; a general data interface 300, connected to the second peripheral circuit 240; wherein the first processor core 210 is used to read firmware data from the storage circuit. Circuit 100 receives first serial port data and provides the first serial port data and the second serial port data generated by the first processor core 210 itself to the first peripheral circuit 230; the first peripheral circuit 230 is used to independently receive and store the first serial port data and the second serial port data; the second processor core 220 is used to read the first serial port data and the second serial port data from the first peripheral circuit 230 and provide them to the second peripheral circuit 240; the second peripheral circuit 240 is used to convert the first serial port data and the second serial port data into a predetermined protocol format and output them through the general data interface 300.

[0031] Firmware storage circuit 100 is a hardware circuit used to store firmware. Its core function is to persistently store the firmware program code in non-volatile memory, ensuring that the device retains critical data even after power loss. Firmware may include the Basic Input / Output System (BIOS), bootloader, embedded system firmware, storage device firmware, etc. The bootloader is responsible for starting the system and loading the operating system. Embedded system firmware includes, for example, microcontroller firmware, which runs on the microcontroller and controls and manages the functions of the embedded device. Storage device firmware includes, for example, hard disk firmware, used to manage and control the operation of the hard disk drive.

[0032] In some embodiments, the firmware storage circuit 100 may also be a network card or a graphics card, etc., which stores their own firmware. Therefore, the firmware storage circuit 100 in this embodiment includes, but is not limited to, at least one of BIOS, network card, and graphics card. Different types of firmware storage circuits 100 may be connected to the management controller 200 of this application at the same time to send serial port data.

[0033] As an example, the management controller 200 may be a baseboard management controller (BMC), for example, it may be implemented as a heterogeneous BMC chip. The management controller 200 includes at least two processor cores, for example, such as... Figure 1As shown, the management controller 200 may include a first processor core 210 and a second processor core 220. The first processor core 210 can act as the main processor core, hereinafter also referred to as the BMC processor core. The second processor core can act as a coprocessor core, for example, it can be implemented as a microprocessor (Microcontroller Unit, MCU) core. The firmware of the microprocessor can be developed based on the Cortex Microcontroller Software Interface Standard (CMSIS) standard library, which has high portability and facilitates subsequent upgrades and maintenance.

[0034] The general data interface 300 can be an interface that conforms to a general serial data transmission protocol, such as a Universal Serial Bus (USB) interface.

[0035] The first peripheral circuit 230 and the second peripheral circuit 240 can be implemented by configuring the firmware and setting the pins of the general peripheral circuits built into the BMC chip.

[0036] Serial port data refers to monitoring data, configuration data, control data, debugging data, and interactive data between the firmware and the software when a fault occurs during software operation. For example, when the first processor core is BIOS, the first serial port data can be hardware initialization logs, startup fault reports, configuration parameter information, etc., while the second serial port data of the BMC processor core can be system operation logs, hardware status information, remote control command feedback, etc.

[0037] When the electronic device 1000 is operating, the firmware storage circuit 100 can transmit the first serial port data it generates to the first processor core 210. The first processor core 210 can provide the first serial port data provided by the firmware storage circuit 100 and the second serial port data generated by the first processor core 210 itself to the first peripheral circuit 230. The first peripheral circuit 230 can independently receive and store the first and second serial port data. The second processor core 220 can read the first and second serial port data from the first peripheral circuit 230 and provide the first and second serial port data to the second peripheral circuit 240. The second peripheral circuit 240 can convert the data protocol format of the serial port data, and after conversion, it can output it through the general data interface 300. In some embodiments, if the general data interface 300 is a USB interface, the second peripheral circuit 240 can convert the serial port data into USB format serial port data for transmission through the USB interface.

[0038] According to embodiments of this application, by configuring a second processor core, a first peripheral circuit, and a second peripheral circuit in the management controller, and connecting them with a universal data interface, the electronic device can transmit first serial port data and second serial port data in parallel to external devices through the universal data interface. Compared to using a serial-to-interface cable for time-sharing transmission, on the one hand, the electronic device supports universal data interface connections, eliminating the need for a dedicated data converter, such as freeing it from reliance on an external USB-to-serial cable, thus improving ease of use; on the other hand, it achieves parallel output from two serial ports, improving debugging and maintenance efficiency.

[0039] Figure 2 A structural block diagram of an electronic device 1000 according to another embodiment of this application is shown.

[0040] According to embodiments of this application, such as Figure 2 As shown, the first peripheral circuit 230 includes: a first interface circuit 231 for receiving first serial port data; a second interface circuit 232 for receiving second serial port data; a first buffer 233 for buffering the first serial port data; and a second buffer 234 for buffering the second serial port data. The first interface circuit 231, the second interface circuit 232, the first buffer 233, and the second buffer 234 are connected to a first processor core 210 and a second processor via a bus. The first processor core 210 provides the first serial port data to the first interface circuit 231 and the second interface circuit 232, respectively. The second processor core 220 reads the first serial port data from the first interface circuit 231 and writes it to the first buffer 233, reads the second serial port data from the second interface circuit 232 and writes it to the second buffer 234, and provides the first serial port data in the first buffer 233 and the second serial port data in the second buffer 234 to the second peripheral circuit 240.

[0041] The first interface circuit 231, the second interface circuit 232, the first cache 233, the second cache 234, and the second peripheral circuit 240 can all be implemented by firmware configuration and pin settings of the general peripheral circuits built into the BMC chip. Among them, the first cache 233 and the second cache 234 are shared memory cache areas.

[0042] The first interface circuit 231 and the second interface circuit 232 can be Universal Asynchronous Receiver / Transmitter (UART) interfaces. Of course, the embodiments of this disclosure are not limited to this; the second interface circuit and the second interface circuit can also be implemented as other interface circuits with serial port capabilities. The first interface circuit 231 can be a UART1 interface, and the second interface circuit 232 can be a UART2 interface, see [link to relevant documentation]. Figure 2Using firmware storage circuit 100 as the basic input / output system (BIOS), first processor core 210 as baseboard management controller (BMC) processor core and second processor core 220 as MCU processor core for example illustration, the BIOS can output BIOS serial port data (i.e. first serial port data) and BMC can output BMC serial port data (i.e. second serial port data).

[0043] It should be noted that more interface circuits can be added to the first peripheral circuit 230 to support the parallel output of serial port data from more serial port devices. For example, it can also support the serial port data output of serial port devices such as Redundant Array of Independent Disks (RAID) cards and network cards.

[0044] like Figure 2 As shown, both the first cache (233) and the second cache (234) are circular buffers, and their capacities can be configured according to actual needs, such as 16KB or 32KB. A circular buffer, also known as a circular queue or circular buffer, is a fixed-size buffer data structure that logically forms a ring structure by connecting the first and last nodes. It achieves efficient data caching and management by cyclically reusing fixed-size memory blocks, and is particularly suitable for producer-consumer models and real-time streaming data processing scenarios.

[0045] When the first processor core 210 provides the first serial port data and the second serial port data to the first peripheral circuit 230, the first interface circuit UART1 mainly receives the first serial port data from the firmware storage circuit 100, and the second interface circuit UART2 receives the second serial port data generated by the first processor core 210 itself.

[0046] The second processor core 220 reads the corresponding serial port data from the two interface circuits UART1 and UART2 respectively. For the first serial port data read, the second processor core 220 can write the first serial port data into the first buffer 233. For the second serial port data read, the second processor core 220 can write the second serial port data into the corresponding second buffer 234. The first buffer 233 and the second buffer 234 can be circular buffers, that is, the previously stored serial port data is overwritten through circular reuse.

[0047] For the first serial port data and the second serial port data stored in the first cache 233 and the second cache 234 respectively, the second processor core 220 can read the first serial port data and the second serial port data from the first cache 233 and the second cache 234 again, and provide the first serial port data and the second serial port data to the second peripheral circuit 240, which has a USB module circuit. In this embodiment, the second peripheral circuit 240 can convert the received first serial port data and the second serial port data into first serial port data and second serial port data in USB protocol format respectively, thereby outputting the format-converted first serial port data and second serial port data through a general data interface 300 (such as a USB interface).

[0048] In this embodiment, the bus described can be an Advanced High-performance Bus (AHB), which is used for communication between the first processor core 210 and the second processor core 220. It supports data interaction functions, such as the first processor core 210 sending configuration commands to configure interface circuits and cache circuits. It can also report status, such as the second processor core 220 reporting the connection status between external devices and electronic device 1000, and the cache status of serial port data, to the first processor core 210. It should be noted that, in addition to the AHB bus, the bus in this embodiment can also be other types of buses, such as the Advanced Peripheral Bus (APB), the Advanced Extensible Interface (AXI) bus, and the Advanced System Bus (ASB).

[0049] In one embodiment, the AHB bus can be used for communication between two processor cores, which can avoid signal interference problems caused by external cable connections and help improve system integration and stability.

[0050] According to the embodiments of this application, by setting a first interface circuit 231 and a second interface circuit 232, along with corresponding first caches 233 and second caches 234, in the management controller 200, after the first peripheral circuit 230 receives the first serial port data and the second serial port data transmitted by the first processor core 210, these data can be received by the corresponding first interface circuit 231 and second interface circuit 232, respectively. The second processor core 220 then writes the first serial port data from the first interface circuit 231 and the second interface circuit 232 into the corresponding first caches 233 and second caches 234, and provides the first serial port data and the second serial port data from the first caches 233 and second caches 234 to the second peripheral circuit 240 for output. This enables simultaneous transmission of the first serial port data from the firmware storage circuit 100 and the second serial port data from the first processor core 210, improving the operation and maintenance response speed. Furthermore, the presence of cache circuits corresponding to different serial port data allows for the storage of generated serial port data at any time, avoiding data loss issues caused by serial port switching, ensuring data integrity, and contributing to improved accuracy in subsequent fault analysis.

[0051] According to an embodiment of this application, the first interface circuit 231 is further configured to provide a first interrupt signal to the second processor core 220 in response to receiving first serial port data, and the second interface circuit 232 is further configured to provide a second interrupt signal to the second processor core 220 in response to receiving second serial port data; the second processor core 220 is configured to read the first serial port data from the first interface circuit 231 and store it in the first cache 233 in response to the first interrupt signal, and to read the second serial port data from the second interface circuit 232 and store it in the second cache 234 in response to the second interrupt signal.

[0052] The first and second interrupt signals can instruct the second processor core 220 to perform data operations.

[0053] When the first interface circuit UART1 receives the corresponding first serial port data, the first interface circuit UART1 can provide a first interrupt signal to the second processor core 220. In response to the first interrupt signal, the second processor core 220 can read the corresponding first serial port data from the corresponding first interface circuit UART1 and store the read first serial port data in the corresponding first cache 233.

[0054] When the second interface circuit UART2 receives the corresponding second serial port data, the second interface circuit UART2 can provide a second interrupt signal to the second processor core 220. In response to the second interrupt signal, the second processor core 220 can read the corresponding second serial port data from the corresponding second interface circuit UART2 and store the read second serial port data in the corresponding second cache 234.

[0055] As can be seen from the above, the second processor core 220 in this embodiment adopts an interrupt-driven approach. This interrupt-driven approach supports parallel operation and does not require polling the state of the interface circuit. It only needs to notify the second processor core 220 through an interrupt signal when the interface device receives serial port data, thereby reducing the invalid occupation of the resources of the second processor core 220.

[0056] According to an embodiment of this application, the second processor core 220 is further configured to: in response to the connection of the general data interface 300 with a debugging device outside the electronic device, receive an enumeration request from the debugging device through the general data interface 300, and provide the debugging device with description information of the first interface circuit 231 and the second interface circuit 232 according to the enumeration request. The description information is used to enable the debugging device to generate a first virtual serial port device for the first interface circuit 231 and a second virtual serial port device for the second interface circuit 232.

[0057] The debugging equipment can be a debugging host, which can debug electronic device 1000 based on serial port data, and can also pinpoint the specific location of the fault in electronic device 1000 or server. For example, in the event of an electronic device crashing or hardware failure, staff can quickly locate the location and cause of the fault by obtaining the first serial port data (such as BIOS boot error reports) and the second serial port data (such as BMC fault alarm logs).

[0058] When staff use a data cable (such as a regular USB data cable) to connect to the general data interface 300 and the debugging device, the USB host controller of the debugging host can send an enumeration request to the second processor core 220 through the USB data cable and the USB interface (i.e., the general data interface 300). The second processor core 220 returns descriptive information such as device descriptors, configuration descriptors, and interface descriptors to the debugging host according to the communication device class protocol. In this embodiment, the communication device class protocol can be the Communication Device Class-Abstract Control Model (CDC-ACM) protocol, which is a subclass of the USB communication device class protocol and is mainly used to implement virtual serial communication. Of course, it can also be other types of communication device class protocols.

[0059] In one specific embodiment, when the general data interface 300 is a USB interface, the USB interface can be located on the front panel or back panel of the server. The interface can specifically adopt the form of USB Type-C or Type-A interface. When the staff connects the debugging equipment such as laptops and desktop computers to the USB interface through the USB data cable, different serial port data can be transmitted simultaneously. This method does not require a serial port adapter cable, which effectively improves the portability of serial port data transmission.

[0060] It should be noted that the length of the USB data cable can be flexibly selected, such as 10m, 20m, etc. Using a USB data cable for connection can meet the needs of long-distance debugging. Moreover, the data cable is low in cost, easy to obtain, and not easily damaged, which can significantly improve the convenience of debugging.

[0061] When the communication device uses the CDC-ACM protocol, the debugging host can determine that the electronic device 1000 is a "USB serial port device" based on the returned description information. The debugging host can then automatically load the built-in CDC-ACM driver and generate virtual serial port devices for the two interface circuits in its system. In one operating system, these two virtual serial port devices can be labeled "ttyUSB0" and "ttyUSB1," while in another operating system, they can be labeled "COMx" and "COMy." Specifically, the first virtual serial port device ttyUSB0 (or COMx) corresponds to the first interface circuit UART1 and is used to receive the first serial port data. The second virtual serial port device ttyUSB1 (or COMy) corresponds to the second interface circuit UART2 and is used to receive the second serial port data.

[0062] It should be noted that when there are many serial port devices, more interface circuits can be set in the first peripheral circuit 230 so that each serial port device can transmit serial data through an interface circuit. During this process, the debugging host (i.e., the debugging device) also needs to generate virtual serial port devices for different interface circuits to simultaneously obtain the serial port data of different serial port data output by the second processor core 220 through the second peripheral circuit 240.

[0063] The two independent virtual serial port devices described above enable simultaneous output of data from both the first and second serial ports. Operators on the debugging equipment can simultaneously view this data. In a specific embodiment, such as in a server production debugging scenario, operators can simultaneously analyze the hardware initialization logs of the Basic Input / Output System (BIOS) and the system startup logs of the Baseboard Management Controller (BMC) 200, quickly pinpointing the correlation between hardware initialization failures (e.g., memory not recognized) and BMC monitoring anomalies (e.g., excessively high memory temperature), reducing debugging time by more than 50%. Furthermore, because the serial port data is output in parallel, there is no need to switch between the BMC and BIOS serial ports, avoiding data loss issues caused by switching processes in traditional solutions, ensuring the integrity of log data, and improving the accuracy of fault location. In addition, regarding response speed, when the server crashes, operators can simultaneously obtain the BMC fault alarm logs (e.g., power failure) and the BIOS startup error reports (e.g., processor initialization failure), enabling rapid identification of the root cause of the fault, reducing maintenance response time by more than 60%.

[0064] According to the embodiments of this application, by enumerating between the debugging device and the electronic device 1000, virtual serial port devices corresponding to different interface circuits are formed in the debugging device. This enables the simultaneous classified reception of different serial port data, which not only improves the data reception efficiency and reduces the cumbersomeness of the debugging process, but also reduces the risk of data loss. Furthermore, by receiving data in a classified manner at the same time, the problem of reduced data availability caused by the confusion of different types of serial port data can be avoided.

[0065] According to an embodiment of this application, the first processor core 210 is further configured to initialize the first interface circuit 231 and the second interface circuit 232 in response to power-on of the electronic device; the second processor core 220 is further configured to initialize the first cache 233, the second cache 234 and the second peripheral circuit 240 in response to power-on of the electronic device.

[0066] After the electronic device is powered on, the management controller 200 first completes the initialization, that is, the first processor core 210 starts the system of the management controller 200, and the second processor core 220 starts and begins to execute the firmware initialization program.

[0067] During the initialization process of the first processor core 210 on the first interface circuit 231 and the second interface circuit 232, the communication parameters of the first interface circuit UART1 (connected to the serial port of the firmware storage circuit 100) and the second interface circuit UART2 (connected to the serial port of the first processor core 210) can be configured, including baud rate (default 115200bps, which can be modified to 9600bps, 38400bps, 57600bps, etc.), data bits (e.g., 8 bits), stop bits (e.g., 1 bit), and parity bit (no parity bit is allowed; this parity bit supports odd parity, even parity, etc.).

[0068] During the initialization process of the second peripheral circuit 240 by the second processor core 220, if the second peripheral circuit 240 is a USB circuit, USB 2.0 (or USB 3.0, etc.) high-speed mode parameters can be configured. Simultaneously, the CDC-ACM protocol firmware is loaded, and the device identifiers of the first and second virtual serial port devices in the USB circuit are set (e.g., VID=0x1234, PID=0x5678, where the first and second virtual serial port devices correspond to the first interface circuit UART1 and the second interface circuit UART2, respectively). In a specific embodiment, USB 3.0 parameters can be configured to further improve data transmission efficiency and meet the demand for higher bandwidth.

[0069] During the initialization process described above, it is also necessary to initialize the communication controller between the first processor core 210 and the second processor core 220, such as initializing the communication parameters of the communicator to establish a data interaction channel. In addition, the AHB bus can be initialized when the electronic device 1000 is powered on.

[0070] According to the embodiment within the device, after the electronic device is powered on, the first peripheral circuit 230 and the second peripheral circuit 240 are initialized by the two processor cores respectively. This prepares for the subsequent output of serial port data, so that the data required for data analysis can be output quickly, which helps to improve the efficiency of data analysis and facilitates the rapid location of faults.

[0071] According to an embodiment of this application, at least one of the first interface circuit and the second interface circuit 232 is a universal asynchronous transceiver interface.

[0072] In one embodiment, both the first interface circuit 231 and the second interface circuit 232 can be Universal Asynchronous Receiver / Transmitter (UART) interfaces. Alternatively, one interface circuit can be a UART interface, and the other interface circuit can be another type of interface.

[0073] According to the embodiments of this application, a Universal Asynchronous Receiver / Transmitter (UART) interface is used as the interface circuit. Since the UART interface is simple, reliable and flexible, the area occupied by the management controller 200 can be reduced, and serial port data can be transmitted accurately, thereby improving the reliability of the serial port data.

[0074] According to an embodiment of this application, the first processor core 210 is further configured to provide a configuration instruction to the second processor core 220 in response to receiving a configuration instruction from a user; the second processor core 220 is further configured to modify the configuration information of at least one of the first peripheral circuit 230 and the second peripheral circuit 240 according to the configuration instruction.

[0075] Staff can send configuration commands to the first processor core 210 through the graphical user interface in the debugging host. After receiving the configuration command, the first processor core 210 can transmit it to the second processor core 220. The second processor core 220 can respond to the configuration command by modifying the configuration information of at least one of the first peripheral circuit 230 and the second peripheral circuit 240. For example, it can modify the communication parameters of the first interface circuit UART1 and the second interface circuit UART2, including baud rate, data bits, stop bits, parity bits, etc.

[0076] In one specific embodiment, the operator can issue configuration commands to the first processor core 210 through a web interface or command line interface (CLI), such as adjusting the baud rate of the first interface circuit UART1 and the second interface circuit UART2; the first processor core 210 sends the configuration commands to the second processor core 220 through the AHB bus, and the second processor core 220 updates the corresponding configuration parameters after receiving the configuration commands, thereby realizing dynamic adjustment.

[0077] In the embodiments of this application, the communication parameters of the peripheral circuit and the configuration of the cache are dynamically adjusted by configuration instructions, thereby realizing the portability of configuration parameter adjustment and adapting to the needs of different debugging scenarios.

[0078] According to an embodiment of this application, the electronic device 1000 modifies the configuration information in the first peripheral circuit 230 and the second peripheral circuit 240 based on the configuration instructions sent by the user. This enables the electronic device 1000 to transmit serial port data according to the user's requirements or format, which facilitates data analysis based on the serial port data in the user's format or requirements and helps to improve the accuracy of data analysis.

[0079] According to an embodiment of this application, the first processor core is also connected to the second processor core 220, and the first processor core 210 is also used to monitor the status signal of the second processor core 220 and determine whether the second processor core 220 has malfunctioned based on the status signal.

[0080] The status signal may include a heartbeat signal. The first processor core 210 queries in real time or periodically whether the second processor core 220 has sent a status signal to the first processor core 210. Periodic querying can refer to querying at preset time intervals, which can be set according to actual needs, for example, 500ms.

[0081] If the first processor core 210 does not receive a status signal from the second processor core 220, it can be determined that the second processor core 220 has malfunctioned. If the first processor core 210 can receive a status signal, it can be determined that the second processor core 220 is in normal working condition.

[0082] In a specific embodiment, the first processor core 210 can query every 500ms whether it has received a heartbeat signal from the second processor core 220. If it fails to receive a heartbeat signal for three consecutive times (or five times, etc., the specific number can be set according to actual needs), it can be considered that the second processor core 220 has malfunctioned and cannot be used.

[0083] Figure 3 A structural block diagram of an electronic device 1000 according to yet another embodiment of this application is shown.

[0084] According to embodiments of this application, such as Figure 3 As shown, the electronic device 1000 further includes a switching controller 400 and a physical serial port 500 connected to the switching controller 400. The first processor core 210 is also configured to switch to a standby mode in response to a failure of the second processor core 220. In the standby mode, the first processor core 210 is configured to receive first serial port data from the firmware storage circuit 100 and generate second serial port data. In response to receiving a switching command provided by the user, it provides the first serial port data, the second serial port data, and a switching signal to the switching controller 400 according to the switching command. The switching controller 400 is configured to output one of the received first serial port data and the second serial port data through the physical serial port 500 according to the switching signal provided by the first processor core 210.

[0085] The switching controller 400 may include a complex programmable logic device (CPLD) or other devices capable of performing the same function.

[0086] If the first processor core 210 fails to detect the status signal of the second processor core 220 and determines that the second processor core 220 has malfunctioned, it can switch to standby mode.

[0087] In standby mode, the first processor core 210 can normally receive the first serial port data generated by the firmware storage circuit 100, and at the same time, the first processor core 210 also normally generates the second serial port data. The user can send a switching command to the first processor core 210 through the debugging device. At this time, the first processor core 210 responds to the switching command and can provide the first serial port data, the second serial port data and the switching signal to the switching controller 400.

[0088] In response to the received switching signal, the switching controller 400 can determine whether the serial port data required by the user is the first serial port data or the second serial port data. If it is confirmed that the user needs the first serial port data, the switching controller 400 can output the first serial port data transmitted by the first processor core 210 through the physical serial port 500. If it is confirmed that the user needs the second serial port data, the switching controller 400 can output the second serial port data transmitted by the first processor core 210 through the physical serial port 500, so that the user can receive the first serial port data or the second serial port data through the debugging device.

[0089] During the process of receiving serial port data through the switching controller 400, the debugging device used by the user can be connected to the physical serial port 500 via a serial cable. For example, when the physical serial port 500 is a USB serial port, a USB to serial cable can be used to connect the debugging device to the electronic device.

[0090] According to the embodiments of this application, in the event of a failure of the second processor core 220, the system can switch to standby mode in a timely manner, so that the user can obtain the serial port data generated by the first processor core 210 and the firmware storage circuit 100 based on the switching controller 400, so as to perform fault analysis based on the serial port data. This avoids the problem of being unable to locate the fault due to the failure of the second processor core 220, and helps to improve the fault recovery efficiency and redundancy of electronic devices or servers.

[0091] According to embodiments of this application, the general data interface includes a universal serial bus interface, and the predetermined protocol format includes a universal serial bus interface format.

[0092] This embodiment can use a Universal Serial Bus (USB) interface as the general data interface 300, mainly considering the uniformity of the USB interface and its commonality in daily life. When performing fault analysis, the corresponding data cable can be quickly found from the working environment, which helps to improve the efficiency of fault analysis and enables electronic devices or servers to quickly recover from the fault state to the working state.

[0093] The Universal Serial Bus (USB) format is designed to enable the USB interface to transmit serial data correctly. When the type of the Universal Data Interface 300 changes, the predefined protocol format should be changed accordingly.

[0094] According to an embodiment of this application, the first processor core 210 includes a BMC processor core, the second processor core 220 includes a microprocessor core, the firmware storage circuit 100 includes a basic input / output system, and the first processor core 210 and the second processor core 220 are connected to the first peripheral circuit 230 and the second peripheral circuit 240 via an advanced high-performance bus.

[0095] The first processor core includes a Baseboard Management Controller (BMC) processor core, and the second processor core 220 includes a Microcontroller Unit (MCU) core.

[0096] In one specific embodiment, if the firmware storage circuit 100 is a basic input / output system, the firmware storage circuit 100 can output hardware initialization logs, startup progress information, fault error codes and other first serial port data during the power-on startup process of the electronic device. The interface circuit of the firmware storage circuit 100 itself is connected to the interface circuit of the first processor core 210 through physical lines, so that the firmware storage circuit 100 transmits the first serial port data to the first processor core 210.

[0097] In one specific embodiment, if the first processor core 210 is a BMC processor core, the first processor core 210 is mainly responsible for the core functions of server hardware monitoring, remote management, fault alarm, etc., and outputs second serial port data such as system operation logs and hardware status information through the built-in interface circuit.

[0098] In this embodiment, the first processor core 210 and the second processor core 220 can be connected to the first peripheral circuit 230 and the second peripheral circuit 240 via an advanced high-performance bus.

[0099] Figure 4 A structural block diagram of an electronic device 1000 according to another embodiment of this application is shown.

[0100] In one illustrative embodiment, such as Figure 4 As shown, the electronic device 1000 can use a USB interface as a general data interface 300. This USB interface is connected to the debugging device through a general data transmission cable (such as a regular USB data cable), and at the same time, the debugging device is connected to the physical serial port in the electronic device 1000 through a USB to serial cable.

[0101] When the first processor core 210 can listen to the status signal of the second processor core 220, the second processor core 220 can read the first serial port data and the second serial port data from the first cache 233 and the second cache 234 respectively, and provide them to the second peripheral circuit 240, i.e., the USB module. The USB module converts the received first serial port data and the second serial port data into USB format and transmits them to the debugging device through the USB interface and ordinary USB data cable.

[0102] If the first processor core 210 fails to detect a status signal three times in a row (e.g., at 500ms intervals), it can determine that the second processor core 220 is in a fault state. At this time, the first processor core 210 is also configured to switch to standby mode in response to the fault of the second processor core 220.

[0103] In standby mode, the user can send a switching command to the first processor core 210 in the debugging device. At this time, the first processor core 210 responds to the switching command by providing a switching signal to the switching controller 400. In response to the received switching signal, the switching controller 400 can determine whether the serial port data required by the user is the first serial port data or the second serial port data. If it is confirmed that the user needs the first serial port data, the switching controller 400 can output the first serial port data transmitted by the first processor core 210 through the physical serial port. If it is confirmed that the user needs the second serial port data, the switching controller 400 can output the second serial port data transmitted by the first processor core 210 through the physical serial port, so that the user can receive the first serial port data or the second serial port data through the debugging device.

[0104] If the switching signal at the current time period corresponds to receiving data from the first serial port, the user can send a switching signal to receive data from the second serial port again after a period of time. The switching controller 400 responds to the switching signal and can output data from the second serial port, thereby realizing time-sharing transmission of data from different serial ports.

[0105] Figure 5 A structural block diagram of a data transmission system according to an embodiment of this application is shown.

[0106] like Figure 5As shown, the data transmission system includes: the aforementioned electronic device 1000; a debugging device 2000, which includes a general data interface 300 that matches the general data interface 300 of the electronic device 1000, and the general data interface 300 of the debugging device 2000 and the general data interface 300 of the electronic device 1000 are connected to each other; and a general data transmission line 3000, through which the general data interface 300 of the debugging device 2000 and the general data interface 300 of the electronic device 1000 are connected to each other.

[0107] The debugging device 2000 can refer to the device used by staff to receive serial port data, such as a laptop or desktop computer, or other devices that can be connected to the electronic device 1000. There are no restrictions here.

[0108] The type of universal data transmission cable 3000 can be specifically set according to actual needs, such as USB data cable or other types of transmission cables. Considering the cost and difficulty of obtaining data cables, this embodiment uses a USB data cable, specifically a USB Type-C data cable.

[0109] In one specific embodiment, when the electronic device is running, the firmware storage circuit 100 in the electronic device 1000 can transmit the first serial port data to the first processor core 210. While receiving the first serial port data, the first processor core 210 also generates the second serial port data. Thus, the first processor core 210 can provide the first serial port data and the second serial port data to the first peripheral circuit 230. The serial port data can be transmitted in the first peripheral circuit 230. At this time, the second processor core 220 can read the first serial port data and the second serial port data from the first peripheral circuit 230 and provide the first serial port data and the second serial port data to the second peripheral circuit 240. The second peripheral circuit 240 can convert the data protocol format of the first serial port data and the second serial port data. After the conversion is completed, it can be transmitted through the general data interface 300.

[0110] When the general data interface 300 is connected to the debugging device 2000 via the general data transmission line 3000, the first serial port data and the second serial port data are simultaneously transmitted to the debugging device 2000 via the general data transmission line 3000. Thus, the staff can perform data analysis on the received first serial port data and second serial port data on the debugging device 2000, such as fault location.

[0111] According to embodiments of this application, by configuring a second processor core, a first peripheral circuit, and a second peripheral circuit in the management controller, and connecting them with a universal data interface, the electronic device can transmit first serial port data and second serial port data in parallel to external devices through the universal data interface. Compared to using a serial-to-serial cable for time-sharing transmission, the electronic device supports universal data interface connections, eliminating the need for a dedicated data converter and improving ease of use; furthermore, it achieves parallel output from both serial ports, improving debugging and maintenance efficiency.

[0112] According to the embodiments of this application, the general data interface 300 of the debugging device 2000 and the general data interface 300 of the electronic device 1000 are both general serial bus interfaces, and the general data transmission line is a general serial bus transmission line.

[0113] In one specific embodiment, the second peripheral circuit 240 can convert the first serial port data and the second serial port data into USB format serial port data. With the USB transmission line connected to the USB interface of the debugging device 2000 and the USB interface of the electronic device 1000 at both ends, the USB formatted first and second serial port data can be transmitted to the debugging device 2000 via the USB transmission line. It should be noted that the length of the USB data cable can be flexibly selected, for example, 10m, 20m, etc.

[0114] According to the embodiments of this application, a USB interface and a USB transmission cable are used to transmit data from the first serial port and the second serial port. Since the USB data cable can be of different lengths as needed, it can meet the requirements of long-distance debugging. At the same time, the USB data cable is low in cost, easy to obtain, and not easily damaged, which can significantly improve the convenience of debugging.

[0115] According to an embodiment of this application, the data transmission system further includes a data converter, and the electronic device 1000 further includes a switching control circuit and a physical serial port connected to the switching control circuit, wherein the physical serial port is connected to the input end of the data converter; the general data interface of the debugging device 2000 includes a first general data interface and a second general data interface, wherein the first general data interface is connected to the general data interface 300 of the electronic device 1000, and the second general data interface is connected to the output end of the data converter.

[0116] A data converter is a device that enables data transmission between electronic device 1000 and debugging device 2000 by converting interface protocols. For example, it can be a USB to serial cable, which is a conversion cable that can convert USB signals from a USB interface into serial signals.

[0117] The switching control circuit may include a complex programmable logic device (CPLD).

[0118] In one specific embodiment, the first processor core 210 in the electronic device 1000 queries in real time or periodically whether the second processor core 220 sends a status signal to the first processor core 210. If the first processor core 210 does not receive the status signal sent by the second processor core 220, it can be determined that the second processor core 220 has failed, and it can switch to standby mode.

[0119] In standby mode, the first processor core 210 in the electronic device 1000 can normally receive the first serial port data generated by the firmware storage circuit 100, and at the same time, the first processor core 210 is also normally generating the second serial port data. The user can send a switching command to the first processor core 210 through the debugging device 2000. At this time, the first processor core 210 responds to the switching command and can provide a switching signal to the switching controller 400, and at the same time transmit the first serial port data and the second serial port data to the switching control circuit.

[0120] In response to the received switching signal, the switching control circuit can determine whether the serial port data required by the user is the first serial port data or the second serial port data. If it is confirmed that the user needs the first serial port data, the switching control circuit can output the first serial port data transmitted by the first processor core 210 through the physical serial port. If it is confirmed that the user needs the second serial port data, the switching control circuit can output the second serial port data transmitted by the first processor core 210 through the physical serial port. The output first or second serial port data is transmitted to the debugging device 2000 via the data converter and the first general-purpose data interface.

[0121] In another specific embodiment, when the second processor core 220 is not faulty, the second processor core 220 provides the first serial port data in the first cache 233 and the second serial port data in the second cache 234 to the second peripheral circuit 240. The second peripheral circuit 240 transmits the first serial port data and the second serial port data to the first general data interface through the general data interface 300 so that the debugging device 2000 can receive the first serial port data and the second serial port data.

[0122] According to the embodiments of this application, in the event of a failure of the second processor core 220, the system can switch to standby mode in a timely manner, so that the user can obtain the first serial port data and the second serial port data based on the switching control circuit, so as to perform fault analysis based on the serial port data. This avoids the problem of being unable to locate the fault due to the failure of the second processor core 220, and helps to improve the fault recovery efficiency and redundancy of the server.

[0123] According to an embodiment of this application, the second processor core 220 is further configured to: receive an enumeration request from the debugging device 2000 through the general data interface 300 of the electronic device, and provide the debugging device 2000 with description information of the first interface circuit 231 and the second interface circuit 232 according to the enumeration request. The debugging device 2000 is further configured to: generate a first virtual serial port device for the first interface circuit 231 and a second virtual serial port device for the second interface circuit 232 according to the description information provided by the second processor core 220. The first virtual serial port device receives first serial port data from the electronic device, and the second serial port device receives second serial port data from the electronic device.

[0124] When staff use the universal data transmission line 3000 to connect the universal data interface of the debugging device 2000 to the universal data interface 300 of the electronic device 1000, the debugging device 2000 can send an enumeration request to the second processor core 220 through the universal data interface 300. The second processor core 220 returns descriptive information such as device descriptors, configuration descriptors, and interface descriptors to the debugging device 2000 according to the communication device class protocol. In this embodiment, the communication device class protocol can be the CDC-ACM protocol.

[0125] In one specific embodiment, the general data interface can be a USB interface. When the staff connects the debugging equipment 2000, such as a laptop or desktop computer, to the USB interface via a USB data cable, data from different serial ports can be transmitted simultaneously. This method does not require a serial port adapter cable, effectively improving the portability of serial port data transmission.

[0126] When the communication device uses the CDC-ACM protocol, the debugging device 2000 can determine that the electronic device 1000 is a "USB serial port device" based on the returned description information. Therefore, the debugging device 2000 can automatically load the built-in CDC-ACM driver, and subsequently generate a first virtual serial port device and a second virtual serial port device for the first interface circuit 231 and the second interface circuit 232, respectively. These two virtual serial port devices can be labeled "ttyUSB0" and "ttyUSB1," and in Windows systems, they can be labeled "COMx" and "COMy." Specifically, the first virtual serial port device ttyUSB0 (or COMx) corresponds to the first interface circuit UART1 and is used to receive first serial port data, while the second virtual serial port device ttyUSB1 (or COMy) corresponds to the second interface circuit UART2 and is used to receive second serial port data.

[0127] According to the embodiments of this application, by enumerating between the debugging device 2000 and the electronic device 1000, a first virtual serial port device and a second virtual serial port device corresponding to the first interface circuit 231 and the second interface circuit 232 are formed in the debugging device 2000. This enables the simultaneous reception of data from different serial ports, which not only improves the data reception efficiency and reduces the complexity of the debugging process, but also reduces the risk of data loss. Furthermore, by receiving data simultaneously, the problem of reduced data availability caused by the confusion of different types of serial port data can be avoided.

[0128] It should be noted that the data transmission system part in the embodiments of this application has the same or similar principle as the electronic device part in the embodiments of this application. The description of the data transmission system part is specifically referred to the electronic device part, and will not be repeated here.

[0129] Figure 6 A flowchart of a data transmission method according to an embodiment of this application is shown.

[0130] like Figure 6 As shown, the data transmission method performed by the electronic device includes operations S601 to S604.

[0131] In operation S601, the first processor core in the management controller receives first serial port data from the firmware storage circuit, generates second serial port data, and provides the first serial port data and the second serial port data to the first peripheral circuit.

[0132] When operating S602, the first peripheral circuit independently receives and stores the data from the first serial port and the second serial port.

[0133] When operating S603, the second processor core reads the first serial port data and the second serial port data from the first peripheral circuit and provides them to the second peripheral circuit.

[0134] When operating the S604, the second peripheral circuit converts the data from the first serial port and the second serial port into a predetermined protocol format and outputs it through a general data interface.

[0135] When the electronic device is working, the firmware storage circuit can transmit the first serial port data to the first processor core. While receiving the first serial port data, the first processor core also generates the second serial port data. Thus, the first processor core can provide the first serial port data and the second serial port data to the first peripheral circuit. The first peripheral circuit independently receives and stores the first serial port data and the second serial port data.

[0136] The second processor core can read first serial port data and second serial port data from the first peripheral circuit and provide the two serial port data to the second peripheral circuit. The second peripheral circuit can convert the data protocol format of the first serial port data and the second serial port data. After the conversion is completed, it can be transmitted through a general data interface. In some embodiments, if the general data interface is a USB interface, the second peripheral circuit can convert the first serial port data and the second serial port data into USB format for transmission through the USB interface.

[0137] According to embodiments of this application, by configuring a second processor core, a first peripheral circuit, and a second peripheral circuit in the management controller, and connecting them with a universal data interface, the electronic device can transmit first serial port data and second serial port data in parallel to external devices through the universal data interface. Compared to using a serial-to-serial cable for time-sharing transmission, the electronic device supports universal data interface connections, eliminating the need for a dedicated data converter and improving ease of use; furthermore, it achieves parallel output from both serial ports, improving debugging and maintenance efficiency.

[0138] According to an embodiment of this application, the data transmission method further includes: in response to a connection between a general data interface and a debugging device outside the electronic device, the second processor core receives an enumeration request from the debugging device through the general data interface, and provides description information of a first interface circuit and a second interface circuit to the debugging device according to the enumeration request. The description information is used to enable the debugging device to generate a first virtual serial port device for the first interface circuit and a second virtual serial port device for the second interface circuit.

[0139] When staff use a universal data transmission line to connect the universal data interface of the debugging equipment to the universal data interface of the electronic equipment, the debugging equipment can send an enumeration request to the second processor core through the universal data transmission line. The second processor core returns descriptive information such as device descriptor, configuration descriptor, and interface descriptor to the debugging equipment according to the communication device class protocol.

[0140] In one specific embodiment, when the communication device class protocol is the CDC-ACM protocol, the debugging device can determine that the electronic device is a "USB serial port device" based on the returned description information. Thus, the debugging device can automatically load the built-in CDC-ACM driver and generate a first virtual serial port device and a second virtual serial port device for the two first interface circuits and the second interface circuit, respectively. The first virtual serial port device corresponds to the first interface circuit UART1 and is used to receive the first serial port data. The second virtual serial port device corresponds to the second interface circuit UART2 and is used to receive the second serial port data.

[0141] According to the embodiments of this application, by enumerating between the debugging device and the electronic device, virtual serial port devices corresponding to different interface circuits are formed in the debugging device. This enables the simultaneous classified reception of different serial port data, which not only improves the data reception efficiency and reduces the cumbersomeness of the debugging process, but also reduces the risk of data loss. Furthermore, by receiving data in a classified manner at the same time, the problem of reduced data availability caused by the confusion of different types of serial port data can be avoided.

[0142] According to an embodiment of this application, the data transmission method further includes: a first processor core providing a configuration instruction to a second processor core in response to receiving a configuration instruction from a user; and the second processor core modifying the configuration information of at least one of the first peripheral circuit and the second peripheral circuit according to the configuration instruction.

[0143] Staff can send configuration commands to the first processor via a web interface or command-line interface on the debugging host. After receiving the configuration command, the first processor core can transmit it to the second processor core. The second processor core can respond to the configuration command by modifying the configuration information of at least one of the first and second peripheral circuits. For example, it can modify the communication parameters of the first interface circuit UART1 and the second interface circuit UART2, including baud rate, data bits, stop bits, parity bits, etc.

[0144] In one specific embodiment, the operator issues a configuration command to the first processor core, such as adjusting the baud rate of the first interface circuit UART1 and the second interface circuit UART2; the first processor core sends the configuration command to the second processor core through the AHB bus, and the second processor core updates the corresponding configuration parameters after receiving the configuration command, thereby achieving dynamic adjustment.

[0145] In the embodiments of this application, the communication parameters of the peripheral circuit and the configuration of the cache are dynamically adjusted by configuration instructions, thereby realizing the portability of configuration parameter adjustment and adapting to the needs of different debugging scenarios.

[0146] According to embodiments of this application, the electronic device modifies the configuration information in the first peripheral circuit and the second peripheral circuit based on the configuration instructions sent by the user. This enables the electronic device to transmit serial port data according to the user's requirements or format, facilitating data analysis based on the serial port data in the user's format or requirements, and helping to improve the accuracy of data analysis.

[0147] Figure 7 A flowchart of a data transmission method according to an embodiment of this application is shown.

[0148] According to an embodiment of this application, the data transmission method further includes: a first processor core listening to the status signal of a second processor core, determining whether the second processor core has malfunctioned based on the status signal, and switching to a standby mode in response to the malfunction of the second processor core.

[0149] like Figure 7 As shown, when the electronic device is working, the second processor core, when not malfunctioning, can generate a heartbeat signal (i.e., a status signal) in operation S701 and provide this heartbeat signal to the first processor core. In operation S702, the first processor core receives the heartbeat signal sent by the second processor core, and in operation S703, it continuously monitors the heartbeat signal. In operation S704, it determines whether the first processor core has detected the heartbeat signal at any given time. If it has not detected the heartbeat signal, it can be determined in operation S705 that the second processor core has malfunctioned, and it can switch to standby mode. If it has detected the heartbeat signal, it can be determined in operation S706 that the second processor core has not malfunctioned, and in normal operating mode, the transmission of first and second serial port data can be output through the second processor core and the data interface.

[0150] According to an embodiment of this application, in standby mode, the first processor core receives first serial port data from the firmware storage circuit and generates second serial port data. In response to receiving a switching instruction provided by the user, it provides the first serial port data, the second serial port data, and a switching signal to the switching controller according to the switching instruction. The switching controller outputs one of the received first serial port data and the second serial port data through a physical serial port according to the switching signal provided by the first processor core.

[0151] Status signals can include heartbeat signals, which the first processor checks periodically to see if the second processor core has sent a status signal to the first processor core. If the first processor core does not receive a status signal from the second processor core, it can be determined that the second processor core has malfunctioned. If the first processor core can receive a status signal, it can be determined that the second processor core is in normal working order.

[0152] If the first processor core fails to detect the status signal of the second processor core and determines that the second processor core has malfunctioned, it can switch to standby mode. In standby mode, the first processor core can normally receive the first serial port data generated by the firmware storage circuit, and at the same time, the first processor core is also normally generating the second serial port data. The user can send a switching command to the first processor core through the debugging device. At this time, the first processor core responds to the switching command by providing a switching signal to the switching controller, and simultaneously transmits the first serial port data and the second serial port data to the switching controller.

[0153] In response to the received switching signal, the switching controller can determine whether the serial port data required by the user is the first serial port data or the second serial port data. If it is confirmed that the user needs the first serial port data, the switching controller can output the first serial port data transmitted by the first processor core through the physical serial port. If it is confirmed that the user needs the second serial port data, the switching controller can output the second serial port data transmitted by the first processor core through the physical serial port, so that the user can receive the first serial port data or the second serial port data through the debugging device.

[0154] During the process of receiving serial port data by switching controllers, the debugging device used by the user can be connected to the physical serial port via a serial cable. For example, when the physical serial port is a USB serial port, a USB to serial cable can be used to connect the debugging device to the electronic device.

[0155] According to the embodiments of this application, in the event of a failure of the second processor core, the system can switch to standby mode in a timely manner. This allows the user to obtain serial port data generated by the first processor core and firmware storage circuit based on the switching controller, so as to perform fault analysis based on the serial port data. This avoids the problem of being unable to locate the fault due to a failure of the second processor core, and helps to improve the fault recovery efficiency and redundancy of the server.

[0156] Figure 8 A flowchart of a data transmission method according to an embodiment of another application is shown.

[0157] like Figure 8 As shown, after the electronic device is powered on, the first processor core and firmware storage circuit are started in operation S801, and serial port data is generated in operation S802. At the same time, in operation S803, the first processor core initializes the network service to enable the network service heartbeat. At this time, when the network service of the first processor core is normal, the first processor core can forward the serial port information of the first processor core and firmware storage circuit to the remote serial port server.

[0158] While executing operation S803, the second processor core is initialized in operation S804, and the second processor core initializes the second peripheral circuit that has been started in operation S805. Thus, in operation 806, the second processor core can read the execution status of the network service of the first processor core, so as to determine whether the heartbeat of the network service is normal in operation 807. If the heartbeat is abnormal, the network service can be started in operation S808 to forward serial port information that may not be exported, and the heartbeat of the network service can be continuously monitored in operation S809. If the heartbeat is confirmed to be restored in operation 810, the network service can be exited in operation S811, so that normal serial port data can be output through the second processor core in operation 812.

[0159] It should be noted that the data transmission method part in the embodiments of this application has the same or similar principle as the electronic device part in the embodiments of this application. The specific description of the data transmission method part is referred to the electronic device part, and will not be repeated here.

[0160] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0161] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. An electronic device, comprising: The electronic device comprises: a firmware storage circuit; a management controller comprising a first processor core, a second processor core, a first peripheral circuit and a second peripheral circuit, wherein the first processor core is connected with the firmware storage circuit and the first peripheral circuit, and the second processor core is connected with the first peripheral circuit and the second peripheral circuit; a general data interface connected with the second peripheral circuit; wherein, the first processor core is configured to receive first serial port data from the firmware storage circuit, and provide the first serial port data and second serial port data generated by the first processor core itself to the first peripheral circuit; the first peripheral circuit is configured to independently receive and store the first serial port data and the second serial port data; the second processor core is configured to read the first serial port data and the second serial port data from the first peripheral circuit and provide them to the second peripheral circuit; the second peripheral circuit is configured to convert the first serial port data and the second serial port data into a predetermined protocol format and output them through the general data interface; wherein, the first peripheral circuit comprises: a first interface circuit configured to receive the first serial port data; a second interface circuit configured to receive the second serial port data; a first cache configured to cache the first serial port data; a second cache configured to cache the second serial port data.

2. The electronic device of claim 1, wherein, The first interface circuit, the second interface circuit, the first cache and the second cache are connected with the first processor core and the second processor core through a bus; the first processor core is configured to provide the first serial port data and the second serial port data to the first interface circuit and the second interface circuit respectively; the second processor core is configured to read the first serial port data from the first interface circuit and write it into the first cache, read the second serial port data from the second interface circuit and write it into the second cache, and provide the first serial port data in the first cache and the second serial port data in the second cache to the second peripheral circuit.

3. The electronic device of claim 2, wherein the first interface circuit is further configured to provide a first interrupt signal to the second processor core in response to receiving the first serial port data, the second interface circuit is further configured to provide a second interrupt signal to the second processor core in response to receiving the second serial port data; the second processor core is configured to read the first serial port data from the first interface circuit and store it into the first cache in response to the first interrupt signal, and read the second serial port data from the second interface circuit and store it into the second cache in response to the second interrupt signal.

4. The electronic device of claim 2, wherein, The second processor core is further configured to, in response to the general data interface being connected with a debugging device outside the electronic device, receive an enumeration request from the debugging device through the general data interface, and provide description information of the first interface circuit and the second interface circuit to the debugging device according to the enumeration request, the description information being used for the debugging device to generate a first virtual serial port device for the first interface circuit and a second virtual serial port device for the second interface circuit.

5. The electronic device of claim 2, wherein the first processor core is further configured to initialize the first interface circuit and the second interface circuit in response to the electronic device being powered on; the second processor core is further configured to initialize the first cache, the second cache and the second peripheral circuit in response to the electronic device being powered on.

6. The electronic device of claim 2, wherein, At least one of the first interface circuit and the second interface circuit is a universal asynchronous receiver-transmitter interface.

7. The electronic device of claim 1, wherein, The first processor core is further configured to, in response to receiving the configuration instruction from the user, provide the configuration instruction to the second processor core; The second processor core is further configured to modify configuration information of at least one of the first peripheral circuit and the second peripheral circuit according to the configuration instruction.

8. The electronic device of claim 1, wherein, The first processor core is further connected with the second processor core, and the first processor core is further configured to listen to a state signal of the second processor core and determine whether the second processor core has failed according to the state signal.

9. The electronic device of claim 8, wherein, The electronic device further comprises a switching controller and a physical serial port connected with the switching controller, The first processor core is further configured to, in response to the second processor core failing, switch to a backup mode, wherein in the backup mode, the first processor core is configured to receive first serial port data from the firmware storage circuit and generate second serial port data, and in response to receiving a switching instruction provided by the user, provide the first serial port data, the second serial port data and a switching signal to the switching controller according to the switching instruction; The switching controller is configured to output one of the received first serial port data and the second serial port data through the physical serial port according to the switching signal provided by the first processor core.

10. The electronic device of claim 1, wherein, The universal data interface comprises a universal serial bus interface, and the predetermined protocol format comprises a universal serial bus interface format.

11. The electronic device of any of claims 1-10, wherein, The first processor core comprises a baseboard management controller processor core, the second processor core comprises a microprocessor core, the firmware storage circuit comprises a basic input / output system, and the first processor core and the second processor core are connected with the first peripheral circuit and the second peripheral circuit through an advanced high-performance bus.

12. A data transmission system, characterized by The data transmission system comprises: The electronic device according to any one of claims 1 to 11; The debugging device comprises a universal data interface matched with the universal data interface of the electronic device, and the universal data interface of the debugging device and the universal data interface of the electronic device are connected with each other; The universal data interface of the debugging device and the universal data interface of the electronic device are both universal serial bus interfaces, and the universal data transmission line is a universal serial bus transmission line.

13. The data transmission system of claim 12, wherein, 14. The data transmission system according to claim 12, wherein The data transmission system further comprises a data converter, and the electronic device further comprises a switching control circuit and a physical serial port connected with the switching control circuit, wherein the physical serial port is connected to an input end of the data converter; The universal data interface of the debugging device comprises a first universal data interface and a second universal data interface, wherein the first universal data interface is connected with the universal data interface of the electronic device, and the second universal data interface is connected with an output end of the data converter.

15. The data transmission system according to claim 14, wherein The data converter comprises a universal serial bus to serial port line.

16. The data transmission system according to claim 12, wherein ​ The second processor core is further configured to receive an enumeration request from the debugging device through the general data interface of the electronic device, and provide description information of the first interface circuit and the second interface circuit to the debugging device according to the enumeration request, The debugging device is further configured to generate a first virtual serial port device for the first interface circuit and a second virtual serial port device for the second interface circuit according to the description information provided by the second processor core, receive first serial port data from the electronic device based on the first virtual serial port device, and receive second serial port data from the electronic device based on the second serial port device.

17. A data transmission method, performed by the electronic device of any one of claims 1 to 11, characterized in that, The data transmission method comprises: The first processor core in the management controller receives first serial port data from the firmware storage circuit, generates second serial port data, and provides the first serial port data and the second serial port data to the first peripheral circuit; The first peripheral circuit independently receives and stores the first serial port data and the second serial port data; The second processor core reads the first serial port data and the second serial port data from the first peripheral circuit and provides them to the second peripheral circuit; The second peripheral circuit converts the first serial port data and the second serial port data into a predetermined protocol format and outputs them through the general data interface.

18. The data transmission method of claim 17, wherein, The data transmission method further comprises: The second processor core receives an enumeration request from the debugging device through the general data interface in response to the connection of the general data interface with the debugging device outside the electronic device, and provides description information of the first interface circuit and the second interface circuit to the debugging device according to the enumeration request, the description information being used for the debugging device to generate a first virtual serial port device for the first interface circuit and a second virtual serial port device for the second interface circuit.

19. The data transmission method of claim 17, wherein, The data transmission method further comprises: The first processor core provides a configuration instruction to the second processor core in response to receiving the configuration instruction from the user; The second processor core modifies configuration information of at least one of the first peripheral circuit and the second peripheral circuit according to the configuration instruction.

20. The data transmission method of claim 17, wherein, The data transmission method further comprises that the first processor core listens to a state signal of the second processor core, judges whether the second processor core has failed according to the state signal, and switches to a backup mode in response to the failure of the second processor core; In the backup mode, the first processor core receives the first serial port data from the firmware storage circuit and generates the second serial port data, and provides the first serial port data, the second serial port data and a switching signal to the switching controller according to a switching instruction provided by the user in response to receiving the switching instruction; the switching controller outputs one of the received first serial port data and second serial port data through the physical serial port according to the switching signal provided by the first processor core.

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