Power distribution control method for upper and lower capacitors of T-type three-level rectifier

Abstract

The invention belongs to the technical field of electronic power, and particularly relates to an upper and lower capacitor power distribution control method of a T-type three-level rectifier, which comprises the following steps of: sampling voltage and current of a grid side and a direct current side, generating d-axis current instructions of upper and lower capacitors, synthesizing a total instruction value, and further determining initial three-phase modulation voltage; injecting a first zero-sequence voltage component into the initial voltage to carry out initial correction, and judging whether a power distribution limit is reached or not; and if so, carrying out secondary adjustment on the zero level duty ratio of the voltage intermediate phase to expand the distribution range. And finally, injecting a second zero-sequence voltage component used for suppressing voltage fluctuation into the voltage to be modulated, generating a final modulation voltage and generating a PWM driving signal. Through two-stage zero-sequence voltage injection and secondary adjustment of the duty ratio of the intermediate phase, wide-range and high-precision independent distribution of the power of the upper capacitor and the lower capacitor is effectively realized, meanwhile, the voltage fluctuation of the direct-current side capacitor is remarkably inhibited, and the stability and the electric energy quality under the asymmetric working condition are improved.

Description

Technical Field

[0001] This invention belongs to the field of electronic power technology, specifically relating to a method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier. Background Technology

[0002] Neutral-point clamped three-level rectifiers (NPC-TLRs) are widely used in aviation, high-voltage frequency conversion, power quality management, and electric vehicles due to their advantages such as bidirectional energy flow, excellent AC-side harmonic performance, and wide DC-side voltage output range. Especially in high-energy-consuming mobile applications such as electric vehicles, to adapt to charging facilities and battery pack platforms of different voltage levels, NPC-TLRs need to have independent control capabilities for the voltage and power of the upper and lower DC-side capacitors to simultaneously supply power to loads of different voltage levels and maintain grid-side current quality. Currently, the modulation strategies of NPC-TLRs mainly include two types: carrier pulse width modulation (CBPWM) and space vector pulse width modulation (SVPWM), with CBPWM being more favored in engineering due to its ease of implementation. However, how to achieve independent and stable control of the DC-side voltage using CBPWM when the DC-side capacitor voltage is asymmetrical remains a challenge in current technology.

[0003] Existing research has made some progress in voltage control under DC-side asymmetric conditions. Some existing technologies indirectly achieve independent voltage regulation by controlling the midpoint current through zero-sequence voltage injection (ZSVI), but this requires an additional DC current sensor, increasing system cost and complexity. Other studies simplify modulation voltage calculation based on the volt-second balance principle to suppress even-order harmonics caused by DC-side imbalance, or employ discontinuous modulation strategies to improve system performance. However, most of these methods do not fully consider the DC voltage fluctuation problem caused by uneven power distribution, or do not further extend the power distribution capability at the modulation level in power decoupling control, resulting in shortcomings such as insufficient regulation accuracy and limited dynamic response in practical applications.

[0004] DC-side capacitor voltage fluctuations not only degrade the power quality of both AC and DC sides, affecting the stability of the battery's constant voltage or trickle charging process, but may also threaten the long-term reliability of the capacitor and load. Although existing literature has proposed virtual vector modulation or hybrid zero-sequence voltage injection methods to address voltage asymmetry and suppress fluctuations, these strategies either lose the ability to actively regulate the midpoint potential or fail to accurately respond to instantaneous changes in load power, resulting in inaccurate zero-sequence voltage calculations and limited suppression effects. Therefore, there is an urgent need for a control method that can flexibly distribute the power of the upper and lower capacitors while effectively suppressing voltage fluctuations under a wide range of operating conditions. Summary of the Invention

[0005] The purpose of this invention is to provide a power distribution control method for the upper and lower capacitors of a T-type three-level rectifier, so as to solve the technical problem that it is difficult to achieve flexible power distribution over a wide range and effectively suppress capacitor voltage fluctuations when the upper and lower capacitor voltages of the T-type three-level rectifier are asymmetrical on the DC side.

[0006] The present invention achieves the above objectives through the following technical solutions: This invention proposes a method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier, comprising the following steps: Acquire sampled values ​​of grid-side voltage, grid-side current, DC-side upper capacitor voltage, and lower capacitor voltage; The d-axis current command values ​​corresponding to the upper and lower capacitors are generated based on the deviation between the given values ​​of the upper and lower capacitor voltages and their sampled values, and the sum of the two is used as the total d-axis current command value. The initial three-phase modulation voltage is determined based on the total d-axis current command value and the set q-axis current command value; A first zero-sequence voltage component is injected into the initial three-phase modulation voltage to obtain a first-corrected modulation voltage; Determine whether the modulated voltage after the first correction meets the preset power distribution limit condition. If so, adjust the zero-level duty cycle of the voltage intermediate phase a second time to generate the voltage to be modulated. Otherwise, use the modulated voltage after the first correction as the voltage to be modulated. A second zero-sequence voltage component is injected into the voltage to be modulated to generate the final modulated voltage; A PWM drive signal is generated based on the final modulation voltage to drive the switching device.

[0007] Furthermore, determining the initial three-phase modulation voltage based on the total d-axis current command value and the set q-axis current command value includes: Based on the current phase angle and angular frequency of the grid voltage phase-locked loop output, predict the grid voltage phase angle for the next control cycle and calculate the corresponding grid voltage value for the next control cycle. The total d-axis current command value, the set q-axis current command value, and the predicted phase angle are input to the current controller to obtain the predicted grid-side current value for the next control cycle. The predicted grid-side current value and the grid voltage value of the next control cycle are input into the deadbeat controller to calculate the uncorrected predicted three-phase modulation voltage value, which is used as the initial three-phase modulation voltage.

[0008] Furthermore, the injection range of the first zero-sequence voltage component is: ; in, This is the first zero-sequence voltage component. upper limit and lower limit They are respectively: ; in, This is a sampled value of the capacitor voltage on the DC side. This is a sampled value of the capacitor voltage on the DC side. This represents the peak value of the phase voltage of the bridge arm.

[0009] Furthermore, the first-corrected modulation voltage includes the following formula: ; Among them, u max u mid and u min These are the maximum phase modulation voltage, the intermediate phase modulation voltage, and the minimum phase modulation voltage, u. max_Z1 u mid_Z1 u min_Z1 These are the maximum phase modulation voltage, intermediate phase modulation voltage, and minimum phase modulation voltage after one correction, respectively.

[0010] Furthermore, the preset power allocation limit condition is: the polarity of the modulation voltage after the first correction is all positive and the power demand of the lower capacitor is greater than zero, or the polarity is all negative and the power demand of the upper capacitor is greater than zero. If the deviation between the given value of the lower capacitor voltage and its sampled value is adjusted by the PI controller and the output value of the lower capacitor d-axis current command is greater than zero, then it is determined that the power demand of the lower capacitor is greater than zero. When the deviation between the given value of the upper capacitor voltage and its sampled value is adjusted by the PI controller and the output value of the upper capacitor d-axis current command is greater than zero, it is determined that the power demand of the upper capacitor is greater than zero.

[0011] Furthermore, the secondary adjustment of the zero-level duty cycle of the intermediate voltage phase to generate the voltage to be modulated includes: Based on the set duty cycle allocation coefficient k D The zero-level duty cycle of the corrected intermediate phase voltage is redistributed. ; Based on the redistributed duty cycle relationship, the intermediate phase modulation voltage u in the first-corrected modulation voltage is... mid_Z1 Decomposition will generate the upmodulated wave component u. max_Z1_up u mid_Z1_up u min_Z1_up and downmodulated wave component u max_Z1_low u mid_Z1_ low u min_Z1_low It satisfies the following formula: ; The maximum phase modulation voltage u in the first corrected modulation voltage max_Z1 With minimum phase modulation voltage u min_Z1 These are respectively their own upper and lower modulation waves, and u is obtained from the decomposition of the voltage intermediate phase. mid_Z1_up and u mid_Z1_ low The final three-phase upper modulation wave set and three-phase lower modulation wave set are formed as the voltage to be modulated.

[0012] Furthermore, the allocation coefficient k based on the set duty cycle... D The zero-level duty cycle of the corrected intermediate phase voltage is redistributed. The redistributed duty cycle relationship is obtained as follows: ; Where, d mid1_Z1’ d mid0_Z1’ d mid-1_Z1’ These represent the duty cycles of the positive, zero, and negative voltage levels after secondary adjustment of the intermediate phase voltage.

[0013] Furthermore, the second zero-sequence voltage component Determined based on the polarity of the current voltage to be modulated, including: When the voltage to be modulated satisfies the condition that the maximum phase and intermediate phase are greater than zero and the minimum phase is less than zero, the second zero-sequence voltage component... for : ; When the voltage to be modulated satisfies the condition that the maximum phase is greater than zero and the intermediate and minimum phases are less than zero, the second zero-sequence voltage component... for : ; in, The power setpoint for the lower capacitor. The power setpoint for the upper capacitor. , and , These represent the voltage and corresponding current of the maximum and minimum phases in the current modulation voltage.

[0014] Furthermore, the second zero-sequence voltage component The determination based on the polarity of the current voltage to be modulated also includes: when the maximum phase, intermediate phase, and minimum phase of the voltage to be modulated are all positive or all negative, the second zero-sequence voltage component... It is zero.

[0015] Furthermore, the method also includes: Real-time acquisition of the current upper capacitor power allocation coefficient k up With lower capacitor power distribution coefficient k low ; Determine k up Whether it is within the first constraint range, k low Whether it is within the second constraint range, where: The first constraint range is as follows: ; The second constraint range is as follows: ; in, I is the phase angle where the bridge arm voltage lags the current. m This represents the peak value of the phase current. If k up Deviating from the first constraint range and k low If the deviation from the second constraint range occurs, an optimization instruction is generated; The optimization instruction is used to correct the upper capacitor voltage setpoint and / or the lower capacitor voltage setpoint, so that k up With k low The value of is adjusted to the corresponding constraint range to realize the second zero-sequence voltage component. It operates in non-limited mode.

[0016] The beneficial effects of this invention are as follows: The control method proposed in this invention achieves active decoupling and preliminary allocation of the average power of the upper and lower capacitors by injecting a first zero-sequence voltage component, overcoming the deficiency of insufficient allocation capability under asymmetrical operating conditions in traditional methods. When zero-sequence voltage regulation alone reaches its limit, a mechanism for secondary adjustment of the duty cycle of the zero-level phase of the voltage intermediate phase is proposed. This further expands the limit range of power allocation without affecting the basic modulation of the system, enhancing the system's adaptability to a wide range of load changes. Furthermore, by injecting a second zero-sequence voltage component and using instantaneous power constancy as the control objective, the method can directly and effectively suppress DC-side capacitor voltage fluctuations caused by power imbalance, improving output voltage quality and system stability. Ultimately, this method achieves independent and precise control of dual-load power and effective suppression of DC-side voltage fluctuations without the need for additional hardware sensors, demonstrating significant engineering application value. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier proposed in this invention. Figure 2 This is a topology diagram of the dual-load T-type three-level rectifier in this invention; Figure 3This is a control block diagram of the dual-load T-type three-level rectifier in this invention; Figure 4 This is a schematic diagram of the modulation voltage integration range after injecting zero-sequence voltages of different polarities in this invention; Figure 5 This is a schematic diagram of the dual-load T-type three-level rectifier test platform in the experimental case of a specific embodiment of the present invention; Figure 6 In the experimental case of the specific implementation of this invention, only u is injected. Z1 A schematic diagram of the capacitor voltage fluctuation suppression waveform; Figure 7 This is a schematic diagram showing that, in an experimental case of a specific embodiment of the present invention, when ZSVI is used, the average power ratio of the dual loads exceeds the ZSVI power allocation limit. Figure 8 This is a schematic diagram showing that, in the experimental case of a specific embodiment of the present invention, when ZSVI is used, the average power ratio of the dual loads is lower than the power allocation limit. Figure 9 In the experimental case of a specific embodiment of the present invention, when ZSVI+SCDA is used and the duty cycle of the intermediate phase of the voltage is adjusted to 0.3, the average power ratio of the dual load is higher than the ZSVI allocation limit diagram. Figure 10 This is a comparison of experimental waveforms of the control method of the present invention under two different steady-state conditions in a specific embodiment of the present invention test case. in, Figure 10 In the diagram, (a) represents the steady-state waveform when operating condition I uses ZSVI; Figure 10 (b) in the figure represents the steady-state waveform when operating condition I uses ZSVI+SDCA; Figure 10 (c) in the figure represents the steady-state waveform when ZSVI is used in operating condition II; Figure 10 In the figure, (d) represents the steady-state waveform when operating condition II uses ZSVI+SDCA; Figure 11 This is a waveform diagram of the control method of the present invention in a dynamic experiment of load change in a specific embodiment of the present invention. in, Figure 11 (a) in the figure represents the dynamic waveform when the load R2 suddenly increases from 20Ω to 30Ω under the condition that the total DC voltage is 600V; Figure 11 (b) in the figure represents the dynamic waveform when R2 suddenly decreases from 30Ω to 20Ω under the condition of a total DC voltage of 600V; Figure 11 (c) in the figure represents the dynamic waveform when R2 suddenly increases from 20Ω to 70Ω under the condition that the total DC voltage is 800V; Figure 11In the figure, (d) represents the dynamic waveform when R2 suddenly decreases from 70Ω to 20Ω under the condition that the total DC voltage is 800V. Detailed Implementation

[0018] The present application will now be described in further detail with reference to the accompanying drawings. It should be noted that the following specific embodiments are only used to further illustrate the present application and should not be construed as limiting the scope of protection of the present application. Those skilled in the art can make some non-essential improvements and adjustments to the present application based on the above application content.

[0019] Example 1 This application proposes a power distribution control method for the upper and lower capacitors of a T-type three-level rectifier. First, based on carrier-based pulse width modulation (CBPWM), the coupling relationship between zero-sequence voltage injection (ZSVI) and the power distribution of the upper and lower capacitors on the DC side in a dual-load T-type three-level rectifier is analyzed, clarifying the limits of ZSVI in power distribution. Based on this, secondary power distribution is achieved by introducing secondary duty cycle adjustment (SDCA). Second, the limiting cases of the average power distribution ratio of the upper and lower capacitors on the DC side under different modulation indices are analyzed. The zero-sequence voltage is determined with the goal of maintaining constant instantaneous power, thereby effectively suppressing capacitor voltage fluctuations.

[0020] Please see Figure 1 and Figure 3 A specific embodiment of this invention proposes a method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier. Please refer to [link to relevant documentation]. Figure 2 The topology of the T-type three-level rectifier shown includes an AC grid side and a DC side. Wherein, e X (X=A, B, C) is the grid voltage, L G For the grid-side filter inductor, L I For the bridge arm side inductance, C F For the filter capacitor, u X i is the phase voltage of the rectifier bridge arm. X For grid-side current, i p For the current flowing into the positive bus (Bus+), i o i is the current flowing into the DC side midpoint (point O). n The current flowing into the negative bus (Bus-) is defined as flowing from the AC side to the DC side in the positive direction. The T-type three-level rectifier uses an LCL filter, and each phase arm consists of S... X1 ~S X4It consists of four IGBT switching devices; C1 and C2 are the upper and lower DC-side capacitors, respectively, and the corresponding upper and lower DC-side voltages are respectively and The upper and lower DC-side loads are R1 and R2, respectively. Let u be the voltage between the entire DC positive and negative buses Bus+ and Bus-. dc = + The grid-side three-phase input power is P in The upper and lower DC output powers are P respectively. up P low .

[0021] In steady state, the three-phase bridge arm phase voltages and grid-side currents are expressed as follows: ; Where ωt is the phase angle of the voltage of phase A bridge arm, U m I represents the peak value of the bridge arm phase voltage. m φ is the peak value of the phase current, and φ is the phase angle of the bridge arm voltage lagging the current. When X=A, k=0, when X=B, k=1, and when X=C, k=2.

[0022] The core control mechanism of this invention lies in carrier pulse width modulation (CBPWM). Two modulation intensities are defined: when the modulation voltage amplitude is greater than or equal to 0, upper capacitor modulation is used, i.e., the modulation voltage and amplitude are both u. C1 The upper carrier phase is compared to generate a modulation pulse, and the modulation degree is defined as m. up When the modulation voltage amplitude is less than 0, lower capacitor modulation is used, that is, the modulation voltage and amplitude are... The downloaded wave is compared to generate a modulation pulse, and the modulation degree is defined as m. low Among them, m up m low The expression is: ; To facilitate subsequent zero-sequence voltage injection and power distribution analysis, the three-phase modulation voltages need to be sorted according to their instantaneous amplitudes within each control cycle, denoted as: ; Among them, u max u mid and u min These represent the maximum phase modulation voltage, the intermediate phase modulation voltage, and the minimum phase modulation voltage, respectively, and the corresponding grid-side currents are labeled as i. max i mid i min .

[0023] Based on the above system modeling and analysis, the control method proposed in this invention mainly includes the following steps, the flowchart of which can be found here. Figure 1and Figure 3 : S1. Signal Sampling and Acquisition: Real-time acquisition of grid-side three-phase voltage (e A , e B , e C ), grid-side three-phase current (i A i B i C Sampled values ​​of DC-side upper and lower capacitor voltages and .

[0024] S2. Current command generation: Generate d-axis current command values ​​for the upper and lower capacitors based on the deviation between the given values ​​of the upper and lower capacitor voltages and their sampled values, and sum the two as the total d-axis current command value.

[0025] S3. Initial Modulation Voltage Calculation: The initial three-phase modulation voltage is determined based on the total d-axis current command value and the set q-axis current command value. Specifically, based on the current phase angle and angular frequency output by the grid voltage phase-locked loop, the grid voltage phase angle for the next control cycle is predicted, and the corresponding grid voltage value for the next control cycle is calculated. The total d-axis current command value, the set q-axis current command value, and the predicted phase angle are input to the current controller to obtain the grid-side current prediction value for the next control cycle. The grid-side current prediction value and the grid voltage value for the next control cycle are input to the deadbeat controller to calculate the uncorrected three-phase modulation voltage prediction value, which is used as the initial three-phase modulation voltage.

[0026] S4. First Correction (Power Decoupling): Inject the first zero-sequence voltage component into the initial three-phase modulation voltage. This yields the modulated voltage after a correction. S5. Secondary Adjustment (Expanding Distribution Range): Determine whether the modulated voltage after the first correction meets the preset power distribution limit conditions (e.g., all voltage polarities are positive and the lower capacitor has power demand, or all polarities are negative and the upper capacitor has power demand). If it does (meets the limit), it indicates that the power distribution limit has been approached or reached by zero-sequence voltage injection alone. In this case, the zero-level duty cycle of the intermediate phase of the voltage needs to be adjusted a second time. The zero-level duty cycle of the intermediate phase is then adjusted a second time to generate the voltage to be modulated. This step further expands the power distribution capability by changing the energy flow time of the intermediate phase between the upper and lower capacitors. Otherwise (does not meet the limit), the modulated voltage after the first correction is used as the voltage to be modulated. S6. Voltage fluctuation suppression: Inject a second zero-sequence voltage component into the voltage to be modulated. This generates the final modulation voltage; S7. PWM Generation and Driving: Based on the final modulation voltage, a PWM driving signal is generated to control the on / off state of each IGBT switching device in the T-type three-level rectifier, thus completing closed-loop control.

[0027] The control block diagram of the T-type three-level rectifier is as follows: Figure 3 As shown, (1) the grid voltage sample value e is obtained through the sampling circuit. A(n-1) e B(n-1) e C(n-1) AC current sampling value i A(n-1) i B(n-1) i C(n-1) DC side upper and lower capacitor voltage sampling value u C1 u C2 ;e A(n-1) e B(n-1) e C(n-1) The grid voltage e in the αβ coordinate system is obtained after the abc-αβ coordinate transformation. α(n-1) e β(n-1) Alternating current i α(n-1) i β(n-1) The value e after two control cycles is obtained through a phase-locked loop (PLL) and grid voltage prediction. α(n+1) e β(n+1) and the power grid phase angle θ (n-1) (2) Setpoint values ​​of upper and lower DC side capacitor voltages and sampled value u C1 u C2 The d-axis current command value of the upper capacitor is obtained by taking the difference and outputting it through the PI regulator. d-axis current command value of the upper capacitor The sum of the two is the total command current along the d-axis. Relative to the grid voltage e in the dq coordinate system d e q Multiply to obtain the power command values ​​of the upper and lower capacitors. Then according to Generate zero-sequence voltage u Z1 (3) Total command current of the d-axis Shaft total command current and θ (n+1) Together, they are fed into the current controller to obtain the predicted grid-side current i. α(n+1) i β(n+1) Next, i α(n+1) i β(n+1) i α(n-1) i β(n-1) e α(n+1) e β(n+1) The uncorrected three-phase modulated voltage prediction value u is obtained after being fed into the deadbeat control (DBC) controller. X1(n+1) (X=A, B, C), change u X1(n+1) with u Z1 The summation yields the updated predicted three-phase modulation voltage value u.X2(n+1) (X=A,B,C). Then, the obtained parameters are fed into the capacitor voltage fluctuation controller to obtain the second zero-sequence component u. Z2 u Z2 with u X2(n+1) The summation yields the final modulation voltage u. X(n+1) (X=A,B,C). Finally, determine if the power allocation exceeds the ZSVI range. If it does, use the SDCA algorithm to extend the range and adjust u. X(n+1) Decompose into u X(n+1)_up u X(n+1)_low (X=A,B,C), the three-phase PWM switching signal S is obtained by comparing it with a dual-carrier modulation method. X (X=A,B,C) and act on the three-phase IGBT to form a closed loop.

[0028] Understandably, the control method of this invention can be applied to power conversion systems based on a T-type three-level neutral-point clamp (NPC) rectifier topology. In this system, the AC side is connected to a three-phase power grid via an LCL filter, and the DC side consists of upper and lower capacitors (C1, C2) connected in series, with their midpoint connected to the midpoint of the rectifier bridge arm, supplying power to two independent loads (R1, R2) connected to the positive-neutral and neutral-negative busbars, respectively. By sampling the grid-side voltage and current and the DC-side capacitor voltage in real time, an initial modulation wave is generated based on prediction and deadbeat control. Then, by injecting a first zero-sequence voltage component, the initial power distribution and decoupling of the upper and lower capacitors is achieved. When the regulation capability reaches its limit, a secondary adjustment of the duty cycle of the zero-level voltage of the intermediate phase is initiated to expand the distribution range. Finally, by injecting a second zero-sequence voltage component to control the instantaneous power, fluctuations in the DC-side capacitor voltage are effectively suppressed, ultimately generating a PWM drive signal to control the IGBT switching devices, enabling the system to operate under asymmetrical load conditions.

[0029] In one specific implementation, a first zero-sequence voltage component u is injected into the initial three-phase modulation voltage. Z1 Its core function is to achieve the initial distribution and decoupling of the average power of the upper and lower capacitors. The modulated voltage after the first correction includes the following formula: ; Among them, u max u mid and u min These are the maximum phase modulation voltage, the intermediate phase modulation voltage, and the minimum phase modulation voltage, u. max_Z1 u mid_Z1 u min_Z1 These are the maximum phase modulation voltage, intermediate phase modulation voltage, and minimum phase modulation voltage after one correction, respectively.

[0030] It should be noted that the core of this invention lies in achieving autonomous power allocation between the upper and lower capacitors on the DC side through precise control of the modulation wave. This function is mainly achieved by injecting the first zero-sequence voltage component u. Z1 This is achieved by extending the voltage regulation capability to its limit through secondary adjustment of the zero-level duty cycle of the intermediate phase. Its physical essence is controlling the flow path and time of currents in different phases within the upper and lower capacitors. To clearly analyze this process, based on the injected u... Z1 The subsequent correction of the modulation voltage polarity combination divides the system's operating state into four typical operating conditions (CASE): Based on the relationship of the modulation voltage after one correction, the following four operating conditions can be distinguished: (Working Condition 1) CASE1: u max_Z1 >u mid_Z1 >u min_Z1 >0; (Case 2) u max_Z1 >u mid_Z1 >0>u min_Z1 ; (Case 3) u max_Z1 >0>u mid_Z1 >u min_Z1 ; (Case 4) 0>u max_Z1 >u mid_Z1 >u min_Z1 .

[0031] It is understood that this invention mainly defines four operating conditions: CASE 1: Refers to the condition where, after correction, all three-phase modulated voltages are greater than zero (all positive).

[0032] CASE 2: Refers to the operating condition in a three-phase modulated voltage where two phases are greater than zero and one phase is less than zero.

[0033] CASE 3: Refers to the condition in a three-phase modulated voltage where one phase is greater than zero and two phases are less than zero.

[0034] CASE 4: Refers to the condition where, after correction, all three-phase modulated voltage values ​​are less than zero (all negative). Under different operating conditions, the power exchange paths between the upper and lower capacitors and the AC side are drastically different. Taking CASE2 as an example, in this state, the modulation voltages of the maximum and middle phases are positive, and their switching actions mainly involve energy exchange between the upper capacitor and the midpoint; while the modulation voltage of the minimum phase is negative, and its switching actions mainly involve energy exchange between the lower capacitor and the midpoint. Therefore, within one switching cycle, the instantaneous power of the upper and lower capacitors can be approximately expressed as: ; Similarly, for CASE1, CASE3, and CASE4, the exchange power of the upper and lower capacitors are respectively: ; This shows that through injection Changing the instantaneous value and polarity of the three-phase modulation voltage essentially changes P. up and P low The composition and weights of each term in the calculation formula are used to adjust the power distribution ratio between the upper and lower capacitors. The first zero-sequence voltage component u... Z1 The given value is determined by the output of the outer loop controller of the upper and lower capacitor voltages.

[0035] In this application, the power allocation principle based on the first zero-sequence voltage is as follows: By injecting the first zero-sequence voltage component This allows for the systematic adjustment of the power distribution between the upper and lower capacitors on the DC side. The principle behind this is that... The injection will shift the reference of the three-phase modulation voltage as a whole, thereby changing the time ratio of energy exchange between different phase bridge arms and the upper and lower capacitors.

[0036] Under steady-state conditions, the injected frequency within one fundamental frequency cycle can be... Consider its average value u Z1_ave This DC offset directly alters the distribution of the modulation voltage relative to zero, thus determining the average duration and extent of energy exchange between the upper and lower capacitors within one cycle. To quantify this effect, a voltage coefficient is defined. for: ; Through the Figure 4 Integral analysis of modulation voltage ranges of different polarities can establish... Average power P of upper and lower capacitors up _ avg and P_ low _ avg The mathematical relationship between them, injected into u Z1 The modulated voltage u after X _ Z1 >0(u X_Z1 =u X +u Z1 P_ of X=A,B,C) up _ avg The integration interval is [-arcsink Z1 ,π+arcsink Z1 ], u X _ Z1 P_ <0 low _ avgThe integration interval is [π + arcsink] Z1 ,2π-arcsink Z1 ]; thereby clarifying Its regulatory effect on the average power distribution ratio.

[0037] To avoid waveform distortion caused by overmodulation, the first zero-sequence voltage component The injection range is: ; in, upper limit and lower limit The values ​​are determined by the DC-side capacitor voltage and the peak value of the modulation wave, respectively: ; in, This is a sampled value of the capacitor voltage on the DC side. This is a sampled value of the capacitor voltage on the DC side. This represents the peak value of the phase voltage of the bridge arm.

[0038] injection Then, the three-phase voltages are sorted to obtain the maximum, intermediate, and minimum phase modulation voltages after one correction, denoted as u. max_Z1 u mid_Z1 u min_Z1 .

[0039] In one implementation, the preset power allocation limit condition of the present invention is directly related to the specific operating condition (CASE) of the modulated voltage after a first correction and its power requirements. This condition is specifically defined as: Condition 1: When the modulated voltage after one correction is in operating condition 1 (CASE 1), that is, when all polarities are positive, if the power demand of the lower capacitor is greater than zero at this time, it is determined that the allocation limit has been reached.

[0040] Condition 2: When the modulated voltage after one correction is in condition 4 (CASE 4), that is, all polarities are negative, if the power demand of the upper capacitor is greater than zero at this time, it is determined that the allocation limit has been reached.

[0041] The power requirements of the upper and lower capacitors are determined by the output of their outer loop controller. The criterion for a positive zero power demand from the lower capacitor is: the deviation between the given lower capacitor voltage and its sampled value, after adjustment by the PI controller, results in a lower capacitor d-axis current command value that is greater than zero. This indicates that the lower capacitor voltage is too low and power needs to be drawn from the AC side to boost the voltage.

[0042] The criterion for a positive zero power demand from the upper capacitor is: the deviation between the upper capacitor voltage setpoint and its sampled value, after adjustment by the PI controller, results in an upper capacitor d-axis current command value that is greater than zero. This indicates that the upper capacitor voltage is too low and power needs to be drawn from the AC side.

[0043] Understandably, the physical meaning of the above limiting conditions is that, under operating condition 1 (all positive), the current in all phases can theoretically only return through the switching transistors associated with the upper capacitor, and its natural characteristic is to transfer power to the upper capacitor. If, under this state, the system requires the lower capacitor to supplement power, it indicates that power can only be transferred through the upper capacitor. The shifting modulation wave can no longer change the basic energy flow direction; the system has reached the distribution limit of the current modulation mode. Similarly, under operating condition 4 (all negative), its natural characteristic is to supply power to the downward capacitor. If power is required to be supplied to the upward capacitor at this time, it also indicates... The regulatory capacity has reached saturation. Therefore, when any of the above limiting conditions are met, it indicates that relying solely on injection... This is no longer sufficient to meet the current conflicting power allocation requirements. At this point, it is necessary to initiate a secondary adjustment of the zero-level duty cycle of the intermediate voltage phase in step S5, thereby changing the assignment of the zero-level state in the switching sequence to break the current imbalance. This addresses the limitations of regulation, thus opening up new pathways for power distribution. If the above limiting conditions are not met, the system remains in a state of flux. Within the adjustable range, the modulated voltage after one correction is directly used as the voltage to be modulated and sent to the subsequent stage.

[0044] In one implementation, the zero-level duty cycle of the intermediate phase of the voltage is adjusted a second time to generate the voltage to be modulated, including: Based on the set duty cycle allocation coefficient k D The zero-level duty cycle of the corrected intermediate phase voltage is redistributed. The redistributed duty cycle relationship is obtained as follows: ; in, These represent the duty cycles of the positive, zero, and negative voltage levels after secondary adjustment of the intermediate phase voltage.

[0045] Based on the redistributed duty cycle relationship, the intermediate phase modulation voltage u in the first-corrected modulation voltage... mid_Z1 Decomposition will generate the upmodulated wave component u. max_Z1_up u mid_Z1_up u min_Z1_up and downmodulated wave component u max_Z1_low u mid_Z1_ low u min_Z1_low It satisfies the following formula: ; Wherein, CASE1 / 2 indicates that when the system is in operating condition 1 or operating condition 2, the zero-level duty cycle formula after secondary adjustment of the corresponding intermediate voltage phase should be used; CASE3 / 4 indicates that when the system is in operating condition 3 or operating condition 4, the zero-level duty cycle formula after secondary adjustment of the corresponding intermediate voltage phase should be used; CASE2 / 3 indicates that when the system is in operating condition 2 or operating condition 3, the corresponding modulation wave decomposition formula should be used.

[0046] The maximum phase modulation voltage u in the first-corrected modulation voltage max_Z1 With minimum phase modulation voltage u min_Z1 These are respectively used as their own upper and lower modulation waves, and are related to u obtained by voltage intermediate phase decomposition. mid_Z1_up and u mid_Z1_ low This constitutes the final set of three-phase upmodulation waves. With three-phase downmodulated wave set , as the voltage to be modulated.

[0047] In one implementation, a second zero-sequence voltage component is injected. The aim is to suppress capacitor voltage fluctuations by controlling instantaneous power, the second zero-sequence voltage component. Determined based on the polarity of the current voltage to be modulated (CASE case above), including: When operating condition 2 is in: that is, when the voltage to be modulated satisfies the condition that the maximum phase and intermediate phase are greater than zero and the minimum phase is less than zero (corresponding to CASE2), the second zero-sequence voltage component... for : ; When in operating condition 3: that is, when the voltage to be modulated satisfies the condition that the maximum phase is greater than zero and the intermediate and minimum phases are less than zero (corresponding to CASE 3), the second zero-sequence voltage component for : ; in, The power setpoint for the lower capacitor (which can be determined by its average power setpoint or by its voltage loop output). The power setpoint for the upper capacitor. , and , These represent the voltage and corresponding current of the maximum and minimum phases in the current modulation voltage.

[0048] When operating under conditions 1 or 4: that is, when the maximum, intermediate, and minimum phases of the voltage to be modulated are all positive (CASE1) or all negative (CASE4), there is no direct instantaneous power exchange path between the upper and lower capacitors, and the second zero-sequence voltage component... It is zero.

[0049] In one implementation, the method further includes an optimization step to ensure the second zero-sequence voltage component Able to work effectively without being limited: Calculate and obtain the current upper capacitor power allocation coefficient k in real time. up With lower capacitor power distribution coefficient k low Determine k up Whether it is within the first constraint range, k low Whether it is within the second constraint range, where: The first constraint range is as follows: ; The second constraint range is as follows: ; in, I is the phase angle where the bridge arm voltage lags the current. m This represents the peak value of the phase current. If k up Deviating from the first constraint range and k low If the deviation from the second constraint range occurs, an optimization instruction is generated; The optimization instruction is used to correct the upper capacitor voltage setpoint and / or lower capacitor voltage setpoint, so that k up With k low The value of is adjusted to the corresponding constraint range, which ensures that the calculated is within the appropriate range. It remains within its effective injection range, thereby achieving continuous and stable suppression of capacitor voltage fluctuations and realizing the second zero-sequence voltage component. It operates in non-limited mode.

[0050] Based on the above embodiments, the present invention provides a method for controlling the power distribution of the upper and lower capacitors of a T-type three-level rectifier. Its core principle is to achieve flexible and precise power distribution of the upper and lower capacitors on the DC side and effective suppression of voltage fluctuations through multi-level modulation wave correction.

[0051] This method first injects a first zero-sequence voltage component to systematically adjust the DC bias of the three-phase modulation wave, thereby changing the average energy exchange time of the upper and lower capacitors within one fundamental frequency cycle and achieving initial power distribution. When When the regulation capability reaches its limit (i.e., the polarity of the modulation wave cannot meet the power demand direction), the method further initiates a second-stage control: a secondary adjustment of the zero-level duty cycle of the intermediate phase voltage. This operation, by redistributing the duration of the intermediate phase switching state on the upper and lower capacitors, expands the system's power distribution capability without affecting the average output voltage.

[0052] Based on the completed power allocation, the method introduces a second zero-sequence voltage component, which is calculated based on the current modulation wave polarity (operating condition) and the instantaneous power setpoints of the upper and lower capacitors. This is achieved by directly controlling the instantaneous power flowing to a specific capacitor. This method effectively suppresses DC-side capacitor voltage fluctuations caused by power imbalance. Furthermore, it includes an optimization step that monitors the power allocation factor and maintains it within theoretical constraints to ensure… It always operates in an unlimited state, ensuring the continuity and stability of the fluctuation suppression effect.

[0053] The main contribution of this method lies in combining zero-sequence voltage injection with intermediate phase duty cycle adjustment to construct a two-stage power distribution architecture. This not only broadens the range of power distribution but also solves the voltage fluctuation problem through instantaneous power control. This method relies solely on existing voltage and current sensors, requiring no additional hardware, and provides an efficient and reliable solution for T-type three-level rectifiers in applications with unbalanced loads or requiring independent dual-path power supply.

[0054] To more clearly illustrate the present invention and its advantages, the methods provided by the embodiments of the present invention will be further explained below in conjunction with specific examples and related drawings.

[0055] 1. Experimental parameters Table 1 Main parameters of the test platform ; To verify the effectiveness of the upper and lower capacitor power distribution control method for the T-type three-level rectifier proposed in this application, a dual-load T-type three-level rectifier test platform was constructed as follows: Figure 5 As shown in Table 1, the main parameters of the platform are as follows. Figures 6-10 middle, , This represents the peak-to-peak value of the DC-side upper and lower capacitor voltage fluctuations. , The sampled values ​​of the upper and lower capacitor voltages on the DC side, u AO The phase voltage u is the output voltage between the input port of phase A IGBT and the midpoint of the DC capacitor. AB i represents the line voltage output between the input ports of phase A and phase B IGBTs. A i B i C For three-phase current, u dc This is the total voltage on the DC side. , This represents the actual average power on the upper and lower DC sides. When ZSVI+SDCA is used in the experiment, the duty cycle allocation factor k... D Both are 0.3.

[0056] 2. Verification of DC-side voltage fluctuation suppression Injection only The waveform is as follows Figure 6 The interval is shown as 0-50ms. When... When R1=20Ω and R2=20Ω: only DC zero-sequence voltage is injected. After decoupling control, the voltages of the upper and lower capacitors track their respective setpoints correctly. However, the voltage fluctuation amplitude of the upper capacitor is approximately 19V, and that of the lower capacitor is approximately 18V. The overall DC-side voltage fluctuation amplitude is approximately 5.5V, and the three-phase current i... A i B i C The THD was measured to be approximately 1.99%; [injection] + The waveform for suppressing capacitor voltage fluctuations is as follows: Figure 6 As shown in the 50-100ms data, the voltage fluctuation of the upper and lower capacitors is approximately 4V while accurately tracking their respective given values. The voltage fluctuation of the entire DC side is approximately 2V, and the THD of the three-phase current is approximately 0.54% as measured.

[0057] Analysis shows that injection After suppressing capacitor voltage fluctuations, the voltage fluctuations of the upper and lower capacitors were reduced by approximately 78.9% and 77.8%, respectively. The voltage fluctuations of each capacitor were significantly suppressed, which is more conducive to the independent control of the upper and lower capacitor voltages and the power of the dual loads in the three-level rectifier. The degree of grid-side current distortion also decreased accordingly with the reduction of voltage fluctuation amplitude, which is consistent with the theoretical analysis.

[0058] 3. Power distribution limits and steady-state performance verification When using ZSVI, the experimental results for exceeding and not exceeding the power distribution limit are as follows: Figures 7-8 As shown. Experimental results using ZSVI+SCDA that exceed the power allocation limit when using ZSVI alone are shown below. Figure 9 As shown.

[0059] Figures 7-9 in, u AO This refers to the phase voltage output between the input port of phase A IGBT and the midpoint of the DC capacitor. For example... Figure 7 As shown, where, R1=20Ω, R2=25Ω, m up = m low ≈0.99, k up ≈0.55, k low ≈0.45, when m up =m low When k = 0.99 up and k low The corresponding upper and lower limits of the average power distribution limit are 0.51 and 0.49, respectively; since kup =0.55 exceeds the upper limit of 0.51, k low =0.45 is lower than the lower limit of 0.49. The system has experienced overmodulation due to severe power asymmetry between the upper and lower DC-side loads, making it unable to achieve the control target. At this time, the voltages of the upper and lower capacitors cannot track the command value of 272V. It fluctuates around 258V with an amplitude of approximately 5V. It fluctuates around 287V with a similar amplitude; the power distribution ratio reaches its limit, that is... : =0.4:0.6.

[0060] Figure 8 This demonstrates the case where the average power does not exceed the distribution limit (k). up =k low =0.5), the system can operate stably, achieving dual-load power decoupling and capacitor voltage fluctuation suppression. Among these, R1=25Ω, R2=25Ω, m up =m low ≈0.99, k up =k low =0.5, the voltage of both the upper and lower capacitors remained around 272V, with a fluctuation amplitude of about 4V. The instantaneous capacitor fluctuation was relatively small. Figure 11 Smaller. The capacitor voltage is symmetrical, and the zero-sequence voltage and three-phase modulation voltage also remain balanced, thus the output bridge arm voltage levels are symmetrical, ultimately achieving... : A power distribution ratio of 0.5:0.5.

[0061] like Figure 9 As shown, where, R1=20Ω, R2=25Ω, m up = m low ≈0.99, k up ≈0.55, k low With a voltage of approximately 0.45, a wider power distribution range is achieved through secondary adjustment of the intermediate phase duty cycle. Within one switching cycle, the intermediate phase outputs three levels, with the upper and lower capacitor voltages maintained around 272V, fluctuating by about 4V. Based on ZSVI, and combined with SDCA, the power distribution limit is further expanded. : =0.55:0.45.

[0062] The above experiments show that under the condition of injecting only zero-sequence voltage, when the average power of the dual loads exceeds the power distribution limit, the system capacitor voltage cannot follow the reference voltage; conversely, the control objective can be achieved. When the average power of the dual loads exceeds the power distribution limit of the zero-sequence voltage injection method but does not exceed the power distribution range of the intermediate phase secondary duty cycle adjustment, power distribution can be achieved by adjusting the voltage intermediate phase duty cycle.

[0063] The steady-state performance verification experiment included two different operating conditions, I and II, as shown in Table 2, using ZSVI and ZSVI+SDCA respectively, and the corresponding waveform data were analyzed. Calculations showed that the average power under both operating conditions exceeded the ZSVI allocation limit but did not exceed the ZSVI+SDCA power allocation limit. Specific experimental waveforms are shown below. Figure 10 As shown.

[0064] Table 2 Steady-state experimental state parameters ; Figure 10 middle u AB This is the line voltage output between the input ports of phase A and phase B IGBTs. Observe. Figure 10 When operating condition I uses ZSVI, the voltages of the upper and lower capacitors stabilize at 244V and 314V respectively, and the current amplitude is 13.6A, which is less than the expected current amplitude. This reaches the power distribution limit and cannot track the given voltage. The peak-to-peak value is 5.1V. The peak-to-peak value is 4.4V. The reason why the power of the upper capacitor is less than that of the lower capacitor is... ＞ The reason is that the bridge arm voltage is clamped during the positive half-cycle, and current continuously flows into the upper capacitor during the clamping interval. ＞ Under operating condition I, with ZSVI+SDCA, the current amplitude is 16.2A, which does not reach the power distribution limit. It can stably track the given voltage, and the voltages of both the upper and lower capacitors are stable at 300V. Peak-to-peak value is 3.75V. The peak-to-peak value is 4V. The reason why the power of the upper capacitor is greater than that of the upper capacitor is because... < The reason is that after adopting ZSVI+SDCA, the bridge arm that should have switched between positive bus level and midpoint potential output a negative bus level, thus increasing the average current flowing into the negative bus. < Under operating condition II, with ZSVI applied, the current amplitude reaches 15.4A, achieving the power distribution limit, and the voltages of the upper and lower capacitors stabilize at 279V and 474V, respectively. , The peak-to-peak values ​​are 4.5V and 3.5V, respectively. Greater than Similarly, the voltage clamping of the bridge arm occurred during the positive half-cycle; under operating condition II, with ZSVI+SDCA, the current amplitude was 22.1A, and the voltages of both the upper and lower capacitors remained stable at 400V, not reaching the power distribution limit. The peak-to-peak value is 2V. The peak-to-peak value is 2.8V. When ZSVI+SDCA is used, the capacitor voltage fluctuation under operating condition II is smaller than that under operating condition I because the modulation degree of operating condition II is reduced and the clamping range is reduced.

[0065] Experimental results show that in cases I and II, when ZSVI+SDCA is used, both the upper and lower DC side voltages can track the given value and contain only a small amount of fluctuation components. The power allocation limit is extended, and the three-phase current i in the dual-load power decoupling and capacitor voltage fluctuation suppression system based on CBPWM modulation and DBC algorithm is improved. A i B i C It can always maintain a sine wave without distortion, consistent with theoretical analysis.

[0066] 4. Power distribution limits and steady-state performance verification Table 3 records the state parameters of the upper and lower loads during stages I-IV of the load change experiment. The upper capacitor load R1 = 20Ω remains constant. Under operating conditions I / II, R2 switches from the ZSVI power distribution range to the ZSVI+SDCA power distribution range; under operating conditions II / IV, R2 switches from the ZSVI+SDCA power distribution range to the ZSVI power distribution range. Experimental results are as follows: Figure 11 As shown.

[0067] Table 3 Load mutation test state parameters ; observe Figure 11 It can be seen that when the DC-side load suddenly increases or decreases, the change in DC-side capacitor voltage increases with the magnitude of the load change. When the system does not exceed the power distribution range of ZSVI, only ZSVI is used; when it exceeds the power range of ZSVI but not exceeding the power range of ZSVI+SDCA, ZSVI+SDCA is used. Observation Figure 11 (a)- Figure 11As can be seen from (d) in the figure, before and after the power range changes, with the reasonable input and output of SCDA, the system can operate stably. The voltages of both the upper and lower DC sides can recover to the reference voltage within 0.08s, track the given value with a very small fluctuation amplitude and always maintain it at the given voltage. During the load change process, both the AC and DC sides of the rectifier have a fast dynamic response speed and high stability.

[0068] In summary, this application proposes a method for power distribution of the upper and lower capacitors in a T-type three-level rectifier based on zero-sequence voltage and voltage intermediate phase adjustment. The zero-sequence component injection method... The coupling relationship between the upper and lower DC power sides has been decoupled. The fluctuation of capacitor voltage was suppressed. After the zero-sequence voltage injection method reached the power distribution limit, the power distribution limit was further extended by adjusting the duty cycle of the intermediate phase of the voltage.

[0069] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated.

[0070] The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0071] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0072] In addition, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0073] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier, characterized in that, Includes the following steps: Acquire sampled values ​​of grid-side voltage, grid-side current, DC-side upper capacitor voltage, and lower capacitor voltage; The d-axis current command values ​​corresponding to the upper and lower capacitors are generated based on the deviation between the given values ​​of the upper and lower capacitor voltages and their sampled values, and the sum of the two is used as the total d-axis current command value. The initial three-phase modulation voltage is determined based on the total d-axis current command value and the set q-axis current command value; A first zero-sequence voltage component is injected into the initial three-phase modulation voltage to obtain a first-corrected modulation voltage; Determine whether the modulated voltage after the first correction meets the preset power distribution limit condition. If so, adjust the zero-level duty cycle of the voltage intermediate phase a second time to generate the voltage to be modulated. Otherwise, use the modulated voltage after the first correction as the voltage to be modulated. A second zero-sequence voltage component is injected into the voltage to be modulated to generate the final modulated voltage; A PWM drive signal is generated based on the final modulation voltage to drive the switching device.

2. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 1, characterized in that, The step of determining the initial three-phase modulation voltage based on the total d-axis current command value and the set q-axis current command value includes: Based on the current phase angle and angular frequency of the grid voltage phase-locked loop output, predict the grid voltage phase angle for the next control cycle and calculate the corresponding grid voltage value for the next control cycle. The total d-axis current command value, the set q-axis current command value, and the predicted phase angle are input to the current controller to obtain the predicted grid-side current value for the next control cycle. The predicted grid-side current value and the grid voltage value of the next control cycle are input into the deadbeat controller to calculate the uncorrected predicted three-phase modulation voltage value, which is used as the initial three-phase modulation voltage.

3. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 2, characterized in that, The injection range of the first zero-sequence voltage component is: ； in, This is the first zero-sequence voltage component. upper limit and lower limit They are respectively: ； in, This is a sampled value of the capacitor voltage on the DC side. This is a sampled value of the capacitor voltage on the DC side. This represents the peak value of the phase voltage of the bridge arm.

4. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 3, characterized in that, The modified modulation voltage after the first correction includes the following formula: ； Among them, u max u mid and u min These are the maximum phase modulation voltage, the intermediate phase modulation voltage, and the minimum phase modulation voltage, u. max_Z1 u mid_Z1 u min_Z1 These are the maximum phase modulation voltage, intermediate phase modulation voltage, and minimum phase modulation voltage after one correction, respectively.

5. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 4, characterized in that, The preset power allocation limit condition is: the polarity of the modulation voltage after the first correction is all positive and the power demand of the lower capacitor is greater than zero, or the polarity is all negative and the power demand of the upper capacitor is greater than zero. If the deviation between the given value of the lower capacitor voltage and its sampled value is adjusted by the PI controller and the output value of the lower capacitor d-axis current command is greater than zero, then it is determined that the power demand of the lower capacitor is greater than zero. When the deviation between the given value of the upper capacitor voltage and its sampled value is adjusted by the PI controller and the output value of the upper capacitor d-axis current command is greater than zero, it is determined that the power demand of the upper capacitor is greater than zero.

6. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 5, characterized in that, The secondary adjustment of the zero-level duty cycle of the intermediate phase of the voltage to generate the voltage to be modulated includes: Based on the set duty cycle allocation coefficient k D The zero-level duty cycle of the corrected intermediate phase voltage is redistributed. ; Based on the redistributed duty cycle relationship, the intermediate phase modulation voltage u in the first-corrected modulation voltage is... mid_Z1 Decomposition will generate the upmodulated wave component u. max_Z1_up u mid_Z1_up u min_Z1_up and downmodulated wave component u max_Z1_low u mid_Z1_ low u min_Z1_low It satisfies the following formula: ； The maximum phase modulation voltage u in the first corrected modulation voltage max_Z1 With minimum phase modulation voltage u min_Z1 These are respectively their own upper and lower modulation waves, and u is obtained from the decomposition of the voltage intermediate phase. mid_Z1_up and u mid_Z1_ low The final three-phase upper modulation wave set and three-phase lower modulation wave set are formed as the voltage to be modulated.

7. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 6, characterized in that, The duty cycle allocation coefficient k is based on the set value. D The zero-level duty cycle of the corrected intermediate phase voltage is redistributed. The redistributed duty cycle relationship is obtained as follows: ； Where, d mid1_Z1’ d mid0_Z1’ d mid-1_Z1’ These represent the duty cycles of the positive, zero, and negative voltage levels after secondary adjustment of the intermediate phase voltage.

8. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 7, characterized in that, Second zero-sequence voltage component Determined based on the polarity of the current voltage to be modulated, including: When the voltage to be modulated satisfies the condition that the maximum phase and intermediate phase are greater than zero and the minimum phase is less than zero, the second zero-sequence voltage component... for : ； When the voltage to be modulated satisfies the condition that the maximum phase is greater than zero and the intermediate and minimum phases are less than zero, the second zero-sequence voltage component... for : ； in, The power setpoint for the lower capacitor. The power setpoint for the upper capacitor. , and , These represent the voltage and corresponding current of the maximum and minimum phases in the current modulation voltage.

9. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 8, characterized in that, Second zero-sequence voltage component The determination based on the polarity of the current voltage to be modulated also includes: when the maximum phase, intermediate phase, and minimum phase of the voltage to be modulated are all positive or all negative, the second zero-sequence voltage component... It is zero.

10. The method for controlling the power distribution of the upper and lower capacitors in a T-type three-level rectifier according to claim 8, characterized in that, The method further includes: Real-time acquisition of the current upper capacitor power allocation coefficient k up With lower capacitor power distribution coefficient k low ; Determine k up Whether it is within the first constraint range, k low Whether it is within the second constraint range, where: The first constraint range is as follows: ； The second constraint range is as follows: ； Where φ is the phase angle of the bridge arm voltage lagging the current, I m This represents the peak value of the phase current. If k up Deviating from the first constraint range and k low If the deviation from the second constraint range occurs, an optimization instruction is generated; The optimization instruction is used to correct the upper capacitor voltage setpoint and / or the lower capacitor voltage setpoint, so that k up With k low The value of is adjusted to the corresponding constraint range to realize the second zero-sequence voltage component. It operates in non-limited mode.

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