Wideband log detector

Abstract

The present application relates to a kind of wideband log detector.It includes the limiting amplifier link for the limiting amplification of signal to be detected, the limiting amplification gain includes first limiting amplification gain or second limiting amplification gain, the value of first limiting amplification gain is greater than the value of second limiting amplification gain, wherein, when the limiting amplification gain of limiting amplifier link is first limiting amplification gain, access the limiting amplifier of first stage number, and each limiting amplifier provides single-stage first amplification gain;When the limiting amplification gain of limiting amplifier link is second limiting amplification gain, access the limiting amplifier of second stage number, and each limiting amplifier provides single-stage second amplification gain;First stage number is less than second stage number, and single-stage first amplification gain is greater than single-stage second amplification gain.The present application can effectively stabilize the translation of the RSSI output characteristic curve of log detector, improve the output characteristic and process robustness of log detector.

Description

TECHNICAL FIELD

[0001] The present application relates to a logarithmic detector, in particular, a wideband logarithmic detector. BACKGROUND

[0002] Wireless communication technology is widely used. In actual communication process, the amplitude of the transmitted signal fluctuates significantly due to different application scenarios and channel conditions. Therefore, the amplitude of the transmitted signal cannot be determined in the signal receiving and transmitting process.

[0003] In order to ensure the stability of wireless communication, the signal should be transmitted with maximum power during the receiving and transmitting process, which will cause a sharp rise in power consumption and seriously affect the battery life. In order to save power and prolong the life of the battery, it is necessary to limit the amplitude of the signal under the premise of ensuring the bit error rate. Therefore, it is desirable for the receiver to work in the best receiving power range, to adjust the power of the transmitted signal by detecting the strength of the received signal, and to control the gain of the receiving end, so as to achieve the purpose of power control, thereby realizing low-power wireless transmission.

[0004] Logarithmic detectors are widely used in wireless communication technology, such as cellular communication, Internet of Things terminals, and satellite navigation, etc. modern wireless communication, which can realize automatic gain control loop and power management, and provide a key signal strength monitoring solution for low-power transceiver design.

[0005] Logarithmic detectors can convert signal power in a large dynamic input range. Logarithmic detectors based on continuous detection structure are widely used due to their high sensitivity and wide dynamic range. However, the conversion characteristics of the logarithmic detector are greatly affected by the gain of the limiting amplifier, the process variation of the summing resistor, Figure 1 An embodiment showing the correspondence between the conversion characteristics of the logarithmic detector and the gain of the limiting amplifier is shown in FIG. 1, Figure 2 An embodiment showing the correspondence between the conversion characteristics of the logarithmic detector and the resistance value of the summing resistor is shown in FIG. 2, Figure 1 and Figure 2 In FIG. 1, the horizontal axis is the power of the received signal, in dBm, and the vertical axis is the received signal strength, in V.

[0006] As shown in the figure, if the gain of the limiting amplifier is larger or smaller than the expected gain, the slope of the RSSI (Received Signal Strength Indicator) output characteristic curve of the logarithmic detector will also be larger or smaller; if the resistance value of the summing resistor deviates from the expected resistance value due to process variation, the RSSI output characteristic curve of the logarithmic detector will be translated. Therefore, how to effectively solve the RSSI output characteristic curve deviation of the logarithmic detector in the case of non-ideal gain of the limiting amplifier and resistance value fluctuation of the summing resistor due to process variation is a difficult problem to be solved at present. SUMMARY

[0007] The purpose of the present application is to overcome the deficiencies in the prior art, and provide a wideband logarithmic detector which can effectively stabilize the translation of the RSSI output characteristic curve of the logarithmic detector and improve the output characteristics and process robustness of the logarithmic detector.

[0008] According to the technical scheme provided by the present application, a wideband logarithmic detector includes a limiting amplifier chain for limiting and amplifying a signal to be detected, the limiting amplifier chain includes a plurality of limiting amplifiers connected in series, and the amplification gain of each limiting amplifier is configurable,

[0009] The number of limiting amplifiers accessed in the limiting amplifier chain and the gain of each limiting amplifier are configured to configure the limiting amplification gain of the limiting amplifier chain, the limiting amplification gain includes a first limiting amplification gain or a second limiting amplification gain, the value of the first limiting amplification gain is greater than the value of the second limiting amplification gain, and wherein,

[0010] When the limiting amplification gain of the limiting amplifier chain is the first limiting amplification gain, a first number of limiting amplifiers are accessed, and each limiting amplifier provides a single first amplification gain;

[0011] When the limiting amplification gain of the limiting amplifier chain is the second limiting amplification gain, a second number of limiting amplifiers are accessed, and each limiting amplifier provides a single second amplification gain;

[0012] The first number is less than the second number, and the single first amplification gain is greater than the single second amplification gain.

[0013] The number of limiting amplifiers in the limiting amplifier chain is not less than the second number;

[0014] A chain-in switch array for configuring the access state of the limiting amplifier is arranged in the limiting amplifier chain, so as to configure the number of limiting amplifiers accessed in the limiting amplifier chain based on the switch state of the chain-in switch array.

[0015] When the first limiting amplification gain is 72dB and the second limiting amplification gain is 66dB, the following equation is satisfied:

[0016] The first stage number is 6, the single-stage first amplification gain is 12dB, and the second stage number is 11, and the single-stage second amplification gain is 6dB.

[0017] The limiting amplifiers in the limiting amplifier chain are in a cascade form of differential input and differential output, wherein the limiting amplifiers are in a current mirror-based cascode diode load gain amplification form;

[0018] The limiting amplifiers include a single-stage amplification current source connected to a differential input pair tube, and each differential input tube in the differential input pair tube is connected to an input tube load circuit;

[0019] The input tube load circuit includes a current mirror connected to the differential input tube, a current buffer connected to the current mirror, and a diode load connected to the current buffer;

[0020] A connection node between the diode load and the current buffer forms a differential output terminal;

[0021] When the amplification gain of the limiting amplifier is configured as the single-stage second amplification gain, the current provided by the single-stage amplification current source and the load state provided by the diode load are configured so that the current flowing through each differential input tube is the first working current;

[0022] When the amplification gain of the limiting amplifier is configured as the single-stage first amplification gain, the current provided by the single-stage amplification current source and the load state provided by the diode load are configured so that the current flowing through each differential input tube is the second working current;

[0023] The size of the second working current is twice the size of the first working current.

[0024] When the two differential input tubes in the differential input pair tube are NMOS tubes, the differential input tubes are a differential input first NMOS tube and a differential input second NMOS tube, respectively, wherein

[0025] The source terminals of the differential input first NMOS tube and the differential input second NMOS tube are connected to the single-stage amplification current source, and the differential input signal is received through the gate terminals of the differential input first NMOS tube and the differential input second NMOS tube;

[0026] The drain terminals of the differential input first NMOS tube and the differential input second NMOS tube are respectively connected to a load current mirror and a current buffer in an input tube load circuit;

[0027] The single-stage amplification current source comprises at least a current source I0 and a current source I1, wherein the current outputted by the current source I0 is equal to the current outputted by the current source I1,

[0028] The current source I0 is configured to keep connection with the source end of the differential input first NMOS tube and the differential input second NMOS tube;

[0029] When the amplification gain of the limiting amplifier is configured as the single-stage second amplification gain, the connection between the current source I1 and the source end of the differential input first NMOS tube and the differential input second NMOS tube is disconnected;

[0030] When the amplification gain of the limiting amplifier is configured as the single-stage first amplification gain, the current source I1 is configured to be connected with the source end of the differential input first NMOS tube and the differential input second NMOS tube.

[0031] The current buffer adopts at least a common-gate amplifier, wherein,

[0032] When the current buffer adopts the common-gate amplifier, the current buffer comprises at least a buffer first PMOS tube and a buffer second PMOS tube, wherein,

[0033] The drain end of the buffer first PMOS tube is connected with the drain end of a differential input tube and the gate end of a current mirror first PMOS tube and the gate end of a current mirror second PMOS tube in a load current mirror, and the gate end of the buffer first PMOS tube and the gate end of the buffer second PMOS tube are connected with a bias voltage V bias The source end of the buffer first PMOS tube is connected with the drain end of the current mirror first PMOS tube;

[0034] The source end of the current mirror first PMOS tube and the source end of the current mirror second PMOS tube are connected with a power supply VDD, and the drain end of the current mirror second PMOS tube is connected with the source end of the buffer second PMOS tube,

[0035] The drain end of the buffer second PMOS tube is connected with a diode load.

[0036] The diode load comprises at least two sub-load units connected in sequence, wherein,

[0037] For any sub-load unit, the sub-load unit comprises a load first NMOS tube and a load second NMOS tube, wherein,

[0038] The gate end of the load first NMOS tube is connected with the gate end of the load second NMOS tube and the drain end of the load first NMOS tube through a load first switch to form a sub-load first connection end of the current sub-load unit;

[0039] The sub-load first connection end is also connected with the source end of the load first NMOS tube and the drain end of the load second NMOS tube through the load second switch, and the source end of the load second NMOS tube forms a sub-load second connection end of the current sub-load unit;

[0040] For any two serially connected sub-load units, the sub-load second connection end of a previous sub-load unit is connected with the sub-load first connection end of a subsequent sub-load unit in the serial connection direction of the sub-load units;

[0041] The sub-load first connection end of a sub-load unit at the head of the series is connected with the current buffer, and the sub-load first connection end of the sub-load unit is grounded through a load unit current source;

[0042] The sub-load second connection end of a sub-load unit at the tail of the series is grounded;

[0043] When the amplification gain of the limiting amplifier is configured as the single-stage second amplification gain, the load first switch in each sub-load unit is configured in an open state, the load second switch is configured in a closed state, and the load unit current source is configured in a non-access working state;

[0044] When the amplification gain of the limiting amplifier is configured as the single-stage first amplification gain, the load first switch in each sub-load unit is configured in a closed state, the load second switch is configured in an open state, and the load unit current source is configured in an access working state.

[0045] The wideband logarithmic detector further comprises a rectifier network, a low-pass filter, and a resistance calibration module for calibrating a summing resistor in the low-pass filter, wherein,

[0046] The rectifier network comprises a plurality of rectifiers, wherein the number of rectifiers in the rectifier network is one more than the number of limiting amplifiers in the limiting amplifier chain;

[0047] The input end and the output end of the limiting amplifier are connected with a rectifier, and the rectifiers connected with the input end and the output end of the limiting amplifier are connected with the summing resistor in the low-pass filter, so as to output the RSSI value of the to-be-detected signal through the low-pass filter;

[0048] After the summing resistor is calibrated by the resistance calibration module, the resistance value of the summing resistor matches the expected resistance value.

[0049] The resistance calibration module comprises a calibration current generation unit, a voltage comparator, a calibration signal generation unit, a multiplexer, and a reference resistor for providing an expected resistance, wherein,

[0050] One end of the summing resistor is connected with the output end of the multiplexer, and the other end of the summing resistor is grounded.

[0051] The first selection end of the multiplexer is connected with the rectifier in the rectification network, and the second selection end of the multiplexer is connected with the inverting end of the voltage comparator;

[0052] The calibration current generating unit generates at least a first calibration current and a second calibration current with equal sizes, the first calibration current and the second calibration current are loaded to the non-inverting end and the inverting end of the voltage comparator respectively, and the non-inverting end of the current comparator is also connected with the reference resistor;

[0053] During calibration, the multiplexer is selected to connect the summing resistor with the inverting end of the voltage comparator, and the voltage comparator loads the comparison result of the voltage comparator to the calibration signal generating unit to calibrate the resistance value of the summing resistor through the calibration signal generating unit until the resistance value of the summing resistor matches the expected resistance value provided by the reference resistor;

[0054] After calibration, the multiplexer is configured to connect the summing resistor with the rectifier in the rectification network.

[0055] The resistance value of the summing resistor is controlled by using a code value;

[0056] When the calibration signal generating unit calibrates the resistance value of the summing resistor, at least a bisection calibration method is used.

[0057] The advantage of the present application is that the limiting amplifier link can include a plurality of limiting amplifiers connected in sequence, by configuring the number of stages of the limiting amplifier link and the amplification gain of each limiting amplifier, the limiting amplifier link can be configured to have a first limiting amplification gain of 72 dB or a second limiting amplification gain of 66 dB, so as to suppress the change of the output characteristic curve slope of the logarithmic detector caused by gain deviation.

[0058] The summing resistor in the low-pass filter is calibrated to match the resistance value of the summing resistor with the expected resistance value, so as to compensate for the resistance value change of the summing resistor caused by process deviation, thereby further stabilizing the translation of the logarithmic detector output curve, and having good output characteristics and process robustness. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figure 1 It is an embodiment schematic diagram of the correspondence between the conversion characteristic of the logarithmic detector and the limiting amplifier gain.

[0060] Figure 2 It is an embodiment schematic diagram of the correspondence between the conversion characteristic of the logarithmic detector and the resistance value of the summing resistor.

[0061] Figure 3 It is an embodiment structure block diagram of the logarithmic detector of the present application.

[0062] Figure 4 A circuit schematic diagram of an embodiment of the limiting amplifier of the present invention.

[0063] Figure 5 A circuit schematic diagram of an embodiment of the connection and cooperation of the resistance calibration module and the low-pass filter of the present invention. DETAILED DESCRIPTION

[0064] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0065] In order to effectively stabilize the translation of the RSSI output characteristic curve of the logarithmic detector and improve the output characteristic of the logarithmic detector, the present invention provides a wideband logarithmic detector, specifically, the wideband logarithmic detector comprises a limiting amplifier chain for limiting amplification of a to-be-detected signal, the limiting amplifier chain comprises a plurality of limiting amplifiers connected in sequence, and the amplification gain of each limiting amplifier is configurable,

[0066] The number of limiting amplifiers accessed in the limiting amplifier chain and the gain of each limiting amplifier are configured to configure the limiting amplification gain of the limiting amplifier chain, and the limiting amplification gain comprises a first limiting amplification gain or a second limiting amplification gain, the value of the first limiting amplification gain is greater than the value of the second limiting amplification gain, wherein,

[0067] When the limiting amplification gain of the limiting amplifier chain is the first limiting amplification gain, a first number of limiting amplifiers are accessed, and each limiting amplifier provides a single-stage first amplification gain;

[0068] When the limiting amplification gain of the limiting amplifier chain is the second limiting amplification gain, a second number of limiting amplifiers are accessed, and each limiting amplifier provides a single-stage second amplification gain;

[0069] The first number is less than the second number, and the single-stage first amplification gain is greater than the single-stage second amplification gain.

[0070] It can be understood that the working principle of the logarithmic detector of the present invention is consistent with that of the existing logarithmic detector, and therefore the logarithmic detector of the present invention should also comprise a limiting amplifier chain, which can receive a to-be-detected signal and limit amplify the received to-be-detected signal to compress the to-be-detected signal with a larger power range into a linear voltage range that is easy to process. The same as the existing logarithmic detector, the limiting amplifier chain can comprise a plurality of limiting amplifiers connected in sequence, and the connection of the limiting amplifiers to form the limiting amplifier chain will be described in detail below. Figure 3

[0071] ​As can be seen from the above description, the RSSI output characteristic curve of the logarithmic detector is related to the limiting amplification gain of the limiting amplifier link, specifically, when the limiting amplification gain of the limiting amplifier link is too low, the dynamic range of the logarithmic detector will be limited, and when the limiting amplification gain of the limiting amplifier link is too high, the gain error of the logarithmic detector will be large, wherein the limiting amplification gain of the limiting amplifier link specifically refers to the gain when the limiting amplifier link amplifies the to-be-detected signal.

[0072] Unlike the existing logarithmic detector, the limiting amplifier link of the present application can provide different limiting amplification gains, and the amplification gain of each limiting amplifier can also be configured, specifically, the limiting amplification gain provided by the limiting amplifier link can be at least a first limiting amplification gain or a second limiting amplification gain, that is, the limiting amplifier link of the present application can provide two optional limiting amplification gains, and in specific implementation, the first limiting amplification gain or the second limiting amplification gain provided by the limiting amplifier link can be selected according to the requirements of the working scene.

[0073] When selecting the limiting amplification gain, the limiting amplification gain can be first selected as the first limiting amplification gain or the second limiting amplification gain, and then the RSSI output characteristic under the current limiting amplification gain is determined, if the RSSI output characteristic cannot meet the requirements, the limiting amplification gain can be switched to the second limiting amplification gain or the first limiting amplification gain, and the case that cannot meet the requirements can refer to the corresponding description in the background art and Figure 1 It should be noted that when the first limiting amplification gain or the second limiting amplification gain is selected, the limiting amplification gain of the limiting amplifier link should be kept as the first limiting amplification gain or the second limiting amplification gain, so as to effectively adapt to the requirements of the working scene. Of course, when the conditions of the working scene change and the current limiting amplification gain cannot meet the working requirements, the current limiting amplification gain can be switched from the first limiting amplification gain to the second limiting amplification gain, or from the second limiting amplification gain to the first limiting amplification gain, the switching direction is related to the current limiting amplification gain, until the selected limiting amplification gain is adapted to the current working scene.

[0074] It should be understood that when the limiting amplification gain is selected as the first limiting amplification gain or the second limiting amplification gain, it is mainly to meet the requirements of the working scene on RSSI detection. When the first limiting amplification gain or the second limiting amplification gain is selected, it should match the expected gain in Figure 1 , that is, it should be consistent with the expected gain, or the difference with the expected gain is within an allowed numerical range, which can be selected as needed to meet the requirements of the working scene, which will not be described here.

[0075] In implementation, the first limiting amplification gain value should be configured to be greater than the second limiting amplification gain value. In order to ensure the detection accuracy of RSSI, when the limiting amplification gain of the limiting amplifier link is the first limiting amplification gain, the limiting amplifiers of the first stage number are configured, and each limiting amplifier provides a single-stage first amplification gain. In addition, when the limiting amplification gain of the limiting amplifier link is the second limiting amplification gain, the limiting amplifiers of the second stage number should be configured, and each limiting amplifier can provide a single-stage second amplification gain. The meaning of the limiting amplifiers of the second stage number can be referred to the above description.

[0076] It should be understood that when the limiting amplifiers form the limiting amplifier link in a cascade form, the product of the first stage number and the single-stage first amplification gain is the first limiting amplification gain, and the product of the second stage number and the single-stage second amplification gain is the second limiting amplification gain. In implementation, the first stage number is less than the second stage number, and the single-stage first amplification gain is greater than the single-stage second amplification gain.

[0077] It should be noted that when the limiting amplification gain of the limiting amplifier link is determined in the above manner, the detection error can be effectively reduced. The detection error of the limiting amplifier link will be described in detail below. Specifically,

[0078]

[0079] wherein, is the maximum detection error when the limiting amplifier link is detected, and the unit is dB, is the limiting amplification gain of the limiting amplifier link, is the stage number of the limiting amplifiers in the limiting amplifier link.

[0080] As can be seen from the above description, N is the first stage number or the second stage number, when the limiting amplification gain is the first limiting amplification gain or the second limiting amplification gain. As can be seen from the expression of the detection error, when the stage number of the limiting amplifiers and the amplification gain of the corresponding limiting amplifiers are configured in the above manner, the RSSI output characteristic curve of the log detector can be effectively stabilized and translated, and the detection error can be effectively reduced, thereby effectively adapting to the working requirements of different working scenarios.

[0081] In an embodiment of the present application, the number of limiting amplifiers in the limiting amplifier link is not less than the second stage number.

[0082] The in-chain switch array is arranged in the limiting amplifier link to configure the access state of the limiting amplifier, so as to configure the number of limiting amplifiers accessed in the limiting amplifier link based on the switch state of the in-chain switch array.

[0083] In implementation, the number of limiting amplifiers in the limiting amplifier link should be no less than the second number, and when the number of limiting amplifiers in the limiting amplifier link is the second number, the limiting amplifier gain of the limiting amplifier link is configured as the second limiting amplifier gain, and then all the limiting amplifiers are accessed.

[0084] Figure 3 An embodiment of the in-chain switch array is shown in FIG. 2, in which the in-chain switch array includes a switch SW0 and a switch SW1, wherein when the switch SW0 is open and the switch SW1 is closed, all the limiting amplifiers are accessed, and when the switch SW0 is closed and the switch SW1 is open, only part of the limiting amplifiers are accessed, and the number of limiting amplifiers accessed is the first number, wherein each limiting amplifier is a stage in the limiting amplifier link. Of course, other ways can be used to configure the number of limiting amplifiers accessed, and the specific selection can be made according to the needs, which will not be illustrated one by one here.

[0085] It can be understood that the switch SW0 and the switch SW1 can be in a form commonly used at present, and the way of controlling the corresponding switch state of the switch SW0 and the switch SW1 can be consistent with the prior art, for example, the switch control signal can be configured in a register to configure the corresponding switch control signal of the switch SW0 and the switch SW1, and when different limiting amplifier gains are needed, the value of the register can be configured to configure the corresponding switch control signal to configure the limiting amplifier gain required. Of course, other ways can be used to configure the switch state of the switch SW0 and the switch SW1, and the specific selection can be made according to the needs, which will not be illustrated one by one here.

[0086] In an embodiment of the present application, when the first limiting amplifier gain is 72 dB and the second limiting amplifier gain is 66 dB, there are:

[0087] The first number is 6, the single-stage first amplification gain is 12 dB, and the second number is 11, and the single-stage second amplification gain is 6 dB.

[0088] In the field of wireless communication, when RSSI detection is performed on a signal to be detected, the dynamic range reaches 60dB or more, the detection sensitivity is higher than -60dB, the gain linear error caused by process variation should be less than 2dB, therefore, in order to meet the requirements of RSSI detection, the first limiting amplifier gain can be configured as 72dB, and the second limiting amplifier gain can be configured as 66dB, that is, when the limiting amplifier gain of the limiting amplifier link is selected as 72dB or 66dB, the dynamic range of the entire logarithmic detector is large, the linear error is small, and it is suitable for most RSSI detection scenarios, that is, a wideband logarithmic detector of the application can be formed. In specific implementation, in order to further optimize the error accuracy of RSSI detection, in an embodiment of the application, the single-stage first amplification gain is 12dB, and the single-stage second amplification gain is 6dB.

[0089] Figure 3 In the application, the limiting amplifier link includes 11 limiting amplifiers, and the 11 limiting amplifiers are A0-A11. One end of switch SW0 is connected to the output end of limiting amplifier A5, one end of switch SW1 is connected to the output end of limiting amplifier A10, and the other end of switch SW0 and the other end of switch SW1 are connected to each other. At this time, when switch SW0 is closed and switch SW1 is closed, limiting amplifiers A0-A5 can be connected, and when switch SW0 is disconnected and switch SW1 is closed, limiting amplifiers A0-A10 can be connected.

[0090] In an embodiment of the application, the limiting amplifiers in the limiting amplifier link adopt a cascade form of differential input and differential output, wherein the limiting amplifiers adopt a common-source common-gate diode load gain amplification form based on a current mirror.

[0091] The limiting amplifier includes a differential input pair tube and a single-stage amplification current source connected to the differential input pair tube, and each differential input tube in the differential input pair tube is connected to an input tube load circuit.

[0092] The input tube load circuit includes a load current mirror connected to the differential input tube, a current buffer connected to the load current mirror, and a diode load connected to the current buffer.

[0093] The connection node between the diode load and the current buffer forms a differential output end.

[0094] When the amplification gain of the limiting amplifier is configured as the single-stage second amplification gain, the current provided by the single-stage amplification current source and the load state provided by the diode load are configured, so that the current flowing through each differential input tube is the first working current.

[0095] When the amplification gain of the limiting amplifier is configured as a single-stage first amplification gain, the current provided by the single-stage amplification current source and the load state provided by the diode load are configured so that the current flowing through each differential input tube is a second working current;

[0096] The second working current is twice the size of the first working current.

[0097] Figure 3 In the limiting amplifier chain, each limiting amplifier adopts a differential input and differential output form, which can effectively offset the burr phenomenon caused by non-ideal factors during signal transmission. Figure 3 In the limiting amplifier chain, each limiting amplifier adopts a differential input and differential output form, which can effectively offset the burr phenomenon caused by non-ideal factors during signal transmission.

[0098] In an embodiment of the present application, the input tube load circuit can include a load current mirror, a current buffer, and a diode load. The load current mirror can make the current flowing through each differential input tube equal, and thus each diode load can have the same bias current. The current buffer can adopt a common gate amplifier form, which can improve the bandwidth and frequency response of the limiting amplifier of the present application. In specific implementation, the single-stage amplifier current source can provide different bias currents, and the diode load can also provide different load states. By configuring the current provided by the single-stage amplifier current source and the load state provided by the diode load, the amplification gain of the limiting amplifier can be 6dB and 12dB as described above, thereby effectively saving the area of each limiting amplifier.

[0099] In an embodiment of the present application, when the two differential input tubes in the differential input pair tube adopt NMOS tubes, the differential input tubes are respectively a differential input first NMOS tube and a differential input second NMOS tube.

[0100] The source end of the differential input first NMOS tube and the source end of the differential input second NMOS tube are connected with the single-stage amplification current source, and the differential input signal is received through the gate end of the differential input first NMOS tube and the gate end of the differential input second NMOS tube.

[0101] The drain terminals of the differential input first NMOS tube and the differential input second NMOS tube are respectively connected to a load current mirror and a current buffer in an input tube load circuit;

[0102] The single-stage amplification current source comprises a current source I0 and a current source I1, wherein the current output by the current source I0 is equal to the current output by the current source I1,

[0103] The current source I0 is configured to maintain connection with the source terminals of the differential input first NMOS tube and the differential input second NMOS tube.

[0104] When the amplification gain of the limiting amplifier is configured as the single-stage second amplification gain, the connection between the current source I1 and the source terminals of the differential input first NMOS tube and the differential input second NMOS tube is disconnected.

[0105] When the amplification gain of the limiting amplifier is configured as the single-stage first amplification gain, the current source I1 is configured to be connected with the source terminals of the differential input first NMOS tube and the differential input second NMOS tube.

[0106] Figure 4 An embodiment circuit schematic diagram of the limiting amplifier is shown in FIG. 1, wherein the NMOS tube NM0 can be used as the differential input first NMOS tube, the NMOS tube NM1 can be used as the differential input second NMOS tube, the gate terminal of the NMOS tube NM0 forms an input terminal VINP0 of the limiting amplifier, and the gate terminal of the NMOS tube NM1 forms another input terminal VINN0 of the limiting amplifier.

[0107] Figure 4 An embodiment of the single-stage amplification current source is also shown in FIG. 2, wherein the single-stage amplification current source comprises a current source I0 and a current source I1, wherein the ground terminals of the current source I0 and the current source I1 are both grounded, the current source I1 is further connected with the source terminals of the NMOS tube NM0 and the NMOS tube NM1 through a switch SW8, when the switch SW8 is closed, the current source I1 is connected with the source terminals of the NMOS tube NM0 and the NMOS tube NM1, otherwise, the connection between the current source I1 and the source terminals of the NMOS tube NM0 and the NMOS tube NM1 is disconnected.

[0108] As can be seen from the above description, the drain terminal of the NMOS tube NM0 and the drain terminal of the NMOS tube NM1 are both connected to a load current mirror and a current buffer in an input tube load circuit, and the specific connection mode will be described below. When the current flowing through the NMOS tube NM0 and the NMOS tube NM1 is the second working current, the switch SW8 should be closed, at this time, the second working current can be provided by the current source I0 and the current source I1 together, and when the current flowing through the NMOS tube NM0 and the NMOS tube NM1 is the first working current, the switch SW8 should be opened, at this time, the second working current can be provided by the current source I0 only.

[0109] In an embodiment of the present application, the current buffer at least adopts a common-gate amplifier, wherein,

[0110] When the current buffer adopts a common-gate amplifier, the current buffer at least includes a buffer first PMOS tube and a buffer second PMOS tube, wherein,

[0111] The drain terminal of the buffer first PMOS tube is connected to the drain terminal of a differential input tube and the gate terminal of a current mirror first PMOS tube and the gate terminal of a current mirror second PMOS tube in a load current mirror, the gate terminal of the buffer first PMOS tube and the gate terminal of the buffer second PMOS tube are both connected to a bias voltage V bias , and the source terminal of the buffer first PMOS tube is connected to the drain terminal of the current mirror first PMOS tube;

[0112] The source terminal of the current mirror first PMOS tube and the source terminal of the current mirror second PMOS tube are both connected to a power supply VDD, and the drain terminal of the current mirror second PMOS tube is connected to the source terminal of the buffer second PMOS tube,

[0113] The drain terminal of the buffer second PMOS tube is connected to a diode load.

[0114] Figure 4 An embodiment of the current buffer and the load current mirror is also shown in the figure. For the current buffer and the load current mirror connected to the NMOS tube NM0, in the figure, the PMOS tube PM4 can be used as the buffer first PMOS tube, the PMOS tube PM5 can be used as the buffer second PMOS tube, the PMOS tube PM0 can be used as the load current mirror first PMOS tube, and the PMOS tube PM1 can be used as the load current mirror second PMOS tube. Similarly, for the current buffer and the load current mirror connected to the NMOS tube NM1, in the figure, the PMOS tube PM6 can be used as the buffer first PMOS tube, the PMOS tube PM7 can be used as the buffer second PMOS tube, the PMOS tube PM2 can be used as the current mirror first PMOS tube, and the PMOS tube PM3 can be used as the current mirror second PMOS tube.

[0115] In implementation, the bias voltage V bias The bias voltage V bias The first PMOS transistor and the second PMOS transistor of the buffer are enabled. The current buffer can be used as a buffer between a load current mirror and a diode load unit.

[0116] In an embodiment of the present application, the diode load includes at least two sub-load units connected in series, wherein,

[0117] For any sub-load unit, the sub-load unit includes a first NMOS transistor and a second NMOS transistor, wherein,

[0118] The gate terminal of the first NMOS transistor is connected to the gate terminal of the second NMOS transistor and the drain terminal of the first NMOS transistor through a first load switch, to form a first connection terminal of the sub-load unit of the current sub-load unit.

[0119] The first connection terminal of the sub-load unit is also connected to the source terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor through a second load switch, and the source terminal of the second NMOS transistor forms a second connection terminal of the sub-load unit of the current sub-load unit.

[0120] For any two sub-load units connected in series, the second connection terminal of the previous sub-load unit is connected to the first connection terminal of the next sub-load unit in the series direction of the sub-load units.

[0121] For the sub-load unit at the head of the series, the first connection terminal of the sub-load unit is connected to the current buffer, and the first connection terminal of the sub-load unit is grounded through a load unit current source.

[0122] For the sub-load unit at the tail of the series, the second connection terminal of the sub-load unit is grounded.

[0123] When the amplification gain of the limiting amplifier is configured as the single-stage second amplification gain, the first load switch in each sub-load unit is configured to be in an open state, the second load switch is configured to be in a closed state, and the load unit current source is configured to be in a non-access working state.

[0124] When the amplification gain of the limiting amplifier is configured as the single-stage first amplification gain, the first load switch in each sub-load unit is configured to be in a closed state, the second load switch is configured to be in an open state, and the load unit current source is configured to be in an access working state.

[0125] In implementation, the diode load can include a plurality of sub-load units, and the number of sub-load units can be selected as needed. Figure 4An embodiment in which each diode load includes two sub-load units is shown in Fig. 2. The two diode loads are described below in connection with Figure 4 An embodiment in which each diode load includes two sub-load units is shown in Fig. 2. The two diode loads are described below in connection with

[0126] For the diode load corresponding to NMOS transistor NM0, NMOS transistor NM2, NMOS transistor NM3, switch SW2, and switch SW9 form a sub-load unit, in which NMOS transistor NM2 is the first NMOS transistor as a load, NMOS transistor NM3 is the second NMOS transistor as a load, switch SW2 is the first switch as a load, and switch SW9 is the second switch as a load. In addition, NMOS transistor NM4, NMOS transistor NM5, switch SW3, and switch SW10 form another sub-load unit, in which NMOS transistor NM4 is the first NMOS transistor as a load, NMOS transistor NM5 is the second NMOS transistor as a load, switch SW3 is the first switch as a load, and switch SW10 is the second switch as a load. Figure 4 In addition, current source I2 is the current source as a load unit, and current source I2 is connected to the drain terminal of NMOS transistor NM2 through switch SW4. In implementation, the drain terminal of NMOS transistor NM2 is connected to one end of switch SW9 and one end of switch SW4 to form a first connection terminal of a sub-load, and the first connection terminal of the sub-load is connected to the drain terminal of PMOS transistor PM5 to form differential output terminal VOUTP0.

[0127]

[0128] In addition, current source I2 is the current source as a load unit, and current source I2 is connected to the drain terminal of NMOS transistor NM2 through switch SW4. In implementation, the drain terminal of NMOS transistor NM2 is connected to one end of switch SW9 and one end of switch SW4 to form a first connection terminal of a sub-load, and the first connection terminal of the sub-load is connected to the drain terminal of PMOS transistor PM5 to form differential output terminal VOUTP0. Figure 4 In addition, current source I2 is the current source as a load unit, and current source I2 is connected to the drain terminal of NMOS transistor NM2 through switch SW4. In implementation, the drain terminal of NMOS transistor NM2 is connected to one end of switch SW9 and one end of switch SW4 to form a first connection terminal of a sub-load, and the first connection terminal of the sub-load is connected to the drain terminal of PMOS transistor PM5 to form differential output terminal VOUTP0.

[0129] In addition, current source I2 is the current source as a load unit, and current source I2 is connected to the drain terminal of NMOS transistor NM2 through switch SW4. In implementation, the drain terminal of NMOS transistor NM2 is connected to one end of switch SW9 and one end of switch SW4 to form a first connection terminal of a sub-load, and the first connection terminal of the sub-load is connected to the drain terminal of PMOS transistor PM5 to form differential output terminal VOUTP0.

[0130] For Figure 4 For the limiting amplifier shown in FIG. 2, the corresponding sizes of the PMOS transistors PM0-PM3 are the same, the corresponding sizes of the PMOS transistors PM4-PM7 are the same, the corresponding sizes of the NMOS transistors NM0-NM9 are the same, and the corresponding output currents of the current sources I0-I3 are equal.

[0131] In particular implementation, when the switches SW2-SW8 are open and the switches SW9-SW12 are closed, at this time, the static currents ID0 flowing through the NMOS transistor NM0, the static current ID3 flowing through the NMOS transistor NM3, and the static current ID5 flowing through the NMOS transistor NM5 are the same, and the static currents ID1 flowing through the NMOS transistor NM1, the static current ID7 flowing through the NMOS transistor NM7, and the static current ID9 flowing through the NMOS transistor NM9 are the same, all of which are 0.5I0, i.e., half of the output current of the current source I0.

[0132] According to the formula of transconductance in the saturation region, there are: gmNM0=gmNM3=gmNM5=gmNM1=gmNM7=gmNM9, where gmNM0 is the transconductance of the NMOS transistor NM0, gmNM3 is the transconductance of the NMOS transistor NM3, gmNM5 is the transconductance of the NMOS transistor NM5, gmNM1 is the transconductance of the NMOS transistor NM1, gmNM7 is the transconductance of the NMOS transistor NM7, and gmNM9 is the transconductance of the NMOS transistor NM9. At this time, for the amplification gain of the limiting amplifier, there are:

[0133]

[0134] wherein, is the amplification gain of the limiting amplifier.

[0135] When the switches SW2-SW8 are closed and the switches SW9-SW12 are open, at this time, the current sources I1-I3 are all connected to the current limiting amplifier, and the static current ID0' flowing through the NMOS transistor NM0 is twice the original, i.e., ID0'=2ID0. Since the current source I2 divides the current, the currents flowing through the NMOS transistors NM2-NM8 remain unchanged, so there are: ID3'=ID3, ID5'=ID5, where ID3' is the current flowing through the NMOS transistor NM3, and ID5' is the current flowing through the NMOS transistor NM5.

[0136] Further, the NMOS transistor NM2 and the NMOS transistor NM4 are also connected in the limiting amplifier, at this time, the NMOS transistor NM2 and the NMOS transistor NM4 are connected in series with the NMOS transistor NM3, and the corresponding gate is connected, and the equivalent is that the corresponding conductive channel length L of the NMOS transistor NM3 and the NMOS transistor NM4 is doubled, at this time, the amplification gain of the current limiting amplifier is changed to 12dB.

[0137] In the above description, the specific way and process of configuring the amplification gain of the limiting amplifier are given by providing the load state of the single-stage amplification current source and the diode load. According to the amplification gain of the limiting amplifier, when the diode load unit is used, the transconductance of the diode load unit and the transconductance of the differential input tube can be offset when calculating the amplification gain, so as to further improve the accuracy of the amplification gain of the limiting amplifier.

[0138] It should be understood that the corresponding switch state of the above-mentioned switches SW2 to SW12 can be controlled by the above-mentioned register configuration, for example, when switching, the switch state of the switches SW2 to SW12 can be configured by configuring the value of the register, and the specific control mode can be selected as required, and the specific configuration of the amplification gain of the limiting amplifier is 12dB or 6dB.

[0139] In an embodiment of the present application, the wideband logarithmic detector further comprises a rectifier network, a low-pass filter, and a resistance calibration module for calibrating the summing resistor in the low-pass filter.

[0140] The rectifier network comprises a plurality of rectifiers, wherein the number of rectifiers in the rectifier network is one more than the number of limiting amplifiers in the limiting amplifier chain.

[0141] The input and output of the limiting amplifier are adaptively connected to a rectifier, and the rectifier adaptively connected to the input and output of the limiting amplifier is adaptively connected to the summing resistor in the low-pass filter to output the RSSI value of the detected signal through the low-pass filter.

[0142] After the summing resistor is calibrated by the resistance calibration module, the resistance value of the summing resistor matches the expected resistance value.

[0143] The same as the existing logarithmic detector is that the logarithmic detector also comprises a rectifier network and a low-pass filter, Figure 3The diagram illustrates an embodiment of a rectifier network and a low-pass filter. In the figure, the LPF represents the low-pass filter. The rectifier network includes several rectifiers. When the number of limiting amplifiers is 11, the number of rectifiers is 12. In the figure, the 12 rectifiers are rectifiers 1 to rectifier 12. The functions of the rectifiers in the rectifier network and the low-pass filter are consistent with existing low-pass filters. Figure 3 As explained above, a low-pass filter should include a summing resistor. Figure 3 The resistor R0 in the diagram is the summing resistor. The connection and coordination between the rectifiers and the summing resistor in the rectifier network can be consistent with existing technology, such as connecting the output terminals of all rectifiers to the summing resistor via an accumulator. It should be noted that... Figure 3 The accumulator that sums the outputs of all rectifiers is not shown in the diagram. It is understood that the accumulator can take the form of commonly used existing ones, and the method of using the accumulator to accumulate current can be consistent with existing technology, which will not be elaborated here.

[0144] As explained above, variations in the summing resistor's value due to manufacturing process deviations can affect the detection accuracy of the logarithmic detector. To improve the detection accuracy of the logarithmic detector, a resistor calibration module can be used to calibrate the summing resistor's value. The purpose of calibrating the summing resistor's value is to match it with the desired value. Matching the desired value specifically means that the two values ​​are identical, or that their difference is within an allowable range. The allowable value can be selected as needed, and will not be elaborated here.

[0145] In one embodiment of the present invention, the resistance calibration module includes a calibration current generation unit, a voltage comparator, a calibration signal generation unit, a multiplexer, and a reference resistor for providing the desired resistance, wherein...

[0146] One end of the summing resistor is connected to the output of the multiplexer, and the other end of the summing resistor is grounded.

[0147] The first selection terminal of the multiplexer is connected to the rectifier adapter in the rectifier network, and the second selection terminal of the multiplexer is connected to the inverting terminal of the voltage comparator.

[0148] The calibration current generating unit generates at least a first calibration current and a second calibration current of equal magnitude. The first calibration current and the second calibration current are applied to the non-inverting and inverting inputs of the voltage comparator, respectively, and the non-inverting input of the current comparator is also connected to the reference resistor.

[0149] When calibrating, the summing resistor and the inverting terminal of the voltage comparator are connected through the multiplexer, the voltage comparator loads the comparison result of the voltage comparator to the calibration signal generating unit to calibrate the resistance value of the summing resistor through the calibration signal generating unit until the resistance value of the summing resistor matches the expected resistance value provided by the reference resistor.

[0150] After calibration, the multiplexer is configured to connect the summing resistor and the rectifier in the rectifier network.

[0151] In order to realize resistance calibration, the resistance calibration module should include a calibration current generating unit, a voltage comparator, a calibration signal generating unit, a multiplexer and a reference resistor, wherein the calibration current generating unit can generate at least a first calibration current and a second calibration current with the same size, that is, at least the first calibration current and the second calibration current are used when calibrating the resistance value, and the following will be described in detail. Figure 5 The way and process of generating the first calibration current and the second calibration current by the calibration current generating unit are exemplified.

[0152] Figure 5 The calibration current generating unit can include an operational amplifier A11, a resistor R1, a PMOS tube PM8, a PMOS tube PM9 and a PMOS tube PM10, wherein the non-inverting terminal of the operational amplifier A11 is connected to a reference voltage Vref, the inverting terminal of the operational amplifier A11 is connected to one end of the resistor R1 and the drain terminal of the PMOS tube PM8, the other end of the resistor R1 is grounded, the output terminal of the operational amplifier A11 is connected to the gate terminal of the PMOS tube PM8, the gate terminal of the PMOS tube PM9 and the gate terminal of the PMOS tube PM10, and the source terminal of the PMOS tube PM8, the source terminal of the PMOS tube PM9 and the source terminal of the PMOS tube PM10 are connected to a power supply VDD.

[0153] Specifically, the reference voltage Vref can be generated by a bandgap reference. Based on the characteristics of the operational amplifier, the inverting terminal of the operational amplifier A11 can be clamped to the same potential, thereby generating a bias current I4 in the resistor R1. The PMOS tubes PM8-PM10 have the same size, therefore, according to the current mirror principle, a current I5 can be generated at the drain terminal of the PMOS tube PM9, and a current I6 can be generated at the drain terminal of the PMOS tube PM10, and I4=I5=I6, wherein the current I5 is the second calibration current, and the current I6 is the first calibration current.

[0154] Figure 5In the specific embodiment, the CMP is a voltage comparator, the non-inverting terminal of the voltage comparator is connected to the drain terminal of the PMOS transistor PM10, and the inverting terminal of the voltage comparator is connected to the drain terminal of the PMOS transistor PM9, so that the first calibration current is loaded to the non-inverting terminal of the voltage comparator and the second calibration current is loaded to the inverting terminal of the voltage comparator.

[0155] It should be noted that the reference resistor can be a high-precision resistor, and the reference resistor has a desired resistance value, that is, the reference resistor can provide a desired resistance value, and the reference resistor can provide a desired resistance value according to the needs, and the specific resistance value can meet the needs of RSSI detection, and the specific resistance value can form Figure 2 a desired resistance value. Generally, the reference resistor is located outside the chip, and the reference resistor is connected to the non-inverting terminal of the voltage comparator through a GPIO (General-Purpose Input / Output) port.

[0156] It should be noted that when the reference resistor is arranged outside the chip, the accuracy of the desired resistance value provided by the reference resistor can be ensured. When there are non-ideal factors, the resistance value of the summing resistor can also be calibrated to the vicinity of the desired resistance value. In addition, the voltage comparator and the drain terminal of the PMOS transistor PM10 can be connected to the reference resistor arranged outside the chip through the GPIO port, otherwise the current I6 cannot be output to the outside of the chip, and a corresponding voltage V2 cannot be generated. The GPIO port can adopt a form commonly used at present, and the specific form can meet the needs of generating the voltage V2.

[0157] In order to realize the resistance value calibration of the summing resistor, the resistance value of the summing resistor should be controllable, for example, the resistance value of the summing resistor can be controlled by a code value, and the code value for controlling the resistance value of the summing resistor is determined by a calibration signal generation unit. When the calibration control signal generated by the calibration signal generation unit, the calibration control signal should be based on the comparison result of the voltage comparator.

[0158] As can be seen from the above description, when the logarithmic detector is working, the summing resistor should be connected to the rectifier network, and when the resistance value of the summing resistor is calibrated, the summing resistor should be connected to the voltage comparator. In order to configure the connection of the summing resistor with the rectifier network and the voltage comparator, the summing resistor is connected to the inverting terminal of the voltage comparator through a multiplexer, and the connection of the summing resistor with the rectifier network or the voltage comparator can be configured through the multiplexer. When the resistance value of the summing resistor is calibrated, the summing resistor should be connected to the inverting terminal of the voltage comparator through the multiplexer, and after the calibration is completed, the summing resistor should be connected to the rectifier network, Figure 5 In the specific embodiment, the MUX is a multiplexer, R0 is the summing resistor, the digital calibration is the calibration signal generation unit mentioned above, and the capacitor C1 is the capacitor in the low-pass filter.

[0159] When the summing resistor is connected to the inverting terminal of the voltage comparator through the multiplexer during the calibration of the resistance value of the summing resistor, the current I5 flowing out of the drain terminal of the PMOS PM9 generates a voltage V1 through the summing resistor and loads the voltage V1 to the inverting terminal of the voltage comparator, and the current I6 flowing out of the drain terminal of the PMOS PM10 is connected to the reference resistor R2 through the GPIO port, thereby generating a voltage V2 loaded to the non-inverting terminal of the voltage comparator. Then, the voltage comparator compares the voltage V1 and the voltage V2, specifically:

[0160] When the voltage V2 is greater than the voltage V1, the voltage comparator outputs a high level; when the voltage V2 is less than the voltage V1, the voltage comparator outputs a low level. The calibration signal generation unit can output a calibration control signal according to the result of the voltage comparator to adjust the resistance value of the summing resistor until the resistance value of the summing resistor matches the resistance value of the expected resistor, at which time the calibration of the resistance value of the summing resistor is completed. It can be understood that after the resistance value of the summing resistor matches the resistance value of the expected resistor, the summing resistor should be connected to the rectifier network through the multiplexer and serve as a resistor in the low-pass filter. Then, the RSSI value corresponding to the to-be-detected signal can be obtained through the low-pass filter in which the summing resistor is located, so as to effectively avoid the output characteristic curve shift problem caused by the non-ideality of the summing resistor, Figure 3 and Figure 5 In the formula, RSSI is the RSSI value output by the low-pass filter.

[0161] In an embodiment of the present application, when the calibration signal generation unit calibrates the resistance value of the summing resistor, at least a bisection calibration method is used.

[0162] As can be seen from the above description, the resistance value of the summing resistor can be controlled by coding. For example, the bit width of the calibration control signal generated by the calibration signal generation unit can be 5, different code values correspond to different resistance values, and the control code value can be selected between 0 and 31. The bisection calibration method and process are described below by way of example.

[0163] In a feasible embodiment, when the bisection calibration method is used, the intermediate code value 15 is first taken. At this time, the voltage V1 generated based on the summing resistor is V1=I5*R0, and the voltage V2 is V2=I6*R2. When the voltage V2 is greater than the voltage V1, the voltage comparator outputs a high level. At this time, the upper half search is performed to generate a control code after the upper half search, such as the code value 23 which is the intermediate code value between the code value 15 and the code value 31. This code value will increase the resistance value of the summing resistor. Then, a new voltage V1 is generated, and the voltage comparator is used to compare the voltage V1 and the voltage V2. If the voltage V2 is still greater than the voltage V1, it indicates that the resistance value of the summing resistor is still low, and the upper half search is performed to the corresponding code value 27 (the intermediate value between 23 and 31) to adjust the resistance value of the summing resistor.

[0164] In the implementation, after adjusting the resistance value of the summing resistor, if the voltage V2 is less than the voltage V1, it indicates that the resistance value of the summing resistor is too high, and then the code value 19 (the intermediate value of 15 and 23) should be halved, and then the above calibration is performed.

[0165] It should be noted that such iterative iteration, each time according to the voltage comparator result, the search range is halved, and the target code value is gradually approached until the optimal code value is found, which makes the voltage V1 closest to the voltage V2, and the calibration is completed. At this time, the resistance value of the summing resistor can be matched with the expected resistance.

[0166] It can be understood that other ways can also be used to calibrate the resistance value of the summing resistor, which can be selected as needed. In the implementation, the resistance value of the summing resistor can be calibrated after selecting the limiting amplification gain, or the calibration can be performed before selecting the limiting amplification gain, and the calibration process is simple and reliable.

Claims

1. A broadband logarithmic detector, characterized in that, The wideband logarithmic detector includes a limiting amplifier link for limiting and amplifying the signal to be detected. The limiting amplifier link includes several limiting amplifiers cascaded in sequence, and the amplification gain of each limiting amplifier is configurable. Configure the number of limiting amplifier stages connected within the limiting amplifier link and the gain of each limiting amplifier stage to configure the limiting amplification gain of the limiting amplifier link. The limiting amplification gain includes a first limiting amplification gain or a second limiting amplification gain, wherein the value of the first limiting amplification gain is greater than the value of the second limiting amplification gain. When the limiting amplifier gain of the limiting amplifier link is the first limiting amplifier gain, the first stage of limiting amplifiers is connected, and each limiting amplifier provides a single stage of first amplification gain; When the limiting amplifier gain of the limiting amplifier link is the second limiting amplifier gain, a second-stage limiting amplifier is connected, and each limiting amplifier provides a single-stage second amplification gain; The first stage number is less than the second stage number, and the gain of the first stage amplification is greater than the gain of the second stage amplification; The limiting amplifiers in the limiting amplifier link are cascaded in a differential input and differential output configuration, wherein the limiting amplifiers are in a common-source cascode diode load gain amplification configuration based on a current mirror. The limiting amplifier includes a differential input pair and a single-stage amplification current source adapted to the differential input pair. Each differential input transistor in the differential input pair is connected to an input transistor load circuit. The input tube load circuit includes a load current mirror adapted to the differential input tube, a current buffer adapted to the load current mirror, and a diode load adapted to the current buffer. The connection point between the diode load and the current buffer forms a differential output terminal; When the amplification gain of the limiting amplifier is configured to the second amplification gain of a single stage, the current provided by the single-stage amplification current source and the load state provided by the diode load are configured so that the current flowing through each differential input transistor is the first operating current. When the amplification gain of the limiting amplifier is configured to the first amplification gain of a single stage, the current provided by the single-stage amplification current source and the load state provided by the diode load are configured so that the current flowing through each differential input transistor is the second operating current. The magnitude of the second operating current is twice the magnitude of the first operating current; When the two differential input transistors in the differential input pair are NMOS transistors, then the differential input transistors are a first differential input NMOS transistor and a second differential input NMOS transistor, wherein, The source terminals of the first differential input NMOS transistor and the second differential input NMOS transistor are both connected to a single-stage amplification current source, and the differential input signal is received through the gate terminals of the first differential input NMOS transistor and the second differential input NMOS transistor. The drain terminals of the first differential input NMOS transistor and the second differential input NMOS transistor are respectively adapted and connected to the load current mirror and current buffer in the load circuit of an input transistor. The single-stage amplified current source includes at least a current source I0 and a current source I1, wherein the current output by current source I0 is equal to the current output by current source I1. The current source I0 is configured to remain connected to the corresponding source terminals of the differential input first NMOS transistor and the differential input second NMOS transistor; When the amplification gain of the limiting amplifier is configured to be the second amplification gain of a single stage, the connection between the current source I1 and the corresponding source terminals of the differential input first NMOS transistor and the differential input second NMOS transistor is disconnected. When the amplification gain of the limiting amplifier is configured to the first amplification gain of a single stage, the current source I1 is configured to be connected to the corresponding source terminals of the differential input first NMOS transistor and the differential input second NMOS transistor.

2. The broadband logarithmic detector according to claim 1, characterized in that, The number of limiting amplifiers in the limiting amplifier link is not less than the second level; An intra-chain switch array is set within the limiting amplifier link to configure the access state of the limiting amplifier, so as to configure the number of limiting amplifier stages connected within the limiting amplifier link based on the switching state of the intra-chain switch array.

3. The broadband logarithmic detector according to claim 1, characterized in that, When the first limiting amplification gain is 72dB and the second limiting amplification gain is 66dB, then: The first stage has 6 stages, with a single-stage first amplification gain of 12dB, and the second stage has 11 stages, with a single-stage second amplification gain of 6dB.

4. The broadband logarithmic detector according to claim 1, characterized in that, The current buffer employs at least a common-gate amplifier, wherein... When a common-gate amplifier is used as the current buffer, the current buffer includes at least a first PMOS transistor and a second PMOS transistor, wherein... The drain terminal of the first PMOS transistor in the buffer is connected to the drain terminal of a differential input transistor, as well as the gate terminals of the first PMOS transistor and the second PMOS transistor in the load current mirror. The gate terminals of both the first and second PMOS transistors in the buffer are connected to a bias voltage V. bias The source terminal of the first PMOS transistor in the buffer is connected to the drain terminal of the first PMOS transistor in the current mirror. The source terminals of the first PMOS transistor in the current mirror and the second PMOS transistor in the current mirror are both connected to the power supply VDD. The drain terminal of the second PMOS transistor in the current mirror is connected to the source terminal of the second PMOS transistor in the buffer. The drain terminal of the second PMOS transistor in the buffer is connected to the diode load adapter.

5. The broadband logarithmic detector according to claim 1, characterized in that, The diode load comprises at least two sub-load units connected in series, wherein, For any sub-load unit, the sub-load unit includes a first load NMOS transistor and a second load NMOS transistor, wherein, The gate terminal of the first load NMOS transistor is connected to the gate terminal of the second load NMOS transistor and the drain terminal of the first load NMOS transistor via the first load switch to form the first sub-load connection terminal of the current sub-load unit. The first connection terminal of the sub-load is also connected to the source terminal of the first load NMOS transistor and the drain terminal of the second load NMOS transistor via the second load switch. The source terminal of the second load NMOS transistor forms the second connection terminal of the current sub-load unit. For any two series-connected sub-load units, along the series connection direction of the sub-load units, the second connection terminal of the sub-load of the previous sub-load unit is connected to the first connection terminal of the sub-load of the next sub-load unit. Located in the first sub-load unit of the series connection, the first connection terminal of the sub-load unit is adapted to be connected to the current buffer, and the first connection terminal of the sub-load unit is grounded through a load unit current source. The sub-load unit located at the end of the series connection has its second sub-load connection terminal grounded; When the amplification gain of the limiting amplifier is configured to the single-stage second amplification gain, the first load switch in each sub-load unit is configured to be in the open state, the second load switch is configured to be in the closed state, and the current source of the load unit is configured to be in the non-connected working state. When the amplification gain of the limiting amplifier is configured to the first amplification gain of a single stage, the first load switch in each sub-load unit is configured to be closed, the second load switch is configured to be open, and the current source of the load unit is configured to be connected and working.

6. The broadband logarithmic detector according to any one of claims 1 to 5, characterized in that, The wideband logarithmic detector also includes a rectifier network, a low-pass filter, and a resistor calibration module for calibrating the summing resistor within the low-pass filter. The rectifier network includes a plurality of rectifiers, wherein the number of rectifiers in the rectifier network is the number of limiting amplifiers in the limiting amplifier link plus 1; The input and output terminals of the limiting amplifier are both connected to a rectifier adapter, and the rectifiers connected to the input and output terminals of the limiting amplifier are both connected to the summing resistor in the low-pass filter, so that the RSSI value of the signal to be tested is output through the low-pass filter. After calibrating the summing resistor using the resistance calibration module, the resistance value of the summing resistor is matched with the desired resistance value.

7. The broadband logarithmic detector according to claim 6, characterized in that, The resistance calibration module includes a calibration current generation unit, a voltage comparator, a calibration signal generation unit, a multiplexer, and a reference resistor for providing the desired resistance. One end of the summing resistor is connected to the output of the multiplexer, and the other end of the summing resistor is grounded. The first selection terminal of the multiplexer is connected to the rectifier adapter in the rectifier network, and the second selection terminal of the multiplexer is connected to the inverting terminal of the voltage comparator. The calibration current generating unit generates at least a first calibration current and a second calibration current of equal magnitude. The first calibration current and the second calibration current are applied to the non-inverting and inverting inputs of the voltage comparator, respectively, and the non-inverting input of the current comparator is also connected to the reference resistor. During calibration, the summing resistor is selected and connected to the inverting input of the voltage comparator via a multiplexer. The voltage comparator loads the comparison result of the voltage comparator into the calibration signal generation unit, so that the resistance value of the summing resistor is calibrated by the calibration signal generation unit until the resistance value of the summing resistor matches the expected resistance value provided by the reference resistor. After calibration, configure the multiplexer to select the summing resistor and connect it to the rectifier adapter in the rectifier network.

8. The broadband logarithmic detector according to claim 7, characterized in that, The resistance value of the summing resistor is controlled by a code value; When the calibration signal generating unit calibrates the resistance value of the summing resistor, at least the binary calibration method should be used.

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