Substrate, semiconductor device and manufacturing method

Abstract

The invention relates to a substrate, a semiconductor device and a manufacturing method. The substrate comprises a core plate structure which comprises a plate core dielectric layer and first power ground plane layers located on the two opposite sides of the plate core dielectric layer; the interconnection structures are located on the two opposite sides of the core board structure, the interconnection structure on each side comprises thin film dielectric layers and metal layers which are alternately stacked, the thin film dielectric layers are located on the first power source ground plane layer, and the metal layers comprise signal layers and second power source ground plane layers which are alternately arranged; the plurality of bonding pads are at least positioned on the second power supply ground plane layer on one side of the core board structure and are used for welding a plurality of functional modules of the computing system; and the wire passes through the interconnection structure and the core board structure, is connected with the bonding pad, and is used for enabling the function modules to be interconnected on a signal layer or a power ground plane layer. According to the substrate, the signal, the power supply and the ground of each functional module are interconnected, the integrity of the signal and the power supply is ensured, welding is completed on the substrate, independent packaging is not needed, and power consumption is also reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a substrate, a semiconductor device and a manufacturing method. BACKGROUND

[0002] The server computing system includes CPU (central processing unit), DCU (deep computing processor), RAM (random access memory), HBM (high bandwidth memory), NAND SSD (non-volatile storage hard disk), IVR (integrated power module), network interface and various devices, which are interconnected with each other to form a complete system to work normally.

[0003] In the traditional technology, the key devices such as CPU, DCU, RAM and NAND SSD are first packaged, and then integrated on a large motherboard to complete the interconnection of each other to form a complete system at the motherboard level.

[0004] However, with the current high signal rate and high power consumption, the traditional technology requires packaging of high-speed signals of CPU, high-speed signals of DCU, and even RAM, NAND, etc., so it must pass through a large number of through holes and BGA (ball grid array) solder balls on the packaging substrate. These are impedance discontinuities in the signal link, which will cause a lot of reflections, resulting in high-speed signal integrity problems. SUMMARY

[0005] Therefore, it is necessary to provide a substrate, a semiconductor device and a manufacturing method capable of ensuring signal integrity in view of the above technical problems.

[0006] In a first aspect, the present application provides a substrate, comprising:

[0007] A core plate structure comprising a core plate dielectric layer and a first power ground plane layer located on opposite sides of the core plate dielectric layer;

[0008] An interconnection structure located on opposite sides of the core plate structure, the interconnection structure on each side comprising alternately stacked thin film dielectric layers and metal layers, the thin film dielectric layers being located on the first power ground plane layer, and the metal layers comprising alternately arranged signal layers and second power ground plane layers;

[0009] A plurality of pads located on at least the second power ground plane layer on one side of the core plate structure, for welding a plurality of functional modules of the computing system;

[0010] A wire trace passing through the interconnection structure and the core plate structure and connected to the pads, for interconnecting the functional modules in the signal layers or the power ground plane layers.

[0011] In one embodiment, the functional module includes a first functional module and a second functional module, the trace density between the first functional module and the second functional module is greater than or equal to a first density threshold, the first functional module and the second functional module are located on one side of the substrate, and the traces pass through a signal layer located on one side of the core board structure in the interconnect structure for signal interconnection and / or through a second power ground plane layer located on one side of the core board structure in the interconnect structure for power ground interconnection.

[0012] In one embodiment, the functional module includes a third functional module and a fourth functional module, the wiring density between the third functional module and the fourth functional module is less than a first density threshold, the third functional module and the fourth functional module are located on different sides of the substrate, and the wiring passes through each layer in the interconnect structure and each layer in the core board structure for signal interconnection and / or power ground interconnection.

[0013] In one embodiment, where the third and fourth functional modules are located on opposite sides of the substrate but not directly opposite each other, the trace is triggered from the pads of the third functional module, extends in the signal layer of the interconnect structure in a direction parallel to the substrate, such that the extended position is directly opposite the position of the pads of the fourth functional module, and passes through each layer of the interconnect structure and each layer of the core board structure for signal interconnection; and / or

[0014] When the third and fourth functional modules are located on opposite sides of the substrate, the trace is triggered from the pad of the third functional module, extends in the second power and ground plane layer of the interconnect structure in a direction parallel to the substrate, so that the extended position is directly opposite the position of the pad of the fourth functional module, and passes through each layer of the interconnect structure and each layer of the core board structure for power and ground interconnection.

[0015] In one embodiment, the bandwidth of the functional module is greater than a bandwidth threshold, and the substrate further includes a 2.5D packaging layer located between the functional module and the pads of the substrate; and / or the transistor density of the functional module is greater than a density threshold, and the substrate further includes a 3D packaging layer located between the functional module and the pads of the substrate.

[0016] In one embodiment, the substrate further includes a heat dissipation structure, the heat dissipation structure comprising:

[0017] The supporting structure has several mechanical through-holes for the heat sink.

[0018] A heat sink, wherein two opposite sides of the heat sink are in contact with one side of the substrate and the functional module, respectively;

[0019] Back plate, located on the other side of the substrate;

[0020] The radiator is fixed to the support structure by fasteners, the back plate, and several mechanical through holes for the radiator.

[0021] In one embodiment, the thickness of the support structure is greater than the thickness of the functional module, and the difference between the thickness of the support structure and the thickness of the functional module is between 10µm and 100µm.

[0022] Secondly, this application also provides a semiconductor device, the semiconductor device comprising:

[0023] The substrate in any of the above embodiments;

[0024] At least one functional module is soldered onto the substrate via pads on the substrate.

[0025] Thirdly, this application also provides a method for fabricating a semiconductor device, the method comprising:

[0026] The substrate is fabricated based on the chip design, and the substrate is the aforementioned substrate;

[0027] Based on the processed substrate, the mounting and reflow of each functional module are performed.

[0028] In one embodiment, the substrate fabrication based on the chip design includes:

[0029] The chip area and the target area are exposed by step exposure method, wherein the target area is the chip interconnect area with a wiring density greater than the density threshold;

[0030] The power supply area is exposed using a linear exposure method;

[0031] The transition area is double-exposed using both the step exposure method and the linear exposure method. The transition area is the area connecting the area corresponding to the step exposure method and the area corresponding to the linear exposure method.

[0032] In one embodiment, the interconnect structure of the substrate includes alternately stacked thin-film dielectric layers and metal layers; the method further includes:

[0033] After each thin-film dielectric layer and each metal layer of the substrate are processed, the image connection lines are automatically detected by optical means, and the target area is electrically tested by an electrical fixture. The target area is a chip interconnect area with a wiring density greater than a density threshold.

[0034] In one embodiment, the mounting and reflow of various functional modules based on the processed substrate includes:

[0035] The back side of the processed substrate is then fitted with each functional module and reflowed.

[0036] Open / short circuit tests are performed on each of the functional modules on the back side of the substrate. If the open / short circuit test results for each of the functional modules on the back side of the substrate are passed, adhesive is applied to the bottom of each of the functional modules on the back side of the substrate. If the open / short circuit test results for each of the functional modules on the back side of the substrate are failed, the functional modules on the back side of the substrate that failed the open / short circuit test are reworked.

[0037] The front side of the processed substrate is then fitted with each functional module and reflowed.

[0038] Open / short circuit tests are performed on each of the functional modules on the front side of the substrate. If the open / short circuit test results for each of the functional modules on the front side of the substrate are passed, adhesive is applied to the bottom of each of the functional modules on the front side of the substrate. If the open / short circuit test results for each of the functional modules on the front side of the substrate are failed, the functional modules on the front side of the substrate that failed the open / short circuit test are reworked.

[0039] In one embodiment, after the fabricated substrate undergoes surface mounting and reflow of each of the functional modules, the process includes:

[0040] The support structure is fixed to one side of the substrate;

[0041] The heat sink is fixed to the front of the support structure by means of fasteners and a back plate corresponding to the heat sink, and the back plate is in contact with the other side of the substrate.

[0042] In one embodiment, the method further includes at least one of the following:

[0043] Based on the chip design, the symmetry of the metal content in the horizontal region and the upper and lower layer regions of the substrate is determined;

[0044] The substrate layers are pressed together using a jig;

[0045] During the mounting and reflow processes of each of the aforementioned functional modules, a fixture is used to press together portions of the substrate without components.

[0046] In one embodiment, each functional module includes a connector; the process based on the fabricated substrate, after surface mounting and reflow of each functional module, includes:

[0047] Connect each connector of the testing machine to the connector on each of the substrates, and obtain the temperature of each functional module on the substrate through the temperature control head of the testing machine;

[0048] The semiconductor device is tested based on the temperature of each of the aforementioned functional modules.

[0049] The aforementioned substrate, semiconductor device, and fabrication method include: a core board structure comprising a core dielectric layer and first power / ground plane layers located on opposite sides of the core dielectric layer; interconnection structures located on opposite sides of the core board structure, each side of the interconnection structure comprising alternately stacked thin film dielectric layers and metal layers, the thin film dielectric layers being located on the first power / ground plane layers, and the metal layers comprising alternately arranged signal layers and second power / ground plane layers; multiple pads located at least on the second power / ground plane layer on one side of the core board structure for soldering multiple functional modules of the computing system; and traces passing through the interconnection structures and the core board structure and connected to the pads for interconnecting the functional modules on the signal layers or power / ground plane layers. This large substrate, with pads for each functional module, interconnects all signals, power, and ground on the substrate, ensuring signal and power integrity. Soldering is completed on the large substrate, eliminating the need for separate packaging and reducing power consumption. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the substrate structure in one embodiment;

[0052] Figure 2 This is a schematic diagram of the wiring in one embodiment;

[0053] Figure 3 This is a schematic diagram of the substrates for each functional module that have been patched and reflowed in one embodiment;

[0054] Figure 4 This is a schematic diagram of the support structure in one embodiment;

[0055] Figure 5 This is a schematic diagram of a packaged semiconductor device in one embodiment;

[0056] Figure 6 This is a schematic diagram of the front of a semiconductor device in one embodiment;

[0057] Figure 7 This is a schematic diagram of the back side of a semiconductor device in one embodiment;

[0058] Figure 8 This is a flowchart of a semiconductor device fabrication method in one embodiment.

[0059] The components are as follows: 100 Core board structure, 101 Core dielectric layer, 102 First power and ground plane layer, 200 Interconnect structure, 210 Thin film dielectric layer, 220 Signal layer, 230 Second power and ground plane layer, 300 Trace, 400 Heat dissipation structure, 401 Support structure, 402 Mechanical via, 403 Backplane, 500 Functional module, 501 Connector, 502 3D RAM (front), 503 CPU, 504 IO chip, 505 HBM, 506 DCU, 507 2.5D package layer, 508 3D NAND SSD (front), 509 IVR (front), 510 Optoelectronic co-package, 511 IVR (back first), 512 3D RAM (back), 513 3D NAND SSD (back), 514 IVR (back second). Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] It should be noted that the terms "comprising" and "having," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusion. The term "multiple" as used in this application refers to two or more.

[0062] To facilitate understanding, the technical terms involved in this application will be explained first: CPU refers to Central Processing Unit, DCU refers to Deep Computing Processor, HBM refers to High Bandwidth Memory, IVR refers to Integrated Power Module, RAM refers to Random Access Memory, NAND SSD refers to Non-Volatile Hard Disk Drive, CPO refers to Co-packaged Optoelectronics, BGA refers to Ball Grid Array, MCM refers to Multi-Module Integration, Chiplet refers to Chip Packaging, PHY refers to High Speed ​​Interconnect Interface, DDR refers to Parallel Data, SerDes refers to Serial Data, CoW is an abbreviation for Chipon Wafer, referring to a module, and c4 bump refers to Controlled Collapse Chip Connector Bump.

[0063] The target system involved in this application can be a server computing system, which includes various functional modules, including but not limited to CPU (Central Processing Unit), DCU (Depth Computing Processor), RAM (Random Access Memory), HBM (High Bandwidth Memory), NAND SSD (Non-Volatile Hard Disk Drive), IVR (Integrated Power Module), opto-co-packaged CPO, and connectors, etc.

[0064] In traditional technologies, key functional modules of the target system, such as the CPU, DCU, RAM, and NAND SSD, are first packaged and then integrated onto a large motherboard. Interconnection between these modules is then completed at the motherboard level to form a complete system. However, as the target signal rate and power consumption increase, this approach presents at least the following problems:

[0065] First, key functional modules such as the CPU and DCU require a large amount of data transmission, which places extremely high demands on data bandwidth and speed. However, high-speed signals are very sensitive to impedance discontinuities in the link. Traditional solutions require packaging for high-speed signals from the CPU, DCU, RAM, NAND, etc. This inevitably involves a large number of vias on the packaging substrate and solder balls in the BGA (Ball Grid Array). These are impedance discontinuities in the signal link, which can cause a large number of reflections and lead to high-speed signal integrity problems. At the same time, due to the high requirements for the link, the area and power consumption of the chip's high-speed interconnect interface PHY are also relatively large.

[0066] Secondly, the clock speed and computational load of key functional modules such as CPU and DCU have increased significantly, and the power consumption required has increased significantly to hundreds of watts or even thousands of watts. The corresponding power supply current has also increased significantly to hundreds of amperes or even thousands of amperes. Due to the additional packaging, the power supply link length has increased, which in turn has increased the DC loss on the link. According to the power formula, the power loss of the link is equal to the DC resistance multiplied by the square of the current. Therefore, the DC power loss brought by the link is proportional to the square of the current. Even if the link is only tens of milliohms or even a few milliohms, the DC loss on the link will reach tens of watts. At the same time, because the power supply module is far away from the power-consuming device, the power supply ripple is also large, which leads to power integrity issues.

[0067] Third, the traditional method involves packaging the chip first and then integrating it onto the motherboard. This process requires a high-temperature soldering step during packaging, and another high-temperature soldering step during integration onto the motherboard. As the integration density of CPUs and DCUs increases, their area also increases. Each high-temperature soldering step causes greater warping of the chip and package, leading to a significant increase in reliability risks and a decrease in yield.

[0068] To address at least one of the aforementioned technical problems in conventional technologies, this application provides a substrate, combined with... Figure 1As shown, the substrate includes a core board structure 100, an interconnect structure 200, multiple pads (not shown in the figure), and traces 300.

[0069] The size of the substrate is determined based on the machine's capabilities; for example, the substrate size can be less than or equal to 512 mm. The substrate size is 512 mm. In other embodiments, the substrate size may be determined to be in other ranges based on the machine's capabilities, and no specific limitation is made here. The dimensions of the core board structure 100 and the interconnect structure 200 in the substrate are the same as the substrate size.

[0070] The core board structure 100 includes a core dielectric layer 101 and a first power ground plane layer 102 located on opposite sides of the core dielectric layer 101.

[0071] Interconnection structures 200 are located on opposite sides of the core board structure 100. Each side of the interconnection structure 200 includes alternately stacked thin film dielectric layers 210 and metal layers. The thin film dielectric layers 210 are located on the first power ground plane layer 102, and the metal layers include alternately arranged signal layers 220 and second power ground plane layers 230.

[0072] Combination Figure 2 As shown, Figure 2 This is a schematic diagram of the core board structure 100 and interconnect structure 200 in a substrate according to one embodiment. The interconnect structure 200 serves as an add-on layer to the core board structure 100. The substrate has an NMN structure, where the first N represents the number of metal layers on one side of the core board structure 100 in the interconnect structure 200, and the second N represents the number of metal layers on the other side of the core board structure 100 in the interconnect structure 200. The number of metal layers on both sides of the core board structure 100 can be the same or different, and no specific limitation is made here. The M in the NMN structure represents the number of metal layers in the core board structure 100, which is also the number of the first power and ground plane layers 102. M is usually two layers, meaning that the two first power and ground plane layers 102 are located on opposite sides of the core dielectric layer 101.

[0073] In one optional embodiment, N and M in the NMN structure are determined by stacking planning based on the number of layers required for each signal and power / ground in the target system. A thin film dielectric layer 210 is disposed between adjacent metal layers, thereby forming alternating stacked thin film dielectric layers 210 and metal layers. The first power / ground plane layer 102 consists of a thin film dielectric layer 210, followed by a metal layer, and then another thin film dielectric layer 210, until the number of layers reaches the number planned in the stacking plan.

[0074] In order to ensure the quality of high-speed signals, since high-speed signals usually adopt striplines, that is, a structure in which a signal plane is sandwiched between two power and ground planes, this application confirms the signal spacing and line width, as well as the thickness of the metal layer and thin film dielectric layer 210 through pre-simulation. Each signal layer needs to be referenced, recirculated, and isolated by a corresponding power and ground plane. Thus, an interconnection structure 200 is formed with alternating signal layers 220 and second power and ground plane layers 230, that is, one power and ground plane layer and one signal layer.

[0075] In some optional embodiments, the thickness of the metal layer of the interconnect structure 200 is between 10 micrometers and 20 micrometers, the thickness of the thin film dielectric layer 210 is between 20 micrometers and 40 micrometers, the thickness of the metal layer of the core board structure 100, namely the first power ground plane layer 102, is between 10 micrometers and 100 micrometers, and the thickness of the core dielectric layer is greater than 1.4 micrometers.

[0076] Among them, the combination Figure 2 As shown, the first power ground plane layer 102 typically consists of two layers. The core dielectric layer corresponding to the first power ground plane layer 102 serves to insulate and reduce warpage. Therefore, it is made of materials with a small coefficient of thermal expansion and a large Young's modulus, and with a relatively large thickness. For example, the thickness of the core dielectric layer is greater than 1.4 micrometers, such as 1.5 micrometers, 2 micrometers, etc. The thickness of the first power ground plane layer 102 is between 10 micrometers and 100 micrometers, such as 15 micrometers, 20 micrometers, 50 micrometers, or 75 micrometers, etc., without specific limitations.

[0077] The thin-film dielectric layer 210, as an insulating dielectric layer, is typically thin, with a thickness between 20 and 40 micrometers, such as 25, 30, 34, or 38 micrometers, etc., without specific limitations. Furthermore, to reduce high-speed signal loss and substrate warping, materials with low dielectric loss and low coefficient of thermal expansion are used whenever possible. The metal layer of the interconnect structure 200 is also relatively thin, generally between 10 and 20 micrometers, such as 12, 15, or 18 micrometers, without specific limitations.

[0078] Each core board structure 100 and each layer in the interconnect structure 200 are vertically connected through laser holes (typically 60µm).

[0079] Furthermore, each metal layer involved in this application may be a copper layer.

[0080] Multiple pads are located at least on the second power ground plane layer 230 on one side of the core board structure 100 for soldering multiple functional modules 500 of the computing system. The pads include controllable collapse chip connection bump pads and / or ordinary pads corresponding to each functional module 500. The controllable collapse chip connection bump pads can be used for soldering chip-type functional modules 500. For example, CPUs and DCUs (typically using 2.5D packaging to co-package DCU chips with HBM as CoW) are soldered onto the substrate using the controllable collapse chip connection bump pads, while modules such as IVRs, 3D RAMs, 3D NAND SSDs, optoelectronic co-packaged CPOs, and connectors are soldered onto the substrate using ordinary pads.

[0081] The metal layer of the interconnect structure 200 can be completed by fine traces 300 to fan out the controllable collapse chip connection bump pad c4 bump (usually 8um-12um due to the small space at c4 bump) and connect (after fan-out, if there is enough space, the line width can be enlarged to tens of micrometers, such as 10 micrometers, 40 micrometers, etc., to reduce signal loss, but no specific limit is made here).

[0082] Trace 300 passes through interconnect structure 200 and core board structure 100, and connects to pads, for interconnecting functional modules 500 on signal layer 220 or power / ground plane layer. Figure 1 As shown, the trace 300 is connected to the pad and can pass through the interconnect structure 200 and the core board structure 100 inside the substrate to realize the signal, power and ground interconnection of each functional module 500, so as to ensure the integrity of signals and power.

[0083] In some alternative embodiments, the thickness and number of each layer of the substrate need to be designed in advance. After the layers of the substrate are determined, the interconnection of each functional module 500 of the target system can be completed in the interconnection structure 200 through the traces 300.

[0084] One point to note is that this application does not limit the number of each functional module 500, for example, it does not limit the number of chips such as CPU, DCU, and connectors. Figure 3 As shown, the substrate may include multiple IVRs, 3DRAMs and 3D NAND SSDs. In other embodiments, the substrate may also include other numbers of functional modules 500. The number of each functional module 500 only needs to be determined according to the configuration requirements, and the chip and substrate are designed and provided, and the integration is completed by packaging.

[0085] This large substrate has 500 pads for each functional module of the target system. All signals, power supplies, and grounds are interconnected on the substrate, ensuring signal and power integrity. Soldering is completed on the large substrate, eliminating the need for separate packaging and reducing power consumption (also known as "large-scale integration technology"). High-speed signals no longer need to go through BGA balls and motherboard vias, reducing many impedance discontinuities, which is very beneficial for high-speed signal integration. The chip does not need BGA balls, and the entire back of the large substrate can be fitted with capacitors. This brings the IVR and back decoupling capacitors closer to the chip, which is very beneficial for high-power voltage drop and PI. The integration is high, some PHYs are close together, speed is increased, and power consumption is reduced.

[0086] In some optional embodiments, the functional module 500 includes a first functional module and a second functional module, the density of the traces 300 between the first functional module and the second functional module is greater than or equal to a first density threshold, the first functional module and the second functional module are located on one side of the substrate, and the traces 300 pass through the signal layer 220 located on one side of the core board structure 100 in the interconnect structure 200 for signal interconnection and / or through the second power ground plane layer 230 located on one side of the core board structure 100 in the interconnect structure 200 for power ground interconnection.

[0087] The position of the functional module 500 in the substrate is related to the density of the traces 300 between the functional modules 500. When the density of the traces 300 between the functional modules 500 is greater than or equal to a first density threshold, the first functional module and the second functional module are located on one side of the substrate, and the traces 300 pass through the signal layer 220 located on one side of the core board structure 100 in the interconnect structure 200 for signal interconnection and / or through the second power ground plane layer 230 located on one side of the core board structure 100 in the interconnect structure 200 for power ground interconnection.

[0088] Among them, the combination Figure 3 As shown, when the first functional module is connector 501 and the second functional module is CPU 503, signal interconnection is required between connector 501 and CPU 503, and the trace density 300 between them is greater than or equal to a first density threshold. Therefore, the trace 300 between connector 501 and CPU 503 passes through the second power ground plane layer 230 and the thin film dielectric layer 210, and then is routed in a signal layer 220 to face CPU 503, and then passes through the aforementioned thin film dielectric layer 210 and the second power ground plane layer 230 to achieve signal interconnection with CPU 503. Different adjacent trace segments 300 are perpendicular to each other.

[0089] In other embodiments, when the first functional module is CPU 503 and the second functional module is IO chip 504, power ground interconnection is required between CPU 503 and IO chip 504, and the density of the trace 300 between them is greater than or equal to the first density threshold. Therefore, the trace 300 between CPU 503 and IO chip 504 passes through the second power ground plane layer 230 to achieve power ground interconnection.

[0090] In other embodiments, the first functional module is DCU506, the second functional module is IO chip 504, and the two are interconnected by power and ground. The density of the trace 300 between the two is greater than or equal to a first density threshold. Therefore, the trace 300 between DCU506 and IO chip 504 passes through the second power and ground plane layer 230 to achieve power and ground interconnection.

[0091] In other embodiments, the first functional module is a 3D NAND SSD (front side) 508, and the second functional module is an I / O chip 504. The two are interconnected by a signal, and the density of the traces 300 between them is greater than or equal to a first density threshold. Therefore, the traces 300 between the 3D NAND SSD (front side) 508 and the I / O chip 504 pass through the second power / ground plane layer 230 and the thin-film dielectric layer 210, then are routed in a signal layer 220 to face the I / O chip 504, and then pass through the aforementioned thin-film dielectric layer 210 and the second power / ground plane layer 230 to achieve signal interconnection with the I / O chip 504. Different adjacent trace segments 300 are perpendicular to each other.

[0092] In other embodiments, the first functional module is a 3D NAND SSD (front side) 508, the second functional module is an IVR (front side) 509, and the two are interconnected by a power ground. The density of the trace 300 between the two is greater than or equal to a first density threshold. Therefore, the trace 300 between the 3D NAND SSD (front side) 508 and the IVR (front side) 509 passes through the second power ground plane layer 230 to achieve a power ground interconnect.

[0093] In other embodiments, the first functional module is DCU506, the second functional module is opto-co-package 510, the two are interconnected by power and ground, and the density of the trace 300 between them is greater than or equal to a first density threshold. Therefore, the trace 300 between DCU506 and opto-co-package 510 passes through the second power and ground plane layer 230 to achieve power and ground interconnection.

[0094] In some optional embodiments, the functional module 500 includes a third functional module and a fourth functional module, the wiring 300 between the third functional module and the fourth functional module has a density less than a first density threshold, the third functional module and the fourth functional module are located on different sides of the substrate, and the wiring 300 passes through each layer in the interconnect structure 200 and each layer in the core board structure 100 for signal interconnection and / or power ground interconnection.

[0095] The position of the functional module 500 in the substrate is related to the density of the traces 300 between the functional modules 500. When the density of the traces 300 between the functional modules 500 is less than the first density threshold, the first functional module and the second functional module are located on different sides of the substrate. In order to achieve signal interconnection, the traces 300 need to pass through the interconnection structure 200 and the core board structure 100.

[0096] Among them, the combination Figure 3 As shown, when the third functional module is connector 501 and the fourth functional module is IVR (first on the back) 511, the two are interconnected by signals, and the density of the traces 300 between them is less than the first density threshold. Therefore, the traces 300 between connector 501 and IVR (first on the back) 511 pass through the interconnection structure 200 and the core board structure 100 to achieve signal interconnection.

[0097] In other embodiments, when both the third and fourth functional modules are 3D RAMs (e.g., the third functional module is a 3D RAM (front) 502 and the fourth functional module is a 3DRAM (back) 512), they are interconnected by signals, and the density of the traces 300 between them is less than a first density threshold. Therefore, the traces 300 between the two 3D RAMs pass through the interconnect structure 200 and the core board structure 100 to achieve signal interconnection.

[0098] In other embodiments, when both the third and fourth functional modules are 3D NAND SSDs (e.g., the third functional module is a 3D NAND SSD (front side) 508 and the fourth functional module is a 3D NAND SSD (back side) 513), they are interconnected by signals, and the density of the traces 300 between them is less than a first density threshold. Therefore, the traces 300 between the two 3D NAND SSDs pass through the interconnect structure 200 and the core board structure 100 to achieve signal interconnection.

[0099] In other embodiments, when the third functional module is DCU506 and the fourth functional module is IVR (second on the back) 514, the two are interconnected by signals, and the density of the traces 300 between them is less than the first density threshold. Therefore, the traces 300 between DCU506 and IVR (second on the back) 514 pass through the interconnect structure 200 and the core board structure 100 to achieve signal interconnection.

[0100] In some optional embodiments, taking the third functional module as DCU506 and the fourth functional module as IVR (second on the back) 514 as an example, the two are located on opposite sides of the substrate, and the position of the trace 300 needs to be optimized.

[0101] In some optional embodiments, when the third and fourth functional modules are located on opposite sides of the substrate, the trace 300 is triggered from the pads of the third functional module, extends in the signal layer 220 of the interconnect structure 200 in a direction parallel to the substrate, so that the extended position is directly opposite the position of the pads of the fourth functional module, and passes through each layer of the interconnect structure 200 and each layer of the core board structure 100 for signal interconnection; and / or when the third and fourth functional modules are located on opposite sides of the substrate, the trace 300 is triggered from the pads of the third functional module, extends in the second power ground plane layer 230 of the interconnect structure 200 in a direction parallel to the substrate, so that the extended position is directly opposite the position of the pads of the fourth functional module, and passes through each layer of the interconnect structure 200 and each layer of the core board structure 100 for power ground interconnection.

[0102] If the third functional module and the fourth functional module are interconnected by signals, then the trace 300 extends in the signal layer 220 in a direction parallel to the substrate. If the third functional module and the fourth functional module are interconnected by power and ground, then the trace 300 extends in the power and ground layer in a direction parallel to the substrate.

[0103] Combination Figure 3 As shown, the third functional module is DCU506, and the fourth functional module is IVR (second back side) 514. The trace 300 starts from the pad of DCU506, passes through the interconnect structure 200 and core board structure 100 on one side of the substrate, and extends in the trace 300 layer of the interconnect structure 200 on the other side of the substrate in a direction parallel to the substrate, so that the extended position is directly opposite to the position of the pad of IVR (second back side) 514, and passes through each layer of the interconnect structure 200 to connect with the pad of IVR (second back side) 514.

[0104] In the above embodiments, the density of the traces 300 between the functional modules 500 determines whether the functional modules 500 are on one side or both sides of the substrate. In addition, the layer where the traces 300 are located is determined based on whether the functional modules 500 are signal interconnects or power / ground interconnects, thus realizing the interconnection between the functional modules 500.

[0105] In some optional embodiments, the bandwidth of the functional module 500 is greater than a bandwidth threshold, and the substrate further includes a 2.5D packaging layer 507 located between the functional module 500 and the substrate pads; and / or the transistor density of the functional module 500 is greater than a density threshold, and the substrate further includes a 3D packaging layer located between the functional module 500 and the substrate pads.

[0106] Combination Figure 3 As shown, when the bandwidth of functional module 500 is greater than the bandwidth threshold, functional module 500 is encapsulated through a 2.5D encapsulation layer 507, for example... Figure 3 In this case, the DCU506 chip and HBM505 are typically packaged together in a CoW (CoW) configuration using 2.5D packaging. In other embodiments, the transistor density of the functional module 500 is greater than a density threshold, and the substrate further includes a 3D packaging layer located between the functional module 500 and the substrate pads.

[0107] One point to note is that there is no limit to the number of IO dies and core dies in each CPU, and there is no limit to the 2D, 2.5D, or 3D packaging used, as long as the final C4 bump is provided for this application; multiple DCUs are also allowed, with any number of DCU dies and HBMs in each DCU, and there is no limit to the 2D, 2.5D, or 3D packaging used, as long as the final C4 bump is provided for this application; any number of conversion chips can also be added, and there is no limit to the 2D, 2.5D, or 3D packaging used, as long as the final C4 bump is provided for this application.

[0108] Since the substrate is no longer soldered onto the motherboard, heat dissipation of the corresponding functional module 500 needs to be performed directly on the substrate. The functional module 500 includes chips with power consumption greater than the power consumption threshold. The power consumption threshold can be determined based on the actual situation and no specific restrictions are imposed here.

[0109] To accommodate the large substrate, this application requires designing the connector 501, the position of the heat sink mechanical via 402 and the metal support ring, the signal and power flow direction (shortest signal and power flow direction), and the requirements of subsequent soldering processes (including the spacing between dies (chips), the requirements for dispensing edges and overflow edges, the distance between dies and capacitors, and the optical positioning points).

[0110] In one alternative embodiment, the substrate further includes a heat dissipation structure 400, combined with Figure 4 As shown, the heat dissipation structure 400 includes: a support structure 401, a heat sink, and a back plate 403. The support structure 401 has a plurality of heat sink mechanical through holes 402. The two opposite sides of the heat sink are in contact with one side of the substrate and the functional module 500, respectively. The back plate 403 is located on the other side of the substrate. The heat sink is fixed to the support structure 401 by fasteners, the back plate 403, and the plurality of heat sink mechanical through holes 402. Figure 5 As shown, Figure 5 The location of the heat dissipation structure 400 is provided. In other embodiments, heat sinks can be provided on both sides of the substrate. In some other embodiments, a heat sink is provided only on one side of the substrate, and a high-power functional module 500, such as a functional module 500 with power consumption greater than a power consumption threshold, can be soldered onto the side of the substrate where the heat sink is provided.

[0111] The support structure 401 can be a support ring. Optionally, the material of the support structure 401 can be metal. The mechanical through hole 402 of the heat sink and the support structure 401 are located around the functional module 500 to ensure sufficient clamping force of the heat sink and reduce thermal resistance.

[0112] The radiator can be a finned radiator or the like, without any specific limitation. The radiator is fixed by a fastener passing through the mechanical through-hole 402 and the back plate 403.

[0113] In the above embodiments, a heat sink mechanical through hole 402 is provided in the support structure 401, which can improve the integration density, reduce the area occupied by the mechanism, and at the same time play the functions of supporting the heat sink, locking the heat sink, and overcoming warping.

[0114] In one optional embodiment, the thickness of the support structure 401 is greater than the thickness of the functional module 500, and the difference between the thickness of the support structure 401 and the thickness of the functional module 500 is between 10 μm and 100 μm. Specifically, the support structure 401 is a metal support ring, and the thickness of the metal support ring is 10 μm to 100 μm greater than the thickness of the functional module 500, such as 15 μm, 50 μm, 75 μm, etc., without specific limitation. The greater thickness of the support structure 401 can ensure the support function of the support structure 401 for the heat sink and prevent the functional module 500 from bearing excessive pressure.

[0115] In some alternative embodiments, the width of the support structure 401 is determined through stress simulation, the goal of which is to ensure that substrate warping meets preset conditions. This is done to prevent substrate warping.

[0116] In one alternative embodiment, the distance between the heat sink mechanical via 402 and the trace 300 of the high-speed signal in the target system is greater than a distance threshold.

[0117] In one alternative embodiment, the material, size, and shape of the backplate 403 may be the same as or different from the material, size, and shape of the support structure 401.

[0118] Among them, the heat sink mechanical via 402 must maintain a certain distance from the subsequent high-speed signal trace 300 to avoid interference with the high-speed signal.

[0119] In order to increase the integration density and reduce the area occupied by the mechanism, several heat sink mechanical through holes 402 are opened in the support structure 401, so that it can simultaneously support the heat sink, lock the heat sink and overcome warping. The back plate 403 on the back of the substrate can be made of metal or other materials. Its size and shape do not need to be the same as the support structure 401 on the front of the substrate. Its main function is to lock the heat sink and overcome warping, and it does not need to provide support.

[0120] In some optional embodiments, this application also provides a semiconductor device, combined with Figure 6 and Figure 7 As shown, Figure 6 This is a schematic diagram of the front side of a semiconductor device in one embodiment. Figure 6 This is a schematic diagram of the back side of a semiconductor device in one embodiment; the semiconductor device includes: a substrate as described in any of the above embodiments and at least one functional module 500. The functional module 500 is soldered onto the substrate via pads on the substrate and interconnected via a core structure 100 and an interconnect structure 200 of the substrate.

[0121] The size of the substrate is determined based on the machine's capabilities; for example, the substrate size can be less than or equal to 512 mm. 512 mm. In other embodiments, the substrate size may be determined to be other ranges based on the machine's capabilities, and no specific limitation is made here.

[0122] The limitations of functional module 500 can be found above and will not be repeated here.

[0123] In this way, each module is soldered onto the substrate via pads, and the signals and power grounds of each functional module 500 are interconnected inside the substrate to ensure the integrity of signals and power.

[0124] One point to note is that this application does not limit the number of each module. For example, it does not limit the number of chips such as CPU, DCU, and connectors. It only requires designing and providing chips and substrates according to configuration requirements, and then packaging and integrating them.

[0125] The aforementioned semiconductor device comprises only one large substrate with pads for the various functional modules of the target system. All signals, power supplies, and grounds are interconnected on the substrate, ensuring signal and power integrity. Soldering is completed on the large substrate, eliminating the need for separate packaging and reducing power consumption. High-speed signals no longer require BGA balls and motherboard vias, reducing impedance discontinuities and significantly benefiting high-speed signal integration. The chip eliminates the need for BGA balls, allowing capacitors to be mounted entirely on the back of the large substrate. This brings the IVR and back-side decoupling capacitors closer to the chip, which is highly advantageous for high-power voltage drops and high-integration devices (PIs). The high integration density, with some PHYs located close together, leads to increased speed and reduced power consumption.

[0126] In one exemplary embodiment, such as Figure 8 As shown, this application also provides a method for fabricating a semiconductor device, including steps 802 to 804. Wherein:

[0127] S802: The substrate is processed based on the chip design, and the substrate is the substrate in any of the above embodiments.

[0128] S804: Based on the processed substrate, perform surface mount and reflow of various functional modules.

[0129] The substrate has pads for each functional module of the target system. The signals, power and ground of each functional module are interconnected on the substrate to ensure signal and power integrity. The soldering is completed on the substrate, eliminating the need for separate packaging and reducing power consumption.

[0130] After the chip design is completed, the semiconductor device needs to be manufactured. The substrate needs to be processed. Because the substrate is large, high-precision control and higher cleanliness are required for both the equipment and the environment to reduce the defect rate.

[0131] In one optional embodiment, the substrate is processed based on the chip design, including: exposing the chip area and the target area by step exposure, wherein the target area is a chip interconnect area with a wiring density greater than a density threshold; exposing the power supply area by linear exposure; and performing double exposure on the connection area by step exposure and linear exposure, wherein the connection area is the area connecting the area corresponding to the step exposure method and the area corresponding to the linear exposure method.

[0132] In this application, for the critical exposure process of each stack of the substrate (wherein, the stack includes each layer in the core board structure and each layer in the interconnect structure, referred to as a stack for convenience), a regional exposure method is adopted. For example, a step-out exposure method is used for the chip area and the target area. This step-out exposure method can improve the exposure accuracy. The target area is the chip interconnect area where the wiring density is greater than the density threshold. For power supply areas such as IVR, a linear exposure machine is used to compensate for the exposure speed, thereby comprehensively considering the processing cycle, cost, and yield. For the high-precision step-out and linear exposure junction area, dual exposure is used to ensure the superposition and alignment accuracy of the junction area.

[0133] The step exposure method transfers the pattern on the reticle to the wafer surface by repeatedly exposing it in steps. Specifically, the wafer is divided into multiple exposure fields, which are aligned and exposed one by one until the entire wafer is covered.

[0134] Linear exposure achieves pattern transfer through the synchronous scanning motion of the mask and the wafer. Specifically, the mask (reticle) and the wafer move synchronously during the exposure process, and the light source illuminates through the slit, scanning line by line to complete the pattern transfer of the entire exposure field.

[0135] In one optional embodiment, the interconnect structure of the substrate includes alternately stacked thin film dielectric layers and metal layers; the method further includes: after each thin film dielectric layer and each metal layer of the substrate is processed, automatically detecting image connection lines by optical means, and performing electrical testing on a target area by an electrical fixture, wherein the target area is a chip interconnect area with a wiring density greater than a density threshold.

[0136] In this process, after each layer of the substrate is processed, the image connection lines are automatically detected by optical inspection, and the target area is electrically tested by electrical fixtures. This ensures that open and short circuits are normal, thereby guaranteeing the yield of each layer.

[0137] The process of automatically detecting image connections using optical sensors typically includes steps such as image acquisition, image processing, and analysis. Generally, a CCD camera is used to acquire images of each completed stack. Specifically, a reference mark is used to align the wafer coordinates of the stack, and then a motion platform drives the camera to move and capture images frame by frame. Finally, the images are processed to detect whether there are any breaks in the connections of signals, power, and ground. The image processing can be done using artificial intelligence, which is not specifically limited here.

[0138] Electrical testing of the target area using electrical fixtures involves performing electrical tests on the target area of ​​the completed laminate, such as conductivity, insulation, and impedance, to ensure that all connections meet design specifications.

[0139] In the above embodiments, after each stack is processed, the stack is subjected to optical automatic detection of image connection lines, and the target area is subjected to electrical testing by an electrical fixture, which ensures the yield of each stack and thus ensures the yield of the substrate.

[0140] In one optional embodiment, the mounting and reflowing of functional modules based on the processed substrate includes: mounting and reflowing the functional modules on the back side of the processed substrate; performing open / short circuit detection on each functional module on the back side of the substrate, and if the open / short circuit detection result of each functional module on the back side of the substrate is passed, applying adhesive to the bottom of each functional module on the back side of the substrate; if the open / short circuit detection result of each functional module on the back side of the substrate is failed, removing the failed open / short circuit... The functional modules on the back side of the substrate are reworked; the functional modules on the front side of the processed substrate are mounted and reflowed; the functional modules on the front side of the substrate are tested for open and short circuits, and if the test results of the open and short circuit tests of the functional modules on the front side of the substrate are passed, the bottom of the functional modules on the front side of the substrate is filled with glue; if the test results of the open and short circuit tests of the functional modules on the front side of the substrate are failed, the functional modules on the front side of the substrate that failed the open and short circuit tests are reworked.

[0141] The mounting and reflow of functional modules involves two steps: first, mounting and reflowing each functional module on the back side of the processed substrate; then, mounting and reflowing each functional module on the front side of the processed substrate.

[0142] In this application, after the substrate is generated, the chip mounting and reflow are carried out. In order to reduce the number of reflows of key front-side chips such as CPU and DCU, the back-side functional modules should be mounted and reflowed first, and then the front-side functional modules should be mounted and reflowed.

[0143] The component placement and reflow processes include steps such as stencil printing of flux, reflow oven processing, cleaning, and drying. Stencil printing of flux is to precisely apply solder paste to the PCB pads. This mainly involves: aligning the stencil with the PCB pads using optical positioning (fiducial mark); and using a squeegee at a specific angle (typically 45°~60°) and pressure (50~150N) to push the solder paste through the stencil openings and deposit it onto the pads. Component placement involves precisely mounting the various functional modules onto the solder paste. Reflow involves heating and melting the solder paste in a reflow oven to form reliable solder joints. Cleaning removes flux residue and ionic contaminants. Drying thoroughly removes moisture after cleaning to prevent electrochemical corrosion.

[0144] In one alternative embodiment, the functional modules are surface-mounted and reflowed using thermoforming.

[0145] The process includes: mounting and reflowing the functional modules on the back side of the processed substrate, and mounting and reflowing the functional modules on the front side of the processed substrate; performing open / short circuit tests on each functional module; filling the bottom of each functional module with adhesive if the open / short circuit test results are passed; and reworking the functional modules that failed the open / short circuit test if the open / short circuit test results are failed.

[0146] To improve yield, after surface mount and reflow of each functional module on the back side, online open / short circuit testing should be performed on each functional module. Optionally, online open / short circuit testing should only be performed on critical functional modules to ensure correct soldering. If any abnormality is found, rework should be carried out immediately to ensure the soldering yield of each functional module on the back side. After completing the testing and rework to ensure the soldering yield of each functional module on the back side, bottom filler should be applied to each critical functional module to improve reliability and prevent back side components from falling off during front reflow soldering.

[0147] After the back side is completed, the front side functional modules are surface mount and reflowed. At this time, the C4 bumps on the relevant chips have been prepared. The overall process is basically the same as the back side process. After the front side functional modules are surface mount and reflowed, online open and short circuit tests are performed to ensure the correctness of the soldering. If any abnormality is found, it is immediately reworked to ensure the soldering yield of each functional module. After the test and rework are completed to ensure the soldering yield of each functional module on the back side, the bottom of the key functional modules is filled with glue.

[0148] In the above embodiments, the chip reflow soldering on the motherboard is eliminated, reducing the number of reflow soldering cycles by less than two. It also eliminates the need to consider warpage and copper core balls during chip BGA soldering, which helps improve yield and reliability.

[0149] In some optional embodiments, after mounting and reflowing each of the functional modules based on the processed substrate, the process includes: fixing a support structure to one side of the substrate; fixing a heat sink to the front side of the support structure by means of fasteners and a back plate corresponding to the heat sink, wherein the back plate is in contact with the other side of the substrate.

[0150] After the front and back functional modules are reflowed, the support structure is fixed to the front of the substrate, for example by bonding the support structure with adhesive and curing it at high temperature.

[0151] In one alternative embodiment, the method further includes at least one of the following: determining the symmetry of metal content in the horizontal region and the upper and lower layer regions of the substrate based on the chip design; pressing the stacked layers of the substrate using a jig; and pressing a portion of the non-device regions of the substrate using a jig during the mounting and reflow processes of each of the functional modules.

[0152] The warpage that occurs during the substrate manufacturing process can be controlled in at least one of the following ways: control in the design, specifically by controlling the symmetry of the metal (e.g., copper) content in the horizontal region and the upper and lower layer regions (i.e., the two layers symmetrical about the core dielectric layer) through the early layout design; and control in the production process, specifically by ensuring the warpage by using the pressing properties of the magnetic fixture during the production process.

[0153] In order to reduce substrate warpage during the surface mount and reflow processes, the following methods can be used: one is to press the substrate layers together using a fixture, and the other is to use thermoforming for surface mount and reflow of each functional module.

[0154] The fixture can be a magnetic fixture. Thermocompression bonding is a microelectronic packaging technology that achieves direct metal-to-metal bonding through heating and pressure, thereby reducing substrate warping.

[0155] In one optional embodiment, each module of the target system includes a connector; based on the processed substrate, after each functional module is surface-mounted and reflowed, the process includes: connecting each connector of the test machine to the connector on each substrate, and obtaining the temperature of each chip on the substrate through the temperature control head of the test machine; and testing each functional module of the semiconductor.

[0156] The testing includes FT (Functional Testing) and SLT (Solution-Based Testing). Unlike traditional FT and SLT tests which use socket connections to the BGA solder balls of the chip under test, this application uses an automated robotic arm to connect multiple connectors of the testing machine to the front connectors of the substrate for testing. Multiple temperature control heads are used to control the temperature of multiple chips on the substrate. These multiple connectors enable parallel testing of multiple substrates.

[0157] In one embodiment, combinedFigure 5 As shown, Figure 5 This is a schematic diagram of the various functional modules of the packaged semiconductor in one embodiment. In this embodiment, after the entire package is completed, it is no longer necessary to solder the package to the motherboard. When packaging the heat sink, the heat sink is fixed to the front support structure by bolts and the heat sink backplate.

[0158] In some alternative embodiments, the modules of the target system include connectors; the method further includes connecting the signals and power supplies to the connectors via cables.

[0159] The connector is used to input signals and power from the motherboard or other chips to the target system via cables.

[0160] In one embodiment, the modules of the target system include an optoelectronic co-encapsulation; the method further includes connecting to the optoelectronic co-encapsulation via optical fiber.

[0161] When signal transmission with the outside world is required via optical fiber, the various modules of the target system include an optoelectronic co-encapsulation, which can be connected to the optoelectronic co-encapsulation via optical fiber to achieve optical fiber signal transmission.

[0162] The above embodiments improve integration, shorten interconnection distance, increase interconnection speed, reduce interconnection power consumption, and reduce chip area by making the interconnection PHY smaller, which is beneficial to PPA. Moreover, it realizes the innovation of the manufacturing mode of various functional modules of semiconductors, that is, in the future, motherboard manufacturers will not need to produce motherboards, but only need to put forward configuration requirements, chip manufacturers will provide chips and substrates, and packaging plants will complete the integration.

[0163] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0164] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0165] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A substrate, characterized in that, include: The core board structure includes a core dielectric layer and a first power ground plane layer located on opposite sides of the core dielectric layer. An interconnect structure is located on opposite sides of the core board structure. The interconnect structure on each side includes alternately stacked thin film dielectric layers and metal layers. The thin film dielectric layers are located on the first power ground plane layer, and the metal layers include alternately arranged signal layers and second power ground plane layers. Multiple pads, located at least on the second power ground plane layer on one side of the core board structure, are used for soldering multiple functional modules of the computing system; The traces pass through the interconnect structure and the core board structure and are connected to pads for interconnecting functional modules on the signal layer or power / ground plane layer.

2. The substrate according to claim 1, characterized in that, The functional module includes a first functional module and a second functional module. The trace density between the first functional module and the second functional module is greater than or equal to a first density threshold. The first functional module and the second functional module are located on one side of the substrate. The traces pass through the signal layer located on one side of the core board structure in the interconnect structure for signal interconnection and / or through the second power ground plane layer located on one side of the core board structure in the interconnect structure for power ground interconnection.

3. The substrate according to claim 1, characterized in that, The functional module includes a third functional module and a fourth functional module. The wiring density between the third functional module and the fourth functional module is less than a first density threshold. The third functional module and the fourth functional module are located on different sides of the substrate. The wiring passes through each layer in the interconnect structure and each layer in the core board structure for signal interconnection and / or power ground interconnection.

4. The substrate according to claim 3, characterized in that, When the third and fourth functional modules are located on opposite sides of the substrate, the traces are triggered from the pads of the third functional module, extend in the signal layer of the interconnect structure in a direction parallel to the substrate, so that the extended position is directly opposite the position of the pads of the fourth functional module, and pass through each layer of the interconnect structure and each layer of the core board structure for signal interconnection. and / or When the third and fourth functional modules are located on opposite sides of the substrate, the trace is triggered from the pad of the third functional module, extends in the second power and ground plane layer of the interconnect structure in a direction parallel to the substrate, so that the extended position is directly opposite the position of the pad of the fourth functional module, and passes through each layer of the interconnect structure and each layer of the core board structure for power and ground interconnection.

5. The substrate according to claim 1, characterized in that, The functional module has a bandwidth greater than a bandwidth threshold, and the substrate further includes a 2.5D packaging layer located between the functional module and the substrate pads; and / or the functional module has a transistor density greater than a density threshold, and the substrate further includes a 3D packaging layer located between the functional module and the substrate pads.

6. The substrate according to any one of claims 1 to 5, characterized in that, The substrate further includes a heat dissipation structure, which includes: The supporting structure has several mechanical through-holes for the heat sink. A heat sink, wherein two opposite sides of the heat sink are in contact with one side of the substrate and the functional module, respectively; Back plate, located on the other side of the substrate; The radiator is fixed to the support structure by fasteners, the back plate, and several mechanical through holes for the radiator.

7. The substrate according to claim 6, characterized in that, The thickness of the support structure is greater than the thickness of the functional module, and the difference between the thickness of the support structure and the thickness of the functional module is between 10µm and 100µm.

8. A semiconductor device, characterized in that, The semiconductor device includes: The substrate according to any one of claims 1 to 7; At least one functional module is soldered onto the substrate via pads on the substrate.

9. A method for fabricating a semiconductor device, characterized in that, The method includes: The substrate is fabricated based on the chip design, and the substrate is the substrate described in any one of claims 1 to 7; Based on the processed substrate, the mounting and reflow of each functional module are performed.

10. The method according to claim 9, characterized in that, The substrate fabrication based on chip design includes: The chip area and the target area are exposed by step exposure method, wherein the target area is the chip interconnect area with a wiring density greater than the density threshold; The power supply area is exposed using a linear exposure method; The transition area is double-exposed using both the step exposure method and the linear exposure method. The transition area is the area connecting the area corresponding to the step exposure method and the area corresponding to the linear exposure method.

11. The method according to claim 9, characterized in that, The interconnect structure of the substrate includes alternately stacked thin-film dielectric layers and metal layers; the method further includes: After each thin-film dielectric layer and each metal layer of the substrate are processed, the image connection lines are automatically detected by optical means, and the target area is electrically tested by an electrical fixture. The target area is a chip interconnect area with a wiring density greater than a density threshold.

12. The method according to any one of claims 9 to 11, characterized in that, The substrate, based on the processing, is used for surface mounting and reflow of various functional modules, including: The back side of the processed substrate is then fitted with each functional module and reflowed. Open / short circuit tests are performed on each of the functional modules on the back side of the substrate. If the open / short circuit test results for each of the functional modules on the back side of the substrate are passed, adhesive is applied to the bottom of each of the functional modules on the back side of the substrate. If the open / short circuit test results for each of the functional modules on the back side of the substrate are failed, the functional modules on the back side of the substrate that failed the open / short circuit test are reworked. The front side of the processed substrate is then fitted with each functional module and reflowed. Open / short circuit tests are performed on each of the functional modules on the front side of the substrate. If the open / short circuit test results for each of the functional modules on the front side of the substrate are passed, adhesive is applied to the bottom of each of the functional modules on the front side of the substrate. If the open / short circuit test results for each of the functional modules on the front side of the substrate are failed, the functional modules on the front side of the substrate that failed the open / short circuit test are reworked.

13. The method according to claim 9, characterized in that, After the substrate based on the processing is surface-mounted and reflowed with each of the functional modules, the process includes: The support structure is fixed to one side of the substrate; The heat sink is fixed to the front of the support structure by means of fasteners and a back plate corresponding to the heat sink, and the back plate is in contact with the other side of the substrate.

14. The method according to claim 9, characterized in that, The method further includes at least one of the following: Based on the chip design, the symmetry of the metal content in the horizontal region and the upper and lower layer regions of the substrate is determined; The substrate layers are pressed together using a jig; During the mounting and reflow processes of each of the aforementioned functional modules, a fixture is used to press together portions of the substrate without components.

15. The method according to claim 9, characterized in that, Each functional module includes a connector; the substrate, after being processed, undergoes surface mounting and reflow of each functional module, including: Connect each connector of the testing machine to the connector on each of the substrates, and obtain the temperature of each functional module on the substrate through the temperature control head of the testing machine; The semiconductor device is tested based on the temperature of each of the aforementioned functional modules.

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