Groove MOSFET device with multiple current channels and manufacturing method thereof

Abstract

The invention discloses a multi-current-channel trench MOSFET device and a manufacturing method thereof, which can be applied to the technical field of semiconductors, and the structure comprises a source electrode, an isolation dielectric layer, a gate structure, an epitaxial structure with an n-level step trench, a buffer layer, a substrate layer and a drain electrode, the buffer layer, the substrate layer and the drain electrode are sequentially arranged on the non-trench side of the epitaxial structure; the gate structure is arranged on the side walls of the first to mth step grooves of the epitaxial structure; the source electrode fills the n-level step groove and is isolated from the grid electrode structure through the isolation dielectric layer; a current flow direction control region is arranged in the epitaxial structure, a contact hole is formed in the isolation dielectric layer, and the source electrode is connected with the current flow direction control region in the epitaxial structure through the contact hole to form ohmic contact; and the current flows to the control region to form a bidirectional vertical channel through ion doping. Therefore, through the arrangement of the stepped groove and the current flow direction control region, the current channel is increased, and the electric field distribution of the MOSFET device is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a trench MOSFET device with multiple current channels and a manufacturing method thereof. BACKGROUND

[0002] Silicon carbide, as a representative material of the third generation semiconductor material, has excellent characteristics such as wide band gap, high critical breakdown field, high electron saturation drift velocity and high thermal conductivity. The metal-oxide semiconductor field effect transistor (MOSFET) manufactured based on silicon carbide is one of the main power device types at present.

[0003] There are two structures of the internal cell unit of the common silicon carbide power MOSFET, one is a planar structure, and the other is a trench structure. The trench structure MOSFET has lower conduction loss and better switching performance than the traditional planar structure MOSFET, but when the device withstands high voltage, the bottom of the gate trench of the SiC device is prone to have the problem of electric field concentration. In order to alleviate the electric field concentration at the bottom of the gate trench, P-type doping ions are usually implanted at the bottom of the gate trench or a gate and source double-trench structure (the gate and source of the trench MOSFET are in two separate trenches), but this will increase the specific on-resistance and reduce the unit current density, and the bottom of the source trench is far away from the bottom of the gate trench, so it is difficult to greatly alleviate the electric field concentration at the bottom of the gate trench. In addition, the short-circuit time of the high-voltage Si IGBT device is about 10 μs, while the short-circuit time of the SiC MOSFET is generally only about 2-3 μs, and the short-circuit endurance time is short.

[0004] Therefore, how to improve the unit current density of the SiC MOSFET device while optimizing the electric field distribution near the gate oxide of the MOSFET device and prolonging the short-circuit endurance time of the device is a problem that those skilled in the art urgently need to solve. SUMMARY

[0005] Based on the above problems, the present application provides a trench MOSFET device with multiple current channels and a manufacturing method thereof, which increases the current channel, improves the channel density, optimizes the electric field distribution of the MOSFET device, and prolongs the short-circuit endurance time by setting the stepped trench and the current flow control region.

[0006] In a first aspect, the embodiments of the present application provide a trench MOSFET device with multiple current channels, which comprises a source, an isolation dielectric layer, a gate structure, an epitaxial structure with n-level stepped trenches, a buffer layer, a substrate layer and a drain; n is a positive integer ≥ 2.

[0007] The buffer layer, the substrate layer and the drain electrode are sequentially arranged on the non-trench side of the epitaxial structure.

[0008] The gate structure is arranged on the sidewall of the first to the mth level stepped trench of the epitaxial structure; the m is a positive integer greater than or equal to 2; the mth level stepped trench is at the bottom of the m-1th level stepped trench.

[0009] The source electrode fills the n level stepped trench and is isolated from the gate structure by the isolation medium layer.

[0010] The epitaxial structure is provided with a current flow control region, a contact hole is opened on the isolation medium layer, and the source electrode is connected to the current flow control region in the epitaxial structure through the contact hole to form an ohmic contact; the current flow control region is formed by ion doping to form a bidirectional vertical channel.

[0011] Optionally, the current flow control region comprises a first N-type doped region, a first P-type doped region and a second P-type doped region; the doping concentration of the second P-type doped region is higher than that of the first P-type doped region.

[0012] The first N-type doped region and the first P-type doped region are sequentially arranged on one side of the source electrode.

[0013] The first P-type doped region connects the first N-type doped region and the gate structure.

[0014] The first N-type doped region connects the source electrode and the gate structure.

[0015] The second P-type doped region is arranged through the first N-type doped region and the first P-type doped region, and simultaneously connects the first N-type doped region, the first P-type doped region and the source electrode.

[0016] Optionally, the gate structure comprises a gate oxide layer and a gate layer; the gate layer is metal or polycrystalline gate.

[0017] The gate layer is wrapped by the gate oxide layer and the isolation medium layer.

[0018] Optionally, the m is equal to the n.

[0019] The gate structure forms a symmetrical trench structure in the n level stepped trench.

[0020] The two gate structures in the symmetrical trench structure connect the same current flow control region.

[0021] Optionally, the m is equal to the n.

[0022] The gate structure forms a symmetrical trench structure in the nth level stepped trench;

[0023] Each of the two gate structures in the symmetrical trench structure is connected with one current flow control region;

[0024] The source in the nth level stepped trench is directly connected with the epitaxial structure to form a Schottky contact.

[0025] Optionally, the epitaxial structure comprises a current spreading layer region.

[0026] The n level stepped trench is arranged in the current spreading layer region.

[0027] Optionally, the m is less than the n.

[0028] The source in the nth level stepped trench is directly connected with the epitaxial structure to form a Schottky contact.

[0029] In a second aspect, the embodiments of the present application provide a manufacturing method of a multi-current channel trench MOSFET device, which is used to manufacture the multi-current channel trench MOSFET device as described above, and the method comprises the following steps:

[0030] A basic manufacturing structure is provided, which comprises, from top to bottom, an epitaxial layer, a buffer layer, a substrate layer and a drain;

[0031] An n level stepped trench is formed on the epitaxial layer based on an etching process, to form an epitaxial structure with n level stepped trenches; the n is a positive integer greater than or equal to 2;

[0032] A current flow control region is formed in the epitaxial structure; the current flow control region forms a bidirectional vertical channel through ion doping;

[0033] A gate structure is formed on the current flow control region on the sidewall of the first to mth level stepped trenches; the m is a positive integer greater than or equal to 2;

[0034] An isolation medium layer is formed on the surface of the gate structure based on a deposition process;

[0035] A contact hole is opened on the isolation medium layer, which can expose the current flow control region;

[0036] A source is formed in the n level stepped trench based on a deposition process, which is connected with the current flow control region through the contact hole to form an ohmic contact.

[0037] Optionally, the step of forming the current flow control region in the epitaxial structure comprises:

[0038] forming a first P-type doped region in the epitaxial structure based on an ion implantation process;

[0039] forming a first N-type doped region on the first P-type doped region in the epitaxial structure based on an ion implantation process;

[0040] forming a second P-type doped region in the first P-type doped region and the first N-type doped region in the epitaxial structure based on an ion implantation process;

[0041] The second P-type doped region penetrates the first N-type doped region and the first P-type doped region, and the doping concentration of the second P-type doped region is higher than the doping concentration of the first P-type doped region.

[0042] Optionally, the gate structure formed on the current flow direction control region on the sidewall of the first to mth step trench includes:

[0043] forming a gate oxide layer on the current flow direction control region on the sidewall of the first to mth step trench;

[0044] forming a gate layer on the gate oxide layer; the gate layer is metal or polycrystalline gate.

[0045] From the above technical solutions, compared with the prior art, the present application has the following advantages:

[0046] The multi-current channel trench MOSFET device provided by the present application includes a source, an isolation medium layer, a gate structure, an epitaxial structure with n-step trenches, a buffer layer, a substrate layer and a drain. Wherein, n is a positive integer greater than or equal to 2; the buffer layer, the substrate layer and the drain are sequentially arranged on the non-trench side of the epitaxial structure; the gate structure is arranged on the sidewall of the first to mth step trench of the epitaxial structure; m is a positive integer greater than or equal to 2; the mth step trench is at the bottom of the m-1th step trench; the source fills the n-step trench and is isolated from the gate structure by the isolation medium layer; the epitaxial structure is provided with a current flow direction control region, a contact hole is opened on the isolation medium layer, and the source is connected to the current flow direction control region in the epitaxial structure through the contact hole to form an ohmic contact; the current flow direction control region is formed by ion doping to form a bidirectional vertical channel. Adjacent P+ implants are not at the same horizontal position, and the mutual influence between adjacent P+ implants is separated in space. In this way, by arranging the step trench and the current flow direction control region, the longitudinal space area is fully utilized to form a multi-current channel, the specific on-resistance of the MOSFET transistor is effectively reduced, the current density per unit area is improved, and the electric field distribution of the MOSFET device is optimized, and the short circuit resistance time is prolonged. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0048] Figure 1 A structural schematic diagram of a trench MOSFET device with multiple current channels provided by an embodiment of the present application;

[0049] Figure 2 A structural schematic diagram of a gate structure provided by an embodiment of the present application;

[0050] Figure 3 An ion implantation schematic diagram provided by an embodiment of the present application;

[0051] Figure 4 A structural schematic diagram of a cross section a provided by an embodiment of the present application;

[0052] Figure 5 A structural schematic diagram of a cross section b provided by an embodiment of the present application;

[0053] Figure 6 A gate oxide layout provided by an embodiment of the present application;

[0054] Figure 7 A source opening layout provided by an embodiment of the present application;

[0055] Figure 8 A structural schematic diagram of an epitaxial structure provided by an embodiment of the present application;

[0056] Figure 9 A structural schematic diagram of a current flow control region in a cross section a provided by an embodiment of the present application;

[0057] Figure 10 A structural schematic diagram of a current flow control region in a cross section b provided by an embodiment of the present application;

[0058] Figure 11 A flow chart of a manufacturing method of a trench MOSFET device with multiple current channels provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] As described above, the existing trench structure MOSFET is prone to electric field concentration. Specifically, since the gate oxide material is generally SiO2, its dielectric constant is 3.9, and the dielectric constant of SiC is 9.7, the electric field in SiO2 at the gate oxide interface is 2.5 times that of SiC, and the critical electric field of SiC is ten times that of Si. Therefore, when the device is subjected to high voltage, the bottom of the gate trench of the SiC device is prone to electric field concentration. To alleviate the electric field concentration at the bottom of the gate trench, P-type doping ions are usually injected at the bottom of the gate trench or a gate and source double-trench structure (the gate and source of the trench MOSFET are in two separate trenches), but this will increase the on-resistance and reduce the unit current density. In addition, the short-circuit time of high-voltage Si IGBT devices is about 10 μs, while the short-circuit time of SiC MOSFET is generally only about 2-3 μs, and the short-circuit resistance time is short, and the heat is almost completely generated in the extremely thin drift region, the isolation oxide layer and the top metal layer near the surface of the chip. The short-circuit time of high-voltage Si IGBT devices is about 10 μs, and the fluctuation amplitude of the peak temperature during short-circuit is small, and is more located in the semiconductor of the device, rather than the surface of the chip. Therefore, the present patent designs a longitudinal device structure of SiC MOSFET, so that after short-circuit occurs, the current and heat are not only on the surface of the chip, but also distributed in the space of multiple current paths, and part of the drift region is utilized to reduce the failure probability of gate oxide melting and gate-source electrode melting short-circuit, delay the time of thermal runaway, thereby increasing the short-circuit time and improving the short-circuit resistance of the device.

[0060] Therefore, how to improve the unit current density of SiC MOSFET devices while optimizing the electric field distribution near the gate oxide of MOSFET devices and prolonging the short-circuit resistance time of the device is a problem that those skilled in the art urgently need to solve.

[0061] To solve the above problems, the embodiment of the present application provides a trench MOSFET device with multiple current channels, which comprises a source, an isolation dielectric layer, a gate structure, an epitaxial structure with n-level stepped trenches, a buffer layer, a substrate layer and a drain, wherein n is a positive integer greater than or equal to 2; the buffer layer, the substrate layer and the drain are sequentially arranged on the non-trench side of the epitaxial structure; the gate structure is arranged on the sidewall of the first to the m-level stepped trenches of the epitaxial structure; m is a positive integer greater than or equal to 2; the m-level stepped trench is at the bottom of the m-1-level stepped trench; the source fills the n-level stepped trenches and is isolated from the gate structure by the isolation dielectric layer; a current flow control region is arranged in the epitaxial structure, a contact hole is opened on the isolation dielectric layer, and the source is connected to the current flow control region in the epitaxial structure through the contact hole to form an ohmic contact; the current flow control region is formed by ion doping to form a bidirectional vertical channel.

[0062] In this way, by arranging the stepped trenches and the current flow control region, the longitudinal space region is fully utilized to form multiple current channels, and the electric field distribution of the MOSFET device is optimized.

[0063] It should be noted that the trench MOSFET device with multiple current channels and the manufacturing method thereof provided by the present application can be applied to the field of semiconductor technology. The above is only an example and does not limit the application field of the trench MOSFET device with multiple current channels and the manufacturing method thereof provided by the present application.

[0064] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0065] Figure 1 A structural schematic diagram of a trench MOSFET device with multiple current channels provided by the embodiment of the present application is shown. As shown in the figure, the trench MOSFET device comprises a source 110, an isolation dielectric layer 120, a gate structure 130, an epitaxial structure 140 with n-level stepped trenches, a buffer layer 150, a substrate layer 160 and a drain 170; n is a positive integer greater than or equal to 2; Figure 1

[0066] The buffer layer 150, the substrate layer 160 and the drain 170 are sequentially arranged on the non-trench side of the epitaxial structure 140;

[0067] ​The gate structure 130 is arranged on the sidewall of the first to mth level stepped trenches of the epitaxial structure 140; m is a positive integer greater than or equal to 2; the mth level stepped trench is at the bottom of the (m-1)th level stepped trench;

[0068] The source 110 fills the n-level stepped trench and is isolated from the gate structure 130 by the isolation medium layer 120.

[0069] The epitaxial structure 140 is provided with a current flow control region 180, a contact hole is opened on the isolation medium layer 120, and the source 110 is connected to the current flow control region 180 in the epitaxial structure 140 through the contact hole to form an ohmic contact; the current flow control region 180 is formed by ion doping to form a bidirectional vertical channel.

[0070] Specifically, the SiC substrate layer 160 provided in the embodiment of the application is N-type doped, the doping concentration is 1E18~5E19cm -3 , and the thickness is 80~400um. The substrate layer 160 is below the metal drain 170 and above the N-type doped SiC buffer layer 150, and the doping concentration of the N-type doped SiC buffer layer 150 is 7E17~3E18cm -3The thickness of the buffer layer 150 is about 1 um. Above the buffer layer 150 is an N-type doped SiC epitaxial structure 140. Above the epitaxial structure 140 is etched with n-level stepped trenches, wherein the uppermost trench is the first-level stepped trench. n can be a positive integer greater than or equal to 2, and the embodiments of the present application only take n = 2 as an example. The gate structure 130 and the source 110 are both inside the same level of stepped trench, that is, the gate structure 130 and the source 110 are both located in the first and second level stepped trenches (when n = 2, m is also 2), and the gate structure 130 and the source 110 are isolated by the isolation medium layer 120. The isolation medium layer 120 has a connecting hole for connecting the source 110 and the epitaxial structure 140. In the epitaxial structure 140, the region connected with the source 110 forms an ohmic contact with the source 110 through ion doping to form a current flow control region 180. The current flow control region 180 can form a multi-directional vertical channel (vertical channel from top to bottom and vertical channel from bottom to top) by controlling the type of injected ions, reduce the specific on-resistance by controlling the ion injection concentration, reduce the chip area, and reduce the cost. It can be understood that when n is greater than 2, for example, n = 3, the gate is located in the first and second level stepped trenches, and the source 110 can also be located in the first, second, and third level stepped trenches; when n = 4, the gate is located in the first and second level stepped trenches, and the source 110 can also be located in the first, second, third, and fourth level stepped trenches, so that the current flow control region 180 can be injected deeper, and the electric field distribution at the bottom of the trench gate oxide can be better protected and optimized. The longitudinal device structure of the SiC MOSFET provided by the embodiments of the present application makes the current and heat not only on the surface of the chip after short circuit occurs, but also in multiple current paths in space, uses part of the drift region to reduce the failure probability of gate oxide melting and gate-source electrode melting short circuit, delays the time of thermal runaway, suppresses the increase speed of short circuit current, thereby increases the short circuit time and improves the short circuit resistance of the device.

[0071] Figure 2 A structure diagram of a gate structure provided by the embodiments of the present application is shown. In combination with Figure 2 the gate structure 130 shown in the figure, the above-mentioned gate structure 130 includes a gate oxide layer 231 and a gate electrode layer 232; the gate electrode layer 232 is a metal or a polycrystalline gate electrode;

[0072] The gate electrode layer 232 is wrapped by the gate oxide layer 231 and the isolation medium layer 120.

[0073] Specifically, the gate structure 130 provided by the embodiments of the present application is composed of a gate oxide layer 231 and a gate electrode layer 232, wherein the gate electrode layer 232 is wrapped by the gate oxide layer 231 and the isolation medium layer 120, and does not contact the source 110 and the epitaxial structure 140. The gate electrode layer 232 is a metal or a polycrystalline gate electrode.

[0074] As one implementation, regarding the design of the current flow control region 180, the current flow control region 180 includes a first N-type doped region 281, a first P-type doped region 282, and a second P-type doped region 283; the doping concentration of the second P-type doped region 283 is higher than the doping concentration of the first P-type doped region 282.

[0075] The first N-type doped region 281 and the first P-type doped region 282 are sequentially disposed on one side of the source 110;

[0076] The first P-type doped region 282 is connected to the first N-type doped region 281 and the gate structure 130;

[0077] The first N-type doped region 281 connects the source 110 and the gate structure 130;

[0078] The second P-type doped region 283 is disposed through the first N-type doped region 281 and the first P-type doped region 282, and simultaneously connects the first N-type doped region 281, the first P-type doped region 282 and the source 110.

[0079] Figure 3 This is a schematic diagram of ion implantation provided for an embodiment of this application. (Combined with...) Figure 3 As shown, looking down at the trench MOSFET device, in the current flow control region 180, a low-doped region of the second doping type (first P-type doped region 282) is placed at the bottom layer, and above it is a high-doped region of the first doping type (first N-type doped region 281). The high-doped region of the second doping type (second P-type doped region 283) is defined according to the layout to penetrate through the first N-type doped region 281 and the first P-type doped region 282, and connects the first N-type doped region 281 and the first P-type doped region 282, and is connected to the source 110 through the first N-type doped region 281. When the device is forward-biased, only intermittent P+ doped ions exist at the bottom of the trench of the gate structure 130, and adjacent P+ implants are not at the same horizontal position, thereby spatially separating the mutual influence between adjacent P+ implants, making full use of the vertical space to form multiple current channels, so as to optimize the electric field distribution of the MOSFET device. When the device is reverse-biased, each gate structure 130 has P-type doped ions near the bottom of the trench that are in contact with the source 110. This effectively alleviates the electric field concentration at the bottom of the trench of the gate structure 130. Furthermore, in the trench MOSFTE device provided in this embodiment, the source 110 and the gate structure 130 are located in the same stepped trench, with a closer lateral distance. The P-type doped ions injected at the bottom of the source trench can effectively and significantly alleviate the electric field concentration at the bottom of the gate trench, thus better protecting the gate oxide layer. Additionally, Figure 3Two cross sections are shown, i.e., a cross section and b cross section. Figure 4 A structure schematic diagram of the a cross section is provided for the embodiment of the present application. Figure 5 A structure schematic diagram of the b cross section is provided for the embodiment of the present application. In combination with Figure 4 and Figure 5 As shown, continuing to take n=2 as an example, a first P-type doped region 282 and a first N-type doped region 281 are injected on the epitaxial structure 140 of the n-level stepped trench, and the first P-type doped region 282 semi-wraps the first N-type doped region 281, the first N-type doped region 281 connects the source 100 and the lower surface of the gate oxide layer 231, and the first P-type doped region 282 simultaneously wraps the side surface of part of the gate oxide layer 231. In this way, the vertical channel from top to bottom can be increased to the vertical channel from bottom to top, as shown by the red arrow. The P-well doped region at the bottom of each gate structure 130 can alleviate the electric field concentration in this region. In this way, the multi-directional vertical current channel is effectively increased by the stepped trench and the doped region, the current density of the trench MOSFET device is effectively improved, and the specific on-resistance is reduced. In addition, in order to reduce the cell size, the second P-type doped region 283 is connected with the source 110 in the Z-axis direction of the MOSFET device structure, penetrates the first N-type doped region 281 and the first P-type doped region 282, and further reduces the specific on-resistance, thereby reducing the chip area and reducing the cost. Furthermore, the second P-type doped region 283 is also extended in the vertical direction near the gate oxide, thereby more effectively improving the reliability of the gate oxide layer and improving the short-circuit resistance of the device. Specifically, the P+ type doped ions in contact with the source 110 act as a P-type ohmic contact with the source 110 on one hand, and on the other hand, the P+ type doped ions can more effectively alleviate the electric field concentration at the bottom of the trench of the gate structure 130 than the P-well, thereby improving the reliability of the gate oxide layer 231. The first P-type doped region 282 is P-type doped, the doping concentration is 1E16~1E18cm -3 , and the depth is 0.2~2.0um; the first N-type doped region 281 is N-type doped, the doping concentration is 1E18~5E20cm -3 , and the depth is 0.1~0.5um; the second P-type doped region 283 is P-type doped, the doping concentration is 1E17~8E20cm -3 , and the depth is 0~2.0um. The SiC MOSFET longitudinal device structure designed in this way makes the current and heat not only distributed on the surface of the chip after short circuit occurs, but also distributed in the spatial multi-current path, uses part of the drift region to reduce the failure probability of gate oxide melting and gate-source electrode melting short circuit, delays the time of thermal runaway, suppresses the short-circuit current increase speed, thereby increases the short-circuit time and improves the short-circuit resistance of the device.

[0080] Figure 6 A gate oxide layout is provided for the embodiment of the present application. As shown in Figure 6 The a cross-section and the b cross-section correspond to the Figure 4 and Figure 5 The gate oxide layer 231 is arranged on and in contact with the first N-type doped region 281 and the first P-type doped region 282.

[0081] Figure 7 A source opening layout is provided for the embodiment of the present application. As shown in Figure 7 The a cross-section and the b cross-section correspond to the Figure 4 and Figure 5 The source 110 is arranged on and in contact with the first N-type doped region 281 and the second P-type doped region 283.

[0082] It can be understood that the bar-shaped cell design provided by the embodiment of the present application is only one of many shape designs, and other shape cell designs such as square shape can also be used. However, it should be noted that no matter what shape is used, the design concept should be the same, that is, the gate oxide layer 231 is arranged on and in contact with the first N-type doped region 281 and the first P-type doped region 282, and the source 110 is arranged on and in contact with the first N-type doped region 281 and the second P-type doped region 283.

[0083] Figure 8 A structure diagram of an epitaxial structure is provided for the embodiment of the present application. As shown in Figure 8 For how to design the epitaxial structure 140, the above-mentioned epitaxial structure 140 includes: a current spreading layer domain 241;

[0084] The n-level stepped trench is arranged in the current spreading layer domain 241.

[0085] Specifically, in order to achieve a balance between conductivity, carrier transport, heat distribution and electric field regulation, and to improve the efficiency, reliability and life of the trench MOSFET device, the epitaxial structure 140 is divided into a current spreading layer domain 241 and a basic epitaxial layer 242 based on different ion implantation concentrations according to the embodiment of the present application. The first N-type doped region 281, the first P-type doped region 282 and the second P-type doped region 283 are all in the current spreading layer domain 241, and the n-level stepped trench is etched for the current spreading layer domain 241. The basic epitaxial layer 242 is N-type doped, and the doping concentration is 1E15~8E16cm -3, thickness is 4~100um; current spreading layer domain 241 is N-type doped, doping concentration is 1E15~1E18cm -3 , depth is 0.3~5um. In addition, under the influence of current spreading layer domain 241, the above-mentioned P+ type doped region (second P type doped region 283) will not affect the current path near the trench bottom, and the current path from the channel to the current spreading layer domain 241, the epitaxial layer is unobstructed.

[0086] As an embodiment, for how to design the gate structure 130 and its corresponding current flow control region 180, the above-mentioned m is equal to n;

[0087] The gate structure 130 forms a symmetrical trench structure in the nth level stepped trench;

[0088] The two gate structures 130 in the symmetrical trench structure are connected to the same current flow control region 180.

[0089] Specifically, in combination with the above, when n=2, m can only be 2, but when n takes a value greater than 2, m can also take a value greater than 2. For example, when n=3, m takes 3, or when n=4, m takes 3 or 4, and so on. It can be understood that when m=n and the cell structure is made into a symmetrical trench structure, in the nth level stepped trench, the left and right gate structures 130 share the same trench of the source 110. Therefore, the two gate structures 130 can be connected to the same current flow control region 180.

[0090] As an embodiment, for how to design the gate structure 130 and its corresponding current flow control region 180, the above-mentioned m is equal to n;

[0091] The gate structure 130 forms a symmetrical trench structure in the nth level stepped trench;

[0092] The two gate structures 130 in the symmetrical trench structure are connected to the same current flow control region 180.

[0093] The source 110 in the nth level stepped trench can be directly connected to the epitaxial structure 140 to form a Schottky contact.

[0094] Figure 9 A structure schematic diagram of a current flow control region provided by an embodiment of the present application under a section a. Figure 10 A structure schematic diagram of a current flow control region provided by an embodiment of the present application under a section b. In combination with Figure 9 and Figure 10As shown, although m=n and the gate structure 130 is designed as a symmetrical trench structure in the nth stage stepped trench, they can not share the same current flow control area 180. At this time, the source 110 in the nth stage stepped trench forms Ohmic contact with both the two current flow control areas 180 and forms Schottky contact with the current spreading layer domain 241, so as to integrate the Schottky diode in the device without affecting the cell size, effectively improve the reverse diode freewheeling capability without affecting the specific on-resistance and current density, significantly reduce the MOSFET transistor diode voltage drop, improve the integration of the chip, and reduce the manufacturing cost of the MOSFET device integrated with the Schottky diode.

[0095] In addition, the multi-current channel trench structure of the structure of the application is provided with multiple P-type Ohmic contacts connected with the source, which increases the P-type Ohmic contact area of the source without changing the cell size, effectively improves the P-type contact resistance, and significantly reduces the diode voltage drop under reverse freewheeling of large current.

[0096] As an embodiment, the above-mentioned m is less than n in terms of how to design the number of steps of the nth stage stepped trench.

[0097] The source 110 in the nth stage stepped trench can be directly connected with the epitaxial structure 140 to form Schottky contact.

[0098] Specifically, when n is greater than m, there is only a metal source 110 in the nth stage stepped trench, and at this time, it is not necessary to consider the case that multiple gate structures 130 share one current flow control area 180. The trench MOSFET device provided by the embodiment of the application can be provided with P-type Ohmic contacts connected with the source 110 on the trench sidewall and bottom, which increases the P-type Ohmic contact area, effectively improves the P-type contact resistance, and significantly reduces the diode voltage drop under reverse freewheeling of large current. In addition, in order to further improve the current, the reserved source 110 area can be directly connected with the current spreading layer domain 241 to form Schottky contact, thereby reducing the specific on-resistance.

[0099] In summary, the multi-current channel trench MOSFET device provided by the application comprises a source electrode, an isolation medium layer, a gate structure, an epitaxial structure with n-level stepped trenches, a buffer layer, a substrate layer, and a drain electrode. Wherein, n is a positive integer greater than or equal to 2; the buffer layer, the substrate layer, and the drain electrode are sequentially arranged on the non-trench side of the epitaxial structure; the gate structure is arranged on the sidewall of the first to the m-level stepped trenches of the epitaxial structure; m is a positive integer greater than or equal to 2; the m-level stepped trench is at the bottom of the m-1-level stepped trench; the source electrode fills the n-level stepped trenches and is isolated from the gate structure by the isolation medium layer; a current flow direction control region is arranged in the epitaxial structure, a contact hole is opened on the isolation medium layer, and the source electrode is connected to the current flow direction control region in the epitaxial structure through the contact hole to form an ohmic contact; the current flow direction control region forms a bidirectional vertical channel through ion doping. In this way, the longitudinal space area is fully utilized to form multiple current channels through the arrangement of the stepped trenches and the current flow direction control region, and the electric field distribution of the MOSFET device is optimized.

[0100] Figure 11 A flowchart of a manufacturing method of a multi-current channel trench MOSFET device provided by an embodiment of the application is shown in FIG. 6. In combination with the multi-current channel trench MOSFET device shown in FIG. 1, the method for manufacturing the multi-current channel trench MOSFET device comprises the following steps. Figure 11

[0101] S1: providing a basic manufacturing structure; the basic manufacturing structure comprises, from top to bottom, an epitaxial layer, a buffer layer, a substrate layer, and a drain electrode.

[0102] In actual application, first, a basic manufacturing structure is provided, which comprises, from top to bottom, an N-type doped SiC epitaxial layer, an N-type doped SiC buffer layer, an N-type doped SiC substrate layer, and a metal drain electrode. The epitaxial layer can comprise, from top to bottom, a current expansion layer and a basic epitaxial layer, and all subsequent processes are completed in the current expansion layer, such as etching trenches, ion implantation, etc.

[0103] S2: forming n-level stepped trenches on the epitaxial layer based on an etching process to form an epitaxial structure with n-level stepped trenches; n is a positive integer greater than or equal to 2.

[0104] In actual application, n-level stepped trenches can be etched on the SiC epitaxial structure by an etching process to obtain an epitaxial structure with n-level stepped trenches. n needs to be greater than or equal to 2, and the n-level stepped trenches can be 2-level, 3-level, 4-level, or even more stepped trenches. The present embodiment only takes 2-level stepped trenches as an example.

[0105] S3: forming a current flow direction control region in the epitaxial structure; the current flow direction control region forms a bidirectional vertical channel through ion doping.

[0106] ​In practical applications, the current flow control region is formed in the epitaxial structure by ion implantation, the vertical channel in both directions (vertical channel from top to bottom and vertical channel from bottom to top) is formed by controlling the type of implanted ions, and the specific on-resistance is reduced by controlling the concentration of ion implantation, thereby reducing the chip area and cost.

[0107] S4: forming a gate structure on the current flow control region on the sidewall of the first to mth step trenches; m is a positive integer greater than or equal to 2.

[0108] In practical applications, the gate structure is formed on the sidewall of the first to mth step trenches of the n-step trenches. Wherein m is a positive integer greater than or equal to 2, and the present application only takes m=2 as an example.

[0109] S5: forming an isolation medium layer on the surface of the gate structure based on a deposition process.

[0110] S6: opening a contact hole on the isolation medium layer, which can expose the current flow control region.

[0111] S7: forming a source electrode in the n-step trenches based on a deposition process, the source electrode being connected to the current flow control region through the contact hole to form an ohmic contact.

[0112] In practical applications, finally, a contact metal is deposited in the n-step trenches to form a source electrode. The contact metal is in contact with the current flow control region through the contact hole to form an ohmic contact.

[0113] In addition, since the methods for constructing the current flow control region are different, the embodiments of the present application can be described in terms of one possible construction method.

[0114] In one case, the formation of the current flow control region in the epitaxial structure specifically includes:

[0115] forming a first P-type doped region in the epitaxial structure based on an ion implantation process;

[0116] forming a first N-type doped region on the first P-type doped region in the epitaxial structure based on an ion implantation process;

[0117] forming a second P-type doped region in the first P-type doped region and the first N-type doped region in the epitaxial structure based on an ion implantation process;

[0118] The second P-type doped region penetrates the first N-type doped region and the first P-type doped region, and the doping concentration of the second P-type doped region is higher than the doping concentration of the first P-type doped region.

[0119] In practical applications, the construction of the current flow control region requires step-by-step injection of different types of ions and different concentrations of ions. Specifically, first, the second type of ions is doped at a low concentration on the bottom layer of the current flow control region to form a first P-type doped region. Then, the first type of ions is doped at a high concentration on the current flow control region and above the first P-type doped region to form a first N-type doped region. In this way, the first P-type doped region semi-wraps the first N-type doped region, which can increase the vertical channel from bottom to top on the basis of the vertical channel from top to bottom. Finally, the second type of ions is doped at a high concentration in the vertical direction according to the layout to form a second P-type doped region, and activation annealing and sacrificial oxidation process are performed under the condition of 1650-1750℃. The second P-type doped region penetrates the first N-type doped region and the first P-type doped region and is connected with the source electrode, further reducing the specific on-resistance, and thus reducing the chip area and cost.

[0120] In addition, since the ways of constructing the gate structure are not the same, the embodiments of the present application can be described with respect to one possible construction method.

[0121] In one case, the gate structure is formed on the side walls of the first to mth stepped trenches and the current flow control region, comprising:

[0122] A gate oxide layer is formed on the side walls of the first to mth stepped trenches and the current flow control region.

[0123] A gate layer is formed on the gate oxide layer; the gate layer is a metal or a polycrystalline gate.

[0124] In practical applications, taking the epitaxial structure of the 2-step stepped trench as an example, at this time m=2, the gate structure is arranged on the side walls of the first and second stepped trenches. Specifically, first, a gate oxide layer is formed on the side walls of the first and second stepped trenches and the corresponding current flow control region, and then a gate layer is formed on the gate oxide layer. The gate layer is a metal or a polycrystalline gate.

[0125] In summary, the method for manufacturing the trench MOSFET device with multiple current channels provided by the embodiments of the present application comprises: providing a basic manufacturing structure; the basic manufacturing structure comprises, from top to bottom, an epitaxial layer, a buffer layer, a substrate layer and a drain; forming n-stage stepped trenches on the epitaxial layer based on an etching process, to form an epitaxial structure with the n-stage stepped trenches; n is a positive integer greater than or equal to 2; forming a current flow control region in the epitaxial structure; the current flow control region is formed by ion doping to form a bidirectional vertical channel; forming a gate structure on the current flow control region on the sidewall of the first to m-stage stepped trenches; m is a positive integer greater than or equal to 2; forming an isolation medium layer on the surface of the gate structure based on a deposition process; opening a contact hole on the isolation medium layer, the contact hole can expose the current flow control region; forming a source electrode in the n-stage stepped trenches based on a deposition process, the source electrode is connected to the current flow control region through the contact hole to form an ohmic contact. In this way, the longitudinal space region is fully utilized to form multiple current channels through the stepped trenches and the current flow control region, and the electric field distribution of the MOSFET device is optimized.

[0126] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-current-path trench MOSFET device, characterized by, The trench MOSFET device comprises a source, an isolation medium layer, a gate structure, an epitaxial structure with n-level stepped trenches, a buffer layer, a substrate layer and a drain; n is a positive integer greater than or equal to 2; The buffer layer, the substrate layer and the drain are sequentially arranged on the non-trench side of the epitaxial structure; The gate structure is arranged on the sidewall of the first to m-level stepped trenches of the epitaxial structure; m is a positive integer greater than or equal to 2; the m-level stepped trench is at the bottom of the m-1-level stepped trench; The source fills the n-level stepped trenches and is isolated from the gate structure by the isolation medium layer; The epitaxial structure is provided with a current flow control area, a contact hole is opened on the isolation medium layer, and the source is connected to the current flow control area in the epitaxial structure through the contact hole to form an ohmic contact; the current flow control area forms a bidirectional vertical channel through ion doping.

2. The multi-current-path trench MOSFET device of claim 1, wherein, The current flow control area comprises a first N-type doped area, a first P-type doped area and a second P-type doped area; the doping concentration of the second P-type doped area is higher than that of the first P-type doped area; The first N-type doped area and the first P-type doped area are sequentially arranged on one side of the source; The first P-type doped area connects the first N-type doped area and the gate structure; The first N-type doped area connects the source and the gate structure; The second P-type doped area is arranged through the first N-type doped area and the first P-type doped area, and simultaneously connects the first N-type doped area, the first P-type doped area and the source.

3. The multi-current-path trench MOSFET device of claim 1, wherein, The gate structure comprises a gate oxide layer and a gate layer; the gate layer is metal or polycrystalline gate; The gate layer is wrapped by the gate oxide layer and the isolation medium layer.

4. The multi-current-path trench MOSFET device of claim 1, wherein, The m is equal to the n; The gate structure forms a symmetrical trench structure in the n-level stepped trench; The two gate structures in the symmetrical trench structure connect the same current flow control area.

5. The multi-current-path trench MOSFET device of claim 1, wherein, The m is equal to the n; The gate structure forms a symmetrical trench structure in the n-level stepped trench; The two gate structures in the symmetrical trench structure each connect one current flow control area; The source in the n-level stepped trench is directly connected to the epitaxial structure to form a Schottky contact.

6. The trench MOSFET device of claim 1, wherein, The epitaxial structure comprises a current expansion layer area; The n-level stepped trench is arranged in the current expansion layer area.

7. The multi-current-path trench MOSFET device of claim 1, wherein, The m is less than the n; The source in the n-level stepped trench is directly connected to the epitaxial structure to form a Schottky contact.

8. A method of fabricating a multi-current-path trench MOSFET device, comprising: A method for manufacturing a multi-current channel trench MOSFET device as claimed in any one of claims 1 to 7, the method comprising: providing a basic manufacturing structure; the basic manufacturing structure comprises, from top to bottom, an epitaxial layer, a buffer layer, a substrate layer and a drain; forming n-level stepped trenches on the epitaxial layer based on an etching process to form an epitaxial structure with n-level stepped trenches; n is a positive integer greater than or equal to 2; forming a current flow control area in the epitaxial structure; the current flow control area forms a bidirectional vertical channel through ion doping; Forming a gate structure on the current flow control region on the sidewall of the 1st to mth level stepped trench; the m is a positive integer ≥2; Forming an isolation medium layer on the surface of the gate structure based on a deposition process; Opening a contact hole on the isolation medium layer, the contact hole can expose the current flow control region; Forming a source electrode in the n level stepped trench based on a deposition process, the source electrode is connected with the current flow control region through the contact hole, forming an ohmic contact.

9. The method of claim 8, wherein, The forming of the current flow control region in the epitaxial structure comprises: Forming a first P-type doped region in the epitaxial structure based on an ion implantation process; Forming a first N-type doped region on the first P-type doped region in the epitaxial structure based on an ion implantation process; Forming a second P-type doped region in the first P-type doped region and the first N-type doped region in the epitaxial structure based on an ion implantation process; The second P-type doped region penetrates the first N-type doped region and the first P-type doped region, and the doping concentration of the second P-type doped region is higher than the doping concentration of the first P-type doped region.

10. The method of claim 8, wherein, The forming of the gate structure on the current flow control region on the sidewall of the 1st to mth level stepped trench comprises: Forming a gate oxide layer on the current flow control region on the sidewall of the 1st to mth level stepped trench; Forming a gate layer on the gate oxide layer; the gate layer is metal or polycrystalline gate.

Images