A wide-range switch tube leakage current detection method and system thereof

Abstract

This application discloses a wide-range leakage current detection method and system for switching transistors, relating to the field of semiconductor device testing technology. The method includes connecting the NMOS switching transistor under test to a transimpedance amplifier to acquire its drain current; the transimpedance amplifier converts the drain current into an output voltage signal V; the switchable feedback resistor includes at least two feedback branches corresponding to different measurement ranges; when the output voltage approaches a negative output saturation threshold, the corresponding gain range is switched; before each measurement cycle, the analog-to-digital converter is grounded via an analog switch, the system offset voltage is sampled, and a digital compensation value for the switching transistor's leakage current is calculated and compensated; the compensated voltage signal is subjected to RC low-pass filtering and software notch filtering before sampling; the sampling result is compared with a preset threshold, and the leakage current detection result is output. This application improves the accuracy of NMOS transistor drain current measurement results and ensures the reliability of device performance evaluation.

Description

Technical Field

[0001] This application relates to the field of semiconductor device testing technology, and in particular to a wide-range switching transistor leakage current detection method and system. Background Technology

[0002] In the production and testing of semiconductor devices, especially NMOS switches, it is crucial to accurately measure their leakage current in the off-state. Leakage current is crucial for evaluating the insulation performance of devices. While existing technologies can detect leakage current, they fall short in terms of high sensitivity, wide range coverage, and interference immunity, making it difficult to meet increasingly stringent testing requirements.

[0003] The currently widely used detection methods rely on traditional voltage or current detection circuits, which can achieve basic leakage current measurement, but their accuracy is often limited by the circuit's input bias current and noise level, especially when measuring tiny currents down to the pA level.

[0004] Existing technologies struggle to maintain high measurement accuracy over a wide range, especially at the pA level, where bias current and noise from conventional circuits have a significant impact, leading to reduced accuracy of measurement results and consequently affecting the reliability of device performance evaluation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, improve the accuracy of NMOS transistor drain current measurement results, and ensure the reliability of device performance evaluation, this application provides a wide-range switching transistor drain current detection method and system.

[0006] Firstly, the objective of this invention is achieved through the following technical solution:

[0007] A wide-range leakage current detection method for switching transistors, comprising:

[0008] With the NMOS switch under test in the off state, its drain connected to the inverting input of the transimpedance amplifier, the drain current is collected. ;

[0009] The drain current is converted into an output voltage signal V by the transimpedance amplifier, and the conversion relationship satisfies... The switchable feedback resistor It includes at least two feedback branches with different resistance values: a first feedback branch and a second feedback branch; the first feedback branch and the second feedback branch correspond to different measurement ranges, respectively.

[0010] When the output voltage is detected to be close to the preset negative output saturation threshold, the corresponding gain range is switched to expand the measurement dynamic range.

[0011] Before the start of each measurement cycle, the input terminal of the analog-to-digital converter is shorted to ground by an analog switch, the system offset voltage is sampled, the digital compensation value of the leakage current of the switching transistor is calculated, and digital compensation is performed in subsequent measurements.

[0012] After performing RC low-pass filtering and software notch filtering on the compensated voltage signal in sequence, digital sampling is performed.

[0013] Based on the comparison between the sampling results and the preset threshold, the leakage current detection result of the switch to be tested is output.

[0014] By adopting the above technical solution, the switching transistor is an NMOS transistor; the system offset voltage is the inherent offset voltage of the analog-to-digital converter, i.e., the front-end circuit; and the leakage current detection result of the switch transistor under test is a conclusion obtained after judging whether the insulation performance of the switch transistor is qualified. The wide-range NMOS switch leakage current detection method of this application is used to detect the reverse leakage current between the drain and source of the NMOS switch transistor under test when it is in the off state. High-precision measurement and insulation performance evaluation are performed. Specifically, to achieve high-precision measurement with a wide dynamic range from 100pA to 11μA and resolve the technical contradiction of traditional detection circuits being unable to balance high sensitivity and large range, this application introduces a transimpedance amplifier (TIA) architecture with multiple switchable feedback resistors. It configures two-stage feedback branches (e.g., feedback branches with 200 MΩ and 680 kΩ resistors) to cover two measurement ranges: 100 pA to 30 nA and 30 nA to 11 μA, effectively extending the system's linear dynamic range. When the output voltage approaches the operational amplifier's negative saturation threshold (e.g., -7.5 V), it automatically switches to a low-gain range to avoid signal distortion and ensure accurate and continuous current response throughout the measurement range, significantly improving the applicability and reliability of the detection. Secondly, to improve the accuracy and stability of pA-level micro-current measurements, the application overcomes the adverse effects of input bias current and system offset on the measurement results. In picoampere-level current sensing, the input bias current of the front-end circuit, PCB surface leakage conductance, and ADC zero-point drift are the main sources of error. This invention constructs a TIA using an electrometer-level operational amplifier (such as the ADA4530-1), whose femtoampere-level input bias current (≤60 fA) is far lower than the level of the leakage current being measured, fundamentally suppressing spurious signals introduced by the front-end circuit itself. Simultaneously, by shorting the ADC input to ground before each measurement cycle using an analog switch, real-time sampling and digital compensation of the overall system offset voltage effectively eliminate static errors caused by device temperature drift, power supply fluctuations, and parasitic parameters, significantly improving the repeatability and long-term stability of low-level measurements. Furthermore, this application also incorporates an RC low-pass filter network at the TIA output to suppress high-frequency switching noise and radio frequency interference; on the other hand, a 50 Hz notch filter algorithm is implemented in the digital domain to accurately attenuate power frequency and its harmonic components, thereby achieving excellent signal-to-noise ratio improvement without sacrificing response speed. This application integrates automated range management and error self-correction mechanisms, possessing good engineering practicality and self-testing adaptability, and is suitable for large-scale online testing scenarios. This application achieves the technical effect of improving the accuracy of drain current measurement results of NMOS transistors and ensuring the reliability of device performance evaluation.

[0015] In a preferred embodiment of this application, the range switching method includes:

[0016] The first feedback branch is set to a 200MΩ high-resistance resistor, corresponding to a range of 100pA~30nA; the second feedback branch is set to a 680kΩ low-resistance resistor, corresponding to a range of 30nA~11μA.

[0017] Monitor the output voltage of the transimpedance amplifier. When the difference between the output voltage and the preset negative output saturation threshold is less than or equal to the threshold, switch the feedback resistor to 680kΩ through an analog switch to extend the range to 11μA.

[0018] After switching, the voltage signal is resampled. If the output voltage is greater than or equal to the preset voltage comparison threshold, the low gain range is maintained; otherwise, the high resistance range is returned.

[0019] By adopting the above technical solution, the first feedback branch is defined as 200 MΩ (corresponding to 100 pA to 30 nA) and the second feedback branch as 680 kΩ (corresponding to 30 nA to 11 μA), thus constructing a dual-range detection system covering three orders of magnitude. This ensures sufficient gain even at extremely low currents and avoids operational amplifier saturation distortion at high currents. In particular, when the output voltage approaches the negative saturation threshold, the system automatically switches to the low-gain range.

[0020] In a preferred embodiment of this application, the offset voltage compensation method includes:

[0021] Before the start of each measurement cycle, the ADC input is shorted to ground using an analog switch to acquire the initial offset voltage. ;

[0022] During formal measurements, calculate the output voltage of the transimpedance amplifier. and The difference is used to obtain the compensated voltage. ;

[0023] For the compensated voltage After digital filtering, it is used in insulation performance determination, and the compensation accuracy reaches the preset full-scale range.

[0024] By adopting the above technical solution, a digital calibration method for zero-point error is provided. An analog switch, such as the ADG1419 analog switch, and an ADC (analog-to-digital converter), are used. The ADG1419 analog switch is used to short-circuit the ADC input to ground before the start of the measurement cycle, allowing real-time acquisition of the initial offset voltage caused by ADC offset, front-end circuit misalignment, and PCB leakage. and during the formal measurement Dynamic compensation is achieved by subtracting from the original output. This method avoids the complexity and temperature drift problems of traditional hardware zero-adjustment circuits.

[0025] In a preferred embodiment of this application, the filtering process includes:

[0026] Hardware RC low-pass filter: A first-order RC filter with a cutoff frequency of 1kHz is used to perform low-pass filtering; the first-order RC filter is located at the output of the transimpedance amplifier.

[0027] Software 50Hz notch filter: Employs a dual-T notch filter, center frequency... =50Hz, quality factor Q=10;

[0028] The digital sampling uses an analog-to-digital converter with a resolution of 16 bits or higher.

[0029] By adopting the above technical solution, the two-stage filtering architecture of hardware RC low-pass filter and software 50Hz notch filter significantly enhances the system's anti-interference capability in complex electromagnetic environments. Specifically, at the hardware level, a first-order RC low-pass filter with a cutoff frequency of 1 kHz is set at the output of the transimpedance amplifier to effectively attenuate high-frequency noise (>1 kHz) from switching power supply and digital circuit coupling, preventing it from entering the ADC and causing aliasing. At the software level, a dual-T digital notch filter can be used, with its center frequency precisely locked at 50 Hz and quality factor Q=10, which can deeply suppress power frequency and its harmonic interference (such as 100 Hz, 150 Hz), with experimentally measured suppression ratios exceeding 40 dB. Combined with an ADC of 16 bits or higher resolution, the system can resolve voltage changes down to the μV level, corresponding to current changes at the pA level. Through the combined hardware and software filtering strategy, the signal-to-noise ratio is significantly improved without sacrificing response speed.

[0030] In a preferred embodiment of this application: the transimpedance amplifier is constructed using an electrometer-level operational amplifier, with an input bias current not exceeding 100 fA; and an overlap range of not less than 10% is set between adjacent ranges.

[0031] By adopting the above technical solution and using an electrometer-level operational amplifier (such as ADA4530-1) with an input bias current not exceeding 100 fA, the spurious current introduced by the preamplifier circuit itself is fundamentally suppressed, ensuring the leakage current under test is measured. It becomes the dominant signal source, avoiding the flooding effect of traditional op-amp bias current (typically >1 pA) on pA-level measurements. At the same time, it clearly defines an overlap range of no less than 10% between adjacent ranges (e.g., the upper and lower limits of the 30 nA range overlap), solving the problem of data breakpoints or misjudgments caused by discontinuous switching points in traditional segmented measurements.

[0032] In a preferred embodiment, this application includes a dynamic operating point tracking unit, which is used to record the voltage and current change trajectories of key nodes in the circuit where the switching transistor is located during simulation; the method further includes:

[0033] Based on the circuit topology of the device under test, the type of switching transistor and key simulation nodes are identified, and a composite equivalent model covering low-frequency conduction, high-frequency switching transients and nonlinear loss characteristics is established; wherein the leakage current parameter in the cutoff region of the composite equivalent model is calibrated based on the wide-range leakage current detection results of the actual switching transistor.

[0034] Configure multi-condition excitation signals to control the composite equivalent model to run simulation under different load conditions, input voltage range and temperature environment. The dynamic operating point tracking unit collects time-domain waveform data of the gate drive signal, drain-source voltage and loop current of the switch transistor.

[0035] Based on the preprocessed time-domain waveform data, the on-resistance, switching loss, reverse recovery characteristics and thermal effect parameters of the switching transistor under various operating conditions are calculated to obtain the simulation calculation parameters.

[0036] The simulation calculation parameters are compared with the preset safe working area boundary to determine whether there is any abnormal risk and generate preliminary abnormal warning information; combined with the nonlinear loss characteristics of the dynamic working point trajectory and the composite equivalent model, potential unstable nodes in the circuit are located and the circuit performance evaluation results are output.

[0037] By adopting the above technical solutions, not only can the performance of the switching transistor and the circuit devices of the target device containing the switching transistor be evaluated, but also potential unstable nodes in the circuit can be located. This application introduces a dynamic operating point tracking unit and a composite equivalent model calibration mechanism, realizing a refined monitoring of changes from the traditional "single parameter detection" to "multi-dimensional circuit performance evaluation". By establishing a composite model covering low-frequency conduction, high-frequency transient and nonlinear loss, and using measured wide-range leakage current data to reverse-calibrate the model parameters, the simulation accuracy is significantly improved.

[0038] In a preferred embodiment, after comparing the simulation calculation parameters with the preset safe working area boundary to determine whether there is an abnormal risk and generating preliminary abnormal warning information, this application further includes:

[0039] The continuous simulation data of the same switching transistor circuit under multiple temperature gradients are normalized, and the switching delay time, threshold voltage drift and saturation voltage drop under different temperature rise conditions are extracted to obtain the electrical parameter change curves.

[0040] Based on multiple sets of time-domain waveform data after normalization and the extracted electrical parameter variation curves, an aging degradation feature set of the switching transistor is constructed.

[0041] The aging and degradation feature set is input into a pre-trained reliability prediction network model to analyze the failure evolution path of the switching transistor during long-term operation, identify potential early degradation regions, and output initial lifetime assessment results.

[0042] Based on the preset device failure classification criteria, the degradation modes in the initial lifetime assessment results are classified to distinguish the failure types caused by thermal fatigue, electromigration, avalanche breakdown or gate punch-through, and degradation cause diagnostic information is generated.

[0043] The initial lifespan assessment results are corrected based on the degradation cause diagnostic information to obtain an optimized remaining lifespan prediction.

[0044] By adopting the above technical solution, the extension from "current state detection" of switching transistors and circuit devices to "future life prediction" is realized. By inputting the aging feature set into the pre-trained reliability prediction network model, early degradation regions driven by physical mechanisms such as thermal fatigue and electromigration are identified, and different failure modes are distinguished. Finally, the initial life assessment results are corrected based on the failure cause diagnosis, and a high-confidence remaining life prediction value is output.

[0045] In a preferred example, this application analyzes the failure evolution path of a switching transistor during long-term operation, identifies potential early degradation regions, and outputs initial lifetime assessment results, including:

[0046] The aging and degradation feature set includes leakage current sequence, junction temperature fluctuation data, switching frequency, duty cycle, peak voltage stress, and peak current stress.

[0047] Based on the peak voltage stress and peak current stress, and combined with the working cycle duration, the energy stress amplitude per unit time is calculated.

[0048] The cumulative fatigue damage factor is calculated based on energy stress amplitude and junction temperature fluctuation data;

[0049] Based on leakage current sequence and cumulative fatigue damage factor, degradation trend feature vector is extracted; input feature matrix is ​​constructed based on degradation trend feature vector and historical operating data, and input into pre-trained reliability prediction network model to analyze the failure evolution path of switch transistor; potential early degradation region is identified based on failure evolution path and degradation state transition rate.

[0050] By employing the above technical solutions, an aging degradation feature set containing multi-dimensional parameters such as leakage current sequence, junction temperature fluctuation, voltage / current stress peak, and switching frequency is constructed to comprehensively characterize the device's operating status. Specifically, this application proposes energy stress amplitude per unit time and cumulative fatigue damage factor as core health indicators, combining them with leakage current degradation trends to construct a degradation trend feature vector, effectively capturing the nonlinear evolution of device performance. Inputting this feature vector into a pre-trained reliability prediction network can identify early degradation regions and output initial lifetime assessment results based on a risk sensitivity index and cumulative damage level, overcoming the limitations of traditional statistical models based on MTBF (Mean Time Between Failures).

[0051] In a preferred embodiment, this application includes: dynamically selecting a matching signal amplification factor through a preset gain switching algorithm, and outputting a gain-adjusted voltage signal. The gain switching algorithm compares the current current signal amplitude with a preset threshold range and automatically switches to the corresponding gain level, so that the output voltage signal is within the optimal sampling range of the analog-to-digital converter.

[0052] The initial voltage value corresponding to the acquired raw leakage current signal is matched with multiple preset threshold intervals, and a gain level is selected that makes the output voltage fall within the input median range of the analog-to-digital converter.

[0053] If the output voltage value continues to approach the upper or lower limit of the analog-to-digital converter input range within a preset number of sampling periods, the gain level will be automatically adjusted up or down by one level.

[0054] During gain switching, a digital filtering algorithm is used to smoothly stitch together the sampled data of adjacent gain levels.

[0055] By adopting the above technical solution and selecting a gain level that ensures the output voltage falls within the median range of the ADC input, the dynamic range of the ADC can be maximized, improving quantization accuracy. During continuous sampling, if the output consistently approaches the upper or lower limit of the range, automatic gain level adjustment is triggered to achieve dynamic tracking. Furthermore, a digital filtering algorithm is introduced during gain switching to smoothly stitch together data from adjacent gain levels, eliminating signal jumps and measurement discontinuities caused by gain transitions, ensuring the continuity and physical consistency of the output voltage sequence; this significantly improves the robustness of the system under varying operating conditions and device conditions.

[0056] Secondly, the objective of this invention is achieved through the following technical solution:

[0057] A wide-range switching transistor leakage current detection system is provided for performing a wide-range switching transistor leakage current detection method as described above.

[0058] In summary, this application includes at least one of the following beneficial technical effects:

[0059] 1. This application provides a wide-range leakage current detection method for switching transistors. By constructing an IV conversion architecture with a transimpedance amplifier (TIA) as its core, continuous and high-precision leakage current measurement from picoampere to microampere levels is achieved. By placing the NMOS switching transistor under test in the off state and connecting its drain to the inverting input of the TIA, multi-range coverage is achieved using a switchable feedback resistor, solving the technical problem of traditional detection circuits struggling to balance sensitivity and linearity over a wide dynamic range. By sampling and digitally compensating the system offset voltage of the ADC and front-end circuit before each measurement cycle, static errors caused by device temperature drift, power supply fluctuations, and PCB parasitic leakage conduction are effectively suppressed, significantly improving the repeatability and long-term stability of low-level measurements.

[0060] 2. This application breaks through the limitations of traditional leakage current detection, which is limited to static parameter measurement. It introduces a dynamic operating point tracking unit and a composite equivalent model calibration mechanism, realizing high-precision performance evaluation from "single parameter detection" to "multi-dimensional circuit performance evaluation". By identifying key nodes in the circuit topology, a composite model covering low-frequency conduction, high-frequency transients and nonlinear losses is established. The model parameters are then reverse-calibrated using measured wide-range leakage current data, which significantly improves simulation accuracy and facilitates refined detection and state tracking of the circuit structure of the switching transistor and the corresponding target device. Attached Figure Description

[0061] Figure 1 This is a circuit diagram illustrating the leakage current detection principle in a wide-range switching transistor leakage current detection method according to an embodiment of this application.

[0062] Figure 2 This is a block diagram illustrating the principle of a wide-range switching transistor leakage current detection system according to one embodiment of this application. Detailed Implementation

[0063] The present application will be further described in detail below with reference to the accompanying drawings.

[0064] In one embodiment, this application discloses a wide-range switching transistor leakage current detection method, which specifically includes the following steps:

[0065] S1: Set the NMOS switch under test to the off state, connect the drain to the inverting input of the transimpedance amplifier, and collect the drain current. .

[0066] In this embodiment, since the NMOS transistor (also called an NMOS tube) has two states when used as a switch: on (conducting) and off (cutoff), theoretically, when the NMOS is in the off state, Id (the drain current of the NMOS transistor) should be zero, but in reality, there is a small leakage current ( The magnitude of leakage current reflects the insulation performance of the device. Leakage current detection assesses the insulation performance by measuring the Id value when the NMOS is off. The normal leakage current of the tested NMOS switch is a few nA or even less, with a maximum leakage current of 1μA. If it exceeds 10μA, its insulation performance is considered unqualified. This leakage current detection system needs to cover a range of 100pA-11μA to meet the leakage current detection requirements of NMOS switches. The wide-range switching transistor leakage current detection method in this embodiment is applicable to NMOS switch leakage current detection systems with a range of 100pA-11μA.

[0067] This embodiment is used to measure the leakage current of NMOS switches in the off-state before semiconductor packaging or during in-line testing. This high-precision measurement, covering a range of 100 pA to 11 μA, meets the testing needs of integrated circuit manufacturing, device R&D, and production line screening. Specifically, the transimpedance amplifier is constructed using an electrometer-level operational amplifier, such as the ADA4530-1, a femtoampere-level (fA, 10-15A) input bias current electrometer operational amplifier. The input bias current does not exceed 100 fA. The typical input bias current of the transimpedance amplifier is 60 fA, the input offset voltage is ≤300 μV, and it integrates a guard buffer. This guard buffer is arranged around the PCB pads of the TIA inverting input terminal and is driven to the same potential as the input terminal by the internal buffer of the ADA4530-1, effectively suppressing the influence of PCB surface leakage current on high-impedance nodes. This embodiment achieves pA-level leakage current detection by selecting an operational amplifier with ultra-low input bias current.

[0068] Specifically, such as Figure 1 The diagram shown is a circuit diagram for leakage current detection. The source (S) of the NMOS switch Q1 (e.g., IRF7407) under test is grounded, and the gate (G) is connected to the off-level (0 V, marked Vin in the diagram) output by the digital control unit, so that it operates in the cutoff region; the drain (D) is connected to the inverting input (-IN) of the transimpedance amplifier (TIA) through a shielded cable to reduce environmental electromagnetic interference.

[0069] S2: The drain current is converted into an output voltage signal V through a transimpedance amplifier, and the conversion relationship satisfies... The switchable feedback resistor It includes at least two feedback branches with different resistance values: a first feedback branch and a second feedback branch; the first feedback branch and the second feedback branch correspond to different measurement ranges.

[0070] In this embodiment, the feedback loop is configured with two branches. The first feedback branch is a 200MΩ high-resistance resistor, corresponding to a range of 100pA to 30nA, to detect weak leakage current within this range. The second feedback branch is a 680kΩ low-resistance resistor, corresponding to a range of 30nA to 11μA, to detect larger leakage current within this range. The first and second feedback branches are switched using a four-channel analog switch ADG1404, which features low charge injection (<10 pC) and high turn-off isolation (>60 dB) to avoid introducing transient interference during the switching process. The TIA power supply uses a ±8V low-noise linear power supply to ensure an output dynamic range of ±7.5V.

[0071] Specifically, an overlap range of no less than 10% is set between adjacent ranges; a Σ-Δ ADC (such as ADS131M04) with 16-bit resolution and a sampling rate of 100kSPS is used as the data acquisition unit to ensure that microvolt-level voltage changes can be accurately quantified.

[0072] The transimpedance amplifier is connected to the first feedback branch by default in the initial stage. ), leakage current Convert to output voltage For example: when When =100 pA, =−20 mV; when =30 nA, =−6 V.

[0073] Furthermore, the entire detection process of the switching transistor leakage current detection method is fully controlled by a microcontroller (MCU, model: STM32H743), including range switching, offset sampling, filtering algorithm execution and result determination.

[0074] S3: When the output voltage is detected to be close to the preset negative output saturation threshold, switch to the corresponding gain range to expand the measurement dynamic range.

[0075] In this embodiment, the range switching method includes:

[0076] The first feedback branch is set to a 200MΩ high-resistance resistor, corresponding to a range of 100pA to 30nA; the second feedback branch is set to a 680kΩ low-resistance resistor, corresponding to a range of 30nA to 11μA. The output voltage of the transimpedance amplifier is monitored. When the difference between the output voltage and the preset negative output saturation threshold is less than or equal to the approach threshold, the feedback resistor is switched to 680kΩ via an analog switch, extending the range to 11μA. After switching, the voltage signal is resampled. If the output voltage is greater than or equal to the preset voltage comparison threshold, the low-gain range is maintained; otherwise, the high-resistance range is returned.

[0077] Specifically, the preset negative output saturation threshold is −7.5 V (at a supply voltage of -8V); the preset voltage comparison threshold is -20mV. Both thresholds can be customized as needed based on the actual NMOS transistor model. The approach threshold is 0.1V. For example: when a threshold is detected... When the voltage is less than or equal to -7.5 V, which is close to the negative output saturation threshold under a -8 V supply, and the difference between the current and -7.5 V is ≤0.1 V (approaching the threshold), it is determined that the current has entered the large signal range, triggering the analog switch ADG1404 to switch to the second feedback branch. ).

[0078] Resampling after switching: If If the voltage is ≥-20mV (preset voltage comparison threshold), the low gain range will be maintained; if If the value is less than -20mV, the measurement returns to the high-gain range, achieving bidirectional adaptive adjustment. Specifically, the overlap between the two ranges of the first and second feedback branches is 30 nA (upper limit of the high range) and 30 nA (lower limit of the low range), with the overlap ratio exceeding 10% to ensure the continuity of the measurement range.

[0079] S4: Before the start of each measurement cycle, the input terminal of the analog-to-digital converter is shorted to ground by an analog switch, the system offset voltage is sampled, the digital compensation value of the leakage current of the switching transistor is calculated, and digital compensation is performed in subsequent measurements.

[0080] In this embodiment, before the start of each measurement cycle (regardless of whether the range is switched), the microcontroller controls the ADG1419 to short-circuit the ADC input to ground, samples and records the output code value at this time, and calculates it back to the initial offset voltage. .

[0081] In this embodiment, the offset voltage compensation method includes: before the start of each measurement cycle, shorting the ADC input terminal to ground via an analog switch to acquire the initial offset voltage. During formal measurements, calculate the output voltage of the transimpedance amplifier. and The difference is used to obtain the compensated voltage. ; for the compensated voltage After digital filtering, it is used in insulation performance determination, and the compensation accuracy reaches the preset full-scale range.

[0082] Specifically, it can be adjusted to four ranges according to actual needs; this embodiment uses two ranges as an example. The preset full-scale range is ±0.1%FSR (Full Scale Range), where FSR is the full-scale range. During actual measurement, the compensated voltage is calculated. Experiments have verified that this compensation mechanism controls the system's zero-point drift within ±0.1% FSR, meeting the technical requirement of "compensation accuracy reaching ±0.1% FSR".

[0083] S5: After performing RC low-pass filtering and software notch filtering on the compensated voltage signal in sequence, digital sampling is performed.

[0084] In this embodiment, the filtering process includes:

[0085] Hardware RC low-pass filter: A first-order RC filter with a cutoff frequency of 1kHz is used to perform low-pass filtering; the first-order RC filter is located at the output of the transimpedance amplifier.

[0086] Software 50Hz notch filter: Employs a dual-T notch filter, center frequency... =50Hz, quality factor Q=10;

[0087] Digital sampling uses analog-to-digital converters with a resolution of 16 bits or higher, such as the 16-bit ADC S8688.

[0088] In this embodiment, the double-T notch filter used for software 50Hz notch filtering has the following transfer function: The center frequency Damping coefficient With a quality factor of Q=10, the measured suppression ratio for 50 Hz power frequency interference is >40 dB.

[0089] The filtered signal is sampled by a 16-bit ADC at a rate of 10 kSPS, and the average value is taken after 100 consecutive sampling cycles to improve the signal-to-noise ratio.

[0090] S6: Based on the comparison between the sampling results and the preset threshold, output the leakage current detection result of the switch to be tested.

[0091] In this embodiment, the core of leakage current detection is to evaluate whether the insulation performance of the NMOS transistor meets the design requirements by measuring its Id in the off state. If the leakage current is >10μA, it is considered unqualified.

[0092] Specifically, based on the feedback resistance value of the currently selected range. Inverted calculation of leakage current ,like If the current is greater than 10μA, the NMOS switch is deemed to have unacceptable insulation performance, and a "FAIL" signal is output; otherwise, a "PASS" signal and specific details are output. Numerical value.

[0093] In one embodiment, a wide-range switching transistor leakage current detection method further includes: dynamically selecting a matching signal amplification factor through a preset gain switching algorithm, outputting a gain-adjusted voltage signal, wherein the gain switching algorithm compares the current current signal amplitude with a preset threshold range and automatically switches to the corresponding gain level, so that the output voltage signal is within the optimal sampling range of the analog-to-digital converter.

[0094] In this embodiment, a dynamic gain switching algorithm and a digital filtering concatenation mechanism are introduced to solve the problems of range switching lag, output jump, and low ADC utilization in traditional multi-range systems. Specifically, the operation process is as follows:

[0095] S100: Matches the initial voltage value corresponding to the acquired raw leakage current signal with multiple preset threshold ranges, and selects the gain level that makes the output voltage fall within the input median range of the analog-to-digital converter.

[0096] In this embodiment, the preset threshold range is the optimal sampling range of the ADC (typically 20% to 80% of the range). Target voltage ranges are defined for two gain levels. The first feedback branch is a low-gain level with a 200MΩ high-resistance resistor, with a target output voltage range of [-7.5 V, -2.0 V]. The second feedback branch is a high-gain level with a 680 kΩ resistor, with a target output voltage range of [-7.5 V, -2.0 V].

[0097] Specifically, after the system is powered on, a trial sampling is first performed at the high gain setting (680kΩ). If the absolute value of the output voltage displayed during the first sampling is less than 20mV, it indicates that the current is extremely small, so switch to the low gain setting (200MΩ). If the absolute value of the output voltage displayed is greater than 7.6V, it indicates that the range may be exceeded, so switch to the high gain setting immediately. Otherwise, keep the current setting.

[0098] S200: If the output voltage value continues to approach the upper or lower limit of the analog-to-digital converter input range within a preset number of sampling periods, the gain level will be automatically adjusted up or down by one level.

[0099] In this embodiment, to avoid false switching due to noise or transient interference, a continuous preset number of sampling confirmation mechanisms is introduced, wherein the continuous preset number of sampling is 3 times and the frequency is 100Hz.

[0100] Specifically, if the output voltage sampled three times consecutively is greater than -1.0V, the trigger gain is increased by one level; if the output voltage sampled three times consecutively is greater than -7.6V, the trigger gain is decreased by one level. After each switch, there is a 50ms delay to wait for the circuit to stabilize before resuming sampling.

[0101] S300: During gain switching, a digital filtering algorithm is used to smoothly stitch together the sampled data of adjacent gain levels.

[0102] In this embodiment, before switching, the last M=5 sampling points (from the original gear) are recorded; after switching, the first M=5 sampling points (from the new gear) are recorded; the two data segments are normalized to the same current scale, and then the overlapping areas are fused using a method such as a Hanning window to achieve a smooth transition.

[0103] In one embodiment, an integrated simulation evaluation platform is also constructed. This platform includes a dynamic operating point tracking unit, which records the voltage and current changes at key nodes in the circuit containing the switching transistor during simulation. The dynamic operating point tracking unit records the voltage and current waveforms of all key nodes in real time during simulation, with a sampling rate of at least 10 MHz and a time resolution of 100 ns, to capture unstable phenomena such as abnormal oscillations, overshoot, and ringing during transient processes. A wide-range switching transistor leakage current detection method further includes:

[0104] S10: Identify the switching transistor type and key simulation nodes based on the circuit topology of the device under test, and establish a composite equivalent model covering low-frequency conduction, high-frequency switching transients and nonlinear loss characteristics; the leakage current parameter in the cutoff region of the composite equivalent model is calibrated based on the wide-range leakage current detection results of the actual switching transistor.

[0105] In this embodiment, based on the target circuit schematic of the device under test (such as a synchronous Buck converter), circuit analysis is performed to identify the type of switching transistor, key simulation nodes, and operating modes. Key simulation nodes include gate drive signals, drain-source voltages, loop currents, and bus voltages. Operating modes include continuous conduction or intermittent conduction.

[0106] Specifically, a composite equivalent model of NMOS is established based on SPICE or Verilog-A language. The composite equivalent model includes a DC conduction model, a transient switching model, a nonlinear loss model, and a cutoff region leakage current model. Among them, the DC conduction model describes the low-frequency conduction characteristics based on Rdson parameters; the transient switching model includes Miller plateau, switching delay, and dV / dt effect; and the nonlinear loss model covers conduction loss, switching loss, and reverse recovery charge. The leakage current model in the cutoff region adopts an exponential function form, with the expression as follows: in, This is the drain-source voltage; , These are the parameters to be calibrated.

[0107] Specifically, the circuit topology identification module is used to analyze the target circuit structure and determine the connection method and operating conditions of the NMOS under test in the circuit. A pre-established NMOS composite equivalent model is then called to apply the measured values ​​from step S1. Import the data into the model calibration module and use the least squares optimization algorithm to adjust the parameters of the cutoff region leakage current model. , This ensures that the error between the simulation output and the measured data is less than ±5%.

[0108] S20: Configure multi-condition excitation signals to control the composite equivalent model to run simulation under different load conditions, input voltage ranges and temperature environments. The dynamic operating point tracking unit collects time-domain waveform data of the gate drive signal, drain-source voltage and loop current of the switching transistor.

[0109] In this embodiment, the integrated simulation evaluation platform defines a test matrix covering the entire working range. For example, the test matrix is ​​as follows:

[0110] Specifically, based on the above test matrix, multiple sets of excitation signals are generated to control the composite equivalent model to run transient simulations under the aforementioned combined conditions. The dynamic operating point tracking unit acquires time-domain waveform data in real time, including the gate drive voltage. Drain-source voltage Drain current Junction temperature change Junction temperature changes are calculated using a thermal resistance model. For example, under high temperature (125°C), full load (5A), and high frequency (1MHz) conditions, we observe whether there are problems such as Miller plateau extension and a surge in switching losses.

[0111] S30: Based on the preprocessed time-domain waveform data, calculate the on-resistance, switching loss, reverse recovery characteristics and thermal effect parameters of the switching transistor under various operating conditions to obtain the simulation calculation parameters.

[0112] In this embodiment, the acquired time-domain waveform data undergoes preprocessing such as denoising, alignment, and periodic averaging. The on-resistance, switching loss, reverse recovery characteristics, and maximum junction temperature are then calculated. The formula for calculating the on-resistance is as follows: , This is the drain-source saturation voltage, i.e., the forward voltage drop. This represents the drain current during simulation, used to measure conduction losses. The formula for calculating switching losses is: Integrating during the switching transition period, This is the drain-source voltage. The reverse recovery characteristic uses the reverse recovery charge. express: , Drain current waveform; maximum junction temperature Power loss is obtained by integrating power loss based on a transient thermal resistance network model to assess the risk of thermal failure. Peak voltage stress extraction is also performed. Maximum instantaneous value, peak current stress extraction The maximum instantaneous value.

[0113] S40: Compare the simulation calculation parameters with the preset safe working area boundary to determine whether there is any abnormal risk and generate preliminary abnormal warning information; combine the dynamic working point trajectory and the nonlinear loss characteristics of the composite equivalent model to locate potential unstable nodes in the circuit and output the circuit performance evaluation results.

[0114] In this embodiment, the simulation calculation parameters in step S30 are compared point by point with the preset safe operating area (SOA) boundary: the SOA boundary defines the device at different drain-source voltages. Maximum allowed Considering factors such as thermal breakdown and secondary breakdown; if under a certain working condition ( , If the trajectory exceeds the SOA envelope, an abnormal risk is identified, and preliminary warning information is generated, such as the possibility of thermal runaway under high temperature and heavy load. The circuit performance evaluation results include circuit performance evaluation reports for each operating condition, including a table of operating condition performance parameters, SOA crossing risk level (which can be divided into high risk, medium risk, and low risk based on thresholds), locations of potential unstable nodes, and improvement suggestions.

[0115] Specifically, combining the dynamic operating point trajectory with nonlinear loss characteristics analysis: observe the drain-source voltage. Is there high-frequency ringing (which may cause EMI to exceed limits)? Analysis Is the rising edge caused by Miller capacitance coupling, resulting in false turn-on? Are there any critical nodes in the positioning circuit that may lead to instability (such as excessive parasitic inductance in the gate drive circuit, unreasonable PCB layout, etc.)?

[0116] In one embodiment, after comparing the simulation calculation parameters with the preset safe working area boundary to determine whether there is an abnormal risk and generating preliminary abnormal warning information, the method further includes:

[0117] S401: Normalize the continuous simulation data of the same switching transistor circuit under multiple temperature gradients, extract the switching delay time, threshold voltage drift and saturation voltage drop changes under different temperature rise conditions, and obtain the electrical parameter change curves.

[0118] In this embodiment, five temperature points are set: T=25℃, 45℃, 65℃, 85℃, and 105℃. Transient simulations are run continuously for no less than 1000 switching cycles at each temperature to simulate the performance evolution of the device under long-term thermal stress. The time-domain waveforms output from each simulation are shown below. Perform time normalization and amplitude normalization. The waveform represents the voltage across the gate over time. Time normalization aligns all waveforms according to the switching cycle and standardizes the sampling rate to 10 MHz. Amplitude normalization uses Z-score standardization to eliminate differences in amplitude dimensions at different temperatures.

[0119] Specifically, the degradation-sensitive parameter—the switching delay time—is extracted periodically from the normalized data. Threshold voltage drift and changes in saturation pressure drop The switching delay time The extraction method is measurement The rising edge reaches 50% to The time difference between the rise to 10%. Threshold voltage drift. pass - Curve fitting yielded Calculate its change with temperature / period. Saturation pressure drop change. By fixing Lower measurement The changes in electrical parameters are plotted as curves representing the variations of key electrical parameters over the simulation period.

[0120] S402: Based on multiple sets of time-domain waveform data after normalization and the extracted electrical parameter change curves, an aging degradation feature set of the switching transistor is constructed.

[0121] In this embodiment, the normalized multiple sets of time-domain waveform data and the extracted electrical parameter variation curves are integrated into a multi-dimensional aging degradation feature set. All data are aligned by timestamps to form a time-series feature matrix. The aging degradation feature set includes leakage current sequences. Junction temperature fluctuation data On / off frequency Duty cycle D, peak voltage stress Peak current stress .

[0122] S403: Input the aging and degradation feature set into the pre-trained reliability prediction network model, analyze the failure evolution path of the switching transistor during long-term operation, identify potential early degradation regions, and output the initial life assessment results.

[0123] In this embodiment, the reliability prediction network model is a pre-trained model constructed using a deep neural network. The input layer of the reliability prediction network model receives the time series of the aging and degradation feature set F, the hidden layer uses a bidirectional LSTM network to capture long-term dependencies, and the output layer outputs the failure evolution path prediction and the initial remaining useful life. The initial lifetime assessment results are in "equivalent operating hours", which represent the time from the current state of the device to failure.

[0124] During training, the reliability prediction network model uses historical accelerated aging experimental data (high temperature reverse bias HTRB, high temperature gate bias HTGB, etc.) as the training set; the label is the actual failure time; the loss function adopts Huber Loss to improve robustness to outliers.

[0125] Specifically, in step S403, the failure evolution path of the switching transistor during long-term operation is analyzed, potential early degradation regions are identified, and initial lifetime assessment results are output, including:

[0126] S4031: Calculate the energy stress amplitude per unit time based on the peak voltage stress and peak current stress, combined with the working cycle duration.

[0127] In this embodiment, based on peak voltage stress and peak current stress Combined with the duration of the work cycle Calculate the energy stress amplitude per unit time. Its expression is: .

[0128] S4032: Calculate the cumulative fatigue damage factor based on energy stress amplitude and junction temperature fluctuation data.

[0129] In this embodiment, a thermo-electric coupling fatigue model of the switching transistor material layer is constructed using Miner's linear damage accumulation theory and a temperature acceleration factor:

[0130] in, As the reference energy stress, Let m be the energy stress amplitude in the k-th cycle, m be the material nonlinearity index, and ΔH be the activation energy. Boltzmann's constant, For reference temperature, Let N be the junction temperature of the k-th cycle. N is the total number of evaluation cycles.

[0131] S4033: Based on leakage current sequence and cumulative fatigue damage factor, a degradation trend feature vector is extracted; based on the degradation trend feature vector and historical operating data, an input feature matrix is ​​constructed and input into a pre-trained reliability prediction network model to analyze the failure evolution path of the switching transistor; based on the failure evolution path and degradation state transition rate, potential early degradation regions are identified.

[0132] In this embodiment, the leakage current growth rate is defined. And calculate its sliding window mean. with standard deviation Simultaneous calculation rate of change ;Will , , and Constructing a four-dimensional degradation trend feature vector yields the degradation trend feature vector. . A value less than 1 indicates that the device is still in a safe operating condition. If the value is greater than or close to 1, the device is considered to have reached the end of its lifespan and may fail.

[0133] Specifically, the degradation trend feature vector Together with historical data, they form the input feature matrix X(t), which is then input into a pre-trained reliability prediction network model. The reliability prediction network model is a CNN-BiLSTM structure with an attention mechanism, and its input layer receives time series data of length T. After extracting local degradation patterns through convolutional layers, bidirectional LSTM layers capture forward and backward temporal dependencies, outputting a hidden state sequence over T time steps. ,in Use an attention mechanism to calculate the importance and attention weights for each time step. ,in, Let be the hidden state vector at the i-th time step. This is the attention weight matrix. This is the attention bias vector, used to adjust the initial position of the attention score; For attention context vectors; For attention scoring functions; This is a softmax normalization term that makes the sum of all attention weights equal to 1. The weighted result is the context vector. It is used for the final classification decision.

[0134] Based on the attention-weighted context vector c, the failure evolution path of the switching transistor is analyzed. The reliability prediction network model outputs the probability distribution of the degradation state at the current moment. ,in These correspond to the degradation types of "healthy", "early degradation", "intermediate degradation" and "imminent failure".

[0135] Based on the state transition probabilities at consecutive time points, a Markov state transition graph G=(V, A) is constructed, where node V represents the degradation stage and edge weights are... This represents the probability of transitioning from stage i to stage j.

[0136] S4034: Outputs initial life assessment results based on the risk sensitivity index of the early degradation region and the current cumulative fatigue damage.

[0137] In this embodiment, potential early degradation regions are identified based on the failure evolution path and degradation state transition rate; that is, when the model outputs a state of "early degradation" for K consecutive steps, and the degradation state transition rate is... At that time, it is determined that the region has entered the early degradation zone; simultaneously, the risk sensitivity index of this zone is calculated. The calculation formula is: ,in The normalized weights are determined by regression calibration using historical fault data.

[0138] Specifically, based on the risk sensitivity index of early degradation areas and current cumulative fatigue damage To output the initial lifetime assessment results, the remaining useful life (RUL) prediction function first needs to be established:

[0139] in, The critical damage threshold, The model parameters are calibrated through accelerated aging experiments; the final output is the initial lifetime assessment result RUL(t) and its confidence interval. .

[0140] S404: Based on the preset device failure classification criteria, classify the degradation modes in the initial lifetime assessment results, distinguish the failure types caused by thermal fatigue, electromigration, avalanche breakdown or gate punch-through, and generate degradation cause diagnostic information.

[0141] In this embodiment, the classifier for the preset device failure classification criteria is a support vector machine (SVM). Degradation cause diagnostic information includes information such as the current degradation being primarily caused by thermal fatigue, with electromigration as a secondary factor.

[0142] Specifically, thermal fatigue is characterized by periodic and drastic fluctuations in junction temperature and on-resistance. A slow increase is observed, with diagnostic criteria including junction temperature change >50°C / cycle (i.e., junction temperature change exceeding 50 degrees Celsius in each duty cycle), and a strong correlation with power cycling. Electromigration is characterized by on-resistance... A sustained increase in leakage current, with a slight increase in leakage current, can be diagnosed based on long-term exposure to high current density (>1 mA / cm²). Avalanche breakdown is characterized by a decrease in drain-source voltage. A momentary overshoot occurs, causing a step increase in leakage current. Diagnostic criteria include leakage-source voltage. The voltage exceeds the breakdown voltage, and the energy integral exceeds the rated value. Gate punch-through is characterized by a sharp increase in leakage current and a significant drift in the threshold voltage. Diagnostic criteria include a synchronous and dramatic increase in gate leakage current, consistent with the characteristics of Fowler-Nordheim tunneling.

[0143] S405: Based on the diagnostic information of degradation causes, the initial life assessment results are corrected to obtain an optimized remaining life prediction value.

[0144] In this embodiment, the initial life assessment results are weighted and corrected based on the degradation cause diagnosis information:

[0145] in, The estimated remaining useful life is the optimized value. This represents the initial remaining useful life. Correction factors for various failure types, such as those for failures dominated by thermal fatigue. =0.8, when electromigration is severe =0.7, when the avalanche event has already occurred. =0.5.

[0146] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0147] In one embodiment, such as Figure 2 As shown, a wide-range switching transistor leakage current detection system is provided, which corresponds to a wide-range switching transistor leakage current detection method in the above embodiments.

[0148] like Figure 2 As shown, a wide-range switching transistor leakage current detection system includes a leakage current acquisition module, an analog-to-digital conversion module, an FPGA control circuit, a bus interface circuit, and a PXI interface. Detailed descriptions of each functional module are as follows:

[0149] The leakage current acquisition module is used to put the NMOS switch under test in the off state and connect the drain of the NMOS switch under test to the inverting input of the transimpedance amplifier in order to acquire the drain current. The feedback network of the transimpedance amplifier is equipped with a switchable feedback resistor, which includes at least two first feedback branches and second feedback branches with different resistance values, each corresponding to a different measurement range. When the output voltage of the transimpedance amplifier is detected to be close to a preset negative saturation threshold, it automatically switches to the corresponding gain programmable branch.

[0150] The analog-to-digital conversion module is used to receive the voltage signal output by the leakage current acquisition module and perform digital sampling to obtain digital sampling data;

[0151] The FPGA control circuit is used to control the working timing of the analog-to-digital conversion module, receive digital sampling data, and sequentially perform RC low-pass filtering and software notch filtering on the digital sampling data; then send the filtered digital sampling data to the bus interface circuit.

[0152] The bus interface circuit is used to implement a double buffering mechanism, alternately receiving data from the FPGA control circuit and transmitting it to the PXI interface.

[0153] The PXI interface is used to output leakage current detection data processed by the ping-pong interface circuit to an external test system or a preset terminal.

[0154] In this embodiment, the analog-to-digital conversion module is a 16-bit ADC chip, model ADS888. Its input is shorted to ground via an analog switch before the start of each measurement cycle to acquire the offset voltage of the sampling system and generate a digital compensation value. The bus interface circuit is a ping-pong interface circuit with a double-buffered mechanism. The PXI interface communicates with the host computer via the standard PXI bus protocol, outputting the leakage current detection result of the NMOS switch under test.

[0155] For specific limitations regarding a wide-range switching transistor leakage current detection system, please refer to the limitations of a wide-range switching transistor leakage current detection method mentioned above, which will not be repeated here. Each module in the aforementioned wide-range switching transistor leakage current detection system can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in the processor of a computer device in hardware form or independent of the processor, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0156] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0157] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for detecting leakage current of a switching transistor with a wide range, characterized in that, include: With the NMOS switch under test in the off state, its drain connected to the inverting input of the transimpedance amplifier, the drain current is collected. ; The drain current is converted into an output voltage signal V by the transimpedance amplifier, and the conversion relationship satisfies... The switchable feedback resistor It includes at least two feedback branches with different resistance values: a first feedback branch and a second feedback branch; the first feedback branch and the second feedback branch correspond to different measurement ranges, respectively. When the output voltage is detected to be close to the preset negative output saturation threshold, the corresponding gain range is switched to expand the measurement dynamic range. Before the start of each measurement cycle, the input terminal of the analog-to-digital converter is shorted to ground by an analog switch, the system offset voltage is sampled, the digital compensation value of the leakage current of the switching transistor is calculated, and digital compensation is performed in subsequent measurements. After performing RC low-pass filtering and software notch filtering on the compensated voltage signal in sequence, digital sampling is performed. Based on the comparison between the sampling results and the preset threshold, the leakage current detection result of the switch to be tested is output. The range switching methods include: The first feedback branch is set to a 200MΩ high-resistance resistor, corresponding to a range of 100pA~30nA; the second feedback branch is set to a 680kΩ low-resistance resistor, corresponding to a range of 30nA~11μA. Monitor the output voltage of the transimpedance amplifier. When the difference between the output voltage and the preset negative output saturation threshold is less than or equal to the threshold, switch the feedback resistor to 680kΩ through an analog switch to extend the range to 11μA. After switching, the voltage signal is resampled. If the output voltage is greater than or equal to the preset voltage comparison threshold, the low gain range is maintained; otherwise, the high resistance range is returned. The method includes a dynamic operating point tracking unit, which records the voltage and current changes at key nodes in the circuit containing the switching transistor during simulation; the method also includes: Based on the circuit topology of the device under test, the type of switching transistor and key simulation nodes are identified, and a composite equivalent model covering low-frequency conduction, high-frequency switching transients and nonlinear loss characteristics is established; wherein the leakage current parameter in the cutoff region of the composite equivalent model is calibrated based on the wide-range leakage current detection results of the actual switching transistor. Configure multi-condition excitation signals to control the composite equivalent model to run simulation under different load conditions, input voltage range and temperature environment. The dynamic operating point tracking unit collects time-domain waveform data of the gate drive signal, drain-source voltage and loop current of the switch transistor. Based on the preprocessed time-domain waveform data, the on-resistance, switching loss, reverse recovery characteristics and thermal effect parameters of the switching transistor under various operating conditions are calculated to obtain the simulation calculation parameters. The simulation calculation parameters are compared with the preset safe working area boundary to determine whether there is any abnormal risk and generate preliminary abnormal warning information; combined with the nonlinear loss characteristics of the dynamic working point trajectory and the composite equivalent model, potential unstable nodes in the circuit are located and the circuit performance evaluation results are output.

2. The method for detecting leakage current of a switching transistor with a wide range according to claim 1, characterized in that, Offset voltage compensation methods include: Before the start of each measurement cycle, the ADC input is shorted to ground using an analog switch to acquire the initial offset voltage. ; During formal measurements, calculate the output voltage of the transimpedance amplifier. and The difference is used to obtain the compensated voltage. ; For the compensated voltage After digital filtering, it is used in insulation performance determination, and the compensation accuracy reaches the preset full-scale range.

3. The method for detecting leakage current of a switching transistor with a wide range according to claim 1, characterized in that, The filtering process includes: Hardware RC low-pass filter: A first-order RC filter with a cutoff frequency of 1kHz is used to perform low-pass filtering; the first-order RC filter is located at the output of the transimpedance amplifier. Software 50Hz notch filter: Employs a dual-T notch filter, center frequency... =50Hz, quality factor Q=10; The digital sampling uses an analog-to-digital converter with a resolution of 16 bits or higher.

4. The method for detecting leakage current of a switching transistor with a wide range according to claim 1, characterized in that, The transimpedance amplifier is constructed using an electrometer-level operational amplifier, with an input bias current not exceeding 100 fA; an overlap range of not less than 10% is set between adjacent ranges.

5. The method for detecting leakage current of a switching transistor with a wide range according to claim 1, characterized in that, After comparing the simulation calculation parameters with the preset safe working area boundary to determine whether there is any abnormal risk and generating preliminary abnormal warning information, the process further includes: The continuous simulation data of the same switching transistor circuit under multiple temperature gradients are normalized, and the switching delay time, threshold voltage drift and saturation voltage drop under different temperature rise conditions are extracted to obtain the electrical parameter change curves. Based on multiple sets of time-domain waveform data after normalization and the extracted electrical parameter variation curves, an aging degradation feature set of the switching transistor is constructed. The aging and degradation feature set is input into a pre-trained reliability prediction network model to analyze the failure evolution path of the switching transistor during long-term operation, identify potential early degradation regions, and output initial lifetime assessment results. Based on the preset device failure classification criteria, the degradation modes in the initial lifetime assessment results are classified to distinguish the failure types caused by thermal fatigue, electromigration, avalanche breakdown or gate punch-through, and degradation cause diagnostic information is generated. The initial lifespan assessment results are corrected based on the degradation cause diagnostic information to obtain an optimized remaining lifespan prediction.

6. The method for detecting leakage current of a switching transistor with a wide range according to claim 5, characterized in that, The analysis examines the failure evolution path of the switching transistor during long-term operation, identifies potential early degradation regions, and outputs initial lifetime assessment results, including: The aging and degradation feature set includes leakage current sequence, junction temperature fluctuation data, switching frequency, duty cycle, voltage stress peak value, and current stress peak value. Based on the peak voltage stress and the peak current stress, and combined with the working cycle duration, the energy stress amplitude per unit time is calculated. Based on the energy stress amplitude and junction temperature fluctuation data, the cumulative fatigue damage factor is calculated; Based on the leakage current sequence and the cumulative fatigue damage factor, a degradation trend feature vector is extracted; based on the degradation trend feature vector and historical operating data, an input feature matrix is ​​constructed and input into a pre-trained reliability prediction network model to analyze the failure evolution path of the switching transistor; based on the failure evolution path and degradation state transition rate, potential early degradation regions are identified. Based on the risk sensitivity index of the early degradation region and the current cumulative fatigue damage, the initial life assessment results are output.

7. The method for detecting leakage current of a switching transistor with a wide range according to claim 1, characterized in that, include: The signal amplification factor is dynamically selected by a preset gain switching algorithm, and the voltage signal with gain adjustment is output. The gain switching algorithm compares the current current signal amplitude with a preset threshold range and automatically switches to the corresponding gain level, so that the output voltage signal is within the optimal sampling range of the analog-to-digital converter. The initial voltage value corresponding to the acquired raw leakage current signal is matched with multiple preset threshold intervals, and a gain level is selected that makes the output voltage fall within the input median range of the analog-to-digital converter. If the output voltage value continues to approach the upper or lower limit of the analog-to-digital converter input range within a preset number of sampling periods, the gain level will be automatically adjusted up or down by one level. During gain switching, a digital filtering algorithm is used to smoothly stitch together the sampled data of adjacent gain levels.

8. A wide-range switching transistor leakage current detection system, characterized in that, Used to perform a wide-range switching transistor leakage current detection method as described in any one of claims 1 to 7.

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