A Fixed-Point Matrix FFT Calculation Method Based on Memristors

Abstract

This invention provides a fixed-point matrix FFT calculation method based on memristors, belonging to the fields of signal processing and image processing technology. First, a nonlinear voltage-controlled memristor model is constructed, simulating state transition behavior in logic operations through a dynamic adjustment mechanism to realize the function of basic logic gates. Second, an FFT algorithm based on matrix block optimization is designed, decomposing the FFT calculation into small-scale matrix operation units and optimizing computational efficiency by combining Kronecker product and permutation matrix. This is then recursively extended to higher-point FFT operations. Simultaneously, a full adder and multiplier are designed based on memristors to achieve efficient fixed-point operations. Finally, the method is applied to image FFT processing to obtain the processing results. This invention achieves higher computational efficiency and lower energy consumption while maintaining computational accuracy, and can be widely applied in image processing, signal analysis, scientific computing, and other fields, possessing significant practical value and application prospects.

Description

Technical Field

[0001] This invention relates to the fields of signal processing and image processing technology, and in particular to a fixed-point matrix FFT calculation method based on memristors. Background Technology

[0002] The Fast Fourier Transform (FFT) is one of the fundamental algorithms in digital signal processing, with wide applications in image processing, communication systems, and scientific computing. Traditional FFT implementations primarily rely on digital processors, employing a von Neumann architecture for serial computation. While this approach is stable on general-purpose computing platforms, it suffers from low computational efficiency and high energy consumption when processing large-scale data due to frequent data transfers between memory and the processor. Furthermore, as application scenarios become more complex, higher demands are placed on the real-time performance and energy efficiency of FFT computations.

[0003] To improve the computational efficiency of FFT, researchers have proposed various optimization schemes, such as using FPGAs for parallel computing and employing dedicated ASIC chips. However, these schemes still face the memory wall limitation, namely the data transmission bottleneck caused by the physical separation of computing and storage units. Meanwhile, the power consumption issues of traditional digital circuits also limit further improvements in computational performance.

[0004] In recent years, with the development of memristor technology, a new computing paradigm has gradually attracted attention. As the fourth basic circuit element, memristors have the dual characteristics of non-volatile storage and analog computing. Their resistance can be dynamically adjusted by applying voltage or current. This characteristic makes them very suitable for implementing matrix operations. Memristor arrays naturally support parallel computing and can complete calculation operations directly in the storage unit. Summary of the Invention

[0005] To address the problems faced by existing FFT calculations, this invention proposes a fixed-point matrix FFT calculation method based on memristors. Compared with traditional digital FFT implementations, this method has higher computational efficiency and lower energy consumption. Through innovative matrix factorization strategies and the parallel computing capabilities of memristor arrays, this method demonstrates significant advantages in applications such as signal processing and image transformation. In particular, when processing large-scale FFT operations, this method effectively solves the data transmission bottleneck problem in traditional architectures by leveraging the in-memory computing characteristics of memristors.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A fixed-point matrix FFT calculation method based on memristors, the method comprising the following steps:

[0008] Step S1: Construct a nonlinear voltage control model for the memristor and use the memristor to implement the logic units of AND gate, OR gate and XOR gate. The AND gate implements the logical AND operation through the series characteristics of the memristor, the OR gate implements the logical OR operation through the parallel characteristics of the memristor, and the XOR gate implements the logical XOR operation by combining the logical relationships of the AND gate and the OR gate.

[0009] Step S2: Design an FFT optimization algorithm based on matrix block partitioning. The FFT calculation is simplified by partitioning the matrix into small-scale matrix operation units.

[0010] Step S3: Construct a fixed-point FFT algorithm based on memristors. In this algorithm, the input signal is first converted into a digital signal and represented in binary form. Then, based on the binary value of the input signal, it is mapped to different conductance levels of the memristor to realize the mapping of the input signal to the conductance state of the memristor. Based on the two-dimensional matrix FFT calculation, it is expanded to a higher-point FFT layer by layer through recursive matrix operations to complete the fixed-point FFT calculation.

[0011] Step S4: Fixed-point addition and multiplication operations are performed using memristor-based full adders and multipliers. The memristor-based full adder consists of multiple memristor-based ternary adders. The number of ternary adders is the same as the number of fixed-point bits. Each ternary adder provides two data input ports and one low-order carry input port. The ternary adder implements the basic logic units of AND gate, OR gate and XOR gate through memristors.

[0012] Step S5: Perform fixed-point matrix FFT processing on the image data according to steps S1 to S4 to obtain the processing result.

[0013] Furthermore, the resistance change in the nonlinear voltage control model of the memristor in step S1 is expressed as: ,in, Indicates the resistance value of the memristor. This is the minimum resistance value of the memristor. This represents the maximum resistance of the memristor. The minimum and maximum resistances of the memristor are determined by its hardware physical characteristics. It is an internal state variable used to control the dynamic changes in resistance.

[0014] Furthermore, in step S2, the overall FFT is decomposed into the FFT calculation of a two-dimensional matrix, which is expressed as:

[0015] ;

[0016] in, This represents the input data matrix for the FFT. It is the weight matrix of a 2-point FFT. It is the weight matrix of a 4-point FFT. It is the core intermediate weight matrix for implementing the 4-point Fast Fourier Transform (FFT-4). It is the identity matrix. Represents the Kronecker product. This is the permutation matrix of the input data, responsible for optimizing the arrangement of the data by reversing the binary bit order. The permutation process is represented in the following matrix form:

[0017] ;

[0018] Weight matrix of 2-point FFT Represented as:

[0019] ;

[0020] Weight matrix of 4-point FFT Represented as: ;

[0021] The core intermediate weight matrix of the 4-point Fast Fourier Transform (FFT-4) is represented as follows: .

[0022] Furthermore, the recursive matrix operation in step S3 is represented as follows:

[0023] ;

[0024] in, This is the output of the current layer. It is the weight matrix of the current layer. pass The k-th order tensor product expansion calculation, Indicates the level of recursion. It is the identity matrix. This is the matrix result generated by the previous layer, where the first layer calculation is a two-point FFT implemented through butterfly operations.

[0025] Furthermore, each ternary adder includes three memristor-based logic function modules, each containing multiple memristors. The operational logic of the ternary adder is as follows:

[0026] ;

[0027] ;

[0028] Where A and B represent the two 1-bit input data of the ternary adder. S represents the carry-in of the ternary adder, and S represents the local bit and output of the ternary adder. This indicates the carry-out output of the ternary adder. This represents the logical AND operation. Represents a logical OR operation. Represents the XOR operation;

[0029] A multiplier based on memristors is constructed to implement fixed-point multiplication using bit-by-bit multiplication and partial accumulation. For an n-bit fixed-point number, an n×n multiplier is constructed to implement fixed-point multiplication, which is represented as follows:

[0030] ;

[0031] in, The result of multiplication of n-digit fixed-point numbers. and For binary bits, and Indicates an index. It represents the logical AND operation, and the accumulation of partial products is completed by a full adder, ultimately forming the complete multiplication result.

[0032] The beneficial technical effects of this invention are as follows:

[0033] This invention constructs a nonlinear voltage-controlled memristor model, simulating state transition behavior in logic operations through a dynamic adjustment mechanism, thus realizing the functionality of basic logic gates. Secondly, it designs an FFT algorithm based on matrix block optimization, decomposing the FFT calculation into small-scale matrix operation units and optimizing computational efficiency by combining Kronecker products and permutation matrices. This is then extended recursively to higher-point FFT operations, utilizing dynamically loaded weight matrices and task queue scheduling to achieve efficient data processing. Simultaneously, a full adder and multiplier are designed based on the memristor to achieve efficient fixed-point arithmetic. Finally, this method is applied to image FFT processing, improving processing speed through data block partitioning and parallel computing. This invention leverages the non-volatility and efficient conductance adjustment capabilities of memristors, eliminating the need for continuous power supply to maintain data and saving the significant energy consumption of traditional digital circuits for data conversion and transmission. While maintaining computational accuracy, this method offers higher computational efficiency and lower energy consumption compared to traditional digital FFT implementations, particularly demonstrating significant advantages when processing large-scale image data. This method can be widely applied in image processing, signal analysis, scientific computing, and other fields, possessing significant practical value and application prospects. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of a fixed-point matrix FFT calculation method based on memristors provided in an embodiment of the present invention;

[0036] Figure 2 This is a flowchart of the recursive calculation and task scheduling of the matrix block-optimized FFT algorithm provided in this embodiment of the invention;

[0037] Figure 3 This is a schematic diagram of a memristor-based full adder circuit constructed according to an embodiment of the present invention;

[0038] Figure 4 This is a flowchart of the FFT algorithm based on memristors provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram illustrating the results of efficient 4-bit fixed-point addition and multiplication operations performed using a memristor-based full adder and multiplier, as provided in this embodiment of the invention. In the diagram, (a) indicates that the first bit of the result from the memristor-based multiplier is 1; (b) indicates that the second bit of the result from the memristor-based multiplier is 0; (c) indicates that the third bit of the result from the memristor-based multiplier is 0; (d) indicates that the fourth bit of the result from the memristor-based multiplier is 0; (e) indicates that the fifth bit of the result from the memristor-based multiplier is 0; and (f) represents the result of the memristor-based multiplier operation. The sixth bit of the binary number is 1, (g) indicates that the seventh bit of the result of the memristor-based multiplier is 1, (h) indicates that the eighth bit of the result of the memristor-based multiplier is 1, (i) indicates that the first bit of the result of the memristor-based full adder is 0, (j) indicates that the second bit of the result of the memristor-based full adder is 1, (k) indicates that the third bit of the result of the memristor-based full adder is 1, (l) indicates that the fourth bit of the result of the memristor-based full adder is 1, and (m) indicates that the fifth bit of the result of the memristor-based full adder is 1.

[0040] Figure 6These are example images of fixed-point matrix FFT processing of images based on memristors, provided in an embodiment of the present invention. (a) represents the result of a 4-point FFT calculation on the image without normalization; (b) represents the result of an 8-point FFT calculation on the image without normalization; (c) represents the result of a 16-point FFT calculation on the image without normalization; (d) represents the result of a 32-point FFT calculation on the image without normalization; (e) represents the result of a 64-point FFT calculation on the image without normalization; (f) represents the result of a 4-point FFT calculation on the image with normalization; (g) represents the result of an 8-point FFT calculation on the image with normalization; (h) represents the result of a 16-point FFT calculation on the image with normalization; (i) represents the result of a 32-point FFT calculation on the image with normalization; and (j) represents the result of a 64-point FFT calculation on the image with normalization. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] A fixed-point matrix FFT calculation method based on memristors, such as Figure 1 As shown, the method includes the following steps:

[0043] Step S1. Construct a nonlinear voltage control model for the memristor. This model, through a nonlinear dynamic adjustment mechanism, can accurately simulate changes and state transitions in logic operations. The resistance change of this nonlinear voltage control model for the memristor is described by the following formula: ,in, Indicates the resistance value of the memristor. This is the minimum resistance value of the memristor. This represents the maximum resistance of the memristor. The minimum and maximum resistances of the memristor are determined by its hardware physical characteristics. This is an internal state variable used to control the dynamic changes in resistance. Memristors are used to implement AND, OR, and XOR logic units. The AND gate uses the series connection of the memristors to perform the logical AND operation, the OR gate uses the parallel connection of the memristors to perform the logical OR operation, and the XOR gate uses the logical relationship between the AND and OR gates to perform the logical XOR operation.

[0044] Step S2. Design an FFT optimization algorithm based on matrix block partitioning. This algorithm simplifies FFT calculation by decomposing the overall FFT into small-scale matrix operation units. In this embodiment, the overall FFT is decomposed into FFT calculation of a two-dimensional matrix. The FFT calculation of a two-dimensional matrix is ​​represented as follows:

[0045] ;

[0046] in, This represents the input data matrix for the FFT. It is the weight matrix of a 2-point FFT. It is the weight matrix of a 4-point FFT. It is the core intermediate weight matrix for implementing the 4-point Fast Fourier Transform (FFT-4). It is the identity matrix. Represents the Kronecker product. This is a permutation matrix of the input data, responsible for optimizing the arrangement of the data by reversing the binary bit order. The permutation process can be represented in the following matrix form:

[0047] ;

[0048] In a butterfly structure, the weight matrix of a 2-point FFT can be represented as:

[0049] ;

[0050] Weight matrix of 4-point FFT Represented as: ;

[0051] The core intermediate weight matrix of the 4-point Fast Fourier Transform (FFT-4) is represented as follows:

[0052] .

[0053] To further optimize computational efficiency and fully utilize the sparsity of the FFT matrix, redundant computations are reduced through block partitioning. This block-based recursive algorithm combines matrix permutation with Kronecker product operations, significantly reducing data transfer and storage requirements.

[0054] This invention decomposes FFT matrix operations into basic 2×2 matrix operations, while It can be further organized into a combination of multiple 2×2 basic modules. This structure can directly match the parallel computing capabilities of memristor basic operational circuit units (such as logic gates and adders).

[0055] Step S3. Construct a fixed-point FFT algorithm based on memristors. In this algorithm, the input signal is first converted into a digital signal and represented in binary form. Then, based on the binary value of the input signal, it is mapped to different conductance levels of the memristor to realize the mapping of the input signal to the conductance state of the memristor. Based on the two-dimensional matrix FFT calculation, it is expanded to higher-point FFT layer by layer through recursive matrix operations to complete the fixed-point FFT calculation.

[0056] The computational task of each layer of the FFT is operated on by dynamically loading the weight matrix. During the operation, the calculation result of the current layer is used as the input of the next layer. The recursive matrix operation is described by the following formula:

[0057] ;

[0058] in, This is the output of the current layer. It is the weight matrix of the current layer. pass The k-th order tensor product expansion calculation, Indicates the level of recursion. It is the identity matrix. This is the result of the matrix generated in the previous layer.

[0059] Through dynamic queues The recursive loading of the weight matrix enables efficient execution of computational tasks at each layer. The parallel computing characteristics of the memristor ensure that computational tasks at each layer are processed simultaneously, significantly improving the efficiency of FFT computation and optimizing resource allocation.

[0060] Figure 2 The flowchart of recursive matrix operations is shown, which is based on a scale of Point FFT (denoted as) Starting from the top level, through (Input rearrangement matrix) (Transformation weight matrix) (Input the transpose of the rearranged matrix) (Identity matrix) (Kronecker product with the next layer's FFT weight matrix) (Input rearrangement matrix) This series of matrix operations is implemented. The point FFT is decomposed, and then the process recursively moves downwards. Point FFT decomposes into smaller scales Point FFT (denoted as) Furthermore, the matrix operation structure of each layer is completely consistent with that of the top layer, only the matrix indices are replaced with the current FFT scale (e.g., ...). Replace with This recursive process continues until it decomposes to an 8-point FFT (fft8) and a 4-point FFT (fft4), ultimately reaching the most basic 2-point FFT unit (fft2), whose weight matrix... (and equal to) ) clearly defined as ,in It is the rotation factor of the 2-point FFT. The entire process recursively decomposes the top-level large-scale FFT into the bottom-level small-scale FFT, and reuses the same matrix operation structure in each layer. With the most basic 2-point FFT unit as the core, it constructs arbitrary... Point-scale FFT operation.

[0061] Step S4. Perform fixed-point addition and multiplication operations using memristor-based full adders and multipliers: The memristor-based full adder consists of multiple memristor-based ternary adders, the number of which is the same as the number of fixed-point bits. Each ternary adder provides two data input ports and one low-order carry input port. The ternary adder implements the basic logic units of AND, OR, and XOR gates through memristors. The operation logic is as follows:

[0062] ;

[0063] ;

[0064] Where A and B represent the two 1-bit input data of the ternary adder. S represents the carry-in of the ternary adder, and S represents the local bit and output of the ternary adder. This indicates the carry-out output of the ternary adder. This represents the logical AND operation. Represents a logical OR operation. This represents the XOR operation, which combines a full adder with a memristor to perform bit-by-bit addition.

[0065] Meanwhile, a multiplier based on memristors is constructed to implement fixed-point multiplication using bit-by-bit multiplication and partial accumulation. For an n-bit fixed-point number, an n×n multiplier is constructed to implement fixed-point multiplication, which is represented as follows:

[0066] ;

[0067] in, The result of multiplication of n-digit fixed-point numbers. and For binary bits, and Indicates an index. The logic AND operation is represented by a full adder, where the accumulation of partial products is performed, ultimately forming the complete multiplication result. By combining full adders and multipliers, memristors can efficiently perform fixed-point addition and multiplication operations, significantly improving the energy efficiency and parallel processing capabilities of hardware computing. Taking 4-bit fixed-point numbers as an example, a 4×4 multiplier is constructed to implement fixed-point multiplication, represented as follows: .

[0068] This embodiment uses Simulink to model a memristor-based logic circuit, such as a full adder circuit based on a memristor. Figure 3 As shown in the diagram, taking 4-bit fixed-point number calculation as an example, the entire architecture adopts a four-layer cascaded computing unit structure, namely four layers of memristor-based ternary adders. The lower left corner of the diagram provides an expanded description of the memristor-based ternary adders. Each layer of ternary adders includes three memristor-based logic function modules, and each logic function module contains multiple basic memristor arithmetic units. Conn1, Conn2, and Conn3 in the memristor-based ternary adder represent input ports used to receive external input signals. The Scope on the right is used to observe the output signal of the oscilloscope. The module on the left side of the oscilloscope is... The analog-to-digital binary interface converts the front-end electrical signal into binary code that the digital system can recognize. The entire four-layer structure has eight parallel input ports, corresponding to the input signals of the full adder. These ports rearrange the input data according to the rules of the IPIV matrix to prepare the data for the subsequent 8-point FFT transformation. The layers are connected through a dedicated data path to ensure that the intermediate results in the calculation process can be correctly passed to the next layer for further processing. This hierarchical structure realizes the butterfly operation in the FFT algorithm and makes full use of the parallel computing characteristics of the memristor.

[0069] Step S5. Perform fixed-point matrix FFT processing on the image based on memristors and optimize performance. By dividing the image data into multiple small regions, perform independent FFT operations on the pixel values ​​of each region, and use the non-volatile characteristics and efficient conductivity adjustment capability of memristors to complete the dynamic loading and calculation of weights according to the methods of steps S1 to S4. In the calculation process of each block, the memristor can accurately simulate the calculation process through its conduction state, avoiding the complex data transmission operations in traditional digital circuits. Multiple block tasks can be processed in parallel by memristors to achieve efficient calculation of large-scale image data.

[0070] When performing specific FFT calculations using the method of this invention, the following process is included: Figure 4 As shown:

[0071] Step 1: Preprocess the input data to adapt it to the subsequent memristor calculation process. Specifically, adjust the input data to the numerical range suitable for memristor calculation through scaling, format conversion and other operations. At the same time, complete the initial hardware parameter configuration of the memristor array, such as voltage and resistance, to ensure that the subsequent FFT operation is performed under the condition of numerical stability and hardware compatibility.

[0072] Step 2: The system enters the FFT algorithm initialization stage, sets the necessary operation parameters, including determining the matrix block size based on the input data size, preset the maximum number of iterations threshold, and initializes basic parameters such as the rotation factor required for FFT, thus building an operation framework for subsequent matrix operations.

[0073] Step 3: Prepare the computation queue The iteration count i is initialized to 0, the matrix to be processed is divided into blocks and sorted according to the scheduling rules of parallel computing. At the same time, the actual number of iterations is determined by combining the number of blocks and the hardware parallel capability, and the computing resources are pre-allocated to prepare for parallel computing.

[0074] Step 4: The system enters the main calculation loop, which controls the calculation process by selecting the input sequence and judging whether the weights have changed. By comparing the weight parameters corresponding to the current calculation task with the weight parameters stored in the memristor, it is determined whether the weights have changed. If the weights have not changed, the calculation is performed directly using the current weights. If the weights have changed, the new weight matrix is ​​written into the memristor to adapt to the current calculation task, and the calculation is performed using the new weight matrix as the current weights. At the same time, the iteration count i is incremented by one.

[0075] Step 5: Determine if the iteration number i is greater than the preset maximum iteration number t. If not, continue the loop of Step 4. If yes, end the calculation loop and integrate the results of all blocks into the final FFT output.

[0076] Furthermore, the inverse FFT operation was combined to reconstruct the image from the processed result, and its advantages in image processing were verified in experiments.

[0077] Figure 5This is a schematic diagram showing the results of efficient 4-bit fixed-point addition and multiplication operations using a memristor-based full adder and multiplier provided by the present invention. This set of waveforms shows the simulation results of the key operation unit in the fixed-point FFT algorithm based on memristors, representing the logic state of each binary bit at different times. The horizontal axis represents time in milliseconds, and the vertical axis represents the digital logic level (i.e., the high and low levels of the binary signal), corresponding to the logic state of 0 or 1. The figure shows the binary multiplication operations involved in the basic FFT operation, including the multiplication of the twiddle factor 1111 with 1111 to obtain 11000001 (225), and intermediate results such as 11110 (30) in the FFT butterfly operation. Each sub-figure (am) shows the calculation result of different bits through voltage waveforms. High and low levels represent binary 1 and 0, respectively. Among them, (a) indicates that the first bit of the binary result of the memristor-based multiplier is 1, (b) indicates that the second bit of the binary result of the memristor-based multiplier is 0, (c) indicates that the third bit of the binary result of the memristor-based multiplier is 0, (d) indicates that the fourth bit of the binary result of the memristor-based multiplier is 0, (e) indicates that the fifth bit of the binary result of the memristor-based multiplier is 0, and (f) indicates that the second bit of the binary result of the memristor-based multiplier is 0. The simulation results show that the sixth bit of the multiplier's result is 1, (g) indicates that the seventh bit of the multiplier's result is 1, (h) indicates that the eighth bit of the multiplier's result is 1, (i) indicates that the first bit of the full adder's result is 0, (j) indicates that the second bit of the full adder's result is 1, (k) indicates that the third bit of the full adder's result is 1, (l) indicates that the fourth bit of the full adder's result is 1, and (m) indicates that the fifth bit of the full adder's result is 1. These simulation results verify the reliability of the memristor-based FFT basic operation unit and prove that the memristor circuit can not only accurately execute the basic operations in the FFT algorithm, but also maintain good signal stability.

[0078] Figure 6This is an example image of fixed-point FFT processing of an image according to the present invention. As shown in the figure, the image uses the classic Lenna image as the material to demonstrate the processing effect of fixed-point FFT with different point counts. Original Image represents the original image. Each sub-image in the figure is represented by a frequency domain image: the top row labeled FFT-4 / 8 / 16 / 32 / 64 Direct (corresponding to (a)-(e)) in the figure) corresponds to the direct FFT processing results from 4 points to 64 points (FFT-4 means transforming according to 4×4 blocks, and the larger the number of points, the larger the size of the transform block). Direct indicates that no normalization processing has been performed. The bottom row labeled FFT-4 / 8 / 16 / 32 / 64 Norm* (corresponding to (f)-(j) in the figure) performs amplitude normalization on the FFT result, avoiding the amplification problem of amplitude increasing with the number of points. As the number of FFT points increases from left to right, the frequency domain representation shows an increasingly fine grid structure. This is because the more points there are, the finer the spectral sampling granularity, which can retain more high-frequency details. Comparing the figures above and below, it can be seen that the normalized frequency domain is more refined, and the detail restoration is more natural. This intuitively demonstrates the impact of the number of points and normalization on the fixed-point FFT image reconstruction effect.

[0079] Compared to traditional processor-based FFT implementations, memristor-based FFTs offer higher computational density, lower energy consumption, and superior parallel computing capabilities. In particular, when handling large-scale FFT operations, the in-memory computing characteristic of memristors can significantly reduce data transmission overhead and improve the overall system performance.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fixed-point matrix FFT computation based on memristors, characterized in that, The method comprises the following steps: Step S1, a nonlinear voltage control model of the memristor is constructed, and a logic unit of an AND gate, an OR gate and an XOR gate is realized by using the memristor, wherein the AND gate realizes a logical AND operation through the series characteristic of the memristor, the OR gate realizes a logical OR operation through the parallel characteristic of the memristor, and the XOR gate realizes a logical XOR operation through the logical relationship of combining the AND gate and the OR gate; Step S2, an FFT optimization algorithm based on matrix block is designed, and the FFT calculation is simplified through the matrix block, so that the overall FFT is decomposed into small-scale matrix operation units; Step S3, a fixed-point FFT algorithm based on the memristor is constructed, in which the input signal is first converted into a digital signal and represented in a binary form, then the binary value of the input signal is mapped to different conductance levels of the memristor according to the binary value, so as to realize the mapping of the input signal to the conductance state of the memristor, and the fixed-point FFT calculation is completed by recursively expanding the two-dimensional matrix FFT calculation into higher-point FFTs layer by layer; Step S4, a full adder and a multiplier based on the memristor are used to complete fixed-point addition and multiplication operations, the full adder based on the memristor is composed of a plurality of ternary adders based on the memristor, the number of the ternary adders is the same as the fixed-point bit number, each ternary adder provides two data input ports and a low-bit carry input port, and the ternary adder realizes the basic logic unit of the AND gate, the OR gate and the XOR gate through the memristor; Step S5, the image data is subjected to fixed-point matrix FFT processing based on the memristor according to steps S1 to S4, and a processing result is obtained; In step S2, the overall FFT is decomposed into two-dimensional matrix FFT calculation, which is represented as: ； wherein denotes the input data matrix of the FFT, is the weight matrix of the 2-point FFT, is the weight matrix of the 4-point FFT, is the core intermediate weight matrix for implementing the 4-point fast Fourier transform, is the identity matrix, denotes the Kronecker product, is the permutation matrix of the input data, responsible for arranging the data in the bit-reversed order, the permutation process is represented by the following matrix form: ； 2-point FFT weight matrix is represented as: ； 4-point FFT weight matrix is represented as: ； The core intermediate weight matrix of the 4-point fast Fourier transform is represented as: 。 2. The memristor-based fixed-point matrix FFT computation method of claim 1, wherein, The resistance variation of the non-linear voltage control model of the memristor in the step S1 is expressed as: wherein, denotes the resistance value of the memristor, is the minimum resistance value of the memristor, is the maximum resistance value of the memristor, is an internal state variable for controlling the dynamic change of the resistance value.

3. The memristor-based fixed-point matrix FFT calculation method according to claim 1, characterized in that, The recursive matrix operation in step S3 is represented as: ； wherein, is the output of the current layer, is the weight matrix of the current layer, is calculated by k-fold tensor product expansion, denotes the number of recurrent layers, is the identity matrix, is the matrix result generated by the previous layer.

4. The memristor-based fixed-point matrix FFT calculation method of claim 1, wherein, Each ternary adder comprises three logic function modules based on the memristor, each logic function module comprises a plurality of memristors, and the operation logic of the ternary adder is: ； ； wherein A, B represent two 1-bit input data of the ternary adder, represents a low bit carry input of the ternary adder, S represents a normal bit sum output of the ternary adder, represents a high bit carry output of the ternary adder, represents a logical and operation, represents a logical or operation, represents an exclusive or operation; The construction of the multiplier based on the memristor realizes fixed-point multiplication through bit-by-bit multiplication and partial accumulation addition, and for n-bit fixed-point numbers, an n*n multiplier is constructed to realize fixed-point multiplication, which is represented as: ； wherein, is the result of an n-bit fixed-point multiplication, and is a binary bit, and denotes an index, denotes a logical AND operation, the accumulation of partial products is done by full adders, eventually forming the complete multiplication result.

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